Enabling AI Silicon Solutions for

Next Generation Data Infrastructure

Igor Arsovski, CTO, ASIC Business Unit

September 29, 2020
Industry trend:
Custom AI silicon needed for data infrastructure
Standard products Custom silicon efforts (ASICs)
Flexibility/ease of use

CPU
IO

TPU1, TPU2,TPU3 …

Graviton, Inferentia, Nitro

IO

FPGA
FPGA AI training and Inference

AI Inference
100X improvement
in TOPS and TOPS/W
(CPU to GPU/FPGA to ASIC) GPU Auto AI Inference

Performance/power efficiency

Higher-performance at a lower energy per operation

Quality and reliability critical
© 2020 Marvell. All rights reserved. 2
Industry trend:
Growing AI models to silicon scaling gap
AI model growth Moore’s law scaling (transistors/die)

th s TNG

th s
17B
on
Graphcore

on
A100 MK2
8 m m 54B 59B

n1 12
0
xi n
50 xi
Megatron 50
8.3B

GPT-2
BERT-Large 1.5B
340M IBM Power 7
1.2B
Rosset,MSFT
07/2018 01/2020 2010 2020

AI models doubling Logic/chip doubling SRAM/chip doubling

every 3.5 months every >18 months every > 48 months
© 2020 Marvell. All rights reserved. 3
Marvell ASIC Introduction
®

Established ASIC business - spanning

14 process nodes Leading-edge Design Advanced
IPs Services Packaging
Technologies

Over 2000 designs

with record first pass successes

© 2020 Marvell. All rights reserved. 4

 N7 N5

N7 N5

Leading-edge Best in class IO

Marvell offers
Highest performance
technology 112G and parallel IOs

the best of breed Highest

Advanced
bandwidth
packaging
SRAM
Modular MCMs
+50-90%
performance
2.5D 3D
High density SRAM

© 2020 Marvell. All rights reserved. 5

Flexible custom ASIC engagement business models
COPD Standard Hybrid Turnkey

RTL
Netlist
Place
Layout

Customer Marvell

Close collaboration from design architecture start to tapeout release

© 2020 Marvell. All rights reserved. 6
Marvell enables Groq’s 1st PetaOPs AI accelerator
First-time-right 700+mm2 custom ASIC in volume production

Groq architectural innovations:

High-performance and low latency
Multi-chip scalability with deterministic execution

Best-in-class Marvell IPs:

High-speed SerDes
Dense SRAM
Full turnkey PCIe & C2C subsystems

Reliability enhancements for 99.999% availability:

Pre-qualified IP and design flow
Custom test, logic redundancy and ECC
Reliability support from netlist to end-of-life

Final netlist to tape-out in < 3months

© 2020 Marvell. All rights reserved. 7
Enabling custom 5G Carriers Enterprise Networking
data infrastructure
silicon solutions

Data Centers Automotive

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 Processors Storage
Marvell offers #1 in baseband and
data plane processors
#1 in HDD, SSD and Fibre
Channel controllers

the most complete data

infrastructure portfolio Networking Security
#2 in Switches and PHYs #1 in security processors

© 2020 Marvell. All rights reserved. 9

Custom silicon for data centers

Building blocks Custom silicon

Optimized 112G+ SerDes / HBM

Machine learning optimized memory

On package
memory
High-perf. custom Programmable
ARM processors Logic AI accelerators

Switch / Routing IP
Chiplet
Encryption / Decryption Based
Accelerators

Compression/Decompression
Data Centers
Smart NICs
RDMA / iWarp / Network Offload Reliability and uptime 99.999%

© 2020 Marvell. All rights reserved. 10

Custom silicon for computational storage

Building blocks Custom silicon

NAND Media Controller
LPDDR
DSP and LDPC ECC
CPU DDR
PCIe or
Encryption / Data Protection On package NVMe AI / ML
memory SCM

High-performance Computational SSD

custom ARM Programmable
Logic
processors Chiplet
based DDR
Ser or
CXL / PCIe / NVMe accelerators SiP Des CXL
SCM
Data Centers
FTL
Disaggregated memory
Firmware
Reliability and uptime 99.999%
Storage capability
IP / subsystems / firmware
© 2020 Marvell. All rights reserved. 11
Custom silicon for automotive

Building blocks Custom silicon

Autonomous drive Automotive storage
Multi-core AI
Secure PHY / Switch / CNTLs Arm & accelerator
NVMe
NVMeOF
security ASIC
NVMe / NVMeOF
On package B I B B A B
High-performance memory A I
B A
multi-core ARM
Security IP A B G G G
processors Central I
A Process
solutions ASIC
or
Central ASIC

Chiplet A Process
Safety Island / Safety Monitors ASIC
or I
based A B
Proven Interface IP accelerators B G I
G G A
A
B B B A B
I
High-bandwidth SRAM / LD / GD A A I
Secure PHY switches
Full turnkey capability Controllers Reliability and uptime 99.999%
Automotive network
© 2020 Marvell. All rights reserved. 12
Proactive measures to maintain reliability & availability
FAB & OSAT partnerships
Deep understanding of technology intrinsic failure mechanisms
Design for reliability

IP design methodology Pre-qualified internal and 3rd party IP

Chip design methodology Pre-qualified chip design methodology

Image/package Pre-qualified image / package offering

(qualified chip carrier)

Test Pre-qualified reliability and quality screens from qualification test vehicles
(module that works as models
predict for supported lifetime) Enhanced escape prevention methodology for Automotive and Aerospace

© 2020 Marvell. All rights reserved. 13

Summary: Marvell’s unique custom silicon offering

1 Industry’s only complete data infrastructure IP portfolio

2 25-year custom ASIC track record of execution with >2000 high-reliability production ASICs

Shipping multiple AI/ML ASICs including PetaOP/s accelerators

3 Scaling to advanced technology nodes with 5nm hardware in the lab

4 Offering industry’s most flexible business models to enable next generation innovations

© 2020 Marvell. All rights reserved. 14

Thank You