Discrete SOGI Based Control of Solar Photovoltaic
Integrated Unified Power Quality Conditioner
Sachin Devassy, Student Member, IEEE
Electrical Engineering Dept.
IIT Delhi
New Delhi-110016, India
Email:sachindevassy@gmail.com
Abstract—A discrete second order generalized integrator
(DSOGI) based control is presented in this work for control of
solar photovoltaic integrated unified power quality conditioner
(SPV-UPQC). Two DSOGI based band-pass filters are used
to extract fundamental positive sequence component (FPSC)
of unbalanced grid voltages. The shunt compensator of SPV-
UPQC is controlled based on philosophy of drawing balanced
positive sequence currents (BPSC) from the point of common
coupling (PCC). The shunt compensator has the dual function of
compensating for load power quality issues along with injecting
power from solar photovoltaic (SPV) array. Sensitive loads
are protected against grid voltage fluctuations such as voltage
sags/swells etc with the help of the series compensator of SPV-
UPQC. A step-up DC-DC converter is used for coupling SPV
array to the DC-bus of SPV-UPQC. A Maximum power point
tracking (MPPT) algorithm generates appropriate duty cycle
for the dc-dc converter so that the SPV array is operated
at its peak power. The performance of DSOGI based SPV-
UPQC is simulated in Matlab-Simulink environment and tested
under dynamic conditions of grid voltage disturbances, load
disturbances and solar irradiation variation.
Index Terms—Power quality, SPV-UPQC, solar mppt, FPSC,
DSOGI, series compensation, shunt compensation, step-up con-
verter, band-pass filter.
I. I NTRODUCTION
W ITH advances in power electronics and micro-
electronics technology, there is an increased prolif-
eration of power electronics based systems which are en-
ergy efficient. However, these power electronics systems are
nonlinear and hence inject harmonic currents into the grid.
Apart from harmonics, various other load side power qualities
in a distribution system include excessive neutral current,
load unbalancing, excessive reactive power demand [1]. In
many countries, the increased installation of renewable energy
systems (RES) has started affecting the voltage quality partic-
ularly in low voltage distribution systems [2]. The grid voltage
fluctuations affect sensitive industrial loads leading to frequent
tripping and thus increased economic losses. Voltage sags are
the most commonly encountered fluctuation [3] which occur
due to faults or due to heavy loading at the point of common
coupling. A detailed discussion on various types of voltage
sags and its causes are described in [3].
c 2016 IEEE
978-1-4799-5141-3/14/$31.00
ory (ISC) [4]. In order to inject balanced positive sequence
Bhim Singh, Fellow, IEEE
Electrical Engineering Dept.
IIT Delhi
New Delhi-110016, India
Email:bhimsinghiitd60@gmail.com
Custom power devices are an attractive option for the
mitigation of power quality issues. Custom power devices in-
clude distribution static compensator (DSTATCOM) for shunt
compensation, dynamic voltage restorer (DVR) for series com-
pensation and unified power quality conditioner (UPQC) for
both shunt and series compensation [4]. Due to its shunt and
series compensation capability, UPQC provides a complete
solution to power quality issues as compared to DSTATCOM
and DVR. In the recent years there has been an increased
focus on integrating RES/energy storage systems with custom
power devices [5]. A study of use of custom power devices
for integrating wind farms to grid was reported in [6]. In
[7], a DVR with an energy storage system with fault current
limiting functionality has been reported. Combining renewable
energy systems with custom power devices gives advantages
of improving power quality, providing clean energy and also
increased fault ride through capability [8], [9].
A comprehensive review of various UPQC topologies and
control structures have been discussed in [10]. Along with
issues of nonlinear currents, another major problem in dis-
tribution systems which are three-phase four-wire (3P4W)
systems is that of load neutral current. Even under case of
balanced loads neutral currents are present if the loads in each
phase are nonlinear. For compensation of neutral current, the
commonly topologies of shunt VSC include four-leg VSC or
three-leg VSC with split capacitor. Similarly, as most of the
sags encountered in distribution systems are unbalanced, the
required series compensator [11] topology is also four leg VSC
with single capacitor or three-leg VSC with split capacitor.
The control of four-leg VSC is simpler as compared three-leg
VSC with split capacitor which involves extra control loop
of balancing the split capacitors and hence four-leg based
topology is preferred for the series and shunt compensator
of UPQC.
Digital signal processing is an important function in the con-
trol of custom power devices (CPD). Most of the methods em-
ployed for control of CPD are time domain based techniques
as it involves simpl calculations and less memory requirements
[1]. The commonly used methods include p-q theory [12], d-
q theory[13] and instantaneous symmetrical component the-
currents into grid under conditions of asymmetrical voltages Ripple
Filter
Ripple
Filter
Rfsh, Cfsh
or harmonic distortion at PCC, the extraction fundamental vMa Ls Rs vsa
Rfs, Cfs Cr Rr

- vsea + vla
positive sequence component (FPSC) of PCC voltage becomes isha
iLa
isa
vital. In [14], the use of two SOGI based band-pass filters have 3-Phase
vMb Ls Rs vsb vlb
been proposed for extracting FPSC. In [15], a cascaded delay - vseb +
4-wire
Linear
ishb
signal cancellation (CDSC) based technique for extraction of isb
iLb and
Nonlinear
FPSC has been proposed to be used as pre-filtering scheme in vMc Ls Rs vsc vlc
Load
- vsec +
three-phase pll. Some other FPSC detection methods include ishc iLc
isc
using adaptive notch-filter (ANF) [16], using complex vector Ls Rs iLn

filter method [17] etc. isn Lr

Lr ishn
Lf
In this paper a DSOGI based control is proposed for the Lr
Lf
Lf
control of SPV-UPQC. An implementation of DSOGI based PV-
ipv
Lr Lf
Array
band-pass filter is simple as it basically consists of two integra- L
tors, three gain blocks and two summers. Two DSOGI based
band-pass filters are used for extraction of FPSC components vpv
Cpv Cdc
vdc

of PCC voltages based on which the reference for shunt

compensator is generated. The resulting currents are balanced
and sinusoidal and UPF with the FPSC of PCC voltages. The
objective of the series compensator is to maintain the voltage
of the load terminals at desired magnitude and in-phase with
the FPSC of PCC voltages. A step-up DC-DC converter is
used for integrating the SPV array at the DC-link of SPV-
UPQC. For operating the SPV array at its MPP, a MPPT
algorithm [18] is used to generate appropriate duty ratio for
the step-up converter. The SPV-UPQC is tested in a 3P4W
system consisting of single phase nonlinear load in each phase.
The performance of SPV-UPQC is evaluated under commonly
encountered dynamic conditions of low voltage distribution
system such as load unbalancing, irradiation level variation
and asymmetrical voltage sags.
II. C ONFIGURATION OF SPV-UPQC
The configuration of SPV-UPQC for a 3P4W system is
presented in Fig.1. The major parts of the system are a series
compensator and a shunt compensator connected back to back
with a common DC-bus. As the shunt compensator has to
compensate for unbalanced loads and the neutral current in
a 3P4W system, a four-leg shunt VSC is used for shunt
compensation. The series VSC used is a four leg VSC which
can compensate for unbalanced voltage sags. The step-up
converter is utilized for coupling the SPV array to the DC-
bus of SPV-UPQC. The shunt and series compensators are
interfaced to the grid through interfacing inductors Lf and Lr
respectively. A series injection transformer is use to inject the
voltages (vsea , vseb , vsec ) generated by the series compensator
to protect sensitive loads against grid voltage sags/swells.
Ripple filters (Rr − Cr , Rf s , Rf sh ) are used to bypass the
harmonics generated due to switching.
III. C ONTROL OF DSOGI BASED SPV-UPQC
The four major control blocks of SPV-UPQC are the dis-
crete SOGI based fundamental positive sequence component
(FPSC) extractor for extracting FPSC of PCC voltage, MPPT
control block for the step-up DC-DC converter, shunt com-
pensator control block and series compensator block. These
blocks are discussed in detail as follows.
Fig. 1. Configuration of SPV-UPQC
A. Extraction of FPSC of PCC Voltages
The extraction of FPSC components of PCC voltage is a
major task in control of SPV-UPQC as the reference signal
generation of both shunt compensator and series compensator
depends upon FPSC of PCC voltage. In this work, the FPSC
are extracted using a discrete SOGI (DSOGI) band-pass filter.
The structure of DSOGI band-pass filter is shown in Fig.
2(a). As can be seen from Fig. 2(a), in the DSOGI band-
pass filter there are two discrete integrators, two summers and
three gain blocks. The Trapezoidal version of integrator is
used in SOGI as it gives more accurate results as compared to
forward or backward Euler discrete integration methods. The
gains ω is set at nominal grid frequency. The gain block K is
adjusted based on compromise between accuracy and speed of
extraction of FPSC. For an input signal vs , the DSOGI band-
pass filter gives the fundamental frequency component vs1 and
fundamental quadrature shifted component qvs1 .
In order to extract FFPS components using DSOGI [14]
band-pass filter, two DSOGI band-pass filters are used as
shown in Fig.2(b)
The PCC voltages (vsa , vsb , vsb ) are transformed into
α − β domain using Clark’s Transform. The α component
vα and β component vβ are filtered using DSOGI band-
pass filter to obtain the fundamental component (vs1α , vs1β )
and its quadrature shifted version (qvs1α , qvs1β ). The relation
between the FPSC and fundamental frequency components is
given as,
+ 1 
vs1α = vs1α − qvs1β (1)
2
+ 1 
vs1β = vs1β + qvs1α (2)
2
 Vpv Ppv Gating Signals
KTs ( z + 1) v s1 Ipv ´ LPF
isa
vs - ws
+ K +- 2( z - 1) isb
Vdc* Ploss isc
+- PI Hysteresis
Current
Vdc

+
+
+
MAF Controller
qv s1 KTs ( z + 1) -1
ws
2( z - 1) vLabc
PLav
Dot +- isn
iLabc MAF +
Product isa* isb* isc* isn*=0
(a) DSOGI band-pass filter
v s+1a ´ ´ ´
v s1a 1 ()2 +
v sa
v sa + 2 v s+1a v s+1b ¸
Discrete - v s+1a () 2
+
abc SOGI-BPF qv s1a abc v s+1c
v sb v s+1b v s+1a v s+1b

v sc qv s1b
v sb
v s+1b v s+1c Fig. 3. Shunt Compensator Control Structure
Discrete
αβ αβ
SOGI-BPF v s1 b + 1
+ 2

harmonic ripple. The DC-bus of SPV-UPQC is regulated at

(b) DSOGI based FPSC Extractor its desired reference value using a digital proportional integral
Fig. 2. Structure of DSOGI and DSOGI based FPSC extraction (PI) controller. The reference for DC-bus PI controller is set
at 700V. The sensed DC-bus voltage is filtered through MAF,
the window length of which, is kept at half the grid period as
+ +
The FPSC of PCC voltage in α − β domain (vs1α , vs1β ) DC-link has even harmonics. The PI controller gives the power
are transformed back using inverse Clark transform to obtain loss component of the SPV-UPQC. The reference power to be
+ + +
FPSC of PCC voltage in stationary frame (vs1a , vs1b , vs1c ). drawn from the grid is then derived as,

B. Control of Step-Up Converter P ∗ = PLavg + Ploss − Ppv (4)

A step-up converter is used for integrating the SPV array where Ppv is the SPV array power. The balanced positive
to the DC-link of SPV-UPQC. The SPV array is operated at sequence reference grid currents are obtained as,
its MPP by controlling the step-up converter using a MPPT +
algorithm. In this work, perturb & observe (P&O) algorithm is vs1,abc
i+
s1,abc = +2 +2 P∗ (5)
implemented for tracking MPP. The MPPT algorithm directly vs1α + vs1β
generates the duty ratio for the next switching period of the
where P ∗ is average power drawn from grid.
step-up converter. The duty ratio updating rule is given as,
The reference neutral current (i∗s ) is set as zero. The
reference currents (i∗sa , i∗sb , i∗sc , i∗sn ) are compared with the
dn+1 = dn + δd.sgn(δPpv ) (3) sensed currents (isa , isb , isc , isn ) in a hysteresis controller to
where dn+1 is duty cycle for next switching cycle, dn is duty generate gating pulses corresponding to shunt VSC.
cycle ratio of current switching period, δd is perturbation size D. Control of Series Compensator of SPV-UPQC
of duty ratio, δPpv is difference in power calculated between
two cycles of MPPT algorithm. The purpose of the series compensator is the protection of
sensitive load against disturbances in PCC voltages. The series
C. Control of Shunt Compensator of SPV-UPQC compensator injects voltage in-phase with the FPSC of the
PCC voltages. The series compensator control block diagram
The two major functions of the shunt compensator is to
is presented in Fig. 4.
mitigate the load side power quality problems and supply real
The amplitude of FPSC of PCC voltages is calculated as,
power obtained from the SPV array. The control methodology q
for the shunt compensator control is such that, the currents Vs+ = vs1α +2 +2
+ vs1β (6)
drawn from PCC are balanced positive sequence currents,
both under unbalanced sags of PCC voltages or unbalanced The unit templates of FPSC of PCC voltages are obtained
condition of nonlinear loads. The shunt compensator control as,
structure is shown in Fig.3. +
vs1,abc
The average load real power (PLavg ) is extracted by filtering u+
s1,abc = (7)
the dot product of load voltages and currents. The filter used Vs+
is a moving average filter (MAF), the window length of The load reference voltages (vLabc
∗
) are obtained by multiply-
which, is fixed at half the grid fundamental period as during ing the peak reference voltage (VL∗ ) with the unit templates
unbalanced condition the instantaneous load power has double (u+
s1,abc ). The reference for the fourth leg of series VSC (vLu )
∗
 VL* Gating Signals 500

v s(V)
v *La v La 0
v s+1a
´
v s+1b
¸u +
s1a
v *Lb
v Lb
v Lc
-500
Voltage 500
¸u ´

v L (V)
+ Hysteresis
v s+1c s1b v *Lc 0
Control

+
+
+
v s+1a
¸u +
s1c
´
-1
-500
800

V dc(V)
v s+1b Amplitude
v *Lu = 0 v Lu 700
Calculation
600
100
Fig. 4. Series Compensator Control Structure

i s(A)
0
-100

is set as zero. The reference voltages (vLa

∗
, vLb
∗
, vLc
∗
, vLu
∗
) 10

i sn (A)
are compared with the sensed voltages (vLa , vLb , vLc , vLu ) 0
in a voltage hysteresis controller, which generates the series -10
compensator gating pulses. 200

i L (A)
0
IV. P ERFORMANCE E VALUATION -200
The DSOGI based SPV-UPQC is simulated in Mat- 200

i Ln(A)
lab/Simulink software using SimPowerSystems blockset. The 0
dynamic performance is evaluated at different scenarios such -200
as unbalanced sag of PCC voltages, irradiation variation and 200
load disturbances. The load used consists three single phase i SH(A) 0
current-fed nonlinear loads each connected between a phase -200
and neutral of the system. The detailed design values of the 200
i SHn(A)

SPV-UPQC are given the Appendix. 0

-200
A. SPV-UPQC performance during Load Disturbances
30
P pv(kW)

The dynamic behavior of SPV-UPQC under load distur- 20

bance is presented Fig.5. The irradiation(G) of SPV array is 10
0
kept at 1000W/m2. The signals shown are PCC voltages(vs ), 700
V pv(V)

load voltages (vL ), DC-bus voltage (Vdc ), grid currents (is ),
grid neutral current (isn ), load current (iL ), load neutral
current (iLn ) shunt compensator current (iSH ), shunt com-
pensator neutral current (iSHn ),SPV array power (Ppv ), SPV
array voltage (Vpv ). It is to be noted that the PCC and load
voltages shown are phase to neutral voltage.
As observed from Fig.5, the shunt compensator keeps the
PCC neutral current (isn ) at nearly zero by compensating
for load neutral current. It can also be observed that the
though the load is nonlinear, the grid current is sinusoidal at
unity power factor. From t=0.6s to t=0.7s phase ’a’ is opened
through circuit breaker. It is observed that the grid currents
are still sinusoidal and balanced. The DC-bus voltage settles
within 4% reference value of 700V within 0.06s after a slight
overshoot/undershoot during opening and closing of circuit
breaker.
B. SPV-UPQC performance during Irradiation change
The dynamic performance of DSOGI based SPV-UPQC is
evaluated by giving a ramp decrease in solar irradiation. The
relevant signals are shown in Fig.6. The signals shown are
three-phase PCC voltages (vs ), load voltages (vL ), DC-bus
voltage (Vdc ), grid currents (is ), grid neutral current (isn ), load
current of phase ’a’ (iL ), load neutral current (iLn ), shunt
compensator current of phase ’a’ (iSH ), shunt compensator
600
500
0.55 0.6 0.65 0.7 0.75 0.8
Time(s)
Fig. 5. Performance of SPV-UPQC under Load Disturbances
neutral current(iSHn), SPV array Power (Ppv ), SPV voltage
(Vpv ), and irradiation (G(W/m2 )). As the load is symmetrical,
the shunt compensator currents are symmetrical and hence
only phase ’a’ current is shown in case of load currents
and shunt compensator currents. From 0.6s to 0.65s, the
solar irradiation(G) is uniformly varied from 1000W/m2 to
200W/m2 . As observed from Fig.6, as the power from the
SPV array reduces, the real power demand of the load side is
supplied by the PCC. The DC-link is regulated at its desired
value.
C. SPV-UPQC during Asymmetrical Sag in PCC Voltages
Fig.7 presents the SPV-UPQC performance under asymmet-
rical sag in PCC voltages. The SPV array is at STC conditions
of 1000W/m2 and 25◦C. Signals shown are grid voltages
(vs ), load voltages (vL ), series compensator voltages (vSE ),
DC-bus voltage (Vdc ), grid currents (is ), grid neutral currents
 500 500

v s(V)
v s(V)
0 0
-500 -500
500 500

v L (V)
v L (V)

0 0
-500 -500
750 200
V dc(V)

v se(V)
700 0
-200
650
800

V dc(V)
100
i s(A)

0 700
-100 600
10 100
i sn (A)

i s(A)
0 0
-100
-10
100 200

i sn (A)
i L (A)

0 0
-100 -200
100 200

i L (A)
i Ln(A)

0 0
-100 -200
100 200

i Ln(A)
i SH(A)

0 0
-200
-100
100 i SH(A) 100
P pv(kW) i SHn(A)

0 0
-100 -100
100
V pv(V) P (kW) I (A)

30
20 0
SHn

10 -100
0
700 30
G(w/m2) V pv(V)

20
600
pv

10
500 0
700
1000 600
500 500
0
0.55 0.6 0.65 0.7 0.75
0.55 0.6 0.65 0.7 0.75
Time(s)
Time(s)

Fig. 6. SPV-UPQC performance under varying irradiation condition Fig. 7. SPV-UPQC performance during asymmetrical sags in PCC voltage

total harmonic distortion (THD) of the nonlinear load current

(isn ), phase ’a’ load current (iL ), load neutral current (iLn ),
phase ’a’ shunt compensator current (iSH ), shunt compensator
neutral current (iSHn ), SPV array power (Ppv ), SPV array
voltage (Vpv ). As the load is symmetrical but nonlinear, the
shunt compensator signals are also symmetrical and nonlinear;
hence, only phase ’a’ current is shown in case of load and
shunt compensator signals for good clarity in representation.
As can be seen from Fig. 7, from t=0.6s to t=0.7s there is an
unsymmetrical sag of 0.3pu in phase ’b’ and ’c’ along with a
phase jump. It can be noted that the load voltage is sinusoidal
and at its reference value despite the distortions in the grid
voltage. Under nominal conditions the series compensator does
not inject voltage. The grid current rises during sag to maintain
real power balance.
The harmonic spectra of grid currents and load currents are
given in Fig.8. The DSOGI based SPV-UPQC compensates for
the harmonics of load current. It can be noted that though the
is 36.44%, the THD of the grid current is 2.17% and is thus
within limits prescribed in IEEE-519 standard [19].
V. C ONCLUSION
A DSOGI based SPV-UPQC and its dynamic performance
has been presented in this work. Two DSOGI band-pass
filters have been used to extract FPSC of PCC voltages. The
extracted FPSC has been used for reference signal generation
in case of shunt and series compensator. The SPV-UPQC
performs satisfactorily under conditions of load unbalance,
asymmetrical sags and solar irradiation variation. The grid
currents are balanced and sinusoidal even under conditions of
nonlinear and unbalanced load. The load voltages are also bal-
anced and sinusoidal under conditions of asymmetrical sags.
The integration of SPV array with SPV-UPQC enhances the
functionality of the UPQC. SPV-UPQC integrates the concept
of clean energy along with power quality improvement.
 100 Series Compensator: 4mH; Injection Transformer: 12kVA,
415V/138V; VA Rating of Shunt Compensator=38kVA, Rat-
ing of Series Compensator=12kVA; Gains of DC-bus PI
i s (A)

0 contoller: Kp =500,Ki=3000; MAF Parameters for DC bus

filtering:N =100,Tw=0.01,Ts=1e-4; MAF Parameters for Load
Power Calculation:N =100,Tw=0.01,Ts=1e-4; DSOGI Par-
-100 maters: Ts =5e-5,K=0.8; DC Inductor: L=0.5mH; Input Capac-
0.76 0.77 0.78 0.79 0.8 itor of Step-Up Converter:100µF; SPV array data: P =13.8kW,
Time(s) Voc =703V, Isc 25.8=A, Vmpp =568V, Impp =24.12A.
100
(% of Fundamental)

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Technology, Govt. of India, under Grant Number: RP02583.
A PPENDIX
Detailed Design Values: Per phase grid voltage: 239.6V,
50Hz; Grid Impedance:0.1mH, 0.02Ω; Reference DC-bus
Voltage: 700V; DC-bus Capacitor: 10mF; Nonlinear Load
in each phase: Bridge Rectifier with R-L: 3Ω, 100mH;
Shunt Compensator Interfacing Inductor:1mH; Shunt com-
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