Design and Evaluation of Performance-efficient
SoC-on-FPGA for Cloud-based Healthcare
Applications
Mayank Kabra, Prashanth H C, and Madhav Rao
International Institute of Information Technology Bangalore, India
Email: {mayank.kabra, prashanth.c, mr}@iiitb.ac.in
Abstract—Cloud computing with more resources at disposal
has served heavy computing demands for various applications.
Health is one such sector where the cloud services have benefited
by not only storing and updating the subscribers’ health records
frequently but also providing useful analytical and predictive
information to the users. However most of the cloud processing
runs are established on general-purpose computing devices that
are non-customized for accelerating medical inferences. Hence,
a special purpose and power-efficient SoC design for cloud
computing targeted towards healthcare applications is desirable.
The study examines the design and evaluation of SoCs for
today’s neural networks trained for healthcare data. The work
realizes fully connected neural networks comprised of 2 and 3
layers that are trained from two freely available datasets; one
meant for detecting the survival status of the individuals suffering
from prostate cancer and the other for survival status post
blood and marrow transplantation, respectively. Additionally, a
light-weight image classifier derived from medical based MNIST
pathological dataset was also considered. The three neural
networks were hardware designed and characterized with two
different processor cores and two extreme cache memory configu-
rations individually and in combination to generate multiple SoC
designs. Each SoC design is illustrated and evaluated in terms
of power and hardware resource utilization. The SoC design
incorporating all three hardware accelerators compared to the
existing cloud platforms showcased power reduction by 7.13X,
5.25X, and 15X, and average throughput improvement by 49.37X,
19.78X, and 26.47X, when compared to its corresponding neural
network, runs on CPU, GPU, and TPU units respectively. The
SoC designs in this work with three different co-processor choices
set an example to achieve customized cloud SoC designs that
are power and performance efficient and targeted for healthcare
applications.
Index Terms—SoC design, Hardware accelerator, AI on-chip,
Cloud computing
I. I NTRODUCTION
Cloud platforms have always been on the fore-front for
serving users’ demands [1]–[8], and healthcare services have
recently relied on the same for either personalized health-
record storage or providing intuition to the individuals based
on their constantly supplied medical data [9]–[12]. In the
past few years, due to the emergence of Artificial Intelligence
(AI) and Machine Learning (ML) techniques, the multi-modal
physiological signals indicate unique characteristics that are
extremely useful for the users’ well-being. The modern-day
cloud platforms are equipped with high-performance proces-
sors, Graphics-Processing-Units (GPUs), Tensor-Processing-
Units (TPUs), and other devices to extract and share the
information with the subscribers. The Cloud-based designs,
especially for healthcare services, require customized pro-
cessing; using general purpose homogeneous processing units
infers sub-optimal utilization of processing units and high
energy consumption. The computing energy and latency costs
are directly charged to the subscribers, which eventually
limits the cloud users and hampers large-scale adoption of
health services on the run. Although the advantages of the
Cloud-supported healthcare services are enormous, the power
inefficient and non-customized design of the cloud engine fails
to attract the needy individuals, which otherwise should be
adopted on a large scale. Hence a cloud-targeted customized
System-on-Chip (SoC) design with accelerated performance
and power-efficient designs for healthcare applications is es-
sential, with the overall cost of using the cloud services for
short duration is likely to come down; the benefit of the same
could be passed on to the customers. However, bespoke SoC
designing has its own challenges.
Until recently, SoC design for specific applications was
always considered a bottom-up approach where the design
involving the particular operation is developed, validated, and
merged with the available processor design [13]. Modern SoC
design involves utilizing many Intellectual Property (IP) cores
over shared-bus, and network-on-chip (NoC) interconnects to
obtain the desired features. The difficulty in SoC design is
due to several factors, including design complexity, protected
IP cores, and tight boundary of design constraints.
Several tools have been developed in the past to design
processor-based memory subsystems [14]–[18], however it
lacks the integration flexibility in IP cores, interconnects, and
parametric optimization leading to customized application-
specific SoCs. Several SoC simulators to aid in the design
evaluation also exist; however, most of them do not extract the
silicon footprint information, which is crucial for physically
validating the design before tape-out [19]–[22]. Besides the
recent surge in convolution neural networks (CNN) and other
fully-connected layers (FN), the hardware designers are com-
pelled to not only realize and characterize the module but also
to try establishing some sort of information when integrated
into the SoC design. The ESP [23], [24], and Chipyard [25]
frameworks allow to design the CNN accelerator and use the
same to realize the SoC design.
 In the past, the neural network architectures were either
completely or partially realized in the hardware blocks [26].
Few techniques, such as quantization [27]–[29] and inte-
gerization [30], were applied to fit the resource constraint
hardware. The neural network hardware accelerator designs
are beneficial, especially for time-critical applications where
the output aids in accelerating the decision-making [26], [30].
The SoC design with an in-built hardware accelerator for
healthcare services are essential; however, most of the attempt
in the past focuses on realizing the hardware accelerator block
designs and showcasing the benefits achieved in terms of
latency and resources utilized instead of characterizing the Fig. 1. Cloud SoC Architecture design equipped with three neural network
complete SoC design. Besides, most of the studies target one hardware accelerator design.
co-processor design by evaluating the performance and hard-
ware metrics, whereas healthcare services mandate multiple TABLE I
inferencing modules running on single or multi-modal data N EURAL NETWORKS IMPLEMENTED AS ACCELERATORS .
and then arrive at a decision. Output Accuracy
Model Dataset Inputs Parameters
This paper focuses on the novel contributions on engineer- Classes (%)
Stage C
ing the SoC design, that are listed below: Dense 2
Prostate 3 7 2563 76
Layers
Cancer [31]
1) Adopting ESP framework developed by the Columbia European Society
University Research group [23], [24] and realize single Dense 3
for Blood and 3 5 6591 90
Layers
and three multiple hardware accelerators in the SoC Marrow (EBMT) [32]
Image
design using two different processor cores and two Classifier Med-MNIST [33] 10 784 5235 81
extreme memory configurations. (2 layers)

2) The SoC design is targeted to offer health-related pre-

dictions, and hence the neural network architecture used
to build the hardware accelerator is selected on the basis
of three different medical dataset.
3) All SoC designs were characterized and evaluated in
terms of power, hardware resources such as BRAMs and
LUTs utilized, and latency incurred.
4) The throughput and power metrics of the proposed
hardware accelerator enabled SoC designs were bench-
marked against three other processing units including
CPU, GPU, and TPU, to showcase the efficacy of the
proposed hardware design.
This is the first time, as per the author’s knowledge, Cloud tar-
geted and health-related SoC designs, and their characteristics
are put across the research community. The SoC design with
AI accelerators is aimed to extract inference from the supplied
data, which is expected to improve the performance efficacy,
besides predicting any complex medical problems, for timely
treatment.
II. S O C D ESIGN
The Cloud-targeted SoC design for healthcare service is
different from other domains considering multiple health-
related information is supplied constantly by the users, and
the derived inference is released to the users and doctors
treating the individuals whenever required, as depicted in
Figure 1. The containers shown in the figure establishes three
different medically relevant dataset stored in the cloud for
achieving inferences made by the SoC design. The health
data is acquired at a different sampling rate, and extracting
useful features toward successful diagnosis requires different
neural network architectures. The paper establishes three dif-
ferent neural network designs that are configured with fully
connected dense layers in the SoC design. Table I shows
these 3 neural networks, structured differently with variations
in output classes, input feature maps, number of trained
parameters, and expected accuracy in the overall SoC design,
in a view to establish an example for SoC design towards
healthcare applications.
The first dense 2-layered neural network with 6 input
features and 3 output classes achieved 91% accuracy on flow-
cytometry results dataset [31], predicting the survival time in
the form of 3 classes for the Stage#C type prostate cancer
individuals. An input shape of 7, with three output shapes
of 32, 64, and 3 in the order were defined for this neural
network, with an overall 2563 parameters. The second dense
3-layered neural network with 8 input features and 3 output
classes achieved an accuracy of 90% on the dataset [32] in the
form of 3 classes of risks suffered by the individuals post blood
and marrow transplantation. An input shape of 5, with three
output shapes of 32, 64, 63, and 3 in the order, was defined
for this neural network, with an overall 6591 parameters. The
third neural network is an image classifier with two layers
that were derived from the medical based pathological dataset
model [33] for performing classification tasks on light-weight
28×28 images. An input image of 28×28 pixels for 10 output
classes with an accuracy of 76%, with dropout and batch
normalization, was also considered in this work. An input
shape of 784, with two output shapes of 5, 64, 64, and 10 in
the order, were defined for this neural network, with an overall
5235 parameters. All three neural network models are designed
as co-processors and are integrated with multiple combinations TABLE II
of open-source processor cores and memory blocks to evaluate S O C CONFIGURATIONS FOR THE NEURAL NETWORK DESIGNED
HARDWARE ACCELERATOR INTEGRATED WITH DIFFERENT PROCESSOR
the characteristics. The SoC was designed and characterized CORES .
using the ESP framework [23], [24] and was characterized in
terms of latency, LUTs used, BRAMs allocated, and power Configuration Accelerator Processor
A1 Dense2layers Ariane
consumption across different components of SoC design. A2 Dense2layers leon3
B1 Dense3layers Ariane
B2 Dense3layers leon3
C1 image classifier Ariane
C2 image classifier leon3
D1 all Accelerators Ariane
D2 all Accelerators leon3

for accelerator. Minimum Cache configuration is (32 set, 2

way L2) + (32 set, 4 way LLC) and (32 sets, 2 way L2) for
accelerator. All 16 SoC designs were synthesized on Xilinx
Vivado and system-level simulation performed using Xcelium
tool of Cadence Suite for establishing the results.

Fig. 2. Schematic showing SoC design and Analysis flow.
The overall SoC design flow and analysis are pictorially
explained in Figure 2. ESP allows tile-based SoC with the
desired mix of accelerator tiles, along with memory and
processor tiles. Each of the tiles is equipped with a channel
to the main memory. An I/O tile is also integrated to manage
various peripherals. ESP is built on a multi-plane network-on-
chip (NoC) interconnect structure. These three hardware accel-
erators were individually incorporated in the SoC design with
two different combinations of processor cores namely - Ariane
and Leon3 with its floating-point unit (FPU) variants. Ariane is
a 6-stage, single-issue, in-order scheduling based 64-bit RISC-
V CPU with 64-bit DMA access [34]. Ariane is engineered
to handle Integer (I), Multiply (M), Accumulate (A), and
Compressed (C) instructions, along with specific extensions.
Leon3 is a 32-bit processor with 32-bit DMA access that
belongs to SPARC V8 architecture [35]. It is designed with 7-
stage advanced pipeline architecture, with hardware multiply,
divide and MAC units, and operates on a double-precision
floating-point format. These two processor cores were opted
due to their popularity in the SoC design, and at the same time,
the two processors belong to a different family of processor
cores with different features. The evaluation of the SoC design
with 32-bit and 64-bit processor cores is expected to influence
the power and throughput of the SoC design. hls4ml tool was
utilized to convert the Keras model for Dense layered network
and Image classifier to synthesize designs. hls4ml tool allows a
maximum of 4096 parameters in a layer to synthesize success-
fully, hence the neural network was designed with less than
4096 parameters in each layer. Overall, 8 pair of SoC designs,
as stated in Table II were investigated and characterized in
this work for minimum and maximum cache configurations
separately, making it a consolidated 16 individual SoC designs.
Maximum Cache configuration is (8192 set, 8 way L2) + (4096
set, 16 way LLC) for processor and (8192 set, 8 way L2)
III. E VALUATIONS
14
Power(W) 12
10
8
Dense 2 layers
Dense 3 layers
6 Image classifier
All accelerators
4
1 2 3 4 5 6 7 8 9 10
LUTs 10 5
Fig. 3. Variation in power and LUTs utilized for different SOC designs with
accelerator choice.
Figure 3 depicts LUT utilization, and power conceded by the
SoC with individual hardware accelerators, and the SoC design
involving all the three hardware accelerators. As expected, it
is evidently clear that SoC with individual accelerator design
demands less LUTs and power requirements when compared
to the SoC with all three accelerators. The Dense 2 layers
have fewer computation requirements than the Dense 3 layers,
which is reflected in the LUTs-Power profile. The Image
classifier based SoC design presents slightly more power
requirement as of Dense 2 layers, but less than fully connected
dense 3-layered network, and utilizes on an average 105 LUTs
more than dense 2 layers, and 105 LUTs less than dense 3
layers. This is attributed to the number of parameters involved
in all the three neural network architectures. The SoC with
all the three accelerator designs shows power consumption of
around 13 W, which is almost 45.8% less than putting together
all the three individual hardware accelerator-designed SoCs.
Figure 4 reports the hardware utilization for all 16 SoC
designs, including minumum and maximum cache configura-
tions. As expected, the minimum cache memory configured
SoC designs shows extremely low requirement of BRAMs
(Block RAM) than the maximum Cache memory configured
SoC design. On an average, 75% less BRAMs were utilized
for the same SoC design when configured with minimum
 5
compared to 8 input features for B1, B2 designs. Additionally,
10
10
min cache
1000
min cache
in an SoC design, separating the power consumed by the
max cache max cache accelerator designs, the CPU, I/O, and memory blocks also

Block RAM
concede power. The power conceded by the I/0, CPU, and
LUTs

5 500 Memory blocks for the 16 SoC designs are categorized into
minimum Cache and maximum Cache enabled designs, and
are reported in the Figure 4. The CPU, Memory, and I/O block
0
A1 A2 B1 B2 C1 C2 D1 D2
0
A1 A2 B1 B2 C1 C2 D1 D2
reported similar power requirements throughout the 16 SoC
Configuration Configuration designs including the maximum and minimum enabled Cache
15 80
configurations.

Accelerator Power (%)

min cache min cache
max cache max cache
Total Power(W)

60
10 static : 5%
cpu : 6%
40
memory : 11% DDR3 + ethernet : 30%
5
20

0 0
A1 A2 B1 B2 C1 C2 D1 D2 A1 A2 B1 B2 C1 C2 D1 D2
Configuration Configuration IO : < 1%
SOC Power(W) : Max Cache

3 3
SOC Power(W) : Min Cache

CPU
Memory accelerator : 48%
IO
2 2

Fig. 5. Average Power distribution among all the 16 SoC designs.

1 1
0 0
A1 A2 B1 B2 C1 C2 D1 D2
Configuration
Fig. 4. Hardware characteristics of the SoC designs. The last two plots show
the SOC power do not include accelerator power.
An average power distribution among different components
for all 16 SoC designs when used as a cloud server is presented
A1 A2 B1 B2 C1 C2 D1 D2 in Figure 5. On an average 48% of the power is consumed by
Configuration
the hardware accelerator, and 30% of total server is expended
by DDR3 and ethernet which are external to the SoC. Memory,
CPU, Static (leakage) power, and IO concede 11%, 6%, 5%,
and 1% respectively.

Cache memory. Additionally, the total power conceded by Cloud TPU

Power (W) in logScale

the minimum cache memory allocated SoC designs were less 10 2 Intel Xeon 2.2GHz

than its corresponding design with maximum cache memory. Tesla T4

On an average the minimum Cache enabled design exhibited
2.13 W less power than the maximum Cache incorporated
10 1
SoC designs. Between minimum and maximum cache enabled
SoC designs, there is hardly any difference between the LUTs. A1 A2 B1 B2 C1 C2 D1 D2 CPU GPU TPU
As expected the LUT utilization grows from SoC designs
(a)
ranging from A1, A2, to D1, D2. The power utilization of
the accelerator design component, when charted in % with
Latency (us) in logScale

respect to the total SoC power, shows that more power is 10 3

conceded by the accelerator designs especially for D1, D2

designs when compared with A1, A2 designs. This resembles SoC
10 2
that three Neural network accelerator design extracts more Intel Xeon 2.2GHz
Tesla T4
computational power than single accelerator designs, albeit the Cloud TPU

three accelerator design power is still less than the sum of three 10 1
Dense 2 layers Dense 3 layers Image Classifier
individual accelerator power. Among all the 16 designs, D1
SoC design consumes maximum power, whereas A1 exhibits (b)
least power, which is attributed to less number of computations Fig. 6. Comparisons of power and latency metrics of the proposed Cloud
involved. Between B1, B2 (Dense 3 layers), and C1,C2 (Image targeted SoC designs with existing cloud platforms.
classifier) designs, the LUTs, total power, and accelerator
power (%) is high for B1,B2 SoCs, however the BRAM The rated power of typical cloud hardware: Intel Xeon
requirements are larger for C1,C2 SoCs, considering the 784 Single-core CPU running at 2.2 GHz, Cloud Tensor-
of input features to be accommodated in C1, C2 designs, when Processing-Unit (TPU), and Tesla T4 GPU were compared
 TABLE III
S UMMARY OF SPEED ACCELERATION , AND POWER REDUCTION FOR THE
PROPOSED S O C DESIGNS WHEN COMPARED WITH EXISTING C LOUD
PLATFORMS . D1 S O C CONSUMES MAXIMUM POWER WHEN COMPARED
WITH OTHER DESIGNED S O C S . A1, B1, AND C1 S O C DESIGN SHOWCASES
MAXIMUM DELAY FROM THE PAIR OF S O C S INVESTIGATED .
Existing Cloud Power reduction for D1 SoC
Average Accelerated speed for 3 individual
SoC designs with respect to other cloud platforms.
platforms design with respect to other
Dense 2 Dense 3
cloud platforms.
(A) (B)
GPU 5.25X 39.23X 16.33X
TPU 15X 48.76X 26.67X
CPU 7.13X 72.72X 70X
with the proposed Cloud targeted SoC designs of 16 con-
figurations, also shown in the Figure 6. The Cloud targeted
SoC platform exhibits extremely low power requirements
when compared with other cloud platforms. The proposed D1
SoC configured with maximum Cache allocation consumes
maximum power consumption among the proposed 16 SoC
configurations. However when compared with Tesla T4 GPU
unit, it shows 5.25X less power consumption than Tesla T4
unit, 15X less than TPU unit, and 7.13X less than CPU.
The proposed SoC architecture is a power-efficient design
when compared with the available cloud resources. For reliable
comparison, the accelerated performance was investigated for
SoC design running individual accelerators with that of single
neural network runs on the corresponding TPU, GPU, and
CPU engines. In terms of latency, the cloud targeted SoC
design showcased accelerated speed ranging from 5.4X to
72.72X with respect to CPU run, 3.8X to 39.23X with respect
to GPU run, and 4X to 48.76X with respect to TPU run for the
individual of the selected neural networks. The average latency
of SoC designs with minimum and maximum cache enabled
configurations were considered for comparisons. A summary
of the power reduction and accelerated output is shown in the
Table III. On an average the SoC design showed throughput
improvement of 49.37X, 26.47X, and 19.78X when compared
with CPU, TPU, and GPU units respectively.
IV. C ONCLUSION
16 SoC designs including three different Neural Network
hardware accelerators individually, and all combined were
evaluated with respect to total power consumed, LUTs uti-
lized, BRAMs required, accelerator power conceded, and
throughput offered. Three neural network accelerators were
picked to demonstrate proof-of-concept in extracting vital
categorical information from the supplied health related data
and demonstrate power and performance efficiency of the
designed SoC. The aim was to demonstrate the advantage
of SoC designs targeted for cloud based healthcare services.
The paper showcases one such SoC design methodology using
a freely available ESP framework and open-source IP cores.
49.37X, 26.47X, and 19.78X when compared with CPU, TPU,
and GPU
Throughput enhancement of 49.37X, 19.78X, and 26.47X
were reported for individual hardware accelerator designed
SoCs, and power reduction of 7.13X, 5.25X, and 15X show-
cases huge advantage with respect to its corresponding individ-
ual neural network inference on CPU, GPU, and TPU respec-
tively. The paper presents SoC design as a step, showcasing the
ability to build many more customized power and throughput
efficient SoC designs. The healthcare services through Cloud
based SoC platform with power and performance efficient
design is likely to aid in accelerating the vital health updates
Image Classifier of the individual’s.
(C)
3.80X R EFERENCES
4X
5.40X [1] Q. Jia, S. Chen, Z. Yan, and Y. Li, “Optimal incentive strategy in
cloud-edge integrated demand response framework for residential air
conditioning loads,” IEEE Transactions on Cloud Computing, vol. 10,
no. 1, pp. 31–42, 2022.
[2] S. Mireslami, L. Rakai, M. Wang, and B. H. Far, “Dynamic cloud
resource allocation considering demand uncertainty,” IEEE Transactions
on Cloud Computing, vol. 9, no. 3, pp. 981–994, 2021.
[3] J. Kumar, A. Malik, S. K. Dhurandher, and P. Nicopolitidis, “Demand-
based computation offloading framework for mobile devices,” IEEE
Systems Journal, vol. 12, no. 4, pp. 3693–3702, 2018.
[4] H.-M. Chung, S. Maharjan, Y. Zhang, F. Eliassen, and K. Strunz,
“Optimal energy trading with demand responses in cloud computing
enabled virtual power plant in smart grids,” IEEE Transactions on Cloud
Computing, vol. 10, no. 1, pp. 17–30, 2022.
[5] J. Li, Y. Zhu, J. Yu, C. Long, G. Xue, and S. Qian, “Online auction for
iaas clouds: Towards elastic user demands and weighted heterogeneous
vms,” IEEE Transactions on Parallel and Distributed Systems, vol. 29,
no. 9, pp. 2075–2089, 2018.
[6] L. Ruan, Y. Yan, S. Guo, F. Wen, and X. Qiu, “Priority-based residential
energy management with collaborative edge and cloud computing,”
IEEE Transactions on Industrial Informatics, vol. 16, no. 3, pp. 1848–
1857, 2020.
[7] X. Chen, W. Li, S. Lu, Z. Zhou, and X. Fu, “Efficient resource allocation
for on-demand mobile-edge cloud computing,” IEEE Transactions on
Vehicular Technology, vol. 67, no. 9, pp. 8769–8780, 2018.
[8] S. Kardani-Moghaddam, R. Buyya, and K. Ramamohanarao, “Adrl:
A hybrid anomaly-aware deep reinforcement learning-based resource
scaling in clouds,” IEEE Transactions on Parallel and Distributed
Systems, vol. 32, no. 3, pp. 514–526, 2021.
[9] R. Ranchal, P. Bastide, X. Wang, A. Gkoulalas-Divanis, M. Mehra,
S. Bakthavachalam, H. Lei, and A. Mohindra, “Disrupting healthcare
silos: Addressing data volume, velocity and variety with a cloud-native
healthcare data ingestion service,” IEEE Journal of Biomedical and
Health Informatics, vol. 24, no. 11, pp. 3182–3188, 2020.
[10] Y. Motai, E. Henderson, N. A. Siddique, and H. Yoshida, “Cloud
colonography: Distributed medical testbed over cloud,” IEEE Transac-
tions on Cloud Computing, vol. 8, no. 2, pp. 495–507, 2020.
[11] L.-p. Jin and J. Dong, “Intelligent health vessel abc-de: An electro-
cardiogram cloud computing service,” IEEE Transactions on Cloud
Computing, vol. 8, no. 3, pp. 861–874, 2020.
[12] M. Akter, A. Gani, M. O. Rahman, M. M. Hassan, A. Almogren, and
S. Ahmad, “Performance analysis of personal cloud storage services for
mobile multimedia health record management,” IEEE Access, vol. 6, pp.
52 625–52 638, 2018.
[13] A. P. Deb Nath, K. Raj, S. Bhunia, and S. Ray, “Soccom: Automated
synthesis of system-on-chip architectures,” IEEE Transactions on Very
Large Scale Integration (VLSI) Systems, vol. 30, no. 4, pp. 449–462,
2022.
[14] M. A. Kinsy, M. Pellauer, and S. Devadas, “Heracles: A tool for
fast rtl-based design space exploration of multicore processors,” in
Proceedings of the ACM/SIGDA International Symposium on Field
Programmable Gate Arrays, ser. FPGA ’13. New York, NY, USA:
Association for Computing Machinery, 2013, p. 125–134. [Online].
Available: https://doi.org/10.1145/2435264.2435287
[15] K. Asanović, R. Avizienis, J. Bachrach, S. Beamer, D. Biancolin,
C. Celio, H. Cook, D. Dabbelt, J. Hauser, A. Izraelevitz, S. Karandikar,
B. Keller, D. Kim, J. Koenig, Y. Lee, E. Love, M. Maas,
A. Magyar, H. Mao, M. Moreto, A. Ou, D. A. Patterson,
B. Richards, C. Schmidt, S. Twigg, H. Vo, and A. Waterman, “The
rocket chip generator,” EECS Department, University of California,
Berkeley, Tech. Rep. UCB/EECS-2016-17, Apr 2016. [Online].
Available: http://www2.eecs.berkeley.edu/Pubs/TechRpts/2016/EECS-
2016-17.html
[16] S. Bandara, A. Ehret, D. Kava, and M. Kinsy, “Brisc-v: An open-source
architecture design space exploration toolbox,” in Proceedings of the
2019 ACM/SIGDA International Symposium on Field-Programmable
Gate Arrays, ser. FPGA ’19. New York, NY, USA: Association
for Computing Machinery, 2019, p. 306. [Online]. Available:
https://doi.org/10.1145/3289602.3293991
[17] F. Fatollahi-Fard, D. Donofrio, G. Michelogiannakis, and J. Shalf,
“Opensoc fabric: On-chip network generator,” in 2016 IEEE Interna-
tional Symposium on Performance Analysis of Systems and Software
(ISPASS), 2016, pp. 194–203.
[18] S. Wallentowitz, A. Lankes, A. Zaib, T. Wild, and A. Herkersdorf,
“A framework for open tiled manycore system-on-chip,” in 22nd In-
ternational Conference on Field Programmable Logic and Applications
(FPL), 2012, pp. 535–538.
[19] J. Leng, T. Hetherington, A. ElTantawy, S. Gilani, N. S. Kim, T. M.
Aamodt, and V. J. Reddi, “Gpuwattch: Enabling energy optimizations
in gpgpus,” in Proceedings of the 40th Annual International Symposium
on Computer Architecture, ser. ISCA ’13. New York, NY, USA:
Association for Computing Machinery, 2013, p. 487–498. [Online].
Available: https://doi.org/10.1145/2485922.2485964
[20] N. Binkert, B. Beckmann, G. Black, S. K. Reinhardt, A. Saidi, A. Basu,
J. Hestness, D. R. Hower, T. Krishna, S. Sardashti, R. Sen, K. Sewell,
M. Shoaib, N. Vaish, M. D. Hill, and D. A. Wood, “The gem5
simulator,” SIGARCH Comput. Archit. News, vol. 39, no. 2, p. 1–7, aug
2011. [Online]. Available: https://doi.org/10.1145/2024716.2024718
[21] N. Agarwal, T. Krishna, L.-S. Peh, and N. K. Jha, “Garnet: A detailed
on-chip network model inside a full-system simulator,” in 2009 IEEE
International Symposium on Performance Analysis of Systems and
Software, 2009, pp. 33–42.
[22] S. Li, J. H. Ahn, R. D. Strong, J. B. Brockman, D. M. Tullsen,
and N. P. Jouppi, “Mcpat: An integrated power, area, and timing
modeling framework for multicore and manycore architectures,” in
Proceedings of the 42nd Annual IEEE/ACM International Symposium
on Microarchitecture, ser. MICRO 42. New York, NY, USA:
Association for Computing Machinery, 2009, p. 469–480. [Online].
Available: https://doi.org/10.1145/1669112.1669172
[23] P. Mantovani, D. Giri, G. Di Guglielmo, L. Piccolboni, J. Zuckerman,
E. G. Cota, M. Petracca, C. Pilato, and L. P. Carloni, “Agile soc devel-
opment with open esp : Invited paper,” in 2020 IEEE/ACM International
Conference On Computer Aided Design (ICCAD), 2020, pp. 1–9.
[24] “Esp the open source soc platform,” https://esp.cs.columbia.edu, ac-
cessed: 10, January, 2022.
[25] “Chipyard documentation,” https://chipyard.readthedocs.io/en/stable/,
accessed: 10, January, 2022.
[26] B. S. Ajay and M. Rao, “Binary neural network based real time emotion
detection on an edge computing device to detect passenger anomaly,”
in 2021 34th International Conference on VLSI Design and 2021 20th
International Conference on Embedded Systems (VLSID), 2021, pp.
175–180.
[27] M. Blott, N. J. Fraser, G. Gambardella, L. Halder, J. Kath, Z. Neveu,
Y. Umuroglu, A. Vasilciuc, M. Leeser, and L. Doyle, “Evaluation of op-
timized cnns on heterogeneous accelerators using a novel benchmarking
approach,” IEEE Transactions on Computers, vol. 70, no. 10, pp. 1654–
1669, 2021.
[28] N. Kim, D. Shin, W. Choi, G. Kim, and J. Park, “Exploiting retraining-
based mixed-precision quantization for low-cost dnn accelerator design,”
IEEE Transactions on Neural Networks and Learning Systems, vol. 32,
no. 7, pp. 2925–2938, 2021.
[29] K. Nakata, A. Maki, D. Miyashita, F. Tachibana, T. Suzuki, and
J. Deguchi, “Live demonstration: Fpga-based cnn accelerator with filter-
wise-optimized bit precision,” in 2019 IEEE International Symposium
on Circuits and Systems (ISCAS), 2019, pp. 1–1.
[30] N. D. Truong, A. D. Nguyen, L. Kuhlmann, M. R. Bonyadi, J. Yang,
S. Ippolito, and O. Kavehei, “Integer convolutional neural network for
seizure detection,” IEEE Journal on Emerging and Selected Topics in
Circuits and Systems, vol. 8, no. 4, pp. 849–857, 2018.
[31] “Stage c prostate cancer,” https://vincentarelbundock.github.io/Rdatasets
/doc/rpart/stagec.html, accessed: 26, February, 2022.
[32] “Data from the european society for blood and marrow transplantation
(ebmt),” https://vincentarelbundock.github.io/Rdatasets
/doc/mstate/ebmt1.html, accessed: 27, February, 2022.
[33] J. Yang, R. Shi, and B. Ni, “Medmnist classification decathlon: A
lightweight automl benchmark for medical image analysis,” in IEEE
18th International Symposium on Biomedical Imaging (ISBI), 2021, pp.
191–195.
[34] “Ariane processor,” https://github.com/lowRISC/ariane, accessed: 30,
January, 2022.
[35] “Leon3 processor,” https://www.gaisler.com/doc/leon3 product sheet.pdf,
accessed: 20, January, 2022.