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Active neutral-point-clamped (ANPC) three-level converter for high-power

applications with optimized PWM strategy

Conference Paper · November 2020

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 PCIM Asia 2020, 16 – 18 November 2020, Shanghai, China
Active neutral-point-clamped (ANPC) three-level converter for
high-power applications with optimized PWM strategy
Heng Wang, Xin Ma, Huibo Sun
Infineon Integrated Circuit (Beijing) Co., Ltd., Beijing, China, heng.wang@infineon.com
Abstract
This paper introduces a three-level solution for
high-power applications, and compares the
differences between the three-level topology
neutral-point diode clamp (NPC1) and the active
neutral-point clamp (ANPC). It then summarizes
three ways to optimize the PWM control method by
taking advantage of the ANPC's new features.
Several PWM algorithms are analyzed in
simulation, and compared with regard to
commutation loop, power losses, and efficiency. It
is very important to balance the resulting losses of
the switches by an optimized switching scheme, as
this limits the output capability when the maximum
junction temperature is reached. From the
comparison result, the optimal PWM algorithm can
be selected to improve system performance based
on the working conditions.
1. Introduction
1.1. The state-of-the-art NPC topology
Customers are striving for higher power-rating
solutions in some applications due to their lower
costs per watt and better levelized cost of energy
(LCOE). These applications include offshore
windmill converters and solar central inverters.
The current power rating of windmills is 6~8 MW.
It was announced that even 12 MW are planned to
enter series production in the near future. The
general 690 V AC operating voltage is too low to
transmit such a high-power rating. Therefore, a
1140 V AC system is being proposed for next-
generation windmills to improve cost
performance[1]~[2]. In photovoltaic (PV) power
generation, the 1500 V DC system has replaced
the 1000 V DC system as the mainstream design
in many countries. The power rating of solar
central inverters is up to 3~4 MW under forced air
cooling[3]-[4]. Thus, the three-level converters could
be used in new designs for both the applications
mentioned above.
ISBN 978-3-8007-5387-1
The half-bridge topology, as the most flexible
power module topology, covers the most popular
two-level applications, combined with a low
inductive commutation path at the same time[4].
When a half-bridge module is used in a three-level
converter, there are two different methods for
designing the system. One is a conventional NPC1
solution, which deactivates two IGBTs, and the
other solution is to use all six switches to operate
in a similar way as the ANPC solution, shown in
Figure1.
Fig 1. Two types of topology with the neutral-
point-clamped, three-level solution composed of
three standard half-bridge modules
1.2. New features of ANPC topology
NPC1 topology only has two current paths when
output is in the “0” state. Its inner switch is strictly
limited by the switching sequence, which requires
earlier switch-on than the outer switch, and later
switch-off than the outer switch. Otherwise it would
have to support the entire DC link voltage, and
would thus be destroyed. In comparison, ANPC
topology can provide four current paths when
output is in the “0” state, and the new switching
sequence is available for the inner switch as well,
shown in Fig. 2. Therefore, ANPC is more flexible
with regard to switching control, and can improve
the performance compared to NPC1[5]~[6].
There are several new modulation methods for
ANPC in the control algorithm. The optimization
30 © VDE VERLAG GMBH · Berlin · Offenbach
 PCIM Asia 2020, 16 – 18 November 2020, Shanghai, China

on the voltage spike of IGBT chips turning off

under higher current.

Classical NPC1-PWM0
A major drawback of the NPC1 typology is that it
has a short commutation loop and a long
commutation loop, which are activated as a
function of the power factor. The stray inductance
of the long loop is 2~3 times higher than for the
short one, as shown in Fig 3. Such high stray
inductance will increase the electrical stress, e.g
NPC1 ANPC
overvoltage when turning off, high peak power in
T1T2 T1T2 reverse recovery, and even snap-off in low-current
+1
D2D1 D2D1 and low temperature. It can lead to failure in some
T6D3 (New) cases.
D5T2 D5T2
0 i>0 i<0
T3D6 T3D6 T1

D2T5 (New) T2

T3T4 T3T4 T3
-1
D4D3 D4D3 T4

Fig 2. Conduction paths of the 3-level solution T5

when output is in “0” voltage state T6

targets can be classified according to the following
three purposes:
• The first aim is to improve the commutation loop
and obtain the minimum parasitic inductance. This
helps to reduce the voltage spike or suppress
switch oscillation from diode or IGBT.
• The second aim is to reduce the losses of the
whole system in order to increase efficiency.
• The third aim is to balance the power loss among
switches to increase output power.
2. The PWM method of ANPC
a) Commutation
a) Commutationloop
loop of NPC1b) Classical NPC1-PWM0
b) PWM of NPC1
Fig 3. The commutation loop of NPC1 topology and
its switching PWM in positive output “V>0”
ANPC-PWM1
Using ANPC can solve the above-mentioned
problem easily by adjusting only the switching
sequence, in which case all switching events stay
within a small loop, as shown in Fig. 4. Such a
PWM modulation method is called ANPC-PWM1
in this paper. The advantage of this method is that
it reduces the stray inductance from a long
commutation loop to a short commutation loop [7].

2.1. Method for improving the commutation

loop T1

T2
The low parasitic inductance of the commutation
T3
loop is very important for a power device, which
has a big impact on the switching performance of T4
power semiconductors. With respect to T5
inductance, the most dominating parts of the
T6
commutation loop are the housing of the power
device, the busbars and the capacitors. A good a) Commutation loop b) ANPC-PWM1
commutation loop has low stray inductance. It is
helpful to eliminate the oscillation of diode chips in Fig 4. The commutation loop of ANPC topology and its
reverse recovery under smaller current, as well as switching PWM1 in positive output “V>0”

ISBN 978-3-8007-5387-1 31 © VDE VERLAG GMBH · Berlin · Offenbach

 PCIM Asia 2020, 16 – 18 November 2020, Shanghai, China
ANPC-PWM2
Another solution is to let T1/T5 and T6/T4 work in
long conduction periods along with the phase
voltage output, while T2/T3 work in high
frequency as a quasi-two-level converter. A small
snubber capacitor can be added for T2 and T3.
The voltage across this device is always one-half
the DC-link voltage. The switching commutation
loop is reduced in the stray inductance as well, as
depicted in Figure 5.
T1
T2
T3
T4
T5
T6
a) Commutation loop b) ANPC-PWM2
Fig 5. The commutation loop of ANPC topology
and its switching PWM2 in positive output “V>0”
As T1/T4/T5/T6 are always switched according to
the basic frequency, the conduction losses
dominate for these switches. An IGBT module
with low VCE(sat) can be used to minimize on-state
loss, and increase the overall efficiency of the
system.
A benchmark test was accomplished with the latest
1700 V/1800 A IGBT module to verify the switching
behavior under different system stray inductance.
The stray inductance of the long commutation loop
is around 81 nH, and the short one is only 30 nH.
Both have been tested at 180 A (10% rated
current) and 1800 A (100% rated current) with
Turn-on Turn-on
Turn-off
Turn-off
Fig 6. The switching waveform with large and small
stray inductance
ISBN 978-3-8007-5387-1
rated DC voltage, at room temperature. The
experiment’s results are shown in Figure 6.
According to these results, it can be highlighted
that the low system stray of 30 nH inductance
allows much smoother reverse recovery behavior
for the diode and no oscillation behavior can be
observed. Accordingly, the low system stray
inductance enables the reduction of the peak
voltage from 1472 V to 1248 V during the IGBT
turn-off.
On the other hand, the short commutation loop
allows the IGBTs to switch faster, and reduce the
switching losses. The peak power of the diode is
also reduced during reverse recovery in case of
the same current change rates.
2.2. The method for total loss reduction
The major part of the power losses in converters
come from the semiconductors. Depending on the
operation conditions(e.g. the DC-link voltage,
modulation index, load current, and switching
frequency), the ratio of the conduction losses and
switching losses can vary. The main parameters
effecting the losses in a semiconductor module are
IGBT-related parameters (e.g. Tvj, Ls, Rg, Vge, etc.).
Switching losses can be reduced if the IGBT
switches faster, for example, by adopting a small
gate resistor or a low operating junction
temperature. For conduction losses, the Vge is
difficult to increase due to the higher short-circuit
current in case of a failure. Reducing the Tvj also
depends on other system conditions.
Nevertheless, the above-mentioned hardware
optimization solutions cannot reduce the losses
easily. The more adequate solution would be to
modify the software control for these three-level
topologies.
ANPC-PWM1-00 and ANPC-PWM2-00
The conduction losses can be reduced by
implementing parallel current paths during the
output “0” state in ANPC topology. This method
generates a new auxiliary “0” state signal named
“0+’ ” and “0-‘ ”, which have a small delay time in
turn-on (td) and a small advance time (tad) prior to
turn-off. The “td” and “tad” are necessary to avoid
destroying the existing commutation loop, and to
ensure the auxiliary switches are operating in zero-
voltage switching (ZVS) mode without additional
switching losses. Thus, conduction losses are
32 © VDE VERLAG GMBH · Berlin · Offenbach
 PCIM Asia 2020, 16 – 18 November 2020, Shanghai, China

reduced successfully by paralleling current

paths.[8] The theory is depicted in Figure 8. ANPC-PWM-DF
A simple way is to use the double-frequency (DF)
ANPC control with two different carrier waves
phase-shifted by 180° to generate the pulse. As
there are two individual on-and-off switchings from
0+ 0-

0+’ 0-’ T1
td tad
T2

Fig 7. The theory for using paralleling conduction T3

paths in “0” state
T4

T5

T6
a) Modulation signals b) ANPC-PWM-DF
Fig 9. Double-frequency ANPC control

the outer and inner switch during each switching

a) ANPC-PWM1-00 b) ANPC-PWM2-00
Fig 8. The switching PWM with double current paths
in “0” state generated from PWM1 and PWM2
respectively
As we know, the duty of “0” state in PWM width is
defined by the modulation index (m). Its flowing
current RMS value is decided by the power factor
(cosφ), with the optimization results being strongly
dependent on m and cosφ. There may only be a
slight improvement for converters with a high
modulation index (m≈1) and a high power factor
(cosφ ≈1), which is very common in voltage source
period, the switching frequency is reduced
approximately to half value [11].
There are equal switching losses between inner
switches and outer switches in the double
frequency strategy, and similar conduction losses
if the modulation index is close to one. Therefore,
very similar losses for outer and inner switches can
be achieved with DF ANPC control.
ANPC-PWM-Hybrid
The second possibility for achieving balanced
losses is to use the hybrid PWM strategy, which is
combined from existing PWM strategies with time
PWM1 PWM2 PWM1 PWM2 PWM1

inverters. Nevertheless, it will considerably T1

improve certain applications with a lower power T2
factor or a lower modulation index, for example,
T3
high reactive power demand on the grid-side
converter or in low-voltage ride through (LVRT) for T4

a windmill. T5

T6

2.3 The method for balancing power losses
The NPC1 topology has a clear disadvantage in
power loss distribution. The outer switch takes
most of the loss both in the rectifier mode and
inverter mode. ANPC topology has the chance to
solve this problem by PWM optimization to
increase output power [9]-[10].
a) Modulation signals b) ANPC-PWM-Hybrid
Fig 10. Hybrid PWM strategy for ANPC
sharing. For example, the ANPC-PWM1 and
ANPC-PWM2 can be used to generate a new
PWM strategy, which is called the ANPC-PWM-
hybrid.

ISBN 978-3-8007-5387-1 33 © VDE VERLAG GMBH · Berlin · Offenbach

 PCIM Asia 2020, 16 – 18 November 2020, Shanghai, China

It is recommended to involve load-current

detection into the PWM control loop to take full
advantage of each PWM strategy. For example,
ANPC-PWM1 is preferred for low-current and
high-current areas as its smallest commutation
loop, while ANPC-PWM2 can be used for the
middle current area to share losses. The share of
PWM1 and PWM2 can be adjusted freely to
achieve balanced power losses between the outer
and inner switch.

ANPC-PWM-ALD
The third possibility is an adjustable loss-
distribution modulation, called ANPC-PWM-ALD
[12]
. It is also a hybrid PWM strategy combining both
the classical and the PWM-DF strategies. PWM- Heatsink

ALD is generated by two reference signals with the

same phase angle and frequency, but different
amplitudes. It is divided into “stress-in” and “stress- Fig 11. Target application and a prototype
out” mode, which means either the inner switch or concept in a power stack design
the outer switch generates the switching losses.
two configurations and seven PWM methods to
Essentially, the “stress-out” mode is equal to that
check the differences, as illustrated in Table I.
of the ANPC-PWM1 and the “stress-in” mode is
Configuration A selects three 1800 A/1700 V IGBT
equal to that of ANPC-PWM2 in commutation loop,
half-bridge modules, and deactivates the IGBT of
with only a slight difference in the switching
T5 and T6 for an NPC1 three-level converter.
sequences of the zero state. Based on this, the
Configuration B selects the same IGBT module
results are similar to ANPC-PWM-Hybrid, but are
and uses the six PWM methods introduced. Thus,
not compared in this paper.
there are seven conditions for comparison. The
Each of the above-mentioned PWM modulations summary of all features of the PWM methods are
has different features in switching behavior as well shown in Table I.
as in loss distribution and efficiency. In order to
quantify these features, simulations are carried out Table I. Summary of PWM methods
using PLECS to best describe the differences. The Commutation Paralleling Loss
comparison results will be described in in the next loop paths balancing
chapter. Classical- Uncertain No No
NPC1-PWM0
ANPC-PWM1 Short No No
3. Prototype and simulation ANPC-PWM2 Short 1) No No
ANPC-PWM1- Short Yes No
00
3.1 Prototype designs
ANPC-PWM2- Short Yes No
00
The application is based on a direct drive offshore ANPC-PWM-DF Uncertain No Yes
wind power converter with a 1140 V AC grid. The ANPC-PWM- Uncertain No Yes
Hybrid
target power rating is a three-megawatt power
1) Add a snubber capacitor for T2&T3
stack, which can be extended to a 12 MW wind
turbine application by the paralleling of further
stacks. Detailed application conditions are shown ANPC-PWM1 and ANPC-PWM2 are aimed to
in Fig. 11. optimize the commutation loop and enlarge the
safe operating area by improving the switching
A prototype is designed to verify the switching and performance with a smaller stray inductance.
thermal performance with the latest IGBT module ANPC-PWM1-00 and ANPC-PWM2-00 contain
FF1800R17IP5. The simulation models involve two parallel current paths of the zero-voltage state

ISBN 978-3-8007-5387-1 34 © VDE VERLAG GMBH · Berlin · Offenbach

 PCIM Asia 2020, 16 – 18 November 2020, Shanghai, China
to reduce the conduction losses, which are
strongly related to the modulation index and power
factor. ANPC-PWM-DF and ANPC-PWM-Hybrid
are used to balance the loss distribution among
switches. Also the maximum junction temperature
and output power rating are improved.
3.2 The power loss distribution and
efficiency
The simulation is done for 3MW/1140V ANPC
converter in PLECS, which generates the power
losses for each device according to the condition
settings, including conduction losses, and turn-on
and turn-off losses. The losses generated in the
lead resistance of the package are also considered
in the model for more accurate results of the total
losses.
On the rectifier side, the fundamental frequency is
10 Hz with a power factor of -0.9, and the switching
frequency is 1.5 kHz. The gate resistor Rgon is
selected at 1.5 Ω to reduce the diode commutation
losses during reverse recovery. In the inverter
mode, the grid frequency is 50/60 Hz with a power
factor of 1. The switching frequency is chosen to
be 2 kHz in order to reduce the resulting
harmonics. The gate resistor Rgon is selected at
0.56 Ω to reduce Eon, and Rgoff is the same as
before with 0.68 Ω. In the simulation, a constant
heat sink temperature is selected at 85℃, which is
typically one of the most critical conditions for liquid
cooling.
Fig 12. Power loss distribution of each switch in ANPC
with different PWM methods
ISBN 978-3-8007-5387-1
The simulation results are shown in Figure 12.
ANPC-PWM1 and ANPC-PWM2 are the simplest
methods to minimize the commutation loop from
NPC1 with similar total power losses. ANPC-
PWM1-00 has the lowest power losses both in
rectifier mode and inverter mode, and obtains a
clear loss reduction of approximately 5.6% in
rectifier mode. The two methods of loss balancing
have similar results in power losses, and gain a
more equivalent distribution between outer and
inner switches, which is very important to improve
the utilization of the chip area.
3.3 Junction temperatures
According to the results, the maximum junction
temperature is observed on the diode at the
generator side, and on the IGBT at the inverter
side respectively. However, the maximum junction
temperature has a wide range among different
PWM methods.
In the rectifier mode, the junction temperature of
D2/D3 rises 2~5 K with ANPC-PWM1 and ANPC-
PWM2 due to more power losses. ANPC-PWM1-
00 has the same maximum Tj with classical NPC1,
while D2/D3 rises approximately 8 K due to more
conduction losses during paralleling conduction
with ANPC-PWM2-00. The loss balancing
methods show the advantage in a maximum Tj
reduction of 5 K. The ANPC-PWM-hybrid is
preferred at a similar Tj for the two hottest
switches.
In the inverter mode, ANPC-PWM1, PWM2 and
PWM1-00 have nearly the same maximum Tj with
classical NPC1-PWM0. The slight increase in Tj for
ANPC-PWM2-00 can be explained by higher
conduction losses. Both ANPC-PWM-DF and
ANPC-PWM-Hybrid show a balanced distribution
of losses and similar junction temperature for IGBT
chips. Compared to NPC1, using the ANPC-PWM-
hybrid control causes a reduction of the maximum
Tj of around 18 K. This reduction is beneficial for
the design of the cooling system and enables
more output current.
According to the results, the temperature ripple
can reach up to 50 K even with an optimized ANPC
PWM strategy. This occurs due to the the low
fundamntal frequency in a direct-drive wind turbine.
State-of-the-art IGBT power modules use soft
soldering technology and aluminum bondwire for
the die attachement. These joining technologies
are not capable of handling such high temperature
swings with the expected lifetime of the systems.
35 © VDE VERLAG GMBH · Berlin · Offenbach
 PCIM Asia 2020, 16 – 18 November 2020, Shanghai, China

Tj [℃] 40 55 70 85 100 115 130 145 160 175 performance to simplify the commutation loop or to
Classical-NPC1-PWM0
balance losses. Additionally, it could maximize the
utilization of standard half-bridge IGBT modules.
ANPC-PWM1 T1/T4
D1/D4
Several PWM modulation methods are analyzed
ANPC-PWM2
T2/T3 for different purposes. The ANPC-PWM1 is the
ANPC-PWM1-00 D2/D3 simplest method for avoiding long commutation
ANPC-PWM2-00
T5/T6 loops, and the parallel conduction ANPC-PWM1-
D5/D6
ANPC-PWM-DF
00 is the best method for improving system
efficiency both in the rectifier mode or inverter
ANPC-PWM-Hybrid02
mode. The loss-balancing method of ANPC-PWM-
(a) Rectifier side Hybrid will reduce the maximum junction
temperature, or provide the degree of freedom to
Tj [℃] 40 55 70 85 100 115 130 145 160 175
increase the system output capability.
Classical-NPC1-PWM0
Nevertheless, the robustness of the power
ANPC-PWM1 T1/T4 modules against cycling loads is the most
ANPC-PWM2
D1/D4 important indicator for system lifetime design. The
T2/T3
D2/D3
latest .XT joint technology with copper bond-wire is
ANPC-PWM1-00
T5/T6 therefore the best solution for addressing this
ANPC-PWM2-00 D5/D6 challange.
ANPC-PWM-DF

ANPC-PWM-Hybrid12 References
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37 © VDE VERLAG GMBH · Berlin · Offenbach