Chipanalog-CA-IF4820HS C2846827

Machine Translated by Google
CA-IF4805/CA-IF4820/CA-IF4850
Shanghai Chuantu Microelectronics Co., Ltd. Preview
3.3V to 5V RS485/RS422 Transceiver with ±30kV ESD Protection
Devices in this family can extend the common-mode voltage range to ±15V, and the fault
1. Product Features
protection range is ±30V. These devices are therefore suitable for applications on long cables.
• Meets or Exceeds TIA/EIA-485A Standard • Data Rates: - CA- The CA-IF48xx family of devices is available in small SOIC8, MSOP, and DFN
IF4850: 50Mbps - CA-IF4820: 20Mbps - CA-IF4805: Low EMI
packages for space-constrained applications.
500Kbps • 3V to 5.5V Supply Voltage • With Current-Limited
The devices are specified to operate over the temperature range of –40°C to 125°C in a free-air
Driver and Thermal Shutdown Function • Bus I/O ESD
environment.
Protection: - Full-duplex: ±15kV HBM - Half-duplex: ±30kV
HBM • 1/8 unit load (supports up to 256 bus nodes) • Operating

Table 1 device information
temperature range: –40° C to 125°C • Common Mode Voltage
Range: ±15V • Fault Protected Range: ±30V • Low Operating Part Number Package Package Dimensions (Nominal)
Current: 960µA Max in Receive Mode • Standby Current:

CA-IF48xxxS SOIC8 3.9mm*4.9mm
<5µA • Small SOIC8 or MSOP Package
CA-IF48xxxM MSOP8 3mm*3mm
CA-IF48xxxD DFN8 3mm*3mm
CA-IF4805H Simplified Schematic
R R
2 7
REB
2. Application B
3 6
FROM A
• Motor drives • Factory
4
automation and control • Grid D D
infrastructure • Building automation
• HVAC systems • Video surveillance
• Process control • Wireless

CA-IF4820F Simplified Schematic
infrastructure
8
A
2
R R
7
B
3. Overview
6
FROM
The CA-IF48xx is a family of noise-immune RS-485/RS-422 full-duplex/half-duplex 3

D D 5
Y
transceivers designed for use in harsh industrial environments. The bus pins of these
devices withstand high levels of IEC electrical fast transients (EFT) and IEC electrostatic
discharge (ESD), eliminating the need for additional system-level protection components.
Copyright © 2019, Chipanalog Incorporated Shanghai

Chuantu Microelectronics Co., Ltd.
Preview Shanghai Chuantu Microelectronics Co., Ltd.
4. Order Guide
Table 2 Valid Ordering Part Numbers
model Full/half duplex rate (Mbps) encapsulation
CA-IF4805HS half duplex 0.5 SOIC8
CA-IF4805FS full duplex 0.5 SOIC8
CA-IF4820HS half duplex 20 SOIC8
CA-IF4820FS full duplex 20 SOIC8
CA-IF4850HS half duplex 50 SOIC8
CA-IF4850FS full duplex 50 SOIC8
CA-IF4805HM half duplex 0.5 MSOP8
CA-IF4805FM full duplex 0.5 MSOP8
CA-IF4820HM half duplex 20 MSOP8
CA-IF4820FM full duplex 20 MSOP8
CA-IF4850HM half duplex 50 MSOP8
CA-IF4850FM full duplex 50 MSOP8
CA-IF4805HD half duplex 0.5 DFN8
CA-IF4805FD full duplex 0.5 DFN8
CA-IF4820HD half duplex 20 DFN8
CA-IF4820FD full duplex 20 DFN8
CA-IF4850HD half duplex 50 DFN8
CA-IF4850FD full duplex 50 DFN8
2 Copyright © 2019, Chipanalog Incorporated Shanghai

Table of contents
1. Product features................................................ ..............1 7. Parameter measurement information................................... ........9
2. Application................................................ ....................1 8. Detailed description................................................ ..........15
3. Overview................................................ ....................1 8.1. Function Description................................................ ..............15 8.2. Device
4. Ordering guide................................................ ..............2 Functional Modes.....................................15 ...................15
5. Pin function description...................................... ..........4 9. Application information................................... ..........16
9.1. Typical applications................................................... ..........16

6. Product Specifications................................... ..........6
10. Packaging Information ................................................ ...17
6.1. Absolute Maximum Ratings1 ................................................ ...6
6.2. 10.1. SOIC8 Outline Dimensions................................... ...17

ESD Rating................................................ ..........6
6.3. 10.2. MSOP8 Dimensions................................................... 18 10.3. Dimensions of

Recommended Operating Conditions ................................................ ......6
6.4. DFN8................................................... ....19

Calorie Information ................................................ ..................6 Electrical
6.5. 11. Soldering Information................................... ...20

Characteristics..................................... ...................................7
6.6. Conversion Time Characteristics ................................................ ......8 12. IMPORTANT DISCLAIMER................................................ ...twenty one
Copyright © 2019, Chipanalog Incorporated Shanghai 3

5. Pin function description
RO 1 8 VCC RO 1 8 VCC RO 1 8 VCC
REB 27 B REB 27 B REB 27 B

C A-IF4805H S 3 C A-IF4805H D 3 C A-IF4805H M 3
FROM 6 A FROM 6 A FROM 6 A
OF 4 5 GND OF 4 5 GND OF 4 5 GND
REB 27 B REB 27 B REB 27 B

REB 2 7 B REB 27 B REB 2 7 B

Figure 1 CA-IF48xxHS/ CA-IF48xxHD// CA-IF48xxHM pin diagram
Table 5-1 CA-IF48xxHS/ CA-IF48xxHD// CA-IF48xxHM pin function description
Pin Name Pin Number Type describe
RO 1 Digital Output Receiver Bus Output Port 2 Digital Input Receiver Enable
REB Signal 3 Digital Input Driver Enable Signal 4 Digital Input Driver Bus Input
FROM Port Ground 6 Bus Input Driver/Receiver Bus Output/Input Port, A 7 Bus
OF Input Driver /Receiver bus output/input port, B power supply
GND 5
VCC 8

VCC 1 8 A VCC 1 8 A VCC 1 8 A
RO 2 7 B RO 2 7 B RO 27 B
C A-IF4805FS C A-IF4805FD C A-IF4805FM
OF 3 6 FROM
OF 3 6 FROM
OF 3 6 FROM
GND 4 5 Y GND 4 5 Y GND 4 5 Y
RO 2 7 B RO 2 7 B RO 2 7 B
C A-IF4820FS C A-IF4820FD 3 C A-IF4820FM 6
OF 3 6 FROM
OF 6 FROM
OF 3 FROM
RO 2 7 B RO 2 7 B RO 27 B
C A-IF4850FS C A-IF4850FD C A-IF4850FM
OF 3 6 FROM
OF 3 6 FROM
OF 3 6 FROM
Figure 2 CA-IF48xxFS/CA-IF48xxFD/CA-IF48xxFM pin diagram
Table 5-2 CA-IF48xxFS/CA-IF48xxFD/CA-IF48xxFM pin function description
Pin Name Pin No. Type Power Supply 2 Digital Output describe
VCC 1 Receiver Bus Output Port
RO 3 Digital Input Driver Bus Input Port Ground Ground 5 Bus Output Driver
OF Positive Output Port 6 Bus Output Driver Negative Output Port 7 Bus Input
GND 4 Receiver Negative Input Port 8 Bus Input Receiver
Y Positive Input Port
FROM
Copyright © 2019, Chipanalog Incorporated Shanghai Chuantu 5
Microelectronics Co., Ltd.

6. Product specifications
6.1. Absolute Maximum Ratings 1
min max unit
VCC Parameter Power Supply -0.3 7.0 IN
HE SAW Voltage Port Voltage A, B, Z, -30 30 IN
HE SAW Y Port Voltage DI, DE, REB Port -0.3 7.0 IN
HE SAW Voltage RO Junction Temperature -0.3 VCC+0.3 IN
TJ Storage Temperature Range 150 °C
TSTG -65 150 °C
Notes: 1.
Stresses equal to or exceeding the above absolute maximum ratings may cause permanent damage to the product. These are ratings only and should not be used to infer proper operation of the product under these or any other conditions beyond the specifications shown in the Operating
section of this specification. Long-term operation beyond the maximum ratings will affect the reliability of the product.
6.2. ESD Rating
parameter Numerical unit
Human Body Model (HBM), according to ANSI/ESDA/JEDEC JS 001, Full Duplex CA-IF48xxF Half ±15 kV
VESD electrostatic discharge
bus pin 1 Human Body Model (HBM), according to ANSI/ESDA/JEDEC Duplex CA-IF48xxH ±30 kV
JS-001, remaining pins 1 ±8 kV
Remarks: 1. JEDEC document JEP155 specifies that 500V HBM can be manufactured safely through standard ESD control process.
6.3. Recommended working conditions
parameter Min Typ Max Unit
VCC Analog Supply Voltage 3 5 5.5 IN
COME Bus Input Voltage Low -15 15 IN
WILL Input Threshold High Input 0 0.8 IN
HIV Threshold Differential Load 2 VCC IN
RL Resistance Data Rate: CA- 54 Ohm
1/tUI 1/ IF4805 Data Rate: CA-IF4820 Data 500 kbps
tUI 1/tUI Rate: CA-IF4850 Ambient 20 Mbps
Temperature Junction Temperature 50 Mbps
PER -40 125 °C
TJ -40 150 °C
6.4. Calorie Information
CA-IF48xxHS/FS CA- IF48xxHM/FD CA- IF48xxHM/FD

heat meter unit
SOIC8 MSOP8 DFN8
RÿJA IC junction-to-ambient thermal resistance tbd tbd tbd °C/W °C/
RÿJC(top) IC Junction-to-Case (Top) Thermal Resistance tbd tbd tbd W °C/W
RÿJB IC junction-to-board thermal resistance tbd tbd tbd °C/W
RÿJC(bottom) IC Junction-to-Case (Bottom) Thermal Resistance N/A N/A N/A
6 Copyright © 2019, Chipanalog Incorporated Shanghai Chuantu

6.5. Electrical characteristics of Shanghai Preview
Over normal operating temperature range (unless otherwise noted). All typical values are from -40°C to 125°C with a supply voltage of VCC = 5 V. Test
parameter Conditions Min Typ Max Unit
driver
RL =60 ÿ, -15 V ÿ Vtest ÿ 15 V (see Figure 24 Measurement of driver
differential output voltage under common mode load Figure 24)(1) 1.5 3.5 IN
|VOD| Differential output voltage RL =60 ÿ, -15 V ÿ Vtest ÿ 15 V VCC ÿ 5.5 V ,

4.5 V ÿ
2.1
(see Figure 24)
RL = 100ÿ (see Figure 25) 2 4 IN
RL = 54ÿ (see Figure 25) 1.5 3.7 IN
ÿ|VOD| Differential Output Voltage Change Common -200 200 mV
VOC Mode Output Voltage RL = 54ÿ (see Figure 25) 1 VCC/2 3 IN
ÿVOC(SS) common mode output voltage change short -200 200 mV
IOS circuit output current -7 V ÿ VO ÿ 12 V -250 250 mA
receiver
VI = 12V 75 125 uA
DE = 0 V, VCC = 0 V or 5 V
VI = -7V -100 -43 uA
II Bus input current
VI = 15V 91 125 uA
DE = 0 V, VCC = 0 V or 5V
VI = -15V -200 -97 uA
VTH+ positive input threshold voltage -100 -20 mV
VTH- negative input threshold voltage common mode range -200 -130 mV
VHYS input hysteresis voltage output high 30 mV
VOH level output low level IOH = -8 mA VCC-0.4 VCC-0.2 IN
VOL IOL = 8 mA 0.2 0.4 IN
IOZR output high-impedance current VO = 0 V or VCC,REB= VCC -1 1 uA
input logic
IIN Logic input current 3 V ÿ VCC ÿ 5.5 V, 0 V ÿ VIN ÿ VCC -6.2 6.2 uA
device
Driver and receiver enable, REB=0V, DE =

0.4 0.8 1.2 mA
VCC, no-load
driver enabled, receiver off,

0.8 1.2 mA
REB=VCC, DE = VCC, the no-load
ICC Working current (static)
driver is off, the receiver is enabled,
700 960 uA
REB=0V, DE = 0V, the no-load
driver is off, the receiver is off,

2.4 5 uA
REB=VCC, DE = 0V, D=open, no load
TSD thermal shutdown temperature 180 ÿ
(1) |VOD| ÿ 1.4 V when TA > 85 ÿ, Vtest < -7 V and VCC < 3.135 V; (2) Ensure that VTH
+ is at least one VHYS higher than VTH– under any specific conditions .

6.6. Conversion Time Characteristics
Over normal operating temperature range (unless otherwise noted). All typical values are from -40°C to 125°C with a supply voltage of VCC = 5 V.
parameter Test Condition Min Typ Max Unit
Driver: CA-IF4805HS/ CA-IF4805HM/ CA-IF4805HD Rise/Fall Time tr, tf tPHL,tPLH Propagation Delay
Pulse Width Distortion, |tPHL – tPLH| tSK(P) tPHZ,tPLZ Off Time 250 360 680 ns
RL = 54 ÿ, CL = 50 pF, see Figure 26 280 500 ns
10 ns
10 200 ns
RE = 0 V, see Figure 27, Figure 28 100 600 ns

tPZH, tPZL enable time
RE = VCC, see Figure 27, Figure 28 7.2 11 us
Receiver: CA-IF4805HS/ CA-IF4805HM/ CA-IF4805HD Rise/Fall Time tPHL, tPLH Propagation Delay Pulse
tr, tf Width Distortion, |tPHL – tPLH| 3.8 10 ns
CL = 15 pF, see Figure 29 23 110 ns
7 ns
tSK(P) tPHZ, tPLZ off time 7 20 ns
tPZH(1), tPZL(1), tPZH(2), tPZL(2), enable time DE = VCC, see Figure 30 8 20 ns
DE = 0 V, see Figure 31 7 14 us
Driver: CA-IF4820HS/ CA-IF4820HM/ CA-IF4820HD Rise/Fall Time tr, tf tPHL,tPLH Propagation
Delay Pulse Width Distortion, |tPHL – tPLH| tSK(P) tPHZ, tPLZOff off time 1 3 6 ns
RL = 54 ÿ, CL = 50 pF, see Figure 26 3 10 20 ns
3.5 ns
15 25 ns
RE = 0 V, see Figure 27, Figure 28 20 50 ns

tPZH, tPZL enable time
RE = VCC, see Figure 27, Figure 28 2.5 10 us
Receiver: CA-IF4820HS/ CA-IF4820HM/ CA-IF4820HD Rise/Fall Time tPHL, tPLH Propagation Delay Pulse
tr, tf Width Distortion, |tPHL – tPLH| 3.8 10 ns
tSK(P) 7 ns
tPHZ, tPLZ turn- off time tPZH(1), tPZL(1), 7 20 ns
tPZH(2), tPZL(2), enable time Driver: CA- DE = VCC, see Figure 30 8 20 ns
IF4820FS/ CA-IF4820FM/ CA-IF4820FD DE = 0 V, see Figure 31 7 14 us
rise/fall time tr, tf tPHL , tPLH Propagation Delay Pulse Width Distortion , | tPHL – tPLH
| , |tPHL – tPLH| tSK(P) 1 3 6 ns
RL = 54 ÿ, CL = 50 pF, see Figure 26 3 10 20 ns
3.5 ns
2 6 ns
3.5 ns

Shanghai Chuantu Microelectronics Co., Preview
Ltd. 6.7. Typical characteristics: all devices
ÿ 3 Driver Output Voltage vs Driver Output Current ÿ 4 Driver Output Differential Voltage vs Driver Output
Current
ÿ 5 Driver Output Voltage vs Driver Output Current ÿ 6 Driver Output Differential Voltage vs Driver Output
Current
Figure 7 VOD vs Temperature Figure 8 VOD vs Temperature

Typical Characteristics : ALL Devices (continued from previous page)
ÿ 9 Quiescent Current vs Temperature ÿ 10 Quiescent Current vs Temperature
ÿ 11 Driver Output Current vs Supply Voltage

Shanghai Chuantu Microelectronics Preview
Co., Ltd. 6.8. Typical characteristics: CA-IF4805HS, CA-IF4805FS, CA-IF4805HM, CA-IF4805FM, CA-IF4805HD, CA-IF4805FD
ÿ 12 Rise Time\Fall Time vs Temperature ÿ 13 Propagation Delay vs Temperature
ÿ 14 ICC SupplyCurrent vs Signaling Rate ÿ 15 Rise Time\Fall Time vs Temperature
ÿ 16 Propagation Delay vs Temperature ÿ 17 ICC SupplyCurrent vs Signaling Rate

6.9. Typical characteristics: CA-IF4820HS, CA-IF4820FS, CA-IF4820HM, CA-IF4820FM, CA-IF4820HD, CA-IF4820FD
ÿ 18 Rise Time\Fall Time vs Temperature ÿ 19 Propagation Delay vs Temperature
ÿ 20 ICC SupplyCurrent vs Signaling Rate ÿ 21 Rise Time\Fall Time vs Temperature
ÿ 22 Propagation Delay vs Temperature ÿ 23 ICC SupplyCurrent vs Signaling Rate

Shanghai Chuantu Microelectronics Co., Ltd. 7. Preview
Parameter measurement information
375ÿ
FROM
FROM
Vtest
OF
VOD RL
375ÿ
Figure 24 Measurement of driver differential output voltage under common mode load
FROM
FROM
RL/2
Y
OF
VOD AND
FROM
Y RL/2 VB
VOC
VOC
YOU (PP)
VOC (SS)
Figure 25 Measuring Driver Differential and Common Mode Outputs Using an RS-485 Load
FROM VCC
FROM WE N 50%
0V
OF
VOD CL tPHL
RL tPLH
90%
Input 54ÿ 50pF
2V
COME 50ÿ Y 50%
generator VOD
-2V
10%
tr tf
Figure 26 Measuring the rise and fall times and propagation delay of the driver differential output
Y
OF S1 Vo
VCC
FROM
FROM
WE N 50%
CL RL
Input 0V
110ÿ
COME 50pF
generator 50ÿ tPZH
tPHL
VOH
90%
VO 50%
tPHZ 0V
Figure 27 Measuring driver enable and disable times with active high output and pull-down load

Y RL
OF 110ÿ
S1
VO
CV
FROM FROM
CL
COME 50%
Input 0V
COME 50pF tPLZ
generator 50ÿ tPZL
tPLZ CV
VO
50% 10%
VOL
Figure 28 Measurement of driver enable and disable times with active low output and pull-up load
3V
VOD
50%
0V
OF A
tPHL
tPLH
Input VO D
RO 90%
VOH
COME
50ÿ
generator CL
RO
50%
1.5V B REB VOL

15pF 10%
0V
tr tf
Figure 29 Measurement of receiver output rise and fall times and propagation delay
CV
Y A
OF RO
S1 CV
COME
CL
50%
FROM FROM B 0V
REB 15pF
tPZH(1)
VOH
90% DI at VCC
RO 50% S1 to GND
Input tPHZ 0V
COME
tPZL(1)
generator 50ÿ
tPLZ
CV
RO DI at 0V
50% 10% S1 to VC C
VOL
Figure 30 Measuring Receiver Enable/Disable Time with Driver Enabled
CV
A
RO
CV
CL COME 50%
B 0V
REB 15pF
tPZH(2)
A at 1.5V B
VOH
at 0V
RO 50%
Input 0V S1 to GND
COME tPZL(2)
generator 50ÿ
VC CABat
at0V
1.5V
RO VOL S1 to
50%
VC C
Figure 31 Measuring Receiver Enable Time With Driver Disabled

Shanghai Chuantu Microelectronics Co., Ltd. 8. Preview
Detailed description
8.1. Function description
The CA-IF48xx device family integrates large hysteretic input thresholds to provide internal biasing for receiver input thresholds. During bus-idle or bus-short conditions, the receiver output maintains a logic-high level
without the need for external fail-safe biasing resistors. The device operates over a wide ambient temperature range of –40°C to 125°C.
8.2. Device Functional Modes When
the driver enable pin DE is logic high, the differential outputs Y and Z follow the logic state of the data input DI. A logic high at DI causes Y to go high and Z to go low. In this case, the differential output voltage
defined VOD = VY – VZ is positive. When DI is low, the output state is reversed: Z becomes high, Y becomes low, and VOD is negative.
When DE is low, both outputs become high-impedance. In this case, the logic state at DI is irrelevant. The DE pin has an internal pull-down resistor to ground, so the driver is disabled (high impedance) by default
when left open. The DI pin has an internal pull-up resistor to VCC, so by leaving it floating when the driver is enabled, output A goes high and B goes low.
Table 3 CA-IF48xx driver truth table
enter Enable output

Function
OF FROM Y FROM
H H H L Active Output High Active
L H L H Output Low Disables Driver
X L FROM FROM
Disables Driver (Default State)
X OPEN FROM FROM

Active Output High (Default State)
OPEN H H L
The receiver is enabled when the receiver enable pin REB is logic low. When the differential input voltage of VID = VA – VB is above the positive input threshold VTH+ , the receiver output RO goes high. When
VID is lower than the negative input threshold VTH-, the receiver output RO goes low. If VID is between VTH + and VTH , the output is undefined. When REB is logic high or floating, the receiver output is high impedance,
and the magnitude and polarity of VID do not matter. The internal biasing of the receiver input causes the output to go fail-safe high (bus idle state) when the transceiver is disconnected from the bus (open circuit), the bus
lines are shorted to each other (short circuit), or the bus is not being driven.
Table 4 CA-IF48xx receiver truth table
differential input enable output

Function
VID = VA – VB REB RO
VTH+ < VID L H Active output high level? Bus intermediate
VTH- < VID < VTH+ L state
VID < VTH- L L Active output low level
X H Z disable receiver
X OPEN Z Disable receiver (default state) H Fail-safe high output
L
Open-circuit bus
Short-circuit bus L H Fail-safe high level output
Idle (terminated) bus L H Fail-safe high level output

9. Application Information
The CA-IF48xx family consists of half-duplex and full-duplex RS-485 transceivers, typically used for asynchronous data transmission. For half-duplex devices, enable pins for the driver and receiver allow
configuration of different operating modes. Full-duplex implementation requires two signal pairs (four wires) to allow each node to transmit data on one pair of signal wires while receiving data on the other pair of signal
wires.
9.1. Typical applications
The RS-485 bus consists of multiple transceivers connected in parallel to the bus cable. In order to eliminate line reflection, the two terminals of the cable are each connected to a terminal resistor
RT, the value of this resistor matches the characteristic impedance ZO of the cable. This approach of parallel termination impedances typically results in higher data rates over longer cable lengths.
R R
R R
REB A A REB
twisted pair
FROM B
RT RT B FROM
POLCOR
D D
D D
B A B
A
R D R D
POLCOR POLCOR
R D R D
FROM FROM
REB REB
Figure 32 Typical RS-485 network structure using half-duplex transceivers

10. Packaging information of Shanghai Chuantu Preview
10.1. SOIC8 Dimensions

5.00
4.80 0.60 1.27
8 5
2.00
4.00 6.20 5.40
3.80 5.80
PIN I ID
1 4
TOP VIEW RECOMMENDED LAND PATTERN
0.70 1.75 0.50

1.25
0.50
1.80 0.25
1.35
0.25 0.80
0.10 8° 0.30
0.51
1.27BSC
0°
0.306
1.04REF
FRONT VIEW LEFT-SIDE VIEW

10.2. MSOP8 Dimensions

Shanghai Chuantu Microelectronics Preview
Co., Ltd. 10.3. Dimensions of DFN8

11. Welding Information
TP
TC-5
tP
Max. Ramp Up Rate=3 /s
TL
tL
Tsmax
Preheat Area
Temperature
Tsmin
ts
25
Time
Time 25 to Peak
Figure 11-1 Soldering temperature curve
Table 11- 1 Soldering temperature parameters
Profile Feature Pb-Free Assembly

Average ramp-up rate(217 ÿ to Peak) 3ÿ/second max
60-120 second
Time of Preheat temp(from 150 ÿ to 200 ÿ
Time to be maintained above 217 ÿ 60-150 second
Peak temperature 260 +5/-0 ÿ

30 second
Time within 5 ÿof actual peak temp
Ramp-down rate 6 ÿ/second max.
8 minutes max
Time from 25ÿ to peak temp

12. Important statement of Shanghai Chuantu Preview
The above information is for reference only to assist Chipanalog customers in design and development. Chipanalog reserves the right, without prior notice, to
The right to change the above information due to technological innovation is reserved.
All Chipanalog products are factory tested. It is the customer's responsibility to make their own evaluation and determine suitability for their specific application. Chipanalog's authorization of customers to use
the resources described is limited to the development of relevant applications for the Chipanalog products involved. In addition, the said resources shall not be reproduced or displayed, and Chipanalog shall not be
liable for any claims, compensations, costs, losses and liabilities arising from the use of the said resources.
Trademark
Information Chipanalog Inc.®, Chipanalog® are registered trademarks of Chipanalog.
http://www.chipanalog.com

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Machine Translated by Google

3.3V to 5V RS485/RS422 Transceiver with ±30kV ESD Protection

HBM • 1/8 unit load (supports up to 256 bus nodes) • Operating

Current: 960µA Max in Receive Mode • Standby Current:

CA-IF48xxxM MSOP8 3mm*3mm

CA-IF48xxxD DFN8 3mm*3mm

CA-IF4805H Simplified Schematic

infrastructure • Building automation

• HVAC systems • Video surveillance

• Process control • Wireless

The CA-IF48xx is a family of noise-immune RS-485/RS-422 full-duplex/half-duplex 3

Copyright © 2019, Chipanalog Incorporated Shanghai

Table 2 Valid Ordering Part Numbers

model Full/half duplex rate (Mbps) encapsulation

CA-IF4805HS half duplex 0.5 SOIC8

CA-IF4805FS full duplex 0.5 SOIC8

CA-IF4820HS half duplex 20 SOIC8

CA-IF4820FS full duplex 20 SOIC8

CA-IF4850HS half duplex 50 SOIC8

CA-IF4850FS full duplex 50 SOIC8

CA-IF4805HM half duplex 0.5 MSOP8

CA-IF4805FM full duplex 0.5 MSOP8

CA-IF4820HM half duplex 20 MSOP8

CA-IF4820FM full duplex 20 MSOP8

CA-IF4850HM half duplex 50 MSOP8

CA-IF4850FM full duplex 50 MSOP8

CA-IF4805HD half duplex 0.5 DFN8

CA-IF4805FD full duplex 0.5 DFN8

CA-IF4820HD half duplex 20 DFN8

CA-IF4820FD full duplex 20 DFN8

CA-IF4850HD half duplex 50 DFN8

CA-IF4850FD full duplex 50 DFN8

2 Copyright © 2019, Chipanalog Incorporated Shanghai

1. Product features................................................ ..............1 7. Parameter measurement information................................... ........9

2. Application................................................ ....................1 8. Detailed description................................................ ..........15

3. Overview................................................ ....................1 8.1. Function Description................................................ ..............15 8.2. Device

4. Ordering guide................................................ ..............2 Functional Modes.....................................15 ...................15

5. Pin function description...................................... ..........4 9. Application information................................... ..........16

9.1. Typical applications................................................... ..........16

6.2. 10.1. SOIC8 Outline Dimensions................................... ...17

6.3. 10.2. MSOP8 Dimensions................................................... 18 10.3. Dimensions of

6.4. DFN8................................................... ....19

6.5. 11. Soldering Information................................... ...20

Copyright © 2019, Chipanalog Incorporated Shanghai 3

Chuantu Microelectronics Co., Ltd.

5. Pin function description

RO 1 8 VCC RO 1 8 VCC RO 1 8 VCC

REB 27 B REB 27 B REB 27 B

FROM 6 A FROM 6 A FROM 6 A

OF 4 5 GND OF 4 5 GND OF 4 5 GND

RO 1 8 VCC RO 1 8 VCC RO 1 8 VCC

REB 27 B REB 27 B REB 27 B

OF 4 5 GND OF 4 5 GND OF 4 5 GND

RO 1 8 VCC RO 1 8 VCC RO 1 8 VCC

REB 2 7 B REB 27 B REB 2 7 B

OF 4 5 GND OF 4 5 GND OF 4 5 GND

Figure 1 CA-IF48xxHS/ CA-IF48xxHD// CA-IF48xxHM pin diagram

Table 5-1 CA-IF48xxHS/ CA-IF48xxHD// CA-IF48xxHM pin function description

Pin Name Pin Number Type describe

OF Input Driver /Receiver bus output/input port, B power supply

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VCC 1 8 A VCC 1 8 A VCC 1 8 A

GND 4 5 Y GND 4 5 Y GND 4 5 Y