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IPS13N03LA IPU13N03LA
OptiMOS®2 Power-Transistor
Product Summary
Features
V DS 25 V
• Ideal for high-frequency dc/dc converters
R DS(on),max 12.8 mΩ
1)
• Qualified according to JEDEC for target applications
ID 30 A
• N-channel, logic level
• Excellent gate charge x R DS(on) product (FOM)
T C=100 °C 30
I D=30 A, V DS=20 V,
Reverse diode dv /dt dv /dt di /dt =200 A/µs, 6 kV/µs
T j,max=175 °C
Thermal characteristics
Static characteristics
V DS=25 V, V GS=0 V,
Zero gate voltage drain current I DSS - 0.1 1 µA
T j=25 °C
V DS=25 V, V GS=0 V,
- 10 100
T j=125 °C
1)
J-STD20 and JESD22
2)
Current is limited by bondwire; with an R thJC=3.2 K/W the chip is able to carry 47 A.
3)
See figure 3
4)
T j,max=150 °C and duty cycle D <0.25 for V GS<-5 V
5)
Device on 40 mm x 40 mm x 1.5 mm epoxy PCB FR4 with 6 cm 2 (one layer, 70 µm thick) copper area for drain
connection. PCB is vertical in still air.
Dynamic characteristics
Q sw V GS=0 to 5 V
Switching charge - 3.3 4.7
V DS=0.1 V,
Gate charge total, sync. FET Q g(sync) - 5.5 7.3 nC
V GS=0 to 5 V
Reverse Diode
V GS=0 V, I F=30 A,
Diode forward voltage V SD - 0.95 1.2 V
T j=25 °C
V R=15 V, I F=I S,
Reverse recovery charge Q rr - - 10 nC
di F/dt =400 A/µs
6)
See figure 16 for gate charge parameter definition
50 40
40
30
30
P tot [W]
I D [A]
20
20
10
10
0 0
0 50 100 150 200 0 50 100 150 200
T C [°C] T C [°C]
1000 10
1 µs
limited by on-state
0.5
resistance
100 1
10 µs
0.2
Z thJC [K/W]
I D [A]
0.1
100 µs
DC 0.05
0.02
10 0.1
1 ms 0.01
10 ms single pulse
1 0.01 0 0 0 0 0 0 1
0.1 1 10 100
10-6 10-5 10-4 10-3 10-2 10-1 100
V DS [V] t p [s]
60 50
10 V
3V 4.1 V
3.5 V 3.8 V
3.2 V
4.5 V
50
40
40
30
R DS(on) [mΩ]
4.1 V
I D [A]
4.5 V
30
3.8 V 20
20
3.5 V
10 10 V
10 3.2 V
3V
2.8 V
0 0
0 1 2 3 0 10 20 30 40 50
V DS [V] I D [A]
60 50
40
40
30
g fs [S]
I D [A]
20
20
10
175 °C
25 °C
0 0
0 1 2 3 4 5 0 10 20 30 40 50 60
V GS [V] I D [A]
24 2.5
20
2
16 200 µA
98 %
R DS(on) [mΩ]
1.5
V GS(th) [V]
20 µA
12
typ
1
8
0.5
4
0 0
-60 -20 20 60 100 140 180 -60 -20 20 60 100 140 180
T j [°C] T j [°C]
104 10000
1000
25 °C
Ciss
103 1000
100
Coss
I F [A]
175 °C
25 °C, 98%
102 100
10
Crss
101 10
1
0 10 20 30 0.0 0.5 1.0 1.5 2.0
V DS [V] V SD [V]
100 12
15 V
10
100 °C 25 °C 5V 20 V
150 °C 8
V GS [V]
I AV [A]
10 6
1 0
1 10 100 1000 0 2 4 6 8 10 12 14
t AV [µs] Q gate [nC]
29
V GS
28
Qg
27
26
V BR(DSS) [V]
25
24
V g s(th)
23
22
Q g (th) Q sw Q gate
21
20 Q gs Q gd
-60 -20 20 60 100 140 180
T j [°C]
Package Outline
P-TO252-3-11: Outline
Footprint: Packaging:
Dimensions in mm
Package Outline
P-TO252-3-23: Outline
Footprint:
Package Outline
P-TO251-3-11: Outline
P-TO251-3-21: Outline
Published by
Infineon Technologies AG
Bereich Kommunikation
St.-Martin-Straße 53
D-81541 München
© Infineon Technologies AG 1999
All Rights Reserved.
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The information herein is given to describe certain components and shall not be considered as
warranted characteristics.
We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement,
regarding circuits, descriptions and charts stated herein.
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