VLSI Design: 2022-23

Lecture 13: Memory Design

By Dr. Sanjay Vidhyadharan

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 Semiconductor Memory Classification

Volatile Non-Volatile Non-Volatile

Read-Write Memory Read-Write Memory Read-Only Memory

Random Access Non-Random Access

EPROM
Mask-Programmed
E2PROM
Programmable (PROM)
FIFO FLASH
SRAM LIFO
DRAM Shift Register
CAM

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 Memory Timing: Definitions

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 Memory Architecture

Decoder reduces the number of select signals K = log2N

Problem: ASPECT RATIO or HEIGHT >> WIDTH

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 Array-Structured Memory Architecture

Better ASPECT RATIO

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 Hierarchical Memory Architecture

Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings
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 Hierarchical Memory Architecture

Column Column Column

Advantages:
1. Shorter wires within blocks
2. Block address activates only 1 block => power savings

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 6T SRAM

Write bit bit_b

word
➢ Drive one bitline high, the other low P1 P2
N2 N4
➢ Then turn on wordline
A A_b
➢ Bitlines overpower cell with new value
N1 N3
➢ Writability
➢Must overpower feedback inverter
A_b
➢N2 >> P1
1.5 A

Ex: A = 0, A_b = 1, bit_b

1.0
bit = 1, bit_b = 0
Force A_b low, then A rises high
0.5
word

0.0
0 100 200 300 400 500 600 700
time (ps)

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 6T SRAM

Read bit bit_b

word
➢ Precharge both bitlines high
P1 P2
➢ Then turn on wordline N2 N4
➢ One of the two bitlines will be pulled A A_b
down by the cell N1 N3
➢ Read stability
➢A must not flip A_b bit_b

➢N1 >> N2 1.5

1.0
bit
Ex: A = 0, A_b = 1 word

bit discharges, bit_b stays high 0.5

But A bumps up slightly A
0.0
0 100 200 300 400 500 600
time (ps)

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 6T SRAM

SRAM Sizing
High bitlines must not overpower inverters during reads
But low bitlines must write new value into cell

bit bit_b
word
weak
med med
A A_b
strong

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 6T SRAM

SRAM Sense Amplifier

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 3-Transistor DRAM Cell

No constraints on device ratios Reads are non-destructive

Value stored at node X when writing a “1” = VWWL-VTn

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 1-Transistor DRAM Cell

Write: CS is charged or discharged by asserting WL and BL.

Read: Charge redistribution takes places between bit line and storage capacitance

Voltage swing is small; typically around 250 mV

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 1-Transistor DRAM Cell

➢ 1T DRAM requires a sense amplifier for each bit line, due to charge redistribution
read-out

➢ DRAM memory cells are single-end in contrast to SRAM cells.

➢ The read-out of the 1T DRAM cell is destructive; read and refresh operations are
necessary for correct operation.

➢ Unlike 3T cell, 1T cell requires presence of an extra capacitance that must be

explicitly included in the design.

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 Read-Only Memory
Internal Logic 32 X 8 ROM

In General for 2k X n ROM

K x 2k Decoder and n OR gates
Each OR gate has 2k inputs
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 Programming the ROM
Address 3 = 10110010 is permanent storage using fuse link

X : means connection

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 Programming the ROM
1. Masking During Metallization

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 Programming the ROM
2. Fuse (PROM)

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 Programming the ROM
3. EPROM

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 Programming the ROM
3. EPROM

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 Programming the ROM

4. EEPROM

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 MOS OR ROM

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 MOS NOR ROM

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 MOS NAND ROM

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 Pre-charged MOS NOR ROM

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 Row Decoders

Example 8 bit Decoder

1. Implementation 8 Inverters + 256 NAND

2. Implementation 8 Inverters + 256 NOR

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 Row Decoders
Multi-stage implementation improves performance

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 Row Decoders

MOS NOR Row Decoder

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 Row Decoders

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 4-to-1 tree based column decoder

Number of devices drastically reduced. Delay increases quadratically with # of sections;

prohibitive for large decoders
Solution : Buffers
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 Flash Storage

• Most prominent solid state storage technology

– No other technology is available at scale
• NAND- and NOR- flash types available
– NOR-flash can be byte-addressed, expensive
– NAND-flash is page addressed, cheap
– Except in very special circumstances, all flash-storage we see are NAND-flash

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 Flash Storage
Flash memories store information in memory cells made from floating gate transistors.

NOR flash is faster to read than NAND flash, but it's also more expensive.
NAND has a higher memory capacity than NOR.
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 Flash Storage
NOR flash

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 Flash Storage
NOR flash

NOR FLASH memories are very fast to program and read. Erasure through tunneling is
much slower. However, this kind of array suffers from low density due to the same
reason that impacts NOR ROM density the need for multiple grounds.

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 Flash Storage
NAND flash

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 Content Addressable Memory (CAM)

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 CAMs

10T CAM Cell

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 CAMs

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 Thank you

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