Manoj Morabad

+918904339440 www.linkedin.com/in/manoj-morabad-9b3900219
Manojmorabad007@gmail.com #645, Khanapur oni, Narendra, Dharwad, Karanataka

Summary
As a DV Engineer with 3 months of experience, I am interested in transitioning to a Physical Design role in the VLSI
Field. I am confident that I have the skills and experience necessary to be successful in this role, and I am eager to
contribute to the company’s growth and my own personal growth.

PROFESSIONAL EXPERIENCE
Smartsocs solutions pvt ltd 03/2023 – Present
Design Verification Intern

• Verilog: Verilog is a hardware description language (HDL) used to describe the behavior of digital circuits. I have
worked on Verilog testbenches, which are used to verify the functionality of Verilog designs .

• SystemVerilog: SystemVerilog is an extended version of Verilog that adds features for describing complex designs
and for verification. I have worked on SystemVerilog testbenches, and I have also used SystemVerilog to create UVM
components.

• UVM: UVM is a verification methodology that uses a layered architecture to create reusable testbenches. I have used
UVM to create testbenches for designs.

Gsemi Technologies pvt ltd 01/2023 – 03/2023

Design Verification Intern

• Digital electronics: Experience with digital logic design, including the principles of Boolean algebra, combinational
and sequential circuits, and timing analysis.

• Verilog: Experience with the Verilog hardware description language (HDL), including the syntax, basic verilog codes,
and verilog testbeches.

EDUCATION
College Name 2012
Course: Course Specialization, GPA
School Name 2012
Course, Percentage
SKILLS & OTHER
 Skill 1  Skill 4
 Skill 2  Skill 5
 Skill 3  Skill 6
CERTIFIATIONS
 Certification 1
 Certification 2
 Certification 3
 Certification 4
ACHIEVEMENTS & AWARDS
 Award 1
 Award 2
 Award 3