Journal of Energy Storage xxx (xxxx) xxx

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Journal of Energy Storage

journal homepage: www.elsevier.com/locate/est

Mathematical modeling and stability analysis of an ultracapacitor based

energy storage system considering non-idealities✩
Naresh P., Sai Vinay Kishore N., V. Seshadri Sravan Kumar ∗
Department of Electrical Engineering, Indian Institute of Technology, Hyderabad, 502285, India

ARTICLE INFO ABSTRACT

Keywords: The typical configuration of an ultracapacitor-based energy storage system comprises of an ultracapacitor
Ultracapacitor stack along with a bidirectional DC/DC converter. Accordingly, this paper focuses on developing mathematical
Bidirectional DC/DC converter models for an ultracapacitor-based energy storage system considering non-idealities. Subsequently, small signal
Energy storage
stability analysis is carried out based on the developed mathematical models. In particular, the impact of non-
Stability
idealities such as ON-state resistance of the switches on the small signal model of the system is highlighted.
It is shown that the transfer function of the system derived by considering the non-idealities has a zero on
the right-hand side of the 𝑠−plane during the discharging mode. The operating conditions under which a right
hand zero can occur are derived, and the behavior of the converter under these operating points is analyzed
with the help of simulation results.

1. Introduction EV, ultracapacitors can be used to supply high currents, resulting in an

During the last decade, there has been a significant increase in
penetration levels of renewable energy systems in several countries.
One of the major challenges associated with a renewable energy source
is its low reliability. One way to improve the reliability is to use the en-
ergy storage systems (ESS) such as Batteries, ultracapacitors, fuel cells,
flywheels, or superconducting magnetic energy storage systems [1–4]
in parallel with the primary renewable energy source. However, the
energy storage devices themselves have certain limitations (such as
the flywheel requires maintenance, the fuel cells have poor turn-on
response, and the batteries are not reliable). Among various ESS, ultra-
capacitor based systems are now succeeding in achieving acceptance
due to its relatively high-reliability, low-maintenance, and fast turn-on
response.
Ultracapacitor based energy storage systems are becoming increas-
ingly popular in various applications related to aerospace, vehicular
technologies, and microgrid applications. In aerospace applications, the
dynamic nature of load [5,6] necessitates more number of batteries that
increase the weight, required space, and cost of the system. Instead,
utilizing the ultracapacitor as an alternative (to batteries) considerably
reduces the overall weight of the system [5]. In the automobile indus-
tries, advancements in battery management systems of electric vehicles
(EVs) can be achieved using ultracapacitors [7]. During the starting of
improved battery life cycle. Further, the higher energy density of ultra-
capacitors makes it feasible to efficiently store energy even for a small
duration of time. On the microgrid front, ultracapacitors are becoming
a popular choice for improving its reliability [8–10]. The design and
integration of an ultracapacitor based ESS with microgrid is reported
in [11]. In addition to improving reliability, ultracapacitors based ESS
can also be used to smoothen out the transients in the DC-link [12].
Further, a hybrid ESS comprising of battery and ultracapacitor provides
a superior choice in applications involving pulsed load currents [13].
Ultracapacitors generally have less terminal voltage and offer capac-
itances of very high value. The terminal voltage of the ultracapacitor is
of the order 2.5 V to 2.7 V [14], which is very low for most practical
applications. As a result, most UC based ESS have a large number of
UCs connected in series and parallel (referred to as UC stack). Further,
contrary to batteries (that behave like a stiff source), the voltage of the
UC stack varies during charging (wherein the voltage across the UC
stack increases to rated value) and discharging (wherein the voltage
falls from its the rated value). However, utilizing a bidirectional DC/DC
converter along with UC stack helps in maintaining a stiff voltage across
its terminals and also boosts the voltage at the output of the UC stack.
Various models and control algorithms for ultracapacitor based ESS
are reported in the literature [15]. A large fraction of the work reported

✩ This work is supported by Department of Science and Technology, Government of India through inspire grant DST/INSPIRE/04/2016/002381 and Early Career
Research scheme ECR/2018/002565.
∗ Corresponding author.
E-mail addresses: ee17resch11014@iith.ac.in (Naresh P.), ee18mtech11034@iith.ac.in (Sai Vinay Kishore N.), seshadri@ee.iith.ac.in
(Seshadri Sravan Kumar V.).

https://doi.org/10.1016/j.est.2020.102112
Received 4 September 2020; Received in revised form 5 November 2020; Accepted 11 November 2020
2352-152X/© 2020 Elsevier Ltd. All rights reserved.

Please cite this article as: Naresh P., Journal of Energy Storage, https://doi.org/10.1016/j.est.2020.102112
Naresh P. et al. Journal of Energy Storage xxx (xxxx) xxx

in literature focuses on modeling and control of energy during the by the UC stack over the discharging time period (𝐼𝑎𝑣𝑔 ), (c) the change
charging and discharging of UC. Besides, algorithms have also been in UC stack voltage during discharge (𝛥𝑉 ).
developed for online power-sharing between different energy storage
devices (for effective usage of UC) [16]. In [17], the energy losses in ( )
𝐼𝑎𝑣𝑔
a hybrid energy storage system (comprising of battery and UC) and its 𝐶𝑢𝑐 = 𝛥𝑡 (2.1)
𝛥𝑉
control based on equivalent series resistance (ESR) is discussed. In [18],
As reported in [21], the UCs are usually discharged up to 50% of
a power management strategy and control logic for parallel operation
their rated value. At 50% of the rated value, 75% of the energy stored
of battery and ultracapacitor for EV application is discussed. In [19], an
in the UC is already discharged. In order to discharge the remaining
electrical equivalent circuit of a Li-ion ultracapacitor is presented. Most
energy, the converter needs to be overrated, which is not economical.
of the approaches developed in the literature are based on equivalent
Moreover, issues related to the initial charging process [23] must be
circuit models of the UC (as reported in [20]). Further, in most of
accounted for while discharging the UC stack completely. Hence, it is
these approaches, the non-idealities (i.e. the parasitic effects associated
preferred to adopt a lower limit (𝑉𝑢𝑐,𝑚𝑖𝑛 ; which is 50% of the rated value
with the circuit elements and the switches) associated with the UC
(𝑉𝑢𝑐𝑛 )) on the voltage during discharge.
based energy storage system are not considered in greater detail. It
is well known that a good mathematical model (that models various 𝑉𝑢𝑐𝑛
𝑉𝑢𝑐,𝑚𝑖𝑛 = (2.2)
non-idealities) is necessary for proper design of an ESS. 2
The average current (𝐼𝑎𝑣𝑔 ) can be computed by taking the average of
1.1. Contributions of this work the maximum and minimum current that is processed by the UC stack.
If 𝑃𝑜 is the power that the converter needs to process during discharge
This work aims to develop a mathematical model and a design (i.e., converter rating), then the minimum (𝐼𝑚𝑖𝑛 ) and maximum (𝐼𝑚𝑎𝑥 )
framework for an UC based ESS considering the associated non- values of current correspond to a scenario where the stack voltage is at
idealities. The non-idealities of significance associated with the UC its rated value and at 50% of its rated value respectively, i.e.,
based ESS are identified, and subsequently, the mathematical model 𝑃𝑜 2𝑃𝑜
𝐼𝑚𝑎𝑥 = =
is derived considering these non-idealities. In particular, this work 𝑉𝑢𝑐,𝑚𝑖𝑛 𝑉𝑢𝑐𝑛
(2.3)
establishes that, when the non-idealities are taken into consideration, 𝑃
𝐼𝑚𝑖𝑛 = 𝑜
the transfer function of an UC-based ESS during the discharging mode 𝑉𝑢𝑐𝑛
has a zero on the right-half of 𝑠−plane. The impact of right hand zero
Accordingly, the average current (𝐼𝑎𝑣𝑔 ) can be computed as
(RHZ) on the performance of UC based ESS is also analyzed. Further,
the effect of non-idealities on (a) the performance of the UC based 1 3𝑃𝑜
𝐼𝑎𝑣𝑔 = [𝐼 + 𝐼𝑚𝑖𝑛 ] = (2.4)
ESS and (b) the design of controllers (for closed-loop operation) is also 2 𝑚𝑎𝑥 𝑉𝑢𝑐𝑛
reported. The minimum value of stack capacitance (𝐶𝑢𝑐,𝑚𝑖𝑛 ) that will ensure that
The paper is organized as follows. Section 2 of the paper discusses the converter can support the desired power for a desired duration of
the methodology employed in designing an UC based bidirectional time can be computed using (2.1) and (2.3), as
converter. The non-idealities associated with the bidirectional DC/DC
3𝑃𝑜 𝛥𝑡
converter are outlined in Section 3. Further, Section 3 also presents the 𝐶𝑢𝑐,𝑚𝑖𝑛 = (2.5)
2
𝑉𝑢𝑐𝑛
modeling and control of UC based bidirectional converter considering
the non-idealities. The controller design for closed loop control of the The variation of minimum stack capacitance as a function of the
UC-based ESS during charging and discharging modes is also discussed processed power and the desired discharge time is shown in Fig. 2a.
in Section 3. Section 4 of the paper deals with the simulation analysis of Fig. 2a indicates that the discharge time of an UC stack of a given
UC based bidirectional DC/DC converter and also establishes the effect capacitance reduces with an increase in the processing power.
to RHZ. Conclusions drawn from the analysis are presented in Section 5. If 𝑉𝑢𝑐𝑐 is the voltage rating of the individual units of the UC stack
(typically around 2.5 V) then, the number of UC cells to be connected
2. Design of an ultracapacitor based energy storage system in series (𝑛) is given by (2.6).
𝑉𝑢𝑐𝑛
𝑛= (2.6)
This section discusses the design aspects (such as component se- 𝑉𝑢𝑐𝑐
lection/rating) of an ultracapacitor-based energy storage system. Typ- The number of parallel branches (𝑝) in the UC stack is usually deter-
ically, an UC-based ESS comprises a UC stack and a bidirectional mined by the total current rating of the UC stack and the current rating
DC/DC converter, as shown in Fig. 1a. The bidirectional converter of individual UCs. For a UC stack comprising of 𝑛 series connected UCs
consists of two switches along with an inductive filter. The controlled and 𝑝 parallel branches, the minimum value of capacitance needed for
operation of the two complementary switches facilitates its operation individual UCs (𝐶𝑢𝑐𝑐,𝑚𝑖𝑛 ) can be computed as
as a buck converter (during charging of the UC stack) and as a boost
𝐶𝑢𝑐,𝑚𝑖𝑛 𝑛
converter (during the discharging cycle). To begin with, the design 𝐶𝑢𝑐𝑐,𝑚𝑖𝑛 = (2.7)
aspects [21,22] associated with the UC based ESS (adopted in this 𝑝
work) are reported for the purpose of completeness.
2.2. Design of filter inductance (𝐿𝑓 )

2.1. Design of ultracapacitor stack
In this paper, the design and analysis of UC stack is carried out by
choosing a simple RC model [20] (as shown in Fig. 1b). The major de-
sign parameter that determines the value of capacitance of the UC stack
is the desired value of converter backup time (i.e., the duration that the
UC stack is designed to discharge). Mathematically, the required value
of capacitance for the UC stack (𝐶𝑢𝑐 ) can be calculated using (a) the
desired duration of discharge (𝛥𝑡), (b) the average current processed
The value of filter inductance is a function of average inductor
current and duty ratio. As the inductor is connected in series to UC
stack, the minimum, maximum and average (𝐼𝐿,𝑎𝑣𝑔 ) values of inductor
current and UC stack current are equal and are given by (2.3). During
charging mode (CM), only switch 𝑠𝑤1 operates and the voltage across
the inductor is the difference between supply voltage (𝑉𝑔 ) and UC stack
voltage i.e.
𝛥𝑖𝐿
𝑉𝑔 − 𝐷𝑉𝑔 = 𝐿𝑐 (2.8)
𝛥𝑡

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Naresh P. et al. Journal of Energy Storage xxx (xxxx) xxx

Fig. 1. Circuit diagram of an UC based energy storage system.

Fig. 2. Variation of minimum stack capacitance and filter inductance.

where 𝐿𝑐 is the value of filter inductance during charging period. Under During discharge mode, the typical variation of filter inductance as
small ripple approximation, (2.8) can be written as, function of duty ratio is shown in Fig. 2c. A unique value of in-
𝑥𝐼𝐿,𝑎𝑣𝑔 ductor (given by (2.15)) is obtained by calculating the inductance
𝑑𝐿
𝑉𝑔 − 𝐷𝑉𝑔 = 𝐿𝑐 (2.9) corresponding to the duty ratio where 𝑑𝐷𝑑 = 0.
𝐷𝑇𝑠
2
where, 𝑥 is the maximum allowable ripple (specified as percentage of 4 𝑉𝑔 𝑇 𝑠
𝐿𝑑,𝑜𝑝𝑡 = (2.15)
average inductor current) and 𝐷 is the duty ratio. Using (2.9) and (2.3), 27 𝑥𝑃𝑜
the value of filter inductance can be computed to be Since the filter inductor must satisfy the ripple criterion for both
charging and discharging modes, the value of filter inductance is chosen
𝑉𝑔2 𝑇𝑠 2𝐷(1 − 𝐷)
𝐿𝑐 = (2.10) to be 𝐿𝑐,𝑜𝑝𝑡 (since 𝐿𝑐,𝑜𝑝𝑡 > 𝐿𝑑,𝑜𝑝𝑡 ).
𝑥𝑃𝑜 3
2
Eqs. (2.10) indicates that the value of filter inductance is dependent on 1 𝑉𝑔 𝑇 𝑠
𝐿𝑓 = 𝐿𝑐,𝑜𝑝𝑡 = (2.16)
the operating duty ratio. The typical variation of Inductance with duty 6 𝑥𝑃𝑜
ratio for three different converters is shown in Fig. 2b. Choosing the 3. Modeling and control
maximum value of inductance will ensure that the current ripple cri-
terion is satisfied irrespective of the operating duty ratio. Accordingly, In this section, the transfer function model of a DC/DC converter
the value of filter inductor during charging mode can be computed to corresponding to different operating modes is derived by considering
𝑑𝐿
the value corresponding to the duty ratio at which 𝑑𝐷𝑐 = 0 (given in the associated non-idealities. In an ideal scenario (typically employed
(2.11)). for developing simplified mathematical models), the UC stack can
2 be modeled as an equivalent capacitance (𝐶𝑢𝑐 ), and the bidirectional
1 𝑉𝑔 𝑇 𝑠 DC/DC converter can be represented using an ideal switch and inductor
𝐿𝑐,𝑜𝑝𝑡 = (2.11)
6 𝑥𝑃𝑜 combination. However, for more practical applications, it is necessary
During the discharging mode, the governing equation corresponding to to take into consideration the non-idealities (i.e. the parasitic effects)
filter inductor is associated with the UC stack and the DC/DC converter. The various
non-idealities associated with the UC based ESS can be classified as
𝛥𝑖 𝑥𝐼𝐿,𝑑𝑖𝑠
𝑉𝑔 = 𝐿𝑑 𝐿 = 𝐿𝑑 (2.12)
𝛥𝑡 𝐷𝑇𝑠 (a) Non-idealities associated with the UC stack: The equivalent cir-
cuit representation of the UC comprises of the equivalent series
where the inductor current during discharging mode is given by
resistance (ESR) and equivalent parallel resistance (EPR) that
𝑃𝑜 𝑃𝑜 model its non-ideal behavior (as shown in Fig. 1b). Typically,
𝐼𝐿,𝑑𝑖𝑠 = = (2.13)
𝑉𝑢𝑐 𝑉𝑔 (1 − 𝐷) the value of EPR is very high (around 1000 Ω) (causing a very
minimal current to flow through the parallel branch) and hence
Substituting (2.13) in (2.12), the value of filter inductance can be
can be neglected for high power and low power applications. On
computed as
the other hand, the ESR of the UC is in the range 0.1 Ω - 0.5 Ω
𝑉𝑔2 𝑇𝑠 and hence is very significant for applications with low voltage
𝐿𝑑 = 𝐷(1 − 𝐷)2 (2.14) and relatively high power.
𝑥𝑃𝑜

3
Naresh P. et al. Journal of Energy Storage xxx (xxxx) xxx

and are neglected in this work. Further, UC based ESS typically is

used as a backup/source support wherein duration of discharge is
very small and the magnitude of current through the switches (during
this period) is relatively high. As a result, the drop due to ON state
resistance of MOSFET switches is significant especially for low power
rated converters. In this work, the effect of ON state resistance on the
performance of the converter is thoroughly analyzed by developing the
appropriate models. To start with, the transfer function models of the
Converter under consideration is derived considering non-idealities.

3.2.1. Transfer function during charging mode

During the charging mode, the UC stack gets charged from the
external source/grid (i.e. 𝑉𝑔 ) and the corresponding state variables are
Fig. 3. Signal flow graph indicating operational states of an UC based bidirectional the average current through the inductor (𝑖𝑙 ) and the voltage across the
DC/DC converter and their transitions [21]. UC stack (𝑣𝑢𝑐 ). The state space model of the system when the switch sw1
is in ON state is given by
[ . ] [1]
⎡− (𝑟+𝑟𝑠𝑤1 ) − 1 ⎤ [ ] [ ]
(b) Non-idealities associated with the bidirectional DC/DC con- 𝑖𝑙 𝐿 ⎥ 𝑖𝑙
=⎢
𝐿 𝐿
. + 𝑣𝑔 (3.1)
verter: The non-idealities associated with the bidirectional DC/ 𝑣𝑢𝑐 ⎢ 1 ⎥
0 ⎦ 𝑢𝑐𝑣 0
⎣ 𝐶 𝑢𝑐
DC converter are the ON-state resistance of the switches, ON-
state voltage drop of the switches, and the parasitic resistance of where, 𝑟𝑠𝑤1 is the ON state resistance of switch sw1 and 𝑟 is the sum of
the inductor. However, the ON-state voltage drop (typically of ESR of the UC stack and parasitic resistance of the filter inductor. The
the order of 0.5 V) is minimal when compared to the drop due state space representation of the DC/DC converter when the switch sw2
to ON-state resistance (mainly for applications involving high is turned OFF is given by
currents) and hence can be neglected. Moreover, the ON-state [ . ]
resistance is very significant for MOSFET based converters whose 𝑖𝑙 ⎡− 𝑟 − 𝐿1 ⎤ [ 𝑖 ]
=⎢ 1 ⎥ 𝑙
𝐿
. (3.2)
ON state resistance can be as high as 0.5 Ω. 𝑣𝑢𝑐 ⎢ 0 ⎥ 𝑣𝑢𝑐
⎣𝐶 𝑢𝑐 ⎦
To start with, the modes of operation of bidirectional DC/DC converter Using state space averaging, the differential equations describing the
are outlined and subsequently, the mathematical models considering behavior of state variables of the converter can be written as
the non-idealities are developed. . ( )
𝐿𝑖𝑙 = − 𝑟 + 𝑑𝑟𝑠𝑤1 𝑖𝑙 − 𝑣𝑢𝑐 + 𝑑𝑣𝑔
. (3.3)
3.1. Modes of operation of bidirectional DC/DC converter 𝐶𝑢𝑐 𝑣𝑢𝑐 = 𝑖𝑙
The set of differential equations given by (3.3) are non-linear since the
The three modes in which a bidirectional DC/DC converter can
control input/variable for the converter is the duty ratio 𝑑. As a result,
operate are (a) charging mode (during which switch 𝑠𝑤1 is controlled
the small signal model of the converter is derived using linearization.
and 𝑠𝑤2 is turned OFF), (b) discharging mode (during which switch
Let ̂𝑖𝑙 , 𝑣̂𝑐 , 𝑑̂ and 𝑣̂𝑔 represent the small signal deviations in the inductor
𝑠𝑤2 is controlled and 𝑠𝑤1 is turned OFF) and (c) PWM blocking mode
current, voltage cross UC stack, duty ratio and grid voltage respectively
(wherein both the switches are blocked). 𝑉
i.e. 𝑖𝑙 = 𝐼𝑙 +̂𝑖𝑙 , 𝑣𝑢𝑐 = 𝑉𝑢𝑐 + 𝑣̂𝑢𝑐 , 𝑑 = 𝐷 + 𝑑̂ and 𝑣𝑔 = 𝑉𝑔 + 𝑣̂𝑔 (with 𝑉𝑢𝑐 = 𝐷𝑔 ).
The typical modes of operation and the transition between modes
The small signal model of the converter during charging mode is given
is represented via a state diagram in Fig. 3. Since the current in the
inductor cannot change instantaneously, the PWM signals for both the by
[ ] [ ] [ 𝑉𝑔 −𝑟𝑠𝑤1 𝐼𝑙 ] [ ]
switches needs to be blocked for a small duration (referred to as PWM ̂𝑖̇𝑙 ⎡− (𝑟+𝐷𝑟𝑠𝑤1 ) − 1 ⎤ ̂𝑖 𝐷 𝑣̂𝑔
=⎢ 𝐿⎥
𝐿 𝑙
blocking state). The transition (indicated by edges 𝐶2 and 𝐷1 in Fig. 3) + 𝐿 𝐿 (3.4)
̇
𝑣̂𝑢𝑐 ⎢ 1
0 ⎥ 𝑣̂𝑢𝑐 0 0 𝑑̂
from charging mode (indicated by state 𝑆1 in Fig. 3) to discharging ⎣ 𝐶𝑢𝑐 ⎦
mode (indicated by state 𝑆2 in Fig. 3) happens through PWM blocking ⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟ ⏟⏟⏟ ⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟
𝐱𝐜 𝐁𝐜
𝐀𝐜
state (indicated by state 𝑆0 in Fig. 3). Similarly, the transition (indi-
cated by edges 𝐷2 and 𝐶1 in Fig. 3) from discharging mode to charging Since, the objective is to control the charging/discharging current to a
mode happens through PWM blocking state. Typically, the converter is desired value, the output equation is given as
in PWM blocking state till the current through the inductor become [ ]
zero. The loops in the state diagram associated with the states indicate 𝐲 = 𝑖𝑙 = 1 0 𝐱𝐜 (3.5)
⏟⏟⏟
that the converter continues to operate in the same state in the absence 𝐂
of any external triggering signal (such as charging/discharging). The
From the state space representation, the desired transfer function
charging and discharging signals (i.e. represented by edges with labels ̂𝑖𝑙 (𝑠)
𝐶 and 𝐷) are toggled using a mode identification algorithm presented i.e. 𝑑(𝑠) can be computed as
in [24]. ̂𝑖𝑙 (𝑠) 𝑠(𝑉𝑔 − 𝑟𝑠𝑤1 𝐼𝑙 )𝐶𝑢𝑐
= 𝐂(𝑠𝐈 − 𝐀𝐜 )−1 𝐁𝐜 = (3.6)
̂
𝑑(𝑠) 𝐿𝐶𝑢𝑐 𝑠2 + (𝑟 + 𝐷𝑟𝑠𝑤1 )𝐶𝑢𝑐 𝑠 + 1
3.2. Modeling of bidirectional converter
In the absence of non-idealities the transfer function of the converter
The non-idealities associated with the UC based bidirectional DC/ is given by (3.7). Comparison of transfer functions given by (3.6) and
DC converter are the ESR and EPR of the UC stack, resistances of (3.7) indicate that non-idealities reduce the gain of the converter and
the filter inductor and switches (especially during ON state), voltage introduce additional damping.
drop of switches (during ON state). Some of the non-idealities such as
𝑖̂𝑙 (𝑠) 𝑠𝑉𝑔 𝐶𝑢𝑐
EPR (typically very high) and the ON state voltage drop of switches = (3.7)
(typically very low) do not impact the performance of the converter ̂
𝑑(𝑠) 𝐿𝐶𝑢𝑐 𝑠2 + (𝐸𝑆𝑅)𝐶𝑢𝑐 𝑠 + 1

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Naresh P. et al. Journal of Energy Storage xxx (xxxx) xxx

3.2.2. Transfer function during discharging mode Table 1

During the discharging mode, the UC stack discharges the stored Parameters of three different converters used for analysis.

energy to the load and 𝐶𝑓 acts as a filter to reduce the ripple in Power (W) Device name 𝑅𝑜𝑛 (Ω) 𝐼𝑟𝑎𝑡𝑒𝑑 (A) 𝐿𝑐, 𝑜𝑝𝑡 (mH) 𝐿𝑓 chosen (mH)
the output voltage. Consequently, the state variables of the converter 100 IRF520 0.27 10 0.375 0.4
during discharging mode are the average current through the inductor 140 IRF530 0.16 14 0.26 0.3
300 IRF540 0.077 30 0.11 0.15
(𝑖𝑙 ) and the voltage across the filter capacitor (𝑣𝑔 ). The state space
model of the system when the switch sw2 is in ON state is given by

[. ] [ ] [1]
𝑖𝑙 ⎡− (𝑟+𝑟𝑠𝑤2 ) 0 ⎤ 𝑖𝑙 [ ] 3.3. Design of PI controller
=⎢ ⎥
𝐿
. + 𝐿 𝑣𝑢𝑐 (3.8)
𝑣𝑔 ⎢ 0 −1 ⎥
𝑣𝑔 0
⎣ 𝑅𝑙 𝐶𝑓 ⎦ In this part, the design philosophy employed for tuning the PI
where 𝑅𝑙 represents the equivalent resistance corresponding to load controller (for controlling the inductor current to a desired value) is
on the converter and 𝑟𝑠𝑤2 represents the ON state resistance of switch presented. Typically, the closed loop control of UC based bidirectional
sw2 . The state space representation of the converter (during discharging converter will have two stages of control i.e., inner current control and
mode) when switch sw2 is in OFF state is given by outer voltage control. However, in some applications such as source
[. ] −1 ⎤ [ ] [1] support, the control have only one loop i.e. current control. The current
𝑖𝑙 ⎡ −𝑟 [ ]
⎢ 𝐿 𝐿 ⎥ 𝑖𝑙
. = + 𝐿 𝑣𝑢𝑐 (3.9) control loop of the DC/DC converter during charging and discharging
𝑣𝑔 ⎢ 1 −1 ⎥ 𝑣
𝑔 0 modes is shown in Fig. 4.
⎣𝐶 𝑓 𝑅𝐶 ⎦
𝑙 𝑓

Using state space averaging, the differential equations describing the In Fig. 4, 𝑖𝑟𝑒𝑓 𝑟𝑒𝑓
𝑐 ∕𝑖𝑑 indicates the reference value of current flowing
behavior of state variables of the converter during discharging mode through the inductor and 𝐻𝑖𝑐 (𝑠) and 𝐻𝑖𝑑 (𝑠) are the controller transfer
can be written as functions during charging and discharging modes of the converter. In
. ( ) this work, the controller chosen for attaining the desired control
( ) is a
𝐿𝑖𝑙 = − 𝑟 + 𝑑𝑟𝑠𝑤2 𝑖𝑙 − (1 − 𝑑)𝑣𝑔 + 𝑣𝑢𝑐
PI controller [25] whose transfer function is of the form 𝑘 𝑠+𝜔 . The
. 𝑣𝑔 (3.10) 𝑠
𝐶𝑓 𝑣𝑔 = (1 − 𝑑)𝑖𝑙 − value of 𝑘 is chosen such that the open loop gain of the compensated
𝑅𝑙
system (i.e. plant + controller) is 0 at desired crossover frequency.
Eq. (3.10) indicates that the resulting state space equations of the Typically, the desired cross over frequency is chosen to be one tenth
converter are non-linear. A small signal model of the converter can of the switching frequency [26] and as a result, the value of 𝑘 is equal
be derived using linearization. The resulting small signal model of the to the gain (in linear scale) of the open loop plant transfer function at
converter during discharging mode is given by the desired corner frequency. Further, the value of 𝜔 is generally chosen
[ ] −(1−𝐷) ⎤ [ ] 𝑉𝑔 −𝑟𝑠𝑤2 𝐼𝑙 [ ]
̂𝑖̇ ⎡− (𝑟+𝐷𝑟𝑠𝑤2 ) ̂𝑖 ⎡1 ⎤ 𝑣̂ to be much lower than the crossover frequency.
= ⎢ (1−𝐷) ⎥ 𝑙 + ⎢𝐿 ⎥ 𝑢𝑐
𝑙 𝐿 𝐿 𝐿
(3.11)
̂
𝑣̇ 𝑔 ⎢ −1 ⎥
𝑣̂𝑔 ⎢0 −𝐼𝑙 ⎥ 𝑑̂
⎣ 𝐶𝑓 𝑅 𝑙 𝐶𝑓 ⎦ ⎣ 𝐶𝑓 ⎦ 4. Simulation analysis
⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏞⏟ ⏟⏞⏞⏞⏞⏞⏞⏞⏞⏟⏞⏞⏞⏞⏞⏞⏞⏞⏟
𝐀𝐝 𝐁𝐝
In this section, simulation analysis of the UC based bidirectional
The transfer function of the converter (𝐂(𝑠𝐈 − 𝐀𝐝 )−1 𝐁𝐝 ) is computing DC/DC converter is reported with an objective to highlight the effect of
using (3.11) and substituting the relationship between the state vari- non-idealities on its overall performance. Three converters comprising
ables at the operating point around which linearization is carried out of MOSFET switches having different power/current ratings are chosen
𝐼𝑜 𝑉𝑔
(i.e. 𝐼𝑙 = 1−𝐷 = 𝑅 (1−𝐷) ). The transfer function of the converter during for the analysis. The UC stack comprises of a 10 series connected
𝑙

discharging mode is given by Maxwell BCAP150 UCs having an overall capacitance of 15 F. The
( ) design is carried out assuming the maximum ripple in the inductor
⎧𝑎 = 𝑅 𝐶 𝑏=2 1−
𝑟𝑠𝑤2 current to be 10% of the rated current and the grid voltage (𝑉𝑔 ) to be
⎪ 𝑙 𝑓 𝑅𝐿 (1−𝐷)
̂𝑖𝑙 (𝑠) 𝑉𝑔 𝑎𝑠 + 𝑏 ⎪ 𝑟+𝐷𝑟𝑠𝑤2 24 V. The parameters of the three converters obtained by employing the
= where ⎨𝑝 = 𝐿𝐶𝑓 𝑞 = ( 𝑅𝐿 + 𝐶𝑓
) outlined design philosophy are given in Table 1. The filter capacitance
̂
𝑑(𝑠) 𝑅𝑙 𝑝𝑠2 + 𝑞𝑠 + 𝑡 ⎪ 𝑙

⎪ 𝑡=
𝑟+𝐷𝑟𝑠𝑤2
+ (1 − 𝐷)2 (𝐶𝑓 ) used on the grid side of the converter is 2200 μF for all the
⎩ 𝑅𝑙
converters and the switching frequency employed for simulation is
(3.12) 25 kHz.
To start with, the effect of non-idealities on the controller design
Condition for existence of right half plane zero (RHZ) : The con-
in the absence of RHZ is indicated. The impact of non-idealities on
verter transfer function given by (3.12) indicates that there can be a
the frequency response of two DC/DC converters (namely 100 W and
pole on the right half of the 𝑠−plane (making the system to be non-
minimum phase) when 𝑏 < 0. The condition for value of load resistance 300 W) during charging and discharging modes is shown in Fig. 5. The
under which 𝑏 < 0 (i.e. existence of a RHZ) is duty ratio corresponding to the operating point at which the transfer
𝑟𝑠𝑤2 functions are derived is 0.5 in both charging and discharging modes.
𝑅𝐿 < 𝑅𝑐𝑙 where 𝑅𝑐𝑙 = (3.13) Observation into Fig. 5 indicates that the reduction in gain due to non-
(1 − 𝐷)
idealities is significant at lower frequencies. The reduction in gain due
where 𝑅𝑐𝑙 is the critical load resistance. The corresponding coordinate
to non-idealities is very small in the typical range of corner frequencies
on the 𝑠−plane at which the right half plane zero occurs (𝑠𝑟ℎ𝑧 ) is given
used for PI controller design (i.e. corner frequencies greater than 103 Hz
by
[ ] because the switching frequency is typically in 10s of kHz). As the result
2 𝑅𝑙 (1 − 𝐷) − 𝑟𝑠𝑤2 the variation in gain 𝑘 of the PI controller is very small. On the other
𝑠𝑟ℎ𝑧 = (3.14)
𝑅2𝑙 𝐶𝑓 (1 − 𝐷) hand, the impact of non-idealities on the phase is very minimal at both
It is to be noted that, the transfer function of the DC/DC converter the lower and higher frequencies. The phase of the converter transfer
in the absence of non-idealities [24] (given by (3.15)) does not have a function settles to −90◦ (i.e. the phase margin is positive and greater
zero on the right half of the 𝑠−plane. than 45◦ ) even in the presence of non-idealities due to which, there
is no need to design any lead or lag compensator. The values of 𝑘
̂𝑖𝐿 (𝑠) 𝑉𝑔 𝑠𝑅𝐿 𝐶𝑓 + 2
= (3.15) and 𝜔 of PI controller for different converters considering the effect
̂
𝑑(𝑠) 𝑅𝐿 𝐿𝐶 𝑠2 + ( 𝐿 + 𝑟 )𝑠 + (1 − 𝐷)2 of non-idealities are given in Table 2.
𝑓 𝑅 𝐶 𝐿 𝑓

5
Naresh P. et al. Journal of Energy Storage xxx (xxxx) xxx

Fig. 4. Block diagram for current control.

Fig. 5. Frequency response of UC based DC/DC converter in the absence of RHZ.

Table 2 (referred to as minimum load resistance in this paper). Any value of

Parameters of PI controllers. load resistance lower than the minimum load resistance will draw
Power Charging mode Discharging mode continuous currents higher than the rated currents of the switches.
(W) Ideal Non-ideal Ideal Non-ideal Under such scenarios, the protection circuits ensure that the converter
𝑘 𝜔 𝑘 𝜔 𝑘 𝜔 𝑘 𝜔 does not operate/disconnects from the grid. The limit on the minimum
100 0.26 100 0.295 100 0.263 100 0.288 100 load resistance for the three converters is shown in Fig. 7b.
140 0.197 100 0.216 100 0.194 100 0.213 100 Observation into Figs. 7a and 7b indicate that the critical resistance
300 0.097 100 0.109 100 0.097 100 0.107 100 of the converter is much lower than the limit on the minimum load
resistance. This indicates that the DC/DC currents through the switches
in the DC/DC converter is much higher than the rated current resulting
in the protection circuit to operate (or) switches to blow out. To
The closed loop response (average inductor current) of the 100 W
substantiate this further, the response of the 100 W converter when the
converter with PI controllers tuned based on ideal and non-ideal trans-
load resistance is lower than the critical resistance is shown in Fig. 8.
fer functions is shown in Fig. 6. Fig. 6 indicates that an improved (albeit
Till 𝑡 = 0.05 s, the converter is discharging its rated current (10 A, as
marginal) transient response is obtained by tuning the PI controller
shown in Fig. 8a) and the UC stack voltage is gradually reducing (as
based on the transfer function obtained by considering non-idealities.
shown in Fig. 8b)). At 𝑡 = 0.05 s, the load resistance of the converter is
In order to study the impact of right half plane zero on the response reduced below the critical resistance resulting in a very high reference
of the DC/DC converter, the reference current during discharge mode current (i.e. 88.9 A). Even if the protection circuits does not operate,
must be set in such a manner that the effective load resistance is below the UC stack cannot deliver such high currents (as shown in Fig. 8) due
the critical resistance. The critical resistance of the three converters un- to limitation on the operating duty ratio.
der consideration is shown in Fig. 7a. The critical resistance is larger at
higher duty ratios as the critical resistance is inversely proportional to 5. Conclusions
(1−𝐷). Further, the switches of the converter cannot carry a contentious
current that is higher than the rated value (given in Table 1). Since This paper models and analyzes the impact of non-idealities on the
the grid voltage 𝑉𝑔 is typically fixed, the maximum current rating of performance of UC based bidirectional DC/DC converter. It is observed
the switches can be translated into a lower limit on the load resistance that the small signal model of the converter (during discharging mode)

6
Naresh P. et al. Journal of Energy Storage xxx (xxxx) xxx

Fig. 6. Closed loop response of 100 W converter during charging and discharging modes.

Fig. 7. Critical and minimum load resistance of the DC/DC converter.

Fig. 8. Response of the DC/DC converter in the presence of RHZ.

derived by considering non-idealities has a zero on the right half of the
𝑠−plane for a particular range of load resistance. This causes the system
to have non-minimum phase and the response under such operating
conditions will have an initial undershoot. However, it is observed
that, in operating conditions where the load resistance is much lower
than the critical resistance, the current through the switches of the
DC/DC converter is very high, causing the protection circuits to operate
eventually. In the absence of RHZ, the non-idealities reduce the gain of
the converter and the closed loop response of the converter designed
by considering the non-idealities has a marginally better transient
response.
CRediT authorship contribution statement
Naresh P.: Methodology, Software, Formal analysis, Validation. Sai
Vinay Kishore N.: Software, Formal analysis, Writing - original draft.
V. Seshadri Sravan Kumar: Conceptualization, Writing - review &
editing, Funding acquisition, Supervision.
Declaration of competing interest
The authors declare that they have no known competing finan-
cial interests or personal relationships that could have appeared to
influence the work reported in this paper.

7
Naresh P. et al.
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