Physical Handout Notes

JOMO KENYATTA UNIVERSITY
OF
AGRICULTURE AND TECHNOLOGY
SCHOOL OF ELECTRICAL, ELECTRONICS AND INFORMATION ENGINEERING
DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING
EEE 2212
PHYSICAL ELECTRONICS II
for
Bachelor of Science
(Electrical & Electronics Engineering / Electrical & Computer Engineering)
Contents
Chapter 1. Review of Semiconductors & PN Junction .............................................................................. 1
1.1. Energy Levels and Energy Bands ....................................................................................................... 1
1.2. Charge Carriers in Semiconductors..................................................................................................... 3
1.3. Conduction in Semiconductors ........................................................................................................... 5
1.4. Excess Carriers Lifetime ..................................................................................................................... 6
1.5. The P-N Junction ................................................................................................................................. 6
Chapter 2. Metal – Semiconductor Junctions .......................................................................................... 14
2.1. Surface Charge and Depletion in a Metal – Semiconductor Capacitor............................................. 14
2.2. Review of Contacts and Contact Potential ........................................................................................ 16
2.3. Electrical Behaviour of Metal - Semiconductor Junctions................................................................ 18
2.4. Schottky Diode Operation ................................................................................................................. 23
2.5. Tunnelling Ohmic Contacts .............................................................................................................. 25
Chapter 3. The Bipolar Junction Transistor ............................................................................................. 27
3.1. Transistor Overview .......................................................................................................................... 27
3.2. Construction and Nomenclature ........................................................................................................ 28
3.3. Charge Flow and Transistor Action .................................................................................................. 33
3.4. Transistor Operation in Active Region ............................................................................................. 37
3.5. BJT Minority Charge Distribution for Different Operating Regions ................................................ 39
3.6. BJT Characteristics ........................................................................................................................... 42
3.7. DC Analysis of BJT Circuits ............................................................................................................. 48
3.8. The BJT as a Switch .......................................................................................................................... 50
3.9. The BJT as an Amplifier ................................................................................................................... 54
3.10. AC Small Signal Models of Transistor Amplifier ......................................................................... 57
3.11. Large Signal Models...................................................................................................................... 63
Chapter 4. Junction Field Effect Transistors............................................................................................ 65
4.1. FET Introduction ............................................................................................................................... 65
4.2. J-FET Structure and Operation ......................................................................................................... 66
Chapter 5. The MOSFET ......................................................................................................................... 70
5.1. The MOS Capacitor .......................................................................................................................... 70
5.2. The MOSFET .................................................................................................................................... 81
5.3. The N-channel enhancement MOSFET ............................................................................................ 82
5.4. N-Channel Depletion MOSFET ........................................................................................................ 87
5.5. Application of MOS Devices ............................................................................................................ 88
5.6. MOSFET Scaling .............................................................................................................................. 90
5.7. Comparison of FET with BJT ........................................................................................................... 90
5.8. CMOS and BiCMOS Technology..................................................................................................... 91
5.9. The MESFET .................................................................................................................................... 93
Chapter 6. Optoelectronic Devices .......................................................................................................... 95
6.1. Introduction ....................................................................................................................................... 95
6.2. Optical Sources ............................................................................................................................... 104
6.3. Optical Detectors ............................................................................................................................. 110
6.4. Optical Amplifiers ........................................................................................................................... 115
6.5. Photovoltaic Devices ....................................................................................................................... 116
6.6. Summary: Optical Electronic Devices ............................................................................................ 121
Appendix A. Electron and Hole Mobility for Silicon ............................................................................ 122
Appendix B. Reference Formulae .......................................................................................................... 123
Appendix C. Revision Questions ........................................................................................................... 124
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EEE 2212 PHYSICAL ELECTRONICS II
Course Objectives
This course seeks to equip the students with knowledge of the basic electronic devices, their characteristics
and limitations as a basis for a future study of electronic circuits.
At the end of this unit, the students should be able to:
1. Describe the parameters of Bipolar Junction Transistors and factors that affect the parameters.
2. Describe the working principles of Bipolar Junction Transistors with the aid of their characteristic curves.
3. Describe the operational limits of BJT characteristics and models.
4. Describe the parameters of MOSFETs and factors that affect the parameters.
5. Describe the working principles of MOSFETs with the aid of their characteristic curves.
6. Describe the operational limits of MOSFETs characteristics and models.
7. Describe the working principle of solar cells, LEDs, photodiodes
Course Outline
• Solar cell: physical processes involved in photovoltaic effect. Solar spectrum: dispersion of light in
semiconductors in relation to energy gap. Solar cell characteristics.
• Light emitting diodes (LED): generation of electromagnetic (EM) radiation by p n junction.
• Semiconductor laser photo diodes, photo transistors, and liquid crystal displays.
• Transistors action on the basis of energy band diagrams. Derivation of equations on the basis of energy band
diagrams.
• Derivation of FET equation.
• MOSFET, UJT and their characteristics. Ideal and non-ideal behaviour of these devices.
Course Resources
Main
S. M. Sze, M-K Lee, Semiconductor Devices: Physics and Technology, 3rd Ed., Wiley, 2012
Reference and Revision Materials
S. O. Kasap, Principles of Electronic Materials and Devices, 3rd Ed., NewYork: Mcgraw-Hill, 2006.
C. G. Fonstad, Microelectronic Devices and Circuits, Electronic Edition, 2006.
M. H. Rashid, Microelectronic Circuits: Analysis and Design, 2nd ed., Stamford, Connecticut:
Cengage Learning, 2011.
A. S. Sedra and K. C. Smith, Microelectronic Circuits, 5th ed., New York: Oxford University
Press, 2004.
S. O. Kasap, Optoelectronics and Photonics: Principles and Practices, 2nd International Ed., Harlow, UK,
Pearson Education, 2013.
B. Van Zeghbroeck , Principles of Semiconductor Devices, Boulder, Colorado, unpublished 2011.
Course Assessment
This course unit will be assessed by Continuous Assessment Tests (CATs), Assignments, Laboratory
Exercises and Final Examination at the end of the semester. These will contribute to the final grade as follows:
CATs (10%), Assignments (5%), Laboratory Exercises (15%), and the Final Examination (70%).
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Chapter 2. Metal – Semiconductor Junctions
A metal semiconductor junction is formed when metallic material is deposited on the surface of a
semiconductor. This may occur out of the need to create contacts between semiconductor devices and external
circuits. It may also occur as a result of the need to create devices that utilise the properties of a metal
semiconductor junctions. In both cases, it is necessary to understand the electrical behaviour of the junction.
2.1. Surface Charge and Depletion in a Metal – Semiconductor Capacitor
The distribution of charges in a metal – semiconductor junction can be understood by reviewing the behaviour
of a parallel plate capacitor with one plate made of a semiconductor while the other plate is made of metal.
A parallel plate capacitor stores energy by using an external DC, V, supply to transfer electrons from one
conducting plate to another. One conducting plate then holds a negative charge, Q, while the other conducting
plate holds an equivalent negative charge, -Q. The ratio of the charge Q to the applied potential, V, is the
capacitance, C.
Figure 2.1: Parallel Plate Capacitor

Consider a parallel plate capacitor made of a copper plate on one side and a P-type silicon plate on the other
has plate area 1cm2 and distance between plates of 0.1μm. The capacitance C is 8.85nF. Suppose a potential
difference of 2V is applied across the capacitor, with the metal at the higher potential. The magnitude of charge
Q on each plate will be 1.77 x 10-8 C. The charge in a material is achieved by having an excess (for negative
charge) or deficiency (for positive charge) of electrons. A charge of 1.77 x 10-8 C will be achieved by an
excess or deficiency of 1.1 x 1011 electrons.
In a metal, each atom contributes its valence electrons to a free electron cloud and becomes a negative ion.
Copper is monovalent (mostly) and each atom will have contributed one electron, leaving the atom as an ion
with a charge of +q. To achieve the positive charge in copper, 1.1 x 1011 electrons will have to be removed,
leaving a net positive charge. From the crystal structure, it can be seen that copper has more than 1x 1015
atoms per cm-2 on the surface. These atoms are more than sufficient to provide the required charge. All that
will be required is for 1 in every 105 free electrons to move away from the surface layer of atoms into the
interior of the metal. The electric field will not penetrate the metal. A similar analysis can be made for
aluminium.
A similar quantity but in this case of negative charge will be required on the silicon side. For P-type silicon,
this will be achieved by adding electrons to 1.1 x 1011 holes, thus converting them to neutral atoms. This leaves
an equivalent number of negative acceptor ions without a matching positive charge in a depletion region. The
total charge, Q in the depletion region will be:
− =−
Where q is the electronic charge, A is cross-sectional area of plate (1cm-2 in this case) and Wd is the depth of
depletion.
In order for a plate of P-type silicon with Na = 1016cm-3 to hold a charge of -Q = -1.77 x 10-8 C, then Wd = 1.1
x 10-5 cm = 0.11μm. This is a distance of about 500 atomic layers (diameter of silicon atom is about 220pm).
14
Compiled by B. M. Ngocho December 2020
The depletion region required to contain this charge will therefore extend beyond the surface into the body of
the semiconductor.
Aside – Silicon Crystal Structures

Silicon has diamond crystal structure with Lattice Constant a = 0.543nm. The surface
concentration of atoms depends on the crystal face along which the surface was cut.
(100) Plane: 6.78 atoms/nm2; (110) Plane: 9.59 atoms/nm2; (111) Plane: 7.83 atoms/nm2.
For Silicon, number of atoms per cm3 is 5 x 1022 and ni= 1 x 1010. Therefore, one atom out of
5 x 1012 contributes a conduction electron.
Aside – Aluminium and Copper Crystal Structures

Aluminium has face centred cubic (FCC) crystal structure with Lattice Constant a =
0.405nm.
Copper has face centred cubic (FCC) crystal structure with Lattice Constant a = 0.3620nm.
The surface concentration of atoms depends on the crystal face along which the surface
was cut.
Aluminium Copper
(100 Plane) = (2/a2) 12.2 atoms nm-2 15.3 atoms nm-2
(110 Plane) = (2/a2 √2) 8.6 atoms nm-2 10.8 atoms nm-2
(111 Plane) = (4/a2 √3) 14.1 atoms nm-2 17.6 atoms nm-2
Conclusion: For a parallel plate capacitor with one metallic plate and one semiconductor plate, all the charge
will be on the surface for the metal plate, while on the semiconductor plate, the charge will be accommodated
in a depletion region that extends to the bulk of the semiconductor material, Figure 2.2.
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Figure 2.2: Metal – Semiconductor Capacitor Showing Surface Charge in Metal and Depletion Region in
Semiconductor
2.2. Review of Contacts and Contact Potential

When two materials with different work functions are brought together, a contact potential is established that
is equal to the difference in the work functions. This section examines why the contact potential exists and the
effect on the ability to of charge carriers to move across the junction:
2.2.1. Fermi Level and Work Function in Extrinsic Semiconductor
The work function is the difference in energy between the Fermi Level and the vacuum level. The work
function has a physical meaning in a metal as the energy required to remove an electron from the metal. In a
semiconductor, the work function is an abstract construct because there are almost always no electrons at the
Fermi Level.
In an intrinsic semiconductor, the Fermi Level is close to the centre of the forbidden band and the following
equations are close approximations:
2.1
E =E + 2
2.2
E =E − 2
Once a semiconductor is doped and becomes extrinsic, the number of quantum states and carriers changes,
hence changing the position of the Fermi Level. The Fermi level moves towards the conduction band in an N-
type semiconductor and towards the valence band in a P-type semiconductor. To establish the position of the
Fermi Level in an extrinsic semiconductor, consider the carrier concentration for intrinsic and extrinsic non-
degenerately doped semiconductor.
For intrinsic semiconductor the carrier concentrations can be approximated as:
( )
= = 2.3
( ) 2.4
= =
The charge concentration for N-type extrinsic semiconductor:

( )
≈ = 2.5
Dividing 2.5 with 2.3:
( )
= ( )
( )
=
16
− = ln
And:
= + ln 2.6
The work function can be evaluated as:
= + −( − ) 2.7
2
A similar treatment for P-type semiconductor will yield;
= − ln 2.8
And the work function:
= + +( − ) 2.9
2
Example: A piece of silicon is doped with donors to a concentration of 1016cm-3. (a) What is the conductivity
type of the doped semiconductor? (b) What is the position of the Fermi Level in the doped semiconductor
relative to the intrinsic Fermi level? (c) What is the work function of the extrinsic silicon?
Answer: (a) Dopant is donor, material is N-type; (b) Using Equation 2.14, EFP = EFi – kTln(Na/ni). HINT: Use
kT in electron volts (divide kT by q, to get 0.0259eV at 300K). EFP = EFi – ln(10E16/10E10) = EFi + 0.356eV;
(c) work function = 4.05+0.56-0.0356 = 4.966eV.
2.2.2. Charge Movement at Junctions and Band Bending

The probability that a quantum state with energy E is occupied by an electron is defined by the Fermi-Dirac
function.
1
( )= ( ) 2.10
1+
The probability depends on the difference in energy between the state under consideration and the Fermi level,
(E-EF). When two different materials with different work functions are brought together, electrons in one
material will find that there are empty quantum states in the other material that are closer to the Fermi level
and therefore have a higher probability of occupation than the states the electrons are currently occupying.
Some of these electrons will move to occupy the states with a higher probability of occupancy. The transport
mechanism will depend on the types of materials and the location in the material where contact is made:
1. For contact between two metals that are not alloyed together, the contact is at the surface and the electrons
have to physically leave one metal, pass through the vacuum between them and move into the other metal.
The possible transport mechanisms are thermionic emission and tunnelling.
2. For contact in a semiconductor doped P type on one side and N type on the other, the contact is inside the
body of the semiconductor. The transport mechanism is diffusion or tunnelling. A drift mechanism,
opposed to the movement of carriers will later be established, once the original movement creates a contact
potential.
3. In contact between metal and semiconductor, the contact is again at the surface and the transport
mechanisms are thermionic emission and tunnelling.
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The movement of charge carriers creates a net charge in the material close to the contact (for metals, the net
charge is only on the surface and does not penetrate inside the body of the metal). This charge creates a positive
potential on one material and a balancing negative potential on the other material. The material with a net
positive charge has its energy bands lowered while the material with a net negative charge has its energy bands
raised. The potential in the depletion region of the semiconductor varies with distance from the junction. The
bands in this region are therefore not flat but have a parabolic shape. The movement energy levels includes
the Fermi levels, which eventually align. Once the Fermi levels align, a dynamic equilibrium is reached and
there is no net movement of charge carriers. A potential difference, equal to the difference in work functions,
appears across the junctions.
A potential difference, equal to the difference in work functions, appears across the junctions.
2.3. Electrical Behaviour of Metal - Semiconductor Junctions

Metal-semiconductor junctions demonstrate two types of electrical behaviour; they can be rectifying or ohmic.
The behaviour depends on:
1. The conductivity of the semiconductor (i.e. N-type or P-type)
2. The value of the work function of the metal, Φm, relative to the work function of the semiconductor, Φs.
3. The doping concentration in the semiconductor. (NOTE: This affects the work function as in (2) above, but
also affects the width of the depletion region. This point refers to the second effect).
2.3.1. N Type Semiconductor – Metal Junction

2.3.1.1. Case 1: Φm > Φs
The formation of a contact between chromium (Φm = 4.5eV) and N-type silicon (Φs ≈ 4.1eV) in a vacuum is
shown in Figure 2.3. In this case, Φm > Φs.
Vacuum
Level
Electron
Movement
EC
EF
EF
EV
(a) (b)
(c)
Figure 2.3: Band Structure of junction between metal and N-semiconductor for (Φm > Φs): (a) Before
contact; (b) Immediately after Contact; (c) At Equilibrium
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Figure 2.3(a) shows the condition before contact is made. Each material is in its equilibrium position for the
given temperature, which is assumed to be around room temperature (300K). Since temperature is above 0 K,
there are some electrons above the Fermi level in the metal. There are also some electrons in the conduction
band in the semiconductor.
For quantum states that are above the Fermi level, the probability that a state is occupied by an electron
decreases with the energy difference from the Fermi Level. Some empty states above the Fermi level in the
metal are at a lower energy than the filled states in the conduction band in the semiconductor. They have a
higher probability of being occupied by an electron,
When the materials are brought into contact, the electrons in the conduction band of the semiconductor will
want to occupy the empty quantum states in the metal that have a higher probability of occupation. To do this,
the electrons will have to leave the silicon, pass through the small vacuum contact and enter the metal. This
requires energy, which comes from the thermal energy of the electrons. The process is thermionic emission.
There is net movement of electrons from semiconductor to metal as shown in Figure 2.3(b).
The movement of electrons from semiconductor to metal leaves a depletion region with a net positive charge
in the semiconductor. This net charge is balanced by a net negative charge on the surface of the metal. A
potential difference is formed from the contact surface and through the depletion region in the semiconductor.
This potential difference causes a movement of the energy bands (and the Fermi level) to a lower level in the
semiconductor. Eventually, the Fermi level in the semiconductor aligns with the Fermi level on the metal.
There is no more net movement of electrons and the equilibrium condition in Figure 2.3(c) is reached.
At equilibrium, the Fermi level in the neutral regions of the semiconductor (away from the depletion region)
will have moved a distance equal to the difference in the work functions (Φm - Φs). At the surface of contact,
the energy bands will not have moved. Moving from the neutral semiconductor towards the contact surface,
the energy bans bend upwards.
Electrons moving from the semiconductor to the metal will see a barrier equal to Φm - Φs. This can be lowered
or raised by application of an external potential difference which causes further movement of the energy bands
in the semiconductor.
Electrons moving from the metal to the semiconductor will have to move from the Fermi level in the metal
over a barrier that is at the position of the energy EC in the isolated semiconductor. The electrons see a barrier
that is equal to the difference between these energies. The barrier is called the Schottky barrier and cannot be
modified by biasing. Schottky barrier height:
φ =Φ −χ 2.11
The contact between metal and N-type semiconductor where Φm > Φs will therefore act as a rectifier.
2.3.1.2. Case 2: Φm < Φs

Now consider a case where an N-type semiconductor is in contact with a metal with a lower work function
(Φm < Φs). Metals with a lower work function than N-type silicon are not common. The condition is however
met by Group I and Group II metals e.g. magnesium (Φm = 3.7eV). The changes in energy bands is shown in
Figure 2.4.
The process in this case can be summarised as follows:
1. On contact, mobile electrons in metal find quantum states in the semiconductor that are closer to the Fermi
level (i.e. have a higher probability of occupancy).
2. Electrons move from metal to semiconductor,
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3. A region in the semiconductor close to the surface of contact with metal has an accumulation of electrons
and is negatively charged. Negative charge in the semiconductor is balanced by positive charge on the
surface of the metal.
4. Because of the negatively charged accumulation region in the semiconductor a negative potential is formed
and energy bands are raised. At equilibrium, Fermi level on semiconductor aligns with Fermi level on
metal, there is no net movement of electrons (Figure 2.4(c)).
Electrons in the accumulation region in the semiconductor is at the same energy level as the electrons above
the Fermi level in the metal. There is no barrier to electron movement from metal to semiconductor or vice
versa. Under an electric field, current will flow. The only barrier to current flow is the resistance of the metal
and semiconductor. The I-V relationship is linear (i.e. Ohmic), Figure 2.4(d).
(a) (b)
(c) (d)
Figure 2.4: Band Structure of junction between metal and N-semiconductor for (Φm < Φs): (a) Before
contact; (b) Immediately after Contact; (c) At Equilibrium; (d) I-V Characteristic
2.3.2. P-Type Semiconductor – Metal Junction

For P-type semiconductor, the Fermi Level is close to the valence band and there is a relatively large number
of empty quantum states in the valence band (holes). The changes in energy bands structure when P-type
silicon is brought into contact with a metal with a lower work function (Φm < Φs) is shown in Figure 2.5.
The process in this case can be summarised as follows:
1. On contact, mobile electrons in metal find quantum states in the semiconductor that are closer to the Fermi
level (i.e. have a higher probability of occupancy). These states are the holes in the valence band.
2. Electrons move from metal to semiconductor, neutralising the holes close to the surface of contact.
3. A region in the semiconductor close to the surface of contact with metal is depleted of holes and becomes
negatively charged. Negative charge in the semiconductor is balanced by positive charge on the surface
of the metal.
20
4. Because of the negatively charged accumulation region in the semiconductor a negative potential is formed
and energy bands are raised. At equilibrium, Fermi level on semiconductor aligns with Fermi level on
metal, there is no net movement of electrons (Figure 2.5 (c)).
5. The empty states in the valence band have moved up in the energy level by a distance equal to the
difference between the Fermi level in the metal and the top of the valence band in the semiconductor.
Electrons moving from the metal to the semiconductor will encounter this barrier.
The Schottky barrier height is given by:
φ =χ+ −Φ 2.12
Vacuum
Level
χs
φm
φs EC
EF
EF
EV
(a) (b)
χs+Eg-φm
EC
EF EF
EV
Metal + -- - Silicon
+ --
Net Charge +
+ --
(c) +
Figure 2.5: Band Structure of junction between metal and P-semiconductor for (Φm < Φs): (a) Before
contact; (b) Immediately after Contact; (c) At Equilibrium
Finally, a junction can also be made between P-type silicon and a metal where Φm > Φs it can be concluded
(and is found to be so) that in this case the junction will have no potential barrier and behaves like a low
resistance.
2.3.3. Summary
It is observed that a junction between a metal and a semiconductor may demonstrate either ohmic or rectifying
properties.
The behaviour is summarised in Table 2.1.
Table 2.1: Electrical Nature of M-S Contacts
Work Function Semiconductor → N-Type P-Type
↓
Φm > Φs Barrier No Barrier
Φm < Φs No Barrier Barrier
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A metal –semiconductor junction with rectifying properties has a Schottky Barrier with barrier height Bn (or
ΦBn) for N-type semiconductor and Bp (or ΦBp) for P-type semiconductor. The barrier height is equal to the
difference in energy between the Fermi Level in the metal and the location of the majority carriers in the
semiconductor (i.e. EC for N-type and EV for P-type semiconductor). A Schottky barrier exists when the energy
of the majority carriers is higher when at their normal location in the semiconductor (EC or EV) than at the
Fermi Level in the metal. It should be noted that in energy band diagrams, the energy of holes increases when
moving in a downward direction.
The Schottky barrier opposes the movement of majority carriers from the metal to the semiconductor.
The relationship between the barrier height for N-type and P-type semiconductor is given by:
+ ≈ 2.13
It is also noted that the practical barrier height observed for metal semiconductor junctions is usually lower
than the theoretical calculated values. The main reason for this is imperfections on the semiconductor surface
which affect the energy band behaviour at the boundary.
Example:
1. A piece of silicon (χ = 4.05eV) is doped with Nd = 1018cm-3.
a. Evaluate Φs. EFN – EFi = 0.48eV; Φs = 4.13eV
b. A junction is made between this material and chrome (Φm = 4.5eV).
I. Is the junction rectifying or ohmic? Rectifying
II. If rectifying, evaluate:
(1) Built-in potential. Φbi = Φm – Φs = 0.37V
(2) Schottky barrier height. ΦBN = Φm – χ = 0.45V
( )
(3) Depletion layer width on Si side under no bias. = = 22nm
(4) What is the width of the depletion region on the metal side? Explain. Zero. Not possible to
deplete metal
2. Repeat for silicon doped with Na = 1018cm-3.
Figure 2.6: Work Function of Different Metals (Sze)

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Table 2.2: Work Function and Barrier Contacts for Selected Metals (Hu (yellow highlight), Zeghbroeck
(Red or Clear), Green = Concurrence)
Metal Mg Ti Ag Al Au Cr Ni Pt W Mo
Φm (in Vacuum) 3.7 4.3 4.3 4.25 4.8 / 5.1 4.5 4.5 5.3 / 5.7 4.6 4.6
Measured Φbn 0.4 0.5 0.78 0.72 0.8 0.61 0.61 0.9 0.67 0.68
Measured Φbp 0.61 0.54 0.58 0.34 0.5 0.51 0.42
2.4. Schottky Diode Operation

A Schottky diode is made from a contact between an N-type semiconductor and a metal, with Φm > Φs.
External contacts are made on both the metal and the semiconductor. The contact on the metal is the anode
while the contact on the semiconductor is the cathode (Figure 2.7).
Figure 2.7: Schottky Barrier Diode: Symbol and Construction Schematic

Under forward bias, the positive contact of the emf source is connected to the metal while the negative contact
is connected to the semiconductor.
The energy band diagram of the Schottky diode with and without DC bias is presented in Figure 2.8.
Figure 2.8: Band Structure under: (a) No Bias; (b) Forward Bias; (c) Reverse Bias
23
Under no bias (Figure 2.8(a)), there is a barrier, ΦBn, restricting the movement of electrons from metal to
semiconductor. A smaller barrier restricts movement of electrons from semiconductor to metal (= Φm – Φs).
The movement of electrons from metal to semiconductor and from semiconductor to metal balance out in a
dynamic equilibrium. There is no net movement of electrons and no net current.
When the diode is forward biased, the semiconductor side (cathode) is connected to a lower voltage than the
metal side (anode). The energy bands are raised on the semiconductor side. Electrons see a lower barrier
moving from semiconductor to metal. The barrier from metal to semiconductor is unchanged. More electrons
will now move from semiconductor to metal than metal to semiconductor. The current density from metal to
semiconductor is unchanged, but the current density from semiconductor to metal is increased by a factor of
exp(qV/kT), where V is the biasing voltage.
There is net movement of electrons from semiconductor to metal, equivalent to a net current flow from metal
to semiconductor.
Under reverse bias, the energy bands on the semiconductor side are lowered while the bands on the metal side
remain the same. The electron flow from semiconductor to metal is reduced by a factor equal to exp(qV/kT),
with the biasing voltage, V, having a negative value. The net current is now from semiconductor to metal.
The current across a biased rectifying M-S contact is given as:
= ( − 1) 2.14
Where =
And K is the Richardson constant, which is related to thermionic emission. K ≈ 100 A/(cm2/K2)
This is similar to the PN diode equation. The main difference is the expression for Io, which is different from
a PN diode equation because:
• The main charge transport factor is thermionic emission, as opposed to diffusion in the PN junction.
• Only one type of charge carrier (electrons) is responsible for the current.
The I-V characteristics of the Schottky diode are shown in Figure 2.9. A comparison of the PN diode is
included.
It is noted that:
1. I0 of a Schottky diode is 103 to 108 times larger than a PN junction diode, depending on fB.
2. A larger I0 means a smaller forward drop V, which is about 0.3V for the Schottky diode compared to 0.6
– 0.7V for the PN diode.
3. A Schottky diode has a lower reverse breakdown voltage than PN junction diode.
4. A Schottky diode is the preferred rectifier in low voltage, high current applications.
5. There is no minority carrier injection at the Schottky junction. Therefore, Schottky diodes have shorter
switching times and can operate at higher frequencies than PN junction diodes.
Figure 2.9: Current characteristics of Schottky diode compared to PN junction diode. (Hu)
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2.5. Tunnelling Ohmic Contacts
Semiconductor devices are connected to each other in an integrated circuit through metal. The semiconductor
to metal contacts should have sufficiently low resistance so that they do not overly degrade the device
performance. A standard metal – semiconductor junction would act as a Schottky diode. It was observed
earlier (Table 2.1) that when the correct relationship between work function of metal and semiconductor is
achieved, metal – semiconductor contacts will be non-rectifying. This is not a satisfactory solution for Ohmic
contacts – in an electronic device or integrated circuit, different metals would require to be used for contact to
P-type and N-type semiconductors. Also, the metals with lower work function than silicon are mainly group
I and group II elements, which may not be good candidates for electrical interconnections.
The solution is to use Ohmic contacts that utilise quantum mechanical tunnelling of electrons between the
metal and semiconductor. In tunnelling Ohmic contacts, the semiconductor is very heavily doped (usually
degenerately ≈ 1019cm-3), which results in a very thin depletion layer (usually less than 1nm). The probability
of electrons tunnelling through a potential barrier increases as the width of the barrier and the barrier height
decreases.
The behaviour of tunnelling Ohmic contacts is presented in Figure 2.10.
Figure 2.10: Energy band diagrams for Ohmic contacts without and with bias (Hu)
The N-silicon is heavily doped and the Fermi level is at (or above) Ec. The depletion region is very narrow.
Depletion width is given by the one sided junction equation:
2 (|Φ − Φ | − )
= 2.15
Where V is the biasing voltage and N is the doping concentration in the semiconductor (Na for N-type and Nd
for P-type).
With no bias, barrier height is ϕBn and electron tunnelling for metal to silicon balances tunnelling from silicon
to metal. There is zero net current.
With a small voltage, V, applied, the barrier height from silicon to metal is reduced to (ϕBn -V). The barrier
from metal to silicon is unchanged. The probability of tunnelling from silicon to metal increases.
A net current flows from metal to silicon (there is net flow of electrons in the reverse direction).
Example: Aluminium (Φm = 4.25eV) is deposited on (a) N-type silicon; (b); P-type silicon.
1. Which of the two will be Ohmic and which will have rectifying properties? Φm > χ. N type will be rectifying.
Φm < χ+Eg. P-type will be rectifying (in theory). It should be noted that since silicon is soluble in
aluminium and also aluminium is an acceptor dopant in silicon, the interactions between the two materials
have the result that in practice, a junction between aluminium and P-silicon will be ohmic.
2. If the onset of tunnelling occurs when the width of the depletion region is 10nm, what is the maximum
doping concentration to ensure rectifying behaviour for:
a. Zero bias. 7.9 x 1017cm-3.
25
b. A bias that raises the total barrier potential from silicon to metal to 5V. (Assume Φm = 4.19eV and does
not change with doping). 6.6 x 1019cm-3.
3. Considering that aluminium is a Group III element, state one possible risk of using it in Ohmic contacts and
Schottky diodes. Some aluminium will dissolve in the silicon and change the dopant concentrations.
Aluminium and copper are the most widely used metals for ohmic contacts in semiconductor manufacturing.
The interaction of aluminium with silicon (silicon dissolves in aluminium and aluminium is an acceptor dopant
in silicon) causes imperfections in metal – aluminium contacts. In the manufacturing process, an aluminium
– silicon alloy is first deposited on the silicon before pure aluminium metal is deposited. The annealing
temperature is also strictly controlled. The alloy acts as a barrier to further dissolving of silicon in aluminium.
The interaction of aluminium and silicon in the manufacturing process changes the electrical behaviour of the
contacts from what is predicted by M-S contact theory.
Aluminium to moderately doped N-silicon forms a rectifying contacts. Tunnelling ohmic contacts are made
by heavily doping the area around the metal contact.
Aluminium to P-type silicon however forms an ohmic contact, unless the silicon is very lightly doped.
Another approach to contact manufacture is to have the contact to the silicon made out of a metal silicide
while the aluminium makes contact to the silicide. Semi-precious metals (Cobalt, Nickel, Platinum, Palladium)
and refractory metals (Titanium, Tungsten, Osmium, Erbium) form conducting silicides which have stable
contacts with silicon).
Table 2.3: Work Function of Silicon for Different Doping Concentrations

N-Type Si P-Type Si
Nd EFN - EFI φ Na EFI-EFP φ
1.00E+15 0.30 4.31 1.00E+15 0.30 4.91
5.00E+15 0.34 4.27 5.00E+15 0.34 4.95
1.00E+16 0.36 4.25 1.00E+16 0.36 4.97
5.00E+16 0.40 4.21 5.00E+16 0.40 5.01
1.00E+17 0.42 4.19 1.00E+17 0.42 5.03
5.00E+17 0.46 4.15 5.00E+17 0.46 5.07
1.00E+18 0.48 4.13 1.00E+18 0.48 5.09
5.00E+18 0.52 4.09 5.00E+18 0.52 5.13
26
Chapter 3. The Bipolar Junction Transistor
3.1. Transistor Overview
Transistors are three terminal semiconductor devices that are the basic components of amplifiers. Transistors
are also used as switches in digital electronics and power electronics. The term transistor is derived from
TRANSfer varISTOR in that it varies the transfer of the current at the input to the output – in most cases
amplifying the current.
The concept of an amplifier is presented in Figure 3.1. With a small signal applied to the transistor amplifier,
the transistor and its associated circuitry can produce an amplified version of the input signal.
iin iout
Gain, A
vin =Output / Input
vout
(a) (b)
Figure 3.1: Amplifier Concept: (a) Input, Output and Common; (b) Two Port
The input and output of an amplifier are related by a factor called the gain of the amplifier. The output signal
is equal to the input signal multiplied by the gain.
= 3.1
Transistors can be classified as follows:
1. Bipolar junction transistors (BJT). These are termed bipolar because they use both majority and minority
carriers in their operations. Their construction is based on the PN junction. They use input current to
regulate the output current.
2. Unipolar transistors. These use only majority carriers to conduct current. They use a voltage generated
electric field to regulate output current and are therefore also known as field effect transistors (FET). They
are further classified into:
a. Devices Based on PN or Metal Semiconductor Junctions:
i. Junction filed effect transistors (JFET). The control voltage is applied through a PN junction.
ii. Metal Semiconductor junction field effect transistors (MESFET). Similar to JFET but they use a
metal – semiconductor junction instead of a PN junction.
b. Metal oxide semiconductor field effect transistor (MOSFET). In these devices, the electric field is
applied through a capacitor made of a metal plate, silicon dioxide dielectric and semiconductor as the
second conducting plate (the MOS capacitor). Since the control terminal (gate) is insulated from the
conducting channel, the devices are sometimes termed as insulated gate transistors. MOSFETs are
further classified by conductivity type (P-channel or N-Channel) and by operating mode:
i. Enhancement mode – the device is normally not conducting. Conductivity is increased by
application of control voltage.
ii. Depletion mode – the device is normally conducting. Conductivity is reduced by application of
control voltage.
27
TRANSISTORS
BIPOLAR UNIPOLAR
NPN BJT PNP BJT JUNCTION INSULATED GATE
JFET MESFET N-CHANNEL P-CHANNEL

MOSFET MOSFET
Figure 3.2: Transistor Classification

The BJT, first demonstrated in 1947 was the first transistor to be commercially produced and dominated the
market for many decades. The MOSFET was developed around 1968. It has grown to be more popular than
the BJT, especially in integrated circuits. The main reasons for this are:
1. The BJT is current operated (base current) while the FET is voltage operated. As a result:
a. The BJT therefore has higher power consumption than FET.
b. The BJT has a lower input impedance than the FET.
c. For switching applications, it is easier to control a FET than a BJT (it is easier to have a steady
voltage than a steady current).
d. FET circuits can user a lower supply voltage and lower power consumption than BJT.
2. The BJT utilises minority carriers in the base while FETs utilises majority carriers only. In switching
applications, the minority carriers need to be cleared from the base. The switching speed is therefore lower
for BJT than for FET.
3. In integrated circuits it is possible to pack more units of MOSFET per unit volume of IC than of BJT.
The BJT has some advantages over MOSFET:
1. The BJT can handle higher voltages than MOSFET. This is useful for power electronics.
2. Because of sensitivity to low voltages, MOSFET devices are easily damaged by static electricity (touching
some devices may be sufficient to destroy them).
3. BJT amplifiers have lower output impedance than MOSFET amplifiers.
3.2. Construction and Nomenclature

The Bipolar Junction Transistor is a three terminal device consisting of two PN junctions. Forming two PN
junctions in one semiconductor devices can be achieved in two ways. The BJT is therefore classified based on
construction as NPN or PNP. In the NPN transistor, a P-type semiconductor is sandwiched between two N-
type semiconductors, while in the PNP transistor, an N-type semiconductor is sandwiched between two P-
type semiconductors (Figure 3.3).
(a) (b)
Figure 3.3: BJT Schematic Cross-Section: (a) NPN; (b) PNP
Terminals are connected (through Ohmic contacts) to each of the semiconductor regions. The centre region is
known as the base. One of the outer regions is more heavily doped than the other two regions and is known
28
as the emitter. The other outer region is known as the collector. The base is normally much narrower than the
emitter and collector. The collector is larger than the emitter.
3.2.1. Construction
In actual construction, the transistor is more complicated than the simplified representation in Figure 3.3. Early
transistors were made by alloying dopant material onto a piece of crystalline silicon, Figure 3.4(a). Current
technology includes diffused transistors and epitaxial transistors. The cross-section of an NPN integrated
circuit epitaxial transistor is shown in Figure 3.4(b).
N-Si Heat N
Al
Al
(a)
(b)
Figure 3.4: BJT Fabrication: (a) Alloy Junction: (b) Cross-Section of NPN Epitaxial BJT. Active area is
highlighted on the right (Identify Schottky Ohmic Contacts and Tunnelling Ohmic Contacts)
The emitter connection is in a heavily doped N type region, the base is in a moderately doped P-type region.
The collector terminal is in a heavily doped N-type region (to create an Ohmic contact). The effective collector
is actually the moderately doped N-type region between the P-type base region and the heavily doped N-type
buried layer. (Question: Why is the P-type base terminal connection not made to a heavily doped region?).
3.2.2. Voltage and Current Nomenclature
The circuit symbol of a BJT is shown in Figure 3.5. The emitter is differentiated from the collector by an
arrow pointing in the direction of a forward biased Base – Emitter junction. The arrow therefore points from
the P-type region to the N-type region.
Figure 3.5: Transistor Circuit Symbol and Nomenclature: Left: NPN; Right: PNP
Figure 3.5 also shows the currents and voltages in a transistor. The voltages have subscripts indicating the
terminals between which voltage is measured, with the order of the letters indicating the polarity (e.g. vBE is
voltage measured between base and emitter which vEB is measured between emitter and base). The currents
29
are indicated in the direction of positive current in the most common configuration (the active region). This is
against the IEEE standard on nomenclature requires that currents into a junction are positive while currents
out of a junction are negative (hence sum of currents at a junction is zero). With the convention used here, all
currents are positive. Hence the relationship between the currents is found by KCL as:
= + 3.2
KVL gives the voltage relationship as:
= + 3.3
The voltage and current symbols and subscripts are in lower case or upper case as follows:
Table 3.1: Convention for Symbols and Subscripts
Symbol Subscript Example Meaning
Lower Case Lower Case vce , ic AC values (small signal)
Lower Case Upper Case vCE , iC Combined AC & DC signals
Upper Case Upper Case VBE , IE DC signal values
Upper Case Upper Case VBEQ , ICQ DC Quiescent Values
Upper Case V Upper Case (Double) VBB , VCC DC Biasing Sources
Upper Case V Single Letter VB , VC, VE Terminal to Ground Voltage

From its construction, the BJT appears like two back to back diodes. The electrical characteristics of the device
are however very different from that expected from back to back diodes. The main reasons for this are the
small base width, the difference in doping concentrations of emitter and collector and the different biasing of
the junctions during operation.
3.2.3. Effective Device Dimensions
An NPN BJT is fabricated to have three regions doped N, P and N-type respectively. Each region has specific
doping concentration and physical width. The energy band diagrams of isolated N, P and N semiconductors
are shown in Figure 3.6. The different doping levels between the section that will form the emitter (on the left)
and the section to form the collector (on the right) can be observed in the different positions of the Fermi
Level.
EC
EC EC
EFN
EFN
EFi EFi EFi
EFP
EV EV EV
N P N
Figure 3.6: Energy Bands for isolated N, P and N Regions with Similar Doping to Emitter, Base and
Collector of BJT
When the NPN semiconductor is formed into one solid, the differences in work function between P and N
regions will cause movement of electrons across the junctions to states with higher probability of occupation.
The transport mechanism is diffusion. At equilibrium, the Fermi levels will align and the energy band diagram
will be like in Figure 3.7(a).
30
Figure 3.7: Energy Bands for, Depletion Regions and Built in Potential after Junction Formation
A depletion region forms around each junction, as shown in Figure 3.7(b). There is built in potential and
depletion region at each junction with a potential profile as shown in Figure 3.7(c). Due to the differences in
doping concentrations, it is found that:
1. The built in potential at the Base – Emitter junction is higher than that at the base – Collector junction.
2. The depletion region at the base – emitter junction is narrower than the one at the base – collector junction.
3. The depletion region at the base – emitter junction is mostly in the base. There is almost no depletion in
the emitter (one sided junction).
4. The depletion region at the base collector junction is wider in the collector than in the base.
The dimensions of the doped regions and charge concentrations are defined by the specifications in
manufacturing as well as the effects of junction formation. Some nomenclature for the band diagram is defined
in Table 3.2.
Table 3.2: Nomenclature for NPN Junction Analysis
Symbol
Description
Emitter Base Collector
XE XB XC Metallurgical Width of Emitter, Base and Collector
WE WB WC Effective Width (=Neutral Region, Excluding Depletion Region) of E, B and C
NdE NaB NdC Doping Concentration in Emitter, Base and Collector
pEo nBo pCo Equilibrium Minority Carrier Concentration in Emitter, Base and Collector
DpE DnB DpC Diffusion Coefficient in Emitter, Base and Collector
τpE τnB τpC Minority Carrier Lifetime in Emitter, Base and Collector
LpE LnB LpC Minority Carrier Diffusion Length in Emitter, Base and Collector
VbiBE Built in potential at Base – Emitter Junction
VbiBC Built in potential at Base – Collector Junction
WBE Width of Depletion Region at Base – Emitter Junction
WBC Width of Depletion Region at Base – Collector Junction
31
The metallurgical width of the individual regions (XE, XB and XC) and the doping concentrations are decided
at the manufacturing of the device. The other parameters (built-in potentials, depletion widths etc) are
calculated by applying the junction equations:
Built in = 3.4
potentials at the
junctions = 3.5
2 ( − ) 1
Width of = 3.6
+
Depletion
Regions 2 ( + ) 1
= 3.7
+
Equilibrium = ; 3.8
Minority
= ; 3.9
Carrier
Concentrations = ; 3.10
Of particular importance is the effective base width, WB and its relationship with the minority carrier diffusion
length in the base. WB is evaluated by subtracting the width of the part of the depletion regions that is contained
in the base.
2 ( − ) 2 ( + )
= − + 3.11
( + ) ( + )
The polarities of VBE and VCB should be entered with the first letter in the subscript as the positive reference
(e.g. VCB is negative is the base is at a higher potential than the collector).
The diffusion length of minority carriers in the base is evaluated as:
= 3.12
The diffusion constant varies with carrier concentrations. Data on carrier mobility for different values of
minority concentration is normally available, and the diffusion constant can be evaluated from the mobility
using Einstein’s relationship. The minority carrier lifetime is also a property of the semiconductor.
In order to achieve transistor action (explained in next section), the following should be considered in device
construction:
1. The effective base width, WB should be much less than the diffusion length for minority carriers in the
base, LnB.
≪ 3.13
2. The effective width of the collector should be larger than the effective width of the emitter.
3. The doping concentration in the emitter should be higher than the doping concentration in the base. The
doping concentration in the base should be higher than the dopant concentration in the collector.
> > 3.14
32
3.3. Charge Flow and Transistor Action
In operation, DC voltage sources, the biasing voltages are applied across both junctions. With two junctions,
there are four possible ways of biasing. The selected biasing determines the operating region as presented in
Table 3.3.
Table 3.3: BJT Biasing for Different Operating Regions
Operating Region Base – Emitter Junction Base – Collector Junction
Active Forward Biased (VBE is positive) Reverse Biased (VCB is positive)
Saturation Forward Biased (VBE is positive) Forward Biased (VCB is negative)
Cut Off Reverse Biased (VBE is negative) Reverse Biased (VCB is positive)
Inverse Active Reverse Biased (VBE is negative) Forward Biased (VCB is negative)
3.3.1. Transistor Action

In the active region, the base – emitter junction is forward biased while the base – collector junction is reverse
biased, Figure 3.8. The collector – base reverse bias voltage is higher than the base – emitter forward bias
voltage (VCB > VBE).
Figure 3.8: Supply Voltage Connections in Forward Active Region

The potential barrier at the base – emitter junction is lowered by a value equivalent to VBE while that at the
base – collector diagram is increased by a value equivalent to VCB. The band diagram is shown in Figure 3.9.
Also, the depletion regions narrows at the base – emitter junction and widens at the base – collector junction.
Figure 3.9: Energy Band Structure in Forward Active Region

Like in the PN junction, the changes occurring with the biased junctions will cause charges to flow across the
junction. The differences in the design of the three regions will however affect the flow of charges. The flow
of charges is shown in Figure 3.10.
Electrons from the emitter are injected across the base – emitter depletion region into the base. Also holes are
injected from the base into the emitter. Under the ideal-diode condition, there is no carrier generation or
recombination current in the depletion region; the injected electrons and holes constitute the total emitter
current. Since the emitter is more heavily doped than the base, more electrons are injected across the junction
than holes and the main component of the current is by electron flow. The situation is described as electrons
being emitted from the emitter into the base, hence the term emitter.
33
Figure 3.10: Charge Flow in Forward Active Region
Since the base width is much narrower than the diffusion length of the injected electrons, most of the electrons
injected from the emitter diffuse through the base and reach the edge of the depletion region at the base-
collector junction. The reverse biased base – collector junction is very favourable to electron flow from base
to collector. The electrons that reach the depletion edge are therefore pulled across the depletion region into
the collector (they are collected). Thus the emitter emits carriers which are collected by the collector.
The collector-base junction is reverse biased, and a small reverse saturation current will flow across the
junction. This current consists of electrons flowing from base to collector and holes from collector to base.
Also, some of the electrons from the emitter recombine with holes in the base, hence ‘exiting’ at the base
terminal. The holes will be replaced by electrons moving to the external circuit through the base terminal.
These constitute the base current.
With a construction that includes a heavily doped emitter, a lightly based collector and a medium doped narrow
base, there is a large number of emitted electrons, most of which reach the collector without recombining with
electrons in the base region. The collector electron current is very close to the emitter electron current.
Therefore, carriers injected from a nearby emitter junction can result in a large current flow in a reverse-biased
collector junction. This is the transistor action: - the modulation of the current flow in one PN junction by
changing the bias on a nearby junction. A large current can flow from the emitter terminal, across a reverse
biased junction and out of the collector terminal. The current is a function of the biasing at the two junctions
(VBE and VCB).
In order to achieve transistor action, a BJT needs to fulfil some construction and biasing requirements:
1. Construction:
a. Base width should be narrow. It is also helpful if collector width is larger than emitter width.
b. Emitter should be more heavily doped than base and base should be more heavily doped than collector.
2. Biasing – Should be in active region, i.e. base – emitter junction forward biased and base – collector
junction reverse biased.
When the emitter is much more heavily doped than the base, electron injection will dominate and will be many
times more than hole injection across the BE junction. Also, a proportional change in the hole injection from
base to emitter will cause the same proportional change in the electron injection from emitter to base.
The electron injection constitutes the collector current while the hole injection is the dominant component in
the base current. The proportional relationship between the small hole injection and the larger electron
injection constitutes a current gain for the bipolar transistor.
34
3.3.2. Current Gain
The flow of charges across the BJT junctions which was presented in Figure 3.10 can further be represented
as components of currents as shown in Figure 3.11.
Emitter (N) Base (P) Collector (N)
IE,n IC,n
IE,n IC
IB,n
IE,p ICBO
IB
VBE VCB
Figure 3.11: Transistor Current Components

The current components resulting from this flow of charge are given in Table 3.4. It should be noted that this
model assumes that there is no charge recombination in the depletion regions.
Table 3.4: BJT Current Components
IE,n Emitter current flow due to electrons injected into base
IC,n Collector current flow due to electrons crossing from emitter through base
IE,p Emitter current flow due to holes injected from Base
IB,n Base current flow due to electron recombination with holes in Base
ICBO Reverse saturation current of B-C Junction (p from B to C and n from C to B)
The subscript O in ICBO indicates that the current is measured with emitter open circuited. In order to achieve
transistor action, it is desirable that most of the emitter current is due to electrons injected into the base (IE,n)
and that most of this current reaches the collector, i.e. is not lost to recombination in the base. Two parameters
to monitor this are emitter efficiency and base transport factor.
The total emitter current, IE is the sum of current due to emitted electrons and current due to holes injected
into emitter from base.
I = , + , 3.15
In order to ensure transistor action, it is desirable the emitter current is mainly due to electrons injected into
base. The emitter efficiency, γ, is the ratio of emitter current due to charges injected into base to the total
emitter current.
, , 3.16
γ= =
, + ,
Some of the electrons injected into the base recombine with holes and do not reach the collector. It is desirable
that all the electrons injected into the base reach the collector. The ratio of collected emitter current to the total
injected current is called the base transport factor, γTB (or in some texts, αTB).
,
γ = 3.17
,
The product of the emitter efficiency and base transport factor is known as the transistor alpha, α.
35
,
α= 3.18
The transistor alpha is also known as the common base current gain. The collector current is the sum of the
current due to collected electrons and the reverse saturation current of the CB junction.
= , + 3.19
Also, KCL with complete BJT as one node gives:
= + 3.20
Combining the equations 3.18, 3.19 and 3.20 results in:
= , + = + = ( + )+
= + 3.21
= + = ( + )+
= +
(1 − ) (1 − )
= + 3.22
Where β is common emitter current gain which is the ratio of collector current, IC, to the base current, IB.
β= = 3.23
(1 − )
Also, the collector-emitter leakage current for IB = 0 is designated ICEO.
= 3.24
(1 − )
This equations are valid for a transistor operating in the active region. Under those conditions, βIB >> ICEO and
αIE >> ICBO. The current relationships can therefore be approximated as:
= 3.25
= 3.26
3.3.3. Bipolar & Minority Carrier Device
The BJT is often describes as a bipolar device and also a minority carrier device:
• A Bipolar Device because both holes and electrons are involved as charge carriers to achieve the device
currents.
• A minority carrier device because the output current, iC, is mostly composed of the current component iE,n
of minority carriers injected into the base.
Example: A bipolar transistor with an emitter current of 1 mA has an emitter efficiency of 0.99 and a base
transport factor of 0.995. Calculate the base current, the collector current and the current gain of the transistor
(common base and common emitter). Answer: α = γ*αT = 0.99*0.995 = 0.985; β = α/(1-α) = 0.985/(1-0.985)
= 65.67. IC = αIE = 1*0.985 = 0.985mA; IC = βIB ; IB = IC /β = 0.985/65.67 = 15μA.
Example (Sze): For an ideal NPN transistor, the current components are given by IEn = 3mA, IEp = 0.01mA,
ICn = 2.99mA and ICp = 0.001mA. Determine the emitter efficiency, base transport factor, the current gains
and ICBO. Answer: γ = IEn / (IEn + IEp) = 3/(3+0.01) = 0.9967 ; αT = ICn / IEn = 2.99/3 = 0.9967. α = γ*αT =
0.9967 * 0.9967 = 0.9934; β = α/(1-α) = 0.9934/(1-0.9934) = 150.5; IC = ICn + ICp = 2.99 + 0.001 =
2.991mA; IE = IEn + IEp = 3 + 0.01 = 3.01mA; IC = αIE + ICBO; ICBO = IC - αIE = 2.991 – 0.9934 * 3.01 =
0.866μA.
36
3.4. Transistor Operation in Active Region
The complete current voltage relationship for a transistor can be described by analysis of carrier distribution
under different bias conditions. The analysis assumes the following:
1. The device has uniform doping in each region.
2. There is no drift current in the base region.
3. The collector saturation current of the collector – base junction (ICBO) is negligible.
4. There is low-level injection, i.e. the majority carrier concentration is not affected by carrier injection in
any region.
5. There is no carrier generation or recombination in the depletion regions.
6. All the regions of the device have zero resistance.
A qualitative view of the carrier distribution is presented here, with a review of changes observed for different
biasing conditions. Expressions for the currents (IS and IB) and current gains (α and β) will also be presented.
3.4.1. Minority Carrier Distribution in Active Region
For a BJT without dopant compensation, the majority carrier concentration is equal to the dopant
concentration, since 100% dopant ionisation is usually true. The equilibrium minority carrier concentration
can be evaluated using the mass action law as described in equations 3.8, 3.9 and 3.10.
A PN junction under forward bias experiences minority carrier injection across the junction. Under reverse
bias, minority carrier extraction occurs. The effect of biasing a PN junction is therefore to change the minority
carrier concentration at the edge of the depletion region by a factor of exponential (qV/kT), where V is the bias
voltage. The concentration is increased for a forward bias junction and reduced for a reverse biased junction.
Diffusion of minority carriers in the neutral regions away from the depletion region works to restore the
equilibrium concentration of minority carriers. This process is described by the continuity equation and results
in an exponential recovery of the minority carrier concentration as in Figure 3.12.
- + N
- +
N P
- +
- +
Carrier Density
nB(E)
pE pC0
nB0
pE0 pC
nB(C)
Figure 3.12: Minority Carrier Concentrations at Forward Biased and Reverse Biased PN Junctions
For a P or N region whose effective width is much less than the diffusion length, it is found that the recovery
of minority carrier concentrations is not an exponential relation with distance. Instead it is a straight line, with
the minority carrier concentration reverting to the equilibrium concentration at the end of the doped region.
In the active region, the base – emitter junction is forward biased (magnitude of bias is vBE) while the base –
collector is reverse biased (magnitude of bias is vCB). For the base region of an NPN transistor, there is injection
of electrons at the base – emitter junction and extraction of electrons at the base collector junction. On the
other sides of the junctions, holes are injected into the emitter and extracted from the collector.
37
The electrons injected from the emitter to base form the emitter electron current, IE,n. The concentration of
excess carriers will reduce as they diffuse through the neutral region of the base. Because the effective base
width is much less than the minority carrier diffusion length in the base (WB << LpB), the concentration of
minority carriers in the base will drop linearly with distance to the equilibrium condition over the effective
base width (excess carriers will drop to zero). The concentration profiles is shown in Figure 3.13.
E Base C
Concentration cm-3
nB(x=0)
nB(x=0)
pE pC0
nB0
pE0 pC
WB
x=0 x
Figure 3.13: Minority Carrier Concentrations for NPN Transistor in Active Region
3.4.2. Collector Current
The electron concentration on the base side of the base – emitter junction is given by:
( = 0) = 3.27
2
The equilibrium concentration, nBo = ni /NaB. The electron concentration at the collector end of the base neutral
region is nBo, with the concentration falling in a straight line over the effective base width. WB. At the edge of
the depletion region, the diffusion of these electrons constitutes the total emitter electron current. Diffusion
current is given by:
=−
In the case of the injection of electrons from emitter to base, the resultant current is therefore:
−1
, = =
, = −1 3.28
For silicon BJT, the recombination current in the base is very low. It can therefore be estimated that the
collector current is equal to the emitter electron current. Then:
= −1 3.29
The negative sign indicates that the current is in the opposite direction to the electron diffusion. This can be
expressed like the diode equation as:
= −1 3.30
with =
From the expression for ISC, it can be concluded that for a given value of VBE, the collector current can be
increased by:
1. Increasing the cross-sectional area of the base – emitter junction.
2. Reducing the doping concentration in the base.
38
3. Reducing the effective base width.
The first concept is known as emitter scaling and is applied when it is desired to have a transistor that delivers
high current. The second and third approaches are also applied in design (as mentioned earlier), but there are
limits to the extent they can be applied without incurring other negative effects.
It should also be noted that the collector current increases with the square of the intrinsic concentration. The
collector current therefore increases with the temperature of the device. This makes the device prone to thermal
runaway.
3.4.3. Base Current
In the evaluation of the collector current, both the base recombination current and ICBO were assumed to be
zero. With those assumptions, the base current is solely due to holes injected from base to the emitter. The
hole concentration on the emitter side of the base – emitter depletion region is given by:
( = 0) = 3.31
Where pEo = ni2/NdE. The hole concentration at the emitter contact is pEo. The change in hole concentration
over the width of the emitter neutral region (WE) depends on the relationship between WE and the hole diffusion
length in the emitter, LpE. If it is assumed that WE << LpE, then the concentration will fall linearly over the
length WE. At the edge of the depletion region, the diffusion of these holes constitutes the total base current.
Therefore:
= −1 3.32
with =
For a BJT whose WE > LpE, the denominator will change, with LpE replacing WE.
3.4.4. The Transistor β
The common emitter current gain is therefore given by:
= = ×
= 3.33
This is the common emitter current gain and it is desirable to have a high value in order for the transistor to
act as an amplifier. This will be achieved by:
1. The emitter dopant concentration should be higher than base dopant concentration.
2. The emitter effective width should be larger than the base effective width.
3. The minority carrier diffusion coefficient in the base should be higher than the minority carrier diffusion
coefficient in the emitter. This is always true for NPN transistor, since electrons have higher mobility than
holes. It is not true for PNP transistors.
3.5. BJT Minority Charge Distribution for Different Operating Regions

The analysis of the BJT so far has been for the active region. The operating region is determined by the biasing
of the base emitter - junction and the base – collector junction. The biasing voltages are VBE and VCB and they
are related as (Figure 3.14(e)):
= + 3.34
39
The biasing determines the flow of minority carriers and hence the electrical behaviour of the device.
(a) (b)
(c) (d)
(e)
Figure 3.14: Minority Carrier Distribution for NPN Transistor in: (a) Cut Off; (b) Forward Active Region;
(c) Saturation; (d) Inverse Active Region; (e) Basic Biasing Circuit
3.5.1. Cut-off Region
In the cut off region, both junctions are reverse biased. There is carrier extraction at both junctions, resulting
in the minority carrier profile in Figure 3.14(a). Minority carrier concentration in the base is zero and only the
reverse saturation currents flow. The collector current is practically zero.
3.5.2. Active Region

Suppose the reverse bias of the base – collector junction is maintained while VBE is increased to a positive
value. Minority carrier injection will start, increasing the transistor currents. However, appreciable emitter
(and hence collector) current will not flow until VBE is equal to or above the diode forward drop, which is
40
about 0.7V for a silicon. The actual changeover from cut off the active occurs for VBE is approximately 0.5V.
Complete active region status will be achieved when VBE is equal to the forward diode drop, approximately
0.7V.
With the base – collector junction reverse biased and VBE at the forward diode drop, a large injection of
minority carriers from emitter to base occurs. The minority carrier distribution in Figure 3.14(b) is achieved
and large values of collector and emitter currents is achieved.
The collector current is (almost) independent of the base – collector biasing voltage (VCB) as long as the
junction is reverse biased (VCB > 0). Collector current, iC is fully controlled by base current, iB (iC = β iB). The
output voltage, vCE = vCB + vBE is controlled by the drop across the collector resistor and has a vary ranging
from about 1 volt to a value close to biasing voltage VCC, with collector current remaining constant.
3.5.3. Saturation Region
If the forward bias at the emitter base junction, VBE is increased further, the collector current, iC continues to
increase and the voltage drop across the collector resistor increases. This reduces the reverse bias of the base
– collector junction since VCB =VCC -VBE-ICRC. Eventually VCB will become negative and the junction goes
into forward bias.
With both B-E and B-C junctions forward biased, there is minority carrier injection at both junctions. The
minority carrier distribution eventually reaches the condition presented in Figure 3.14(c). The base is said to
be saturated with minority carriers. Since the minority carrier concentration at the collector edge of the base
neutral region is now high, the concentration gradient is low and thus diffusion current is reduced. A large
collector current will still flow but it is not as high as in the active region. This iC < β iB. Also, the collector
current now varies with the base – collector biasing voltage (VCB) and hence with VCE.
3.5.4. Inverse Active Region
The Base – emitter junction is reverse biased while the base –collector junction is reverse biased. The transistor
operates like in the active region. However, the values of the current gain parameters, αR and βR (where the
subscript R stands for reverse region) are much lower because the unsymmetrical doping of the emitter and
collector regions is not suited for high current gain in this region. There is less carrier injection into the base
and higher majority carrier base current.
Example: A silicon NPN transistor has the following parameters: Emitter width = 2μm; Base width = 1.5μm;
Collector width 4μm; NaB = 1017cm-3; NdE = 1019cm-3; NdC = 5 x 1015cm-3 and minority carrier lifetimes in
emitter, base and collector of 10-8, 10-7and 10-6s respectively.
1. Evaluate the following for no bias condition:
a. Equilibrium minority carrier concentrations in Emitter, Base and Collector. No dopant compensation:
≈ ; ≈ ; ≈ ; ≈ ; Emitter: 10cm-3; Base: 103 cm-3; Collector: 2 x
104 cm-3.
b. The build in potentials at the BE and BC junctions. = ; = . BE:
0.954Volts; BC: 0.757Volts.
( ) ( )
c. The effective base width, WB. = − ( )
+ ( )
= 1.5 x 10-4cm – (1.114
x 10-5cm + 2.18 x 10-6cm) = 1.37 x 10-4cm. No bias ≡ VBE = VCB = 0
d. The transistor β. = = 0.0259 * 750 = 19.425cm2s-1; = = 0.0259 * 80 = 2.072
cm2s-1; = = sqrt(19.425 x 10-7) = 1.39 x 10-3cm. > ; = =
41
.
sqrt(2.072 x 10-8) = 1.44 x 10-4cm. Assume = ; ; . .
= . β = 985. NOTE: Use cm for length throughout
2. If the transistor is biased with VBE = 0.8V and VBC = -0.7V:
a. Evaluate VCE. = 0.7 + 0.8 = 1.5V.
b. What is the operating region of the transistor? NPN transistor; BE Junction is Forward Biased; BC
Junction is Reverse Biased. BJT is in Active mode.
c. Evaluate the minority carrier concentration at either end of the BE and BC junctions. At BE junction:
( = 0) = ; Similarly for pE, and for BC junction.
Assume none of the regions has dopant compensation.
3.6. BJT Characteristics

Characteristics is the name given to the relationship between current and voltage in a device.
3.6.1. BJT Operating Configurations
As a three terminal device, the BJT is normally connected in circuit with one terminal as input, one terminal
as output and one terminal shared between input and output. The shared terminal is called the common
terminal and is normally connected to ground. We therefore have the configurations as in Table 3.5.
Table 3.5: Transistor Configurations
Configuration Input Output Gain, Av, Ai Rin Rout Phase
Common Base Emitter Collector High, ≤ 1 Low High 0°
Common Emitter Base Collector High, High Medium Medium 180°
Common Collector Base Emitter ≤ 1, High High Low 0°
3.6.2. BJT Characteristics

The output of a transistor in common emitter configuration is the collector current. The collector current is a
function of emitter current, iE through the collected electrons. The emitter current is itself a function of the
base emitter voltage, vBE (this can also be represented as iC being a function of base current, iB). The collector
current is also a function of the collector emitter voltage, vCE especially in the cut off and saturation operating
regions. In total, the BJT has six variables, of which four are independent (three currents, three voltages).
The multiple current and voltage relationships can be captured in a family of curves known as characteristics.
The Characteristics refer to the relationship between voltage and current. It is a plot of the voltage against
current, with the independent variable on the x-axis and the dependent variable on the y-axis. Transistors have
different characteristics depending on the configuration. For each configuration, we can have three sets of
characteristics. For example the common emitter configuration has the characteristics as in Table 3.6.
42
Table 3.6: Common Emitter Transistor Characteristic Variables
Characteristic x- Axis y-axis
Input Characteristic Base – Emitter Voltage (VBE) Base Current (IB)
Transfer Characteristic Base – Emitter Voltage (VBE) Base Current (IC)
Output Characteristic Collector – Base Voltage (VCE) Base Current (IC)
The output characteristics of the common emitter transistor can be measured using the circuit in Figure 3.15.
Figure 3.15: Circuit for Measuring CE Output Characteristics

The characteristics are as shown in Figure 3.16.
(a) (b)
(c)
Figure 3.16: Characteristics of Common Emitter BJT: (a) Input; (b) Transfer; (c) Output
The input characteristics are equivalent to the characteristics of a PN diode. Once the base – emitter junction
is biased to a few tenths of a volt, there is little change in vBE for a large change in iB. The base current iB is
therefore considered to be a better choice of control parameter than vBE. The base current is independent of
vCE, as long as vCE is large enough (> 0.2V) to keep the base collector –base junction in non-conducting state.
The transfer characteristics (iC against vBE) are also similar to the characteristics of a PN diode.
43
Ideally, the output characteristics should present iC against vCE for different values of vBE. However, since iC
has a very large change for small changes in vBE, it is usual to plot the characteristics for different values of iB
as in Figure 3.16(c). From the characteristics, it is possible to identify the operating region of the transistor:
1. The cut-off region, where both junctions are reverse biased. It should be noted that the base – emitter
voltage does not have to be negative as long as vBE << 0.7 volts so that iB ≈ 0A. Collector current is almost
equal to zero, irrespective of the value of vCE.
2. The saturation region, where vCE < vBE, which means the collector – base junction is forward biased (as is
the base-emitter junction). Collector current, iC is high but is less than β iB. The junction do not need to be
fully conducting, but
3. The active region, where base emitter junction is forward biased while base collector junction is reverse
biased. In this case, iC = β iB
3.6.3. Departure of Characteristics from Ideal Behaviour
The derivation of minority carrier flow in a BJT and hence the characteristics made some assumptions. At the
extremes of each operating region, these assumptions may no longer be valid and the effect is then noticeable
on the characteristics. The effects that are noticeable on the characteristics include carrier recombination in
depletion regions, high level injection, base width modulation (Early Effect) and junction breakdown.
3.6.3.1. Space Charge Recombination and High Level Injection
In the active region, the base current is related to the collector current by the expression iC = βiB This is the
result of both currents being related to the base emitter voltage, vBE by the exponential diode equation. A semi
log plot of both input characteristics (iB against vBE) and transfer characteristics (iC against vBE) should result
in a linear plot. This is found not true in practice, as can be observed in Figure 3.17(a).
(b)
Figure 3.17: (a) iB and iC as a function of vBE (semi-log plot); (b) Variation of β with iC
It can be noted that:
1. The input characteristic deviates from the expected linear plot for low values of vBE. This can be explained
as due to electron – hole recombination in the depletion region of the base – emitter junction. This
increases the base current but has negligible effect on the collector current. The effect is a reduction in the
value of β. Recombination in the depletion region was assumed to be negligible in derivation of BJT
currents. The small recombination current cannot however be ignored at low levels of iB. Recombination
44
in the depletion region can be almost eliminated by eliminating impurities in the silicon. This is done by
heat treatment during the manufacturing process.
2. At high values of vBE, it is noted that the curve for iC deviates from the expected linear plot. This is the
result of high level injection. At high values of vBE, the carriers injected into the base (and the emitter)
are large enough to affect the concentration of majority carriers. This reduces the diffusion current. Since
there is more carrier injection into the base than the emitter, the effect is more pronounced for the collector
current. The effect in the base reduces the collector current. The lower effect in the emitter reduces the
base current. Since the collector current is more affected than base current, there is reduction in β.
Recombination and high level injection also affect β which does not remain constant throughout the active
region. It can be noted in Figure 3.17(b) that as iC increases from near zero, β first increases, reaches a peak
and then decreases.
BJT amplifiers will normally operate at medium levels of iC where β is stable. However, high-speed circuits
operate at high iC, while low-power circuits may operate at low iC. Current gain, β, drops at both high iC and
at low iC.
Example: An NPN transistor has the base doped to a concentration of NaB = 1017cm-3. Determine the
maximum value of VBE that avoids high level injection. (ANS: 0.775Volts)
3.6.3.2. Base Width Modulation: -The Early Effect
The analysis of BJT concluded that in the active region, the collector current, iC is independent of the collector
emitter voltage, vCE. In practice, it is found that the collector current increases with vCE, as presented in Figure
3.18. It is observed that the characteristics are not flat in the active region, but instead, collector current
increases with collector – emitter voltage. If the curve is extrapolated backwards to the vCE axis, it is found
that the crosses the axes at the same voltage, irrespective of the base current. This voltage is known as the
Early Voltage, VA and the behaviour is known as the Early effect.
Figure 3.18: The Early Effect

The cause of the Early effect is that an increase in vCE increases the reverse bias of the CB junction, vCB which
in turn increases the width of the depletion region at this junction. The effect is to reduce the effective base
width, , WB. This increases the collector current, iC, (as well as the common emitter current gain, β). The effect
is demonstrated in Figure 3.19.
45
Figure 3.19: Effective Base Width for Difference Values of vCE (Early Effect).
The Early effect means that the dynamic resistance of the collector in the active region is not infinite, but is
instead ro, which is the inverse slop for the output characteristic. A large VA (i.e., a large ro) is desirable for
high voltage gains. A typical VA is 50 V. Since the Early voltage is usually much larger than the operating
value of vCE, the output resistance can be approximated as:
+
= = ≈ 3.35
VA can be increased by selecting design parameters of the transistor that:

1. Metallurgical width of the base, XB, is increased. This reduces the sensitivity of effective base width to
collector – base voltage.
2. The doping concentration in the base, NaB is increased. This reduces the width of the BC depletion region
on the base side.
3. The doping concentration in the collector, NdC is decreased. This increases the width of the BC depletion
region on the emitter side (and decreases it on the base side).
The first two solutions are not desirable because they would also reduce the transistor β. The third solution is
therefore the only acceptable one. . It also reduces the base–collector junction capacitance, which is a good
thing. Therefore, the collector doping is typically ten times lighter than base doping.
Punch-through is the extreme case of base width modulation where the base-collector junction space charge
layer reaches through to the emitter and the effective base width, WB is zero. This causes the collector current
to increase uncontrollably and all transistor action is lost. If the current is not limited by the external circuit,
the device will be destroyed by heat.
3.6.3.3. Junction Breakdown
Like the PN diode, the BJT is susceptible to junction breakdown under reverse bias. The BJT has two junctions
where breakdown can occur. The base – collector junction is normally reverse biased and will be the most
likely to experience breakdown. The breakdown voltage of the Base – Collector junction is known as VCBO.
In practice, due to transistor action having an amplification effect on flow of charge. The breakdown occurs
at a lower voltage than VCBO which is known as VCEO.
Once breakdown occurs, the collector current will continue to increase with no change in base – emitter
voltage. The current can only be limited by the external circuit. The output characteristics bend upward as in
Figure 3.20.
46
The junction breakdown is the determining factor in setting the maximum voltage rating of a transistor.
Figure 3.20: CE Output Characteristics showing junction breakdown and maximum power.
3.6.3.1. Maximum Power Dissipation
The BJT has current passing through it and it also has a voltage drop across it. Work is done in driving charges
through a potential difference. The power used to drive the charges is dissipated as heat in the transistor. The
power dissipated is iC*vCE. The dissipated power causes the temperature of the device to rise. The conduction
of heat away from the device will increase with temperature until the heat generation matches dissipation and
a stable temperature will be achieved. Each device has a maximum temperature it can withstand without
damage. The power dissipation that will not lead to a temperature exceeding the maximum temperature is the
maximum power output of the device. A locus of the product iC*vCE that equals this maximum dissipation
marks the operating limit of the device (the red dashed line in Figure 3.20).
3.6.4. Biasing Voltages and Operating Region

The transistor operating region depends on the biasing status of the two junctions. The base –emitter junction
is forward biased in the active and saturation regions while the base – collector junction is forward biased in
the saturation region. Since the base – emitter voltage is the controlling parameter, it is necessary for the
junction to be fully forward biased (i.e. have a voltage drop equal to or slightly greater than the forward drop
of a forward biasing diode, 0.6 – 0.7V) in order for the BJT to be in the active or saturation region. For the
base – collector junction, the requirement for saturation is that the junction should not be reverse biased. It
does not need to achieve the forward drop of a diode.
The changeover from active to saturation region occurs when VCB < -0.4V, since below this voltage, the
junction is still well below the forward conducting voltage of a diode. The collector – emitter voltage at the
changeover is approximately vCE = vCB + vBE ≈ 0.2 Volts.
47
Typical Values for NPN Si Transistor
Parameter Value (Volts)

v CE(sat) 0.2
v BE(sat) 0.8
v BE(active) 0.7
v BE(cut-in) 0.5
v BE(cut-out) 0
Figure 3.21: BJT Changeover from Active Region to Saturation

The changeover from active to saturation can be summarised as:
1. Soft saturation: 0.7 ≥ vCE ≥ 0.3 V (for Si) VCB ≥ -0.4 V (for Si), diffusion current is small and iC is very
close to its active-region level. (iC ≈ β iB).
2. Deep saturation region: 0.1 < vCE ≤ 0.3 V (Si) or vCE ≈ 0.2 V = Vsat (Si), iC is smaller than its active-region
level (iC < β iB).
3. Near cut-off: vCE ≤ 0.1 V (Si) Both iC & iB are close to zero.
3.6.5. Transistor Applications

Transistors have two main applications, as switch and as an amplifier.
A switch requires the following characteristics:
1. Zero voltage drop and high current flow when in closed (ON) position. This is approximated by the
transistor in the saturation region.
2. Zero current and high voltage drop when in open (OFF) position. This is approximated by a transistor in
the cut-off region.
An amplifier requires a linear relationship between the input signal and the output signal. In the cut-off and
saturation regions, the output of a BJT is almost independent of input. For a BJT operating in the active region,
there is an almost linear relationship between input and output current in a transistor (iC = β iB). The BJT can
therefore serve as a current amplifier when in the active region. The following modifications are however
necessary:
1. To ensure that the BJT amplifier operates in the active region where linear amplification is obtained, DC
biasing voltages are applied to fix an operating point (quiescent point) in the middle of the active region.
2. AC signals to be amplified are superimposed on the DC biasing signals and cause variations around the
operating point. The AC signals have to be much smaller than DC biasing signals to ensure linear amplifier
operation. (Rule of thumb: A small signal is equal to or less than one tenth of equivalent biasing value,
e.g. ic ≤ 0.1ICQ)
3.7. DC Analysis of BJT Circuits

DC analysis is carried out for both switching circuits and amplifier circuits. In switching circuits, DC analysis
is required to establish the supply required at the base in order to drive the transistor into saturation and
therefore achieve ON status for the switch. In amplifier circuits, DC analysis is required in order to determine
the operating point of the amplifier.
48
3.7.1. Determining Operating Region of Transistor
First a look at how to determine the operating region of a BJT circuit. This is done by the approximation
method and involves four steps (it can end at any of steps 2, 3, or 4).
STEP 1: Write down KVL equations for base emitter (input) loop and collector – emitter (output) loop).
STEP 2: Assume BJT is OFF, hence IB = 0 and IC = 0. Use BE-KVL to confirm VBE < 0.7V. If yes – confirmed.
If No, move to next step.
STEP 3: Assume is in active region. VBE = 0.7V. Use KVL in BE loop to evaluate iB. Set IC = β IB. Use CE
KVL to evaluate vCE. If VCE > 0.2V – confirmed. If not, move to next step.
STEP 4: BJT in Saturation. Set VCE = VCE(sat)≈ 0.2V. Use CE-KVL to evaluate IC and confirm IC < βIB.
Example: Consider the circuit of Figure 3.23(a), with β = 100, RC = 3kΩ. Vcc = 10V, VBB = 4V, vs = 0V and
RB = 50kΩ. Find the operating region of the transistor.
Answer: Step 1 (IB = 0) gives VBE = 4V, hence not in cut off.
Step 2 gives IB= 66μA, IC = βIB.= 6.6mA and VCE = -9.8V. This would suggest forward biased BC junction
(although the value is unreasonable, being higher in magnitude than Vcc). BJT is not in active region.
Step 3: Assume BJT in saturation. Use a higher VBE = 0.8V and VCE = 0.2V. This gives IB= 64μA and IC =
βIB.= 3.27mA. IC < βIB hence in saturation.
3.7.2. Determining Operating Point of Transistor
Transistor biasing resistors and voltages are known. By assuming BJT is in active region (confirm!) and
assuming VBE = 0.7V, KVL analysis of input loop and output loop is carried out to determine:
1. Operating point in the input circuit, VBEQ and IBQ.
2. Operating Point on the output circuit, VCEQ and ICQ.
These are used to determine a small signal equivalent circuit for AC analysis.
3.7.3. Other DC Analysis
DC analysis can also be carried out to determine the voltages and currents at all nodes in a transistor circuit.
This is carried out in a circuit with no AC signals. The analysis starts by assuming that the transistor is in
active region and assigning VBE = 0.7V and VCE > 0.2V. If unreasonable values of IC are obtained, a further
check is done to confirm if BJT is in saturation.
This analysis is important in computer simulation, which is based on nodal voltages.
Example: For the circuit in Figure 3.22, β = 100. The nodal voltages and currents are analysed in the order of
the circled numbers.
Figure 3.22: DC Analysis of BJT

Step 1: KVL input loop gives VE.
Step 2: VE and RE used to evaluate IE.
49
Step 3: Ic = αIE.
Step 4: VO evaluated through VCC - IcRC.
Step 5: IB = IE- Ic
3.8. The BJT as a Switch

Transistors are used as switches in digital electronics and in power electronics. In digital electronics, the
purpose of a switch is to indicate the logic status by giving either a high output voltage or a low output voltage.
In power electronics, the aim is to deliver current from a DC power source to a load. The role of the transistor
is to switch the current OFF or ON. Transistor switches are used when there is need to turn the current ON
and OFF many times a second, which is not possible with mechanical or electromechanical switches.
3.8.1. Circuit Arrangement
In switching applications, the transistor is usually connected in the common emitter configurations as in Figure
3.23(a).
CUT OFF SATURATION
Carrier Concentration
n BO
Distance from BE Junction Distance from BE Junction

(a) (b)
(c) (d)
Figure 3.23: Transistor as a Switch: (a) Circuit; (b) Minority Carrier Concentration in Base; (c) Switching
Waveforms:- Input (IB) and Output (IC); (d) Switching Path (Along Red Line)
50
The load is connected between the power supply, VCC and the collector terminal. The supply ground is
connected to the emitter. The switch is operated by a voltage applied at the gate. A high voltage turns the
switch ON (in saturation) while a low voltage turns the switch OFF (in cut OFF). When the transistor is ON,
it conducts and a current flows through the load. When the transistor is OFF, the current through the load is
nearly zero.
For a given load RL, designing a switching circuit involves selecting the supply voltage VCC, the peak and
minimum values of the switching voltage, vi and the base resistance, RB.
The supply voltage, VCC, is set to meet the voltage rating of the load while allowing for a small voltage drop
across the transistor, vCE(sat) ≈ 0.2V. Thus, VCC ≈ Desired Load Voltage + 0.2. Once VCC has been set, the
collector current, IC can be evaluated as VCC/RL.
Once the collector current, IC, is known, the required peak value of the base current, IB can be determined. It
should be noted here that a value IB of that is sufficient to drive the transistor into the active region will deliver
power to the load but with a fairly high collector – emitter voltage, VCE, which results in two major problems:
1. The voltage across the load will be much lower than VCC due to the relatively high value of VCE in the
active region.
2. The power dissipated in the transistor will be high, due to the high load current (≡ IC) and fairly high VCE.
Two avoid the transistor remaining in the active region when switched ON, the value of base current, IB, is set
to be high enough to overdrive the transistor by a factor of 5 – 10. This means that the base current would
deliver a collector current that is 5 – 10 times the required load current if the BJT were in the active region
and satisfied the relation IC = βIB. The peak of the input voltage, vi and the base resistance, RB are therefore
selected to satisfy the relationship:
= ×
Where also:
−
=
The overdrive also helps to ensure that the transition from cut-off to saturation is fast, thus minimising the
time spent crossing through the active region (which has associated high power dissipation).
The low value of the input voltage is usually set to be slightly below zero. This ensures that a negative current
flows when the transistor is switched off. This ensures removal of injected minority carriers in the base to
allow change over from the status in saturation to the status in cut-off, Figure 3.23(b).
The design can be summarised in the following steps:
STEP 1: Establish value of collector current, iC, using KVL of output loop, with vCE(sat) ≈ 0.2V.
STEP 2: Determine value of iB required to deliver the desired iC, with an over drive factor KOD, i.e. iB = KOD
* iC /β. The extra base current (overdrive) ensures that the transistor goes into deep saturation. Analysis is
done using KVL of input loop with vBE(sat) ≈ 0.2V.
STEP 3: Use iB and available pulse source to determine value of RB.
Example: For the circuit in Figure 3.23(a), the transistor has β = 50 and RL = 1kΩ. Vcc = 10V and VBB = 5V.
Find RB in order to drive the transistor into saturation with overdrive factor of 10. (This means that ic,≤ 10βiB).
51
Answer: When the transistor is saturated, the collector voltage will be vCE(sat) ≈ 0.2V. Collector current is
given by: iC(sat), = (Vcc - vCE(sat) )/RC = 9.8/1000 = 9.8mA. Base current required to saturate this transistor is
iC(sat)/ β = 9.8/50 = 196μA (use lowest value of β to ensure base current is sufficient to drive BJT into
saturation).
With overdrive factor of 10, iB = 10*196mA = 1.96mA.
RB = (VBB - VBE)/iB = (5-0.8)/1.96E-3 = 2.2kΩ.
3.8.2. Switching Speed
In many applications, a transistor switch has to be switched ON and OFF many times in a second. This is
achieved by using a high frequency pulse as the input to the base. Applications in power electronics usually
require switching at frequencies over 20kHz (to avoid the audio range). The switchign cycles invlove moving
a lot of minority carrier charge into the base and removing it again for every switching cycle (i.e. switchign
between the two conditions in Figure 3.23(b)). The transistor will not be able to faithfully reproduce the
rectangular input pulse and the input and output pulses will be like those shown in Figure 3.23 (c).
The output pulse demonstrates a delay time, td, rise time, tr, storage time, ts and fall time, tf. These times are
described as follows:
1. td is time taken for collector current to rise from zero to 10% of its value at saturation while tr is time taken
for collector current to rise from 10% to 90% of its value at saturation. These times arise as a result of:
a. The depletion regions at the junctions change from cut off to saturation condition during the time td.
b. Minority carrier concentration changes from cut off to saturation condition during the time tr.
2. The depletion regions are re-established to reverse bias (cut off) condition and minority carrier
concentration changes from saturation to cut off condition during the time ts, and tf.
a. ts is time taken for collector current to fall to 90% of its value at saturation. During this time, most of
the excess minority carrier charge is removed from the base. This is the most critical time limiting
switching speeds of transistors.
b. tf is time taken for collector current to fall from 90% to 10% of its value at saturation. This time allows
for the re-establishment of the depletion regions.
The switching speed can be improved by reducing the minority carrier lifetime in the base or by preventing
the transistor from moving to deep saturation when in the ON condition.
3.8.3. The Schottky Clamped BJT
The Schottky clamped BJT is a transistor designed to improve the speed for transistors in switching
applications. It is an NPN BJT with a Schottky diode connected between the base and the collector. The
Schottky diode limits the base – collector voltage to a maximum of one Schottky diode drop or approximately
0.3V. This ensures that the transistor does not go into deep saturation when in ON condition, The quantity of
minority carriers to be removed from base during change-over from ON state to OFF state is therefore reduced
and a high switching speed can be achieved. A schematic of the clamped transistor is shown in Figure 3.24.
The construction of a Schottky clamped transistor involves having a metal contact that is common to both
base and collector regions. The contact wil the base is Ohmic (and also serves as the base terminal). The
contact to the collector is a rectifying Schottky contact. An extra ohmic contact has then to be provided for
the collector – the colector has two metal contacts.
52
(a) (b)
Figure 3.24: Schottky Clamped BJT: (a) Schematic; (b) Construction
3.8.4. Parallel Operation

Suppose the load to be switched demands a higher current than can be supplied by one transistor? Can the
switching requirement be met by connecting two or more transistors in parallel, as proposed in the circuit of
Figure 3.25?
Figure 3.25: Parallel Operation of BJT – Guaranteed to Fail

This would be a very bad idea which would guarantee that all the transistors are eventually destroyed by high
current resulting in high temperature. As mentioned earlier, the collector current of a BJT is given by:
= −1
The intrinsic concentration, ni, increases with temperature. This means that the collector current increases with
temperature. The output of a BJT in CE configuration behaves like a resistor with negative temperature
coefficient of resistance.
If BJTs were connected in parallel, there is bound to be some mismatch and the current will not be shared
equally. The BJT with high current will have a larger temperature increase. This will cause it to take an even
larger share of the current. This will further increase its tmeperature and eventually lead to its destruction. The
remaining transistor will then face a large current than it can carry and will be destroyed too.
53
3.9. The BJT as an Amplifier
The purpose of an amplifier is to take as input a small ac signal and deliver a larger version of this signal at
the output. For a transistor, this can be achieved by using the transistor in the active region where there is a
linear relationship between base current and collector current, iC = βiB. This is achieved by connecting DC
biasing sources to the transistor. These set up an operating point, i.e. define values of ICQ, VCEQ, and VBEQ. The
operating point is selected to be in the middle of the active region.
The ac signal to be amplified is superimposed on the DC input at the base (Figure 3.26(b)). To ensure that the
BJT remains in the active region even with the input superimposed, the input signal needs to be a small signal,
i.e. it needs to be smaller than the DC current and voltage at the operating point. A useful rule of thumb is: ac
value ≤ 0.1 DC signal at operating point, e.g.:
0.1
Analysis of a transistor amplifier circuit therefore starts with DC analysis to identify the operating point
followed by AC Analysis of the amplifier function.
3.9.1. The Operating Point
As an amplifier, the transistor can be applied in any configuration, although the common emitter configuration
is very common. A widely used CE amplifier is shown in Figure 3.26(a). The circuit has one DC biasing
supply, VCC which provides CE and BE biasing voltages through the resistor RC. RE , RB1 and RB2.
RC VCC
RB1 IC
C
IB
B
IE
E
RB2
RE
(a) (b) (c)

Figure 3.26: Transistor as Amplifier: (a) Circuit in CE; (b); DC Equivalent; (c) DC Equivalent Circuit
Simplified using Thevenin’s Theorem
For DC analysis:
1. All AC sources are replaced by their internal impedance (zero for ideal sources).
2. All capacitors are replaced by open circuits.
The resultant circuit is shown in Figure 3.26(b). For analysis, the circuit is simplified using Thevenin’s
theorem to the form in Figure 3.26(c). A full analysis is done as an example.
Example: The BJT amplifier in Figure 3.26(a) has RB1 = 27kΩ, RB2 = 15kΩ, RC = 2.2kΩ, RE = 1.2kΩ, RL =
2kΩ, RS = 10kΩ, VCC = 9V and C1,C2 and CE are large. Assume β= 100 and VA = 200 V. Find the Q-point
defined by IBQ, ICQ and VCEQ
Answer: For Thevenin Equivalent, RB = 9.64kΩ, Vth = 3.21V.
Assume BJT is in active mode, VBE = 0.7V; IE = (β+1)IB and IC = βIB.
Now KVL input loop gives IB = (Vth –(VBE +VE))/RB.
Thus IE = (β+1)(Vth –(VBE +VE))/RB.
54
Also, IE = VE/RE.
Equating the expressions for IE yields, VE = 2.325V.
Hence, IE = 1.9375mA; IB = 19.18μA and IC = 1.918 mA.
KVL output loop will yield, VCE = 2.455V.
The BJT can be confirmed to be in active region by checking that VCB = 1.755V, hence the junction is reverse
biased, as expected in active region.
3.9.2. Amplifier Inputs and Outputs
Amplifier inputs are alternating signals of unknown form. For the study of amplifier performance, sinusoidal
signals can be used as the inputs. Figure 3.27(a) shows the Thevenin equivalent circuit of the CE amplifier
with the both the AC and DC supplies. The coupling and bypass capacitors are restored and the signal source,
vs is connected.
10
Base Current
4
0
0 1π 2π 3π 4π 5π
-2
ωt, Rad /Sec
IBQ iin
i =i iB=IBQ+iin
iin+IBQ
(a) (b) b in
Figure 3.27: Transistor as Amplifier: (a) Thevenin Equivalent Circuit with both DC Biasing and AC Input
Signals; (b) Signal to be amplified (Blue Solid), and superimposed on VBEQ (Red Dotted).
The input at the base of the transistor consists of a DC component, IBQ, which results from the DC biasing
source and an AC component, iB, which results from the ac input signal. The total biasing is the sum of the
two, which is a composite signal iB. The signals are shown in Figure 3.27(b), with the small AC signal
superimposed on the large DC biasing current.
The input current causes the output current at the collector, iC, to fluctuate around the quiescent value of the
DC biasing current, ICQ. This causes a similar fluctuation in the output voltage, vCE. The coupling capacitor
C2 separates the AC part of the output voltage from the DC part and only the AC part is delivered to the load,
RL.
AC analysis of a transistor amplifier circuit is interested in deriving relationships between the input signal, vs
and the output signal, vo. It is not possible to apply the same assumptions used for DC analysis of amplifier
circuits, e.g VBE = 0.7V, because this is only true for biasing DC signals and not true for varying small signals.
AC analysis is therefore requires one to revert to the equations relating voltage and current such as:
≈
These equations have interdependencies between voltages and currents that do not render themselves to
analytical solution. The other options available are solution by graphical methods, approximation methods or
iterative methods.
55
Graphical and approximation methods are suitable for simple one transistor circuits, and even then will be
slow. Iterative methods can be carried out by computer, and in many cases will require a model to allow
formulation of mathematical expressions for use in the analysis.
Analysis of amplifier circuits is a two stage process. First, a DC analysis is carried out to identify the operating
point. The operating point has to be selected such that a small signal ac input will not drive the transistor into
saturation or cut off. The transistor will therefore remain in the active region for the entire range of expected
input signals. AC analysis can then be carried out either by graphical methods or equivalent circuit methods.
3.9.3. Graphical Analysis of Transistor Amplifier
Once the transistor biasing arrangement is known, ac analysis can be carried out to determine transfer function
for ac signals. The first method reviewed is graphical analysis. This requires BJT output characteristics to be
available. An example of graphical analysis of a BJT amplifier circuit using the output characteristics is shown
in Figure 3.28.
(a) (b)
Figure 3.28: Graphical Analysis of Transistor Amplifier: (a) Load Line; (b) AC signal Swings.
A load line is constructed crossing the collector current axis at VCC/IcRC and the collector voltage axis at VCC.
The intersection of the load line with VCEQ and ICQ is the operating point.
The extent of variation of the peak to peak ac input, ib is marked on the load line. The extent of variation of
the collector current, iC and collector emitter voltage, vCE is obtained by extending the limits on the load line
to the y and x axis respectively.
For small signals, these values should not go outside the active region (otherwise the output will be distorted).
Example: The output characteristics of a transistor operating in CE configuration are shown in Figure 3.28.
The transistor is to be operated as an amplifier with DC bias set at IB = 30μA. The load resistor, RL = 1.2kΩ
and VCC = 18Volts.
Determine the biasing current and voltage ICQ IB and VCEQ.
If an AC current is applied at the input so that the base current has a peak to peak variation of 20μA, what is
the peak to peak value of the output voltage?
Answer: Draw the DC load line: x-intercept is when VCE = VCC. The y-intercept is when VCE = 0, in which
case IC = VCC / RL = 15mA. The two lines are plotted on the graph and joined with a straight line.
56
The operating point occurs when the curve for IB = 30μA intercepts the load line. Reading off the curve, ICQ
= 7.3mA and VCEQ = 9.2V.
The ac input signal will cause IB to oscillate around the Q-point. Maximum IB = 30μA + 40μA/ 2 = 50μA.
Minimum IB = 30μA - 40μA/ 2 = 10μA. The points where the curves for the maximum and minimum values
IB of intercept the load line give the minimum and maximum values of VCE. (3.3V and 14.8V). It is noted that
the minimum value of VCE occurs when IB is maximum and vice versa. The amplifier inverts the signal (180°
phase shift).
Graphical analysis is slow and cannot work for complex amplifier circuits. The solution is to develop a small
signal AC model of the BJT using passive components. This model is can be inserted in AC form of the
amplifier circuit. Circuit theory methods can then be applied to derive voltages and currents in the amplifier
circuit.
3.10. AC Small Signal Models of Transistor Amplifier

An AC model is used for determining the voltage gain, current gain or power gain when the transistor is
operated as an amplifier in the active region. Supposing a small sinusoidal input voltage vbe= VMsin(ωt) is
superimposed on the base while operating in the active region.
• Total base voltage, vBE = VBEQ + vbe = VBEQ + VMsin(ωt) ;
• Total base current, iB = IBQ + ib = VBEQ + VMsin(ωt)
• Total collector current, iC = ICQ + ic = VBEQ + VMsin(ωt)
Small signal models are designed to analyse the small variations of these input and output signals. These need
to be dynamic and are therefore based on the small variations around the operating point, not on global
parameters like the DC β. (The dynamic value of β is very close to the value of DC β, therefore DC β can be
used in derivation of small signal models).
3.10.1. The Small Signal, Low Frequency Hybrid π Model
The hybrid π model represents the BJT as a two port network. For the CE configuration, the input port is
between base and emitter and the output port is between collector and emitter. The relationships between
voltages and currents are represented by ordinary circuit elements – voltage sources, current sources, resistors
and capacitors. The most important relationships are:
1. At the input: The base current is a function of the base – emitter voltage.
2. At the output: The collector current is a function of the collector – emitter voltage (as a result of the Early
effect).
3. Between input and output:
a. The collector current is a function of base – emitter voltage, OR,
b. The collector current is a function if base current.
This gives three basic parameters for the model. A choice has to be made on the relationship to represent for
item 3. There are therefore two forms of the model:
1. The transconductance model represents the collector current as a function of the base – emitter voltage.
2. The current gain model represents the collector current as a function of base current.
The two models are shown in Figure 3.29.
57
(a) (b)
(c) (d)
Figure 3.29: Small Signal Pi Model of BJT: (a) Transconductance; (b) Current Gain; (c) Evaluation of Input
Resistance; (b) Evaluation of Transconductance and Output Resistance.
The change in collector current for a change in base collector voltage is represented by the parameter
transconductance, gm.
( )
= | = = ( )
=
3.36
The change in base current for a change in base emitter voltage is represented by the parameter input
conductance, gπ or more commonly, its reciprocal, the input resistance, rπ.
1 ( )
= | = = ( )
= 3.37
The change in collector current for a change in collector-emitter voltage is represented by the parameter output
resistance, ro, which was evaluated in equation 3.35.
+
= | =
≈ 3.38
For ease of calculation, it should be noted that at T = 300 K (27°C):

= 0.0259
Example: A BJT with β=90 and VA = 40V is biased at ICQ = 1 mA and VCEQ = 3 V. Evaluate gm, rπ ro. Assume
T = 300 K.
Answer: gm,= 1E-3/0.0259 = 0.0386 Siemens; rπ,= 90/0.0386 = 2.331kΩ; ro,= 40/1E-3 = 40kΩ.
58
The parameters of the hybrid π equivalent circuit can also be evaluated from the output characteristics if the
Q point is known.
Figure 3.30: Evaluation of Equivalent Circuit Parameters

Example: Figure 3.30 shows the output characteristics of an NPN BJT. The BJT is biased with IBQ = 0.4 mA
and VCEQ = 4.8 V. Evaluate gm, rπ and ro. Assume T = 300 K.
Answer: From the graph, ICQ = 22 mA.
Dynamic β is evaluated as (NOTE: Follow the load line when tracking changes in IB and IC):
∆ 30 − 10
= | = = 50
∆ 0.6 − 0.2
ro is evaluated from the inverse slope of the characteristics (for IB = IBQ = 0.4 mA ) as:
∆ 10 − 1
= = = 4500Ω
∆ 0.022 − 0.02
The other model parameters can now be evaluated:
gm,= 22E-3/0.0259 = 0.849 Siemens; rπ,= 50/0.849 = 58.89kΩ; If VA is required, it can be approximated
as VA ≈ ICQ*ro,= 1750*22E-3 = 40V.
3.10.2. Analysis of Amplifier Circuits Using Small Signal Models
Once a model parameters have been evaluated, it can be applied to analyse a transistor amplifier circuit for
voltage and current gain, input and output impedances. The procedure is:
1. Determine the dc operating point of the BJT and in particular the dc collector current IC.
2. Evaluate the values of the small-signal model parameters.
3. Eliminate the independent dc sources by replacing each dc voltage source with a short circuit and each dc
current source with an open circuit. NOTE: Dependent sources must never be eliminated, not even to
perform superposition.
4. Replace the BJT with one of its small-signal equivalent circuit models. Although any one of the models
can be used, one might be more convenient than the others for the particular circuit being analysed.
5. Analyse the resulting circuit to determine the required quantities (e.g., voltage gain, input resistance).
59
Example: The BJT amplifier in Figure 3.26(a) has RB1 = 27kΩ, RB2 = 15kΩ, RC = 2.2kΩ, RE = 1.2kΩ, RL =
2kΩ, RS = 10kΩ, VCC = 9V and C1,C2 and CE are large. Assume β= 100 and VA = 200 V.
a. Find the Q-point defined by IBQ, ICQ and VCEQ.
b. Evaluate Evaluate gm, rπ and ro. Assume T = 300 K.
c. Obtain Voltage Gain and Current gain.
Answer:
STEP (a): DC analysis
Draw equivalent DC circuit
Evaluate parameters for Thevenin equivalent circuit: RB = 9.64kΩ, Vth = 3.21V.
Assume in active mode as expected for an amplifier: VBE = 0.7V; IE = (β+1)IB and IC = βIB
KVL input loop: IB = (Vth –(VBE +VE))/RB. Thus IE = (β+1)(Vth –(VBE +VE))/RB. Also, IE = VE/RE.
Equating the expressions for IE yields, VE = 2.325V.
Hence, IE = 1.9375mA; IB = 19.18μA and IC = 1.918 mA.
KVL output loop: VCE = 2.455V.
Evaluate VCB = 1.755V, confirms active region
STEP (b): AC small signal parameters
= = 1.918E-3/0.0259 = 0.0741 Siemens
= = 100/0.0741 = 1.35kΩ
= = 200/1.918E-3 = 104kΩ
STEP (c): AC analysis of amplifier using circuit theory concepts
AC equivalent circuit is obtained by replacing the BJT with the AC small signal model. Also, DC sources are
replaced by internal impedances and capacitors are replaced by short circuits. The resultant circuit is shown
in Figure 3.31(a).
(a) (b)
Figure 3.31: (a) AC Equivalent Circuit of CE Amplifier using Hybrid Pi Model; (b) Minority Carriers in
Base for BJT Amplifier Operation
AC circuit can be simplified further by combining resistors in parallel to give the circuit in Figure 3.31(b):
Input Resistance, = ⫽ ⫽ = 1.18kΩ
Output Resistance, = ⫽ ⫽ = 1.03kΩ
60
Applying circuit theory concepts to the simplified ac circuit:
= = vs*1.18/(1.18+10) = 0.106vs
=− =− =-74E-3*0.106vs *1.03E3 = -8.08vs (Negative because direction of ic needs to be
reversed to obtain indicated polarity)
= = -8.08 V/V
= ; =
= = = ((10+1.18)/2)*-8.08 = -45.2 A/A
3.10.3. Hybrid π Model at High Frequency

During operation, a BJT amplifier has to move charges across the depletion regions of the base – emitter and
the base –collector junctions. Also, the variations of the base – emitter voltage with the input AC voltage also
requires variation of the minority carrier charge in the base, as shown by the dashed lines in Figure 3.31(b).
At high frequency, the required rate of change in concentration of charge is very high and the BJT may not
respond fast enough. This limits the amount of current flowing in the transistor.
The effect is represented in the equivalent circuit as depletion capacitances and diffusion capacitance.
3.10.3.1. Depletion Capacitance
A biased PN junction has depletion capacitance as a result of the depletion region. This is significant under
reverse bias and is therefore more important for the base – collector junction. The junction also has diffusion
capacitance due to injected minority carriers. This is only occurs under forward bias and is therefore important
for the base emitter junction. These capacitances are included in high frequency models as the depletion
capacitance of the base – emitter junction (or junction capacitance), CDBE and the depletion capacitance of the
base – collector junction (or junction capacitance), CDBC. Since the base – collector junction is reverse biased
in active region, CDBC is more significant than CDBE.
3.10.3.2. Transit Time and Diffusion Capacitance
During operations a large amount of charge carriers are injected across the junctions. This is especially
significant for minority carrier injected into the base. During normal operations, these carriers have to be
alternately injected and removed. This affects the ability of the BJT to operate with high frequency signals. It
is therefore necessary to quantify the injected charge and model it as a circuit element to allow proper analysis
of high frequency circuits.
The time that would be taken to remove all the excess injected charge through the collector current is known
as the transit time.
= 3.39
The minority charge stored in the base is modelled as the diffusion capacitance. The diffusion capacitance is
expressed in terms of the transit time.
( )
= | = = 3.40
The input capacitance, Cπ is the sum of the base – emitter junction depletion capacitance and the diffusion
capacitance.
61
= + ≈ 3.41
The simplified high frequency model is shown in Figure 3.32.

Example: For the first example in the previous section, evaluate the input capacitance if τF = 5 pS.
Answer: Cπ = 5E-12 * 0.039 = 195 fF (Femto Farad).
Figure 3.32: Hybrid π High Frequency Model

3.10.4. Other Small Signal Models
There are other small signal models of the BJTs which may be preferred in certain applications.
The T model has similar parameters to the hybrid π model except that instead of dynamic input resistance rπ,
there is dynamic emitter resistance re., which can be evaluated from the hybrid π model as:
= + = (1 + )= (1 + ) =
= = 3.42
1+
The layout of the model is also different as shown in Figure 3.33(a).
(a) (b)
Figure 3.33: Other BJT Small Signal Models: (a) T Model; (b) Hybrid Parameter Model
The Hybrid Parameter model represents the BJT as a black box and evaluates two Z parameters and two Y
parameters without any consideration to the actual working of the BJT. A two port network should have four
Y and four Z parameters. The selected two in each case have close parallels with hybrid π parameters.
Models for computer simulation use a more complex equivalent circuit that includes the resistances of
emitter, base and collector regions. Also included is the capacitance due to base width modulation, Cμ. It
should be noted that computers usually use large signal models.
62
Figure 3.34: Hybrid π Model for Small Signal Computer Simulation
3.11. Large Signal Models
Small signal models are only valid for transistors in the forward active mode. They cannot predict behaviour
of the transistor in the cut off, saturation and reverse active modes. If a large signal is applied as input and
analysis carried out with a small signal model, wrong results will be obtained.
Large signal models are therefore required in order to predict the full range of transistor behaviour. This is
especially important for computer models.
3.11.1. The Ebers – Moll Model
The Ebers-Moll model of the BJT is a large signal model that can be used to predict current and voltage
relationships from cut off through the active region and into the saturation region. It was developed by Messrs
Ebbers and Moll in 1954. The full model and a simplified model are presented in Figure 3.35.
Figure 3.35: The Ebers – Moll Model - Injection Version: (a) Full; (b) Simplified
The Ebers-Moll model depicts the transistor as two back-back diodes, with each diode being in counter parallel
with a current source (direction of current source is opposite that of diode). The diodes obey the Shockley
equation while the current sources follow the relationship between emitter current, collector current and the
common base current gain, α. The current source across the base – collector diode represents the reverse active
region. The current source across the base emitter diode represents the forward active region.
3.11.2. The Gummel–Poon Model
The Gummel–Poon model, developed by Messrs Gummel and Poon in 1970 is based on the transport version
of Ebers-Moll model. It contains additional capacitances and resistances to represent:
1. Junction capacitances
2. Diffusion capacitances in forward and reverse modes.
3. Collector to substrate capacitance (applicable for BJTs fabricated using the planar process used for
integrated circuits).
4. Intrinsic resistances for emitter, base and collector.
63
In addition to modelling all four operating modes of the BJT, it also takes into account high-level injection,
voltage-dependence of capacitances, variation of β with collector current, parasitic resistances and the Early
effect. The model is presented in Figure 3.36.
The Gummel–Poon model model is applied in SPICE models of the BJT.
Figure 3.36: The Gummel – Poon Model
64
Chapter 4. Junction Field Effect Transistors
4.1. FET Introduction
In a bipolar junction transistor, the output current, iC, is controlled by the base current, iB. One result of being
a current controlled device is that the BJT has a fairly low input impedance, which is not desirable for a voltage
amplifier. In the Field Effect Transistor (FET), the output current, iD, is controlled by an electric field applied
parallel to the direction of flow of the current. The electric filed is controlled by a voltage applied through a
terminal called the gate. Main current flow is from a terminal called the source to a terminal called the drain,
through a semiconductor channel.
Field effect transistors are classified into two types based on the device construction and the way the electric
field is applied. In the Junction Field Effect Transistor (JFET), the electric field is applied through a junction.
This is a PN junction for the Junction Field Effect Transistor (JFET) and a metal – semiconductor junction for
the Metal Semiconductor Field Effect Transistor (MESFET). In the Metal Oxide Semiconductor Field Effect
Transistor (MOSFET), the electric field is applied through an insulated gate. All field effect transistors are
unipolar and use only one type of charge carrier. If the charge carriers are electrons, then the transistor is N-
channel, otherwise, the carriers are holes and it is P-channel. The devices are further classified depending on
whether the channel is conducting or non-conducting when there is no gate voltage applied. Depletion devices
have a channel that is conducting (low resistance) without an open circuited gate. Enhancement devices have
a channel that is not conducting (very high resistance) when the gate is open circuited. Depletion devices can
be operated in enhancement mode (the conductivity of the channel is increased from the value with open
circuited gate). The classification of filed effect transistors is summarised in Figure 4.1.
Figure 4.1: Field Effect Transistor Classification

FET type devices were first patented in 1926 and 1934. They were however not produced until mid-1950s for
JFET and 1968 for MOSFET (BJT developed in 1947). Since then, the MOSFET has become the most widely
used transistor device, surpassing even the BJT, especially in integrated circuits. JFETs are no longer used for
general purpose applications. They are however applied in special applications because of their low noise and
high radiation tolerance. The MESFET was developed to utilise the properties of new semiconductor materials
such as Gallium Arsenide (GaAS). MOSFET devices could not be easily developed using GaAS because of
the inability to grow a stable oxide layer on the material.
65
4.2. J-FET Structure and Operation
4.2.1. Construction
The N-channel JFET consists of a cubic or cylindrical bar of N-Type silicon with two ohmic contacts at the
ends. One contact is the source, S and the other contact is the drain, D. Two opposite faces of the bar are
heavily doped P type (to a shallow depth) and interconnected through ohmic contacts. The contact on the P
type faces are called the gate, G. The semiconductor between source and drain is known as the channel. The
construction and symbols are shown in Figure 4.2.
(a) (b)
(c) (d) (e)

Figure 4.2: N-Channel JFET: (a) Simplified Structure; (b) Cross-Section; (c) Cross-section of Practical JFET
(b) Circuit Symbol, N-Channel; (c) Circuit Symbol, P-Channel (Kasap)
The circuit symbol has a vertical bar representing the channel and three contacts representing drain, source
and gate. An arrow on the gate terminal indicates the forward bias direction of the PN junction between gate
and channel.
4.2.2. Enhancement JFET and Depletion JFET
Consider an N Channel JFET. The combination of the N Channel and P Gate forms a P-N junction. A depletion
region always forms around the channel. The gate is doped more heavily than the channel so that the depletion
region is almost always entirely in the channel. The channel between source and drain has resistance RDS,
where:
=
Where A is cross-section of part of channel that is not depleted (depletion region is assumed to have no charge
carriers, therefore has infinite resistance).
In operation, a bias can be applied between gate and channel by applying a voltage, VGS, between Gate and
Source. JFETs are classified as enhancement mode or depletion mode depending on the status of channel
resistance when there is no bias between gate and source.
In Enhancement JFET, the depletion region includes the whole channel without bias (VGS = 0). There is
therefore no Conduction between source and drain (RDS = ∞) unless bias voltage between gate and source
reduces depletion region. Reducing the depletion region reduces the resistance of the channel hence is
equivalent to enhancement of channel conductivity
66
In Depletion JFET, the depletion region covers only part of the channel without bias (VGS = 0). The Source
to Drain resistance, RDS , is therefore low and conduction is possible between the terminals. A voltage that
reverse biases the PN junction between Gate and Channel can be applied between gate and source to increase
the width of the depletion region. This increases the resistance of the channel hence is equivalent to depletion
of channel conductivity
(a) (b)
Figure 4.3: N-Channel JFET with no bias: (a) Enhancement Type; (b) Depletion Type
4.2.3. N-Channel D JFET Operation
The operation of the N-Channel Depletion JFET is shown in Figure 4.4.
(a) (b) (c)

Figure 4.4: N-Channel JFET Operation: (a) Depletion Layer Formation and channel voltage profile; (b)
Pinch-Off Condition; (c) Pinch-Off extends into channel (saturation)
With no external voltages connected, a depletion region forms in the channel at the junction with the gate. The
depletion region has no mobile charges and is an insulator. It is however too small to appreciably affect the
dimensions of the channel.
In normal operation, the N-channel JFET is biased with the drain positive with respect to the source. With the
gate open circuited (Figure 4.4(a)), the channel behaves like resistor. Current flows from drain to source, with
the current proportional to drain – source voltage, VDS.
When a negative voltage is applied to the P-type gate (e.g. by connecting it to the source), the gate-channel
junction is reverse biased. The depletion region widens, causing the channel to become narrower and
increasing its resistance. As the drain – source voltage, VDS, is increased, the drain current increases. This
however increases the voltage drop along the channel, raising the reverse bias between gate and channel near
the drain end. The result is that the depletion region widens. Eventually a point is reached at which the
depletion region completely absorbs the N-channel, and the drain–source current iD reaches a limiting value
67
called the saturation current for zero gate voltage (VGS = 0), IDSS. The saturation point is termed the pinch-off
point. At this point, VDS, = VP0, the pinch off voltage for zero gate voltage (VGS = 0).
A better reverse bias is obtained by connecting a supply voltage between gate and source, Figure 4.5. This is
the gate – source voltage, VGS. The depletion region is then more uniform and pinch off is achieved at a lower
drain – source voltage.
Figure 4.5: N-Channel JFET with Separate VGS supply: (a) VDS = 0; Uniform Depletion Layer: (b) Pinch-Off
Condition
A JFET is said to operate in depletion mode when it passes a high current with no voltage supplied to the
gate and passes no current when the gate – source voltage has a large magnitude (negative for N-channel).
The output and transfer characteristics are shown in Figure 4.6. The transfer characteristic shows the saturation
current for different values of VGS.
Figure 4.6: N-Channel JFET: Transfer & Output Characteristics

From the transfer characteristic, it is observed that the gate – source voltage, VGS is able to control the output
current, IDS as long as it is within the range of –VP (or VPO) and zero. When VGS = –VP, drain current is zero
and the JFET is said to be in cut-off. When VGS = 0, the saturation current is IDSS.
The output characteristic plots drain current, IDS against drain – source voltage, VDS.
From the output characteristics two distinct current voltage relationships ate observed. This can be classified
as 3 operating regions:
1. Cut-off Region – When VGS < -VP, the pinch off region extends over the complete channel and no current
can flow. The JFET is in the cut off region.
2. Ohmic Region –To the left of the characteristic VD and VDS have a linear relationship. The JFET acts like
a resistor. This occurs when VGS > -VP and VDS < VGS + VP. In this region, the device has not reached pinch
off and there is a conducting channel between drain and source. The width of the channel reduces as VDS
is increased and the JFET approaches cut off. The resistance of the channel is therefore not constant.
68
3. Saturation or Active Region - VDS ≥ VGS + VP. The JFET becomes a good conductor and is controlled by
the gate-source voltage, (VGS) while the drain-source voltage, (VDS) has little or no effect.
In the active or saturation region, the output current is only controlled by the gate bias, VGS. In this operating
region, the JFET can be used as an amplifier. The current voltage relationship in the active region can be
estimated as:
= 1+ 4.1
Where:
IDSS is the saturation current without gate bias (VGS is = 0).
VP is the Drain – Source pinch off voltage without gate bias (VGS is = 0).
The JFET can experience breakdown if VDS is raised above a certain limit. The output characteristics will then
demonstrate increase in current with no change in VDS.
69
Chapter 5. The MOSFET
The Metal Oxide Semiconductor Field Effect Transistor, MOSFET, is a field effect transistor where the
controlling voltage is applied through a gate terminal that is electrically insulated from the conducting channel.
The MOSFET was first developed in the late 1960s. Since the late 1970s, MOSFETs have become very
popular especially for application in digital integrated circuits (ICs). The manufacturing of MOSFETs is
relatively simple. A MOSFET device can be made small, and it occupies a small silicon area in an IC chip.
Because of the use of an insulated gate, the power consumption is also very low. MOSFETs are currently
used for very-large-scale integrated (VLSI) circuits such as microprocessors, system on chip (SoC) and
memory chips. A 2018 study estimated that of all transistors ever made, 99.9% have been MOSFET.
5.1. The MOS Capacitor
All the devices studied so far use either the PN junction or the metal semiconductor junction, The MOSFET
uses completely different technology. The control device in a MOSFET is the Metal Oxide Semiconductor
(MOS) capacitor.
In analysis of the MOS capacitor, it should be recalled (as explained for the Metal Semiconductor contact) for
a parallel plate capacitor with one metallic plate and one semiconductor plate, all the charge will be on the
surface for the metal plate, while on the semiconductor plate, the charge will be accommodated in a depletion
region that extends to the bulk of the semiconductor material. Where the metal is replaced by degenerately
doped polycrystalline silicon, it will be assumed that the poly silicon has enough mobile charge carriers to
behave as a metal.
5.1.1. Construction
The metal oxide semiconductor (MOS) capacitor consists of a piece of silicon (lightly doped P or N-type),
called the substrate with a layer of silicon dioxide of thickness tox on top. A metal layer (traditionally
aluminium) is deposited on top of the silicon. The oxide layer is made very thin, with width in the order of
1.2nm. Ohmic contacts are made to the metal and to the semiconductor. The contact on the metal is called the
Gate (G) and the contact on the substrate is called the Body (B) or Bulk. A view of the device is shown in
Figure 5.1.
(a) (b)
Figure 5.1: MOS Capacitor: (a) Construction; (b) Cross Section
For an area of 1 cm-2, the capacitance is given by:
ε
= 5.1
Where εox is the permittivity of the oxide. If εox is in Farads per cm and tox is in centimetres, the Cox is the
oxide capacitance in Farads per square cm.
Other materials may also be used for example the metal may be replaced by heavily doped polycrystalline
silicon and the oxide replaced by silicon nitride. Degenerately doped silicon will behave like a metal and the
analysis carried out for an aluminium gate applies to a polysilicon gate.
70
5.1.2. Energy Band Analysis
Consider a MOS capacitor made from lightly doped P-type silicon and aluminium. Aluminium has a work
function, Φm =4.25eV. The work function of P-type silicon is will be higher than this (between χ+Eg/2 =
4.61eV and χ+Eg = 5.17eV). The band diagram of the capacitor will look like the band diagram of metal and
P-type semiconductor with Φm < Φs, but with a thin layer of oxide between metal and semiconductor.
The metal and semiconductor are no in direct contact and even though there is a difference in work function,
there cannot be no movement of mobile charges directly between them. Both metal and semiconductor are
however in contact with the SiO2. However, the oxide has χ = 0.9eV, Eg = 9eV. It can be assumed that due to
the large bandgap, there are no mobile charges in the SiO2. Also, the mobile electrons in the metal and
semiconductor will not move to the conduction band of the oxide because the quantum states there have very
low probability of being occupied. There will be no movement of mobile charges and the Fermi levels will
not align. The situation will be like in the isolated metal, semiconductor and oxide, as shown in Figure 5.2(b).
Vacuum
Level
EC
EFi
qVB EF
EV
EF
Metal Silicon
(a) (b)
Figure 5.2: MOS Capacitor with no Electrical Connection between Gate and Body: (a) Capacitor; (b) Band
Diagrams
Since the semiconductor body is P-type, the Fermi level, EF is at a lower energy than the intrinsic Fermi level,
EFi. The difference between the intrinsic Fermi level and the Fermi level in the isolated P-type body is known
as the body or bulk potential, VB.
1
= − = ln 5.2
NOTE: When work function of intrinsic silicon is given as 4.05eV, this is actually equal to 4.05q in Joules.
Therefore = 4.05 Volts.
5.1.2.1. Flat band Condition

If an external connection is now made between the gate and the body as in Figure 5.3(a), there is an electrical
connection between the metal and the silicon.
The difference in work function will drive electrons to move from the metal, through the external circuit to
the semiconductor. The net movement of electrons will only stop when the Fermi Levels have aligned. As a
result there will be a potential difference between the metal and semiconductor equal to the difference in work
functions (Φm/q - Φs/q). The metal will have lost electrons and will be at a higher potential. The charge in the
metal is contained at the surface of the metal while the charge in the semiconductor extends into the body of
the semiconductor. As a result of the charge in the semiconductor, the energy bands will bend as shown in
Figure 5.3(b).
71
(a) (b)
Figure 5.3: MOS Capacitor with Gate Shorted to Body: (a) Capacitor Wiring; (b) Band Diagrams
In order to bring the energy bands to a flat level again, an external potential difference would have to be
connected between the gate and body. This would have to be equal to the contact potential between the gate
and body materials. The voltage is known as the flat band voltage, Vfb. The capacitor wiring and resultant band
diagrams are shown in Figure 5.4.
(a) (b)
Figure 5.4: MOS Capacitor biased to Flat Band Condition: (a) Capacitor Wiring (NOTE: Flat band voltage
is usually negative and the source positive will therefore be connected to the body); (b) Band Diagrams
The result of a positive voltage connected to the semiconductor body is to lower the energy bands on that side
(Since the body contact is grounded and thus used as reference, the situation will be treated here as if the bands
are raised on the metal side). The Fermi level on the metal rises by Vfb and is no longer aligned with the one
on the semiconductor side (in reality, the Fermi Level is lowered on the semiconductor side). There are no
charges on either metal or semiconductor and the energy bands on the semiconductor side are flat. The flat
band voltage is given by:
φ φ
= − 5.3
The negative sign is included because VGB is positive when the gate it at a higher potential than the body.
Example: What is the flat-band voltage for a MOS capacitor with gate made of aluminium (Φm / q = 4.25V)
and body of P-type silicon with Na = 1016cm-3?
Answer: For the silicon body, VB = (EFp - EFi)/q = kT/q ln(Na/ni) = 0.356. Work function, Φs /q =
4.05+0.56+0.0356 = 4.966. Vfb = (4.25V- 4.966V) = - 0.716Volts.
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5.1.2.2. Accumulation
Under flat band condition, the gate is at a more negative voltage than the substrate. There is no net charge on
either the semiconductor or the metal. If the biasing voltage is reduced to be more negative than Vfb, a negative
charge is induced on the surface of the metal gate, next to the oxide. This induces a positive charge on the
semiconductor. The positive charge is achieved by attracting more holes from the bulk of the substrate to a
layer near the boundary with the oxide. This layer will have more holes than the doping concentration, Na.
The region is said to be experiencing accumulation.
As a result of the charge in the semiconductor, the energy bands will be lowered in the bulk of the
semiconductor away from the accumulation region. The bands will bend upwards moving from the bulk
towards the surface of contact with the oxide. The Fermi Level will be lowered by a value equivalent to the
applied voltage. The situation is presented in Figure 5.5.
(a) (b) (c)

Figure 5.5: MOS Capacitor in Accumulation Condition: (a) Biasing Arrangement; (b)Energy Band
Diagrams; (c) Net Charge in Metal and Semiconductor
It should be noted that although there is a potential difference applied across the device, there is no current
flow in the steady state because of the oxide. In the steady state, there is no movement of charges, the
semiconductor is in equilibrium and the Fermi level is at one constant value throughout the semiconductor.
The lines representing the energy levels EC, EV and EFi bend in the depletion region, but the line representing
EF is flat.
Also, The equations for carrier concentration for a semiconductor under equilibrium are applicable.
5.1.2.3. Depletion
If the voltage between gate and body was now raised above the flat bad voltage. For example, the gate is
positive with respect to the body. The metal gate would now accumulate a net positive charge, which will be
accommodated on the surface of the metal. This will in turn induce a net negative charge on the body.
At low gate bias voltages, holes will be repelled away from the oxide surface into the bulk of the
semiconductor. This will leave a depletion region with negative donor ions and very few holes and very few
electrons. The device is said to be in depletion. The situation is presented in Figure 5.6.
The negative charge in the semiconductor raises the energy bands. This causes the bands to bend downwards
moving from the body towards the oxide. On the metal side, the Fermi Level is lowered by an amount
equivalent to the biasing voltage.
73
(a) (b) (c)
Figure 5.6: MOS Capacitor in Depletion Condition: (a) Biasing Arrangement; (b) Energy Band Diagrams;
(c) Net Charge in Metal and Semiconductor
5.1.2.4. Inversion
If the biasing voltage is raised further, there is more positive charge on the metal surface. In order to match
this with negative charge on the semiconductor side, the depletion region extends further into the bulk of the
substrate. At the same time, electrons are attracted from the bulk of the semiconductor into the depletion region
to contribute to the negative charge. The increased negative charge raises the energy bends further, causing
more bending of the bands in the depletion region. Eventually, the situation depicted in Figure 5.7(b) is
reached.
(a) (b) (c)

Figure 5.7: MOS Capacitor in Inversion Condition: (a) Biasing Arrangement; (b) Energy Band Diagrams;
(c) Net Charge in Metal and Semiconductor
In Figure 5.7(b), the energy bands have been raised so much that for a small region next to the oxide surface,
the Fermi Level is above the intrinsic Fermi Level (EF > EFi). This is the condition for an N-type
semiconductor, not a P-type semiconductor. Starting from the expressions for hole concentration in P-type
semiconductor:
( )
=
And in intrinsic semiconductor:
( )
=
A relationship between hole concentration and Fermi Level can be derived as:
( )
=
( )
= 5.4
74
And similarly for electrons:
= = ( )
( )
= 5.5
With EF > EFi, e(EF- EFi)/kT > 1 and therefore np > ni. The thermally generated electron concentration is higher
than the intrinsic concentration of electrons. Since nppp = ni2, the electron concentration is also higher than the
hole concentration. The semiconductor is now N-type.
The phenomenon of changing a semiconductor from P-type to N-type is called inversion.
Inversion occurs in a thin layer of semiconductor at the surface, next to the oxide. The rest of the depletion
layer remains in depletion.
5.1.2.5. Energy Band Analysis under Depletion
The behaviour of the energy bands in the P type semiconductor body of a MOS capacitor under different
biasing conditions is summarised in Figure 5.8.
(a) (b) (c)
(d) (e)
Figure 5.8: P-Type Semiconductor Body of MOS Capacitor Showing: (a) Energy Bands for Flat-Band
Condition; (b) Charge Distribution for Depletion Condition; (c) Energy Bands for Depletion Condition; (d)
Energy bands for Mid-Gap Condition (EF = EFi); (e) Energy Bands for Threshold Condition
Under flat band-conditions (Figure 5.8(a)), the flat-band voltage has been applied between the body and the
gate. This balances the built-in potential between the gate and body and ensures that there is no charge
movement between them. The whole semiconductor is electrically neutral and the bands are flat. The
difference between the Fermi level and the intrinsic Fermi level is the bulk potential, VB (=kT/q ln(Na/ni)).
If the gate to body voltage is increased above the flat band voltage, the MOS capacitor goes to depletion
condition. There is accumulation of negative charge due to negative donor ions in the depletion region, as
shown in (Figure 5.8(b)). Due to the presence of this charge, the potential in the depletion region is not
constant. The potential can be evaluated by integration of the one dimensional Poisson’s equation:
=−
75
Where ρ is the charge per unit volume (charge density) and ε is the permittivity of the medium.
For the depletion region, ρ = -qNa (since all the charge is due to acceptor ions) while ε = εs, the permittivity of
the semiconductor. The equation becomes:
= 5.6
Integrating once gives the electric field:
− = = +
The constant can be determined by applying continuity at the boundaries.

At x = 0, the electric field is equal to the field in the oxide. This is not determined.
At x = WDep, the electric field is equal to the field in the semiconductor outside the depletion region. Since this
region is at constant potential (zero net charge), the electric field is zero. Thus C1 = -qNaWDep/ εs and:
= − 5.7
Integrating again gives the electric potential as a function of distance from the semiconductor surface, x:
= − +
2
The body contact is connected to ground and is therefore the reference voltage. Therefore at x = WDep, V = 0.
Substituting gives:
=
2
And:
= − +
2 2
This can be re-written as:
= 1− 5.8
Where:
=
2
VS is the electric potential at the surface of the semiconductor in contact with the oxide. It is termed as the
surface potential. Since it is assumed that there is no voltage drop across the neutral region of the
semiconductor, VS is the potential drop across the depletion region. Also, the width of the depletion region is
given by:
2
= 5.9
Which is similar to the one sided P-N junction with VS replacing the built-in potential.
The conclusion to be drawn here is that the electric potential in the depletion region decreases with the square
of the distance from the surface at the semiconductor – oxide boundary.
76
As the potential drops, the potential energy of an electron increases and the energy bands are therefore raised.
This is presented in (Figure 5.8(c)). The depletion region does not cause a change in potential at the surface
and the energy bands remain at the same level as in the isolated semiconductor.
Moving into the depletion region of the semiconductor, the reducing potential causes the bands to move
upwards. The bands will become flat again at the edge of the depletion region where there is no more change
in potential.
The intrinsic Fermi Level, EFi, is always approximately half-way between EC and EV and therefore
demonstrates the same curvature in the depletion region. The actual Fermi level, EF, will be constant under
equilibrium conditions and is therefore a flat line. The level is determined by the position of the bands in the
neutral region of the semiconductor outside the depletion region. The difference in energy between the
intrinsic Fermi level and the actual Fermi level is therefore not constant in the depletion region.
As the gate to body voltage is increased further, the energy bands in the neutral region of the semiconductor
are raised further. The difference between the actual Fermi level and the intrinsic Fermi level in the depletion
region continues to decrease until the situation in Figure 5.8(d) is reached. The Fermi level at the
semiconductor surface is at the same level as the intrinsic Fermi level. The material at the surface is now
intrinsic with p = n = ni.
Further increase in the gate – body voltage, VGB will result in inversion condition at the surface. Under these
conditions, the inversion layer has very few mobile electrons and the conductivity is very low. The condition
is known as Weak Inversion.
5.1.2.6. The Threshold Voltage

It has been observed that under weak inversion, the conductivity of the inversion channel is very low.
Significant conductivity of the inversion channel is observed when the electron concentration is equal to or
higher than the hole concentration in the P-Type semiconductor. This condition is known as Strong Inversion.
The carrier concentration is determined by the difference between the energy at the band edge and the Fermi
Level. For electron concentration at the surface of the semiconductor to be equal to the whole concentration
in the neutral bulk of the P-type semiconductor, it is therefore necessary to have:
EF(Surface) – EFi = EFi - EF(Bulk). This occurs when
=2 =2 ln
The energy band condition at the onset of strong inversion (i.e at threshold) is shown in Figure 5.9(a).
It can be seen that the Fermi level at the surface of the semiconductor is at an energy qVB below the intrinsic
Fermi level. On the other hand, the Fermi level in the neutral bulk of the semiconductor (outside the depletion
region) is at an energy qVB above the intrinsic Fermi level.
Once inversion occurs, the semiconductor is able to meet the requirements of negative charge through
thermally generated electrons. The depletion region stops extending into the bulk of the substrate. The width
of the depletion region at this point is its maximum width, Wm.
Example: A MOS capacitor has P-type substrate with Na = 1017cm-3. Evaluate the maximum width of the
depletion region.
Answer: The maximum width of the depletion region, Wm is achieved when VS = 2VB = 2(kT/q ln(Na/ni)).
Applying this to the formula for WDep gives:
77
=2 ln 5.10
Substituting the values:

Wm = 2 * SQRT (11.9 * 8.85 x 10-14*0.0259*ln(1017/1010)/(1.6x10-19*1017)) = 1.05 x 10-5cm = 0.105μm.
(a) (b)
Depletion Region
Inversion Layer
Surface Charge
Semiconductor Bulk
Metal Gate Oxide
(Neutral)
Potential
(c)
Figure 5.9: P-Type MOS Capacitor at Threshold: (a) Energy Bands Structure; (b) Cross-section Showing
Charges; (c) Potential Profile Along Line X - X
The gate to body voltage, VGB at the onset of strong inversion is known as the Threshold Voltage, Vth. In
order to derive the threshold voltage, it is necessary to evaluate all the voltage drops across the MOS capacitor
between the gate terminal and the body terminal. The cross-section in Figure 5.9(b) illustrates the areas where
a voltage drop is expected. Starting from the gate terminal, the cross-section goes through:
1. The metal gate. A metal will have uniform potential. The metal will therefore have the potential VG with
respect to ground.
2. The layer of positive charge on the surface of the gate, next to the oxide. The potential across this layer
can be evaluated using Poisson’s equation. Since the layer has infinitesimal thickness, integration of the
Poisson’s equation will lead to zero voltage drop.
3. The oxide. An ideal oxide contains no charges. The change in potential is the result of the oxide being the
dielectric in the MOS capacitor. The electric field in a capacitor dielectric is constant. This implies a
constant potential gradient. The potential will therefore fall linearly across the dielectric from the metal
gate to the semiconductor body, with a total drop of Vox.
4. The inversion layer in the semiconductor next to the oxide. This has a net negative charge as a result of
thermally generated electrons. This layer is also considered to have infinitesimal thickness, hence a
potential drop of zero.
5. The depletion region. This will have the voltage falling with the square of the distance from the oxide, as
evaluated in the previous section. The total drop is VS = 2VB.
78
6. The bulk semiconductor outside the depletion region. This material is electrically neutral and will be at
constant potential.
The potential profile across the device at threshold is shown in Figure 5.9(c).
The voltage that equals the total drop across the device will be sufficient to change the device from flat-band
condition to the threshold condition. However, an external voltage is required to move the device to the flat-
band condition. The threshold voltage is therefore the flat band voltage plus the total voltage drop in Figure
5.9(c).
= +V +V 5.11
The flat band voltage and the voltage across the depletion region have already been derived. The voltage drop
across the capacitor can be evaluated using the relationship:
=
The oxide capacitance (per unit area) is given by
= 5.12
Where εox is the permittivity of the oxide and tox is the thickness of the oxide.
The charge on the gate is equal and of opposite polarity to the charge on the semiconductor. It is therefore
sufficient to evaluate the charge in the semiconductor. At threshold, the charge in the semiconductor is mostly
held in the depletion region, which has achieved its maximum width, Wm. The charge per unit volume is qNa.
The total charge per unit area is therefore:
= =2 ln 5.13
The voltage drop across the oxide is therefore:
2 2 5.14
= ln = ln
Substituting gives threshold voltage as:

2
= +2 ln + ln 5.15
The threshold voltage can be set by adjustment of semiconductor doping concentration (Na) and the oxide
thickness.
Example: Consider a MOS capacitor fabricated on a P-type silicon substrate that is doped with a net acceptor
concentration Na of 2 x 10l6 cm-3. The difference in work function between the gate metal and intrinsic silicon,
is -0.3eV; and the gate dielectric is silicon dioxide 25nm thick. The relative permittivity of silicon dioxide is
3.9, and that of silicon is 11.9. What are the flat-band and threshold voltages, Vfb and Vth, respectively? What
is the width of the depletion region above threshold, Wm? ni = 1010 cm-3, kT/q = 0.0259V.
Answer: For intrinsic silicon, Φs = χ + Eg / 2 = 4.05 +1.12/2 = 4.61eV.
For Gate Metal, Φm = -0.3 + 4.61 = 4.31eV.
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For the Substrate, VS = 2kT/q (ln(Na/ni)) =2*0.0259*ln(2x 1016/1010) = 0.751V
For Substrate, Φs = χ + Eg / 2 + kT/q (ln(Na/ni)) = 4.61+0.376 = 4.986eV
Vfb = ( Φm - Φs)/ q = (4.31 – 4.986) = -0.676V. And using Equation 5.15:
Vth = -0.676 + 0.751 + 0.516 = 0.591V.
Wm = 2.22 x 10-5cm = 0.22μm. (Equation 5.10)
5.1.3. Summary
The MOS capacitor has three different operating modes and two transition points depending on the gate to
body bias voltage. The operating modes are Accumulation, Depletion and Inversion. The transition points are
Flat band and Threshold. The MOS capacitor forms the control part of the MOS transistor (MOSFET).
Table 5.1: Biasing Conditions for MOS Capacitor with P-Type Body
Condition Biasing Band Structure Comments
Hole
Accummulation
EC Accumulation of holes in body,
close to oxide. The
Accumulation VGB < Vfb EF EF
EV
accumulation region has net
positive charge
Metal Silicon
Energy bands are flat like in

Flat Band VGB = Vfb isolated metal and
semiconductor
-Ve Acceptor Ions in

Depletion Region EC
EFi Depletion of holes in body,
EF EF
EV close to oxide. The depletion
Depletion Vth > VGB > Vfb
region has net negative charge
due to negative donor ions
Metal Silicon
The Fermi level in

semiconductor body is raised
Threshold VGB = Vth by
2 =2 ln
An N-type conduction channel

with free electrons is formed on
Inversion VGB > Vth
surface of semiconductor body
next to the oxide
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5.2. The MOSFET
5.2.1. Construction
The MOSFET is a MOS capacitor in which two heavily counter-doped regions are introduced in the substrate
on each side of the gate. Terminals are fitted through ohmic contacts to the counter-doped regions. The
terminals are called the Source, S and the Drain, D. Added to the Gate and Body contacts in the MOS capacitor,
the MOSFET can therefore have four terminals. However, it is usual for the source and body terminals to be
internally connected together, in which case the MOSFET has three terminals just like the BJT.
The region in the substrate between the counter-doped source and drain is called the channel. MOSFETs can
be N-Channel or P-Channel. In an N-channel MOSFET, the substrate is a P-type while the counter-doped
regions are N-type. In a P-channel MOSFET, the substrate is N-type while the counter-doped regions are P-
type.
The structure and schematic cross section of an N-channel MOSFET are shown in Figure 5.10.
(a) (b)
Figure 5.10: N-Channel MOSFET: (a) Structure; (b) Schematic Cross-Section
The key dimensions of the MOSFET are shown in Figure 5.11. These are:
• Channel length, L:-This is defined as the distance between the Source and Drain regions.
• Channel width, W: - This is the width of the channel. The metal, oxide, source, and drain all run this
distance over the cross-section of the substrate.
• Oxide thickness, tox: - the thickness of the oxide between the metal and semiconductor.
• Depth of doping, xj : - the extent to which the drain and source regions penetrate the substrate.
It can be seen from the schematic that the source and drain are interchangeable.
Figure 5.11: N-Channel MOSFET Key Dimensions

The circuit symbol of the MOSFET is shown in Figure 5.12.
81
(a) (b) (c) (d) (e)
Figure 5.12: MOSFET Circuit Symbol: (a) NMOS Enhancement; (b) PMOS Enhancement; (c) NMOS
Depletion; (d) Abbreviated, NMOS; (e) Abbreviated, PMOS
The symbol has a vertical bar representing the channel with horizontal bars connecting the drain and source
terminals at each end. The gate contact is indicated without a connection to the channel – since the gate is
insulated by the oxide. A body contact is included in the middle of the channel. An arrow on the channel
indicates the forward bias direction of substrate (body) to the channel. For enhancement MOSFETs, the
channel is shown as a dotted line while for depletion MOSFETs, the channel is shown as a solid line.
The abbreviated symbol does not show the substrate (body) contact. The bias arrow now shows the direction
of forward bias between channel and source.
5.3. The N-channel enhancement MOSFET
5.3.1. Operation
In operation an N-channel MOSFET uses a voltage source, vDS, to deliver current, iD from the Drain to the
Source. The drain current is regulated by the gate voltage via the MOS capacitor. In a three terminal MOSFET
(and in many cases for the 4 terminal device), the source is connected to the body and the gate to body bias is
therefore expressed as vGS, the gate to source voltage.
5.3.1.1. Cut OFF (VGS < VTh)
Consider a MOSFET with drain – source voltage applied and gate – source voltage at zero volts as in Figure
5.13(a). The channel is P-type while both source and drain are N-type. The junction between source and
channel (or drain and channel) is a diode, which is forward biased from channel to source (or channel to drain).
The diodes are back to back and will not allow current to flow either from source to drain or from drain to
source. ID = 0.
VDS
VDS VGS
S G D
S G D
+++++++ ID
Oxide Oxide
_ _ _ _
+ + + _
_
+
N Channel N N _
N
+++++++
Depletion
Depletion P- Type Body
P- Type Body
Body Body
(a) (b)
Figure 5.13: MOSFET Biasing: (a) VGS = 0, VDS is Positive; (b) 0 < VGS < Vth, VDS is Positive
Now consider a case where gate to source voltage is applied, with source connected to the body, Figure
5.13(b). The gate –source voltage is set at VGS < Vth. For this value of gate – source voltage, the gate – channel
capacitor is in depletion. The gate voltage induces a positive charge on the gate, which induces a positive
82
charge on the channel. The negative charge is achieved by driving mobile holes away from the channel,
leaving only immobile negative donor ions. There are no mobile charge carriers in channel and ID = 0.
If drain – source voltage, VGS is increased further, more negative charge is build up in the channel. Some of
the negative charge comes from electrons attracted from the N-type source and drain regions. However, the
number of mobile electrons is still low and the channel is still P-type. Diode at source –channel junction is
still reverse biased and there is no significant drain current. ID ≈ 0.
5.3.1.2. Ohmic Region - Linear (VTh < VGS ; VDS << (VGS - VTh))
Further increase in gate – source voltage will lead to a situation where VGS > Vth. Inversion occurs in the
channel and a thin N-type layer will form below the oxide layer, Figure 5.14(a). For small values of VDS, the
channel acts like a resistor and the relationship between IDS and VDS is linear, Figure 5.14(b).
VDS
VGS
S G D
+++++++ ID
Oxide
+ _
¯ ¯ ¯ ¯ ¯
_
_
_ _
_
_
_
+
N N
_ _ _ _
_ _
Inverted
Channel
P- Type Body
Body
(a) (b)
Figure 5.14: (a) MOSFET Biasing with VGS > Vth, VDS << (VGS- Vth); (b) I-V Curves
The resistance of the channel, rDS, can be evaluated from the dimensions of the device and the charge in the
inversion layer, which is the charge available for conduction.
1
= μ ( − ) 5.16
The drain current in the linear region of the characteristic is therefore:
= = μ ( − ) = ( − ) 5.17
Where Km is a constant of the MOSFET given by:
= μ
5.3.1.3. Ohmic Region - Non-Linear (VTh < VGS ; VDS < (VGS - VTh))
As VDS is increased further, it has an effect on the channel. The high voltage at the drain has the effect of
reducing the voltage drop between gate and channel. This causes a reduction in the dimensions of the channel,
starting from the Drain end, Figure 5.15(a). The channel becomes narrower and its resistance increases. The
drain current is now given by:
2( =− ) − 5.18
2
The drain current is now as shown in Figure 5.15(b).
83
(a) (b)
Figure 5.15: (a) Channel Tapering with Increased VDS ; (b) Effect on I-V Curves in Ohmic Region
At VDS = Vth, The channel is closed at the drain end. IDS reaches saturation value and does not increase with
VDS any more. The doted part of the curves in Figure 5.15(b) is therefore not valid.
5.3.1.4. Saturation Region (VTh < VGS ; VDS > (VGS - VTh))
The onset of saturation is when
= − 5.19
Substituting 5.19 in the current equation (5.18), the saturation current is given by:
( ) = = 5.20
2
Where Kn is a constant of the MOSFET given by:
= = μ
2 2
In saturation, the drain current IDS is independent of the drain to source voltage, VDS.
5.3.2. Transfer and Output Characteristics

The input parameter in a MOSFET is the gate to source voltage while the output parameters are the drain
current and drain to source voltage. Gate current for a MOSFET is almost zero. There are therefore no input
characteristics and only transfer and output characteristics. The characteristics are presented in Figure 5.16.
(a) (b)
Figure 5.16: Characteristics for N-Channel Enhancement MOSFET (a) Transfer; (b) Output
84
The characteristics show two distinct operating regions – the Ohmic Region and the Active (or Saturation)
Region. The MOSFET also has cut off when VGS < Vth. The MOSFET is operated in the three regions for the
following applications:
1. An amplifier in the Saturation Region.
2. As a switch in the Cut Off and Ohmic Regions:
a. Cut Off for OFF condition.
b. Ohmic for ON condition.
5.3.3. Non-Ideal Behaviour & Operating Limits
5.3.3.1. Channel Breakdown
If the drain source voltage is very high, the electric field across the channel can be high enough to cause
avalanche breakdown in the reverse biased Body – Drain junction. The drain current will then continue to
increase without change in VDS or VGS. This phenomenon is shown in Figure 5.17(a).
(a) (b)
Figure 5.17: (a) Output Characteristics Showing Channel Breakdown: (b) Channel Length Modulation
5.3.3.2. Channel Length Modulation
It was earlier premised that ID remains constant when VDS is increased beyond VDSS (VDS(sat)). However, the
increase in this voltage leads to the channel modulation effect. The pinch off point moves towards the drain
and the channel is effectively shortened, Figure 5.17(b).
Figure 5.18: Output Characteristics showing Effect of Channel Modulation
85
Current will continue to flow across the depleted region between channel and drain, by the same mechanism
as observed for the collector current in a BJT. However, a shorter channel will have less resistance (R=ρl/A).
The drain current will therefore increase.
As a result of channel length modulation, the output characteristics (Figure 5.18) show that the drain current
continues to increase with drain to source voltage in the saturation region. Extrapolating the curves backwards
sees them cross the x-axis and VDS = VM, the modulation voltage. This voltage is also known as the Early
voltage, VA, in line with the nomenclature for BJT.
5.3.3.3. Gate Oxide Breakdown
The gate oxide of a MOSFET is very thin and can experience breakdown if a high voltage is applied across it.
The oxide then becomes conducting and the device can no longer work. The breakdown voltage is about 30V.
Although 30V may seem high, it must be remembered that the MOSFET has a very high input resistance, and
a very small input capacitance, and thus small amounts of static charge accumulating on the device can cause
the breakdown voltage to be reached. The static charge may even arise due to touching the device with hands.
To prevent the accumulation of static charge on the gate capacitor of a MOSFET, gate protection devices are
usually included at the input terminals of MOS integrated circuits. These may be back to back Zener diodes
between source and gate or other diode clamping circuits.
Handling precautions can also prevent oxide breakdown. These include standing on earthed conducting mat
and wearing Earthing strips when handling MOS devices.
Figure 5.19: MOSFET with protection Zener Diodes
86
5.4. N-Channel Depletion MOSFET
A Depletion MOSFET will have a conducting channel with zero gate bias. It cannot therefore depend on
channel inversion to create a conducting channel between gate and source. The N-Channel device is therefore
constructed with the following features:
1. A P-Type Substrate
2. N-Type Source and Drain Regions
3. An N-region constructed on top of the substrate between drain and source to act as the channel.
A schematic cross-section of the device is shown in Figure 5.20(a).
(a)
Figure 5.20: N-Channel D MOSFET: (a) Schematic Cross-Section; (b) Transfer Characteristics; (c) Output
Characteristics
Like the enhancement MOSFET, the depletion MOSFET seeks to control the current between drain and source
by use of a voltage between gate and source, VGS. A negative VGS induces negative charge on the gate. The
capacitor effect induces a positive charge on the channel. This is achieved by depleting channel of electrons
(the channel operates in depletion state). As a result, the conductivity of channel decreases and less current
flows. A D-MOSFET will therefore have drain current with zero gate to source voltage. As the gate to source
voltage is decreased, the conductivity of the channel is reduced and the drain current decreases.
A D-MOSFET can be used in enhancement mode. When the gate to source voltage, VGS is positive, it induces
a positive charge on the gate. This in turn induces a negative charge on the channel, which is achieved by
attracting more electrons into the channel (the channel is driven into accumulation state). The resultant
increase in electron concentration in the channel leads to increased conductivity of the channel.
The transfer and output characteristics of the N-Channel Depletion MOSFET are shown in Figure 5.20(b) and
Figure 5.20(c) respectively.
Depletion MOSFETs are mainly used as amplifiers. An operating point can be selected with zero gate bias.
The input signal will then drive the device into enhancement mode when positive and into depletion mode
when negative.
87
5.5. Application of MOS Devices
The MOSFET can be used as a switch or as an amplifier.
5.5.1. MOSFET as a Switch
Switching applications usually apply the enhancement MOSFET in which the channel is not conducting under
zero bias. The MOSFET is connected in the common source configuration, with a DC source connected in
series with the channel and a load, Figure 5.21(a).
When the gate to source voltage is zero, the device is in Cut Off and there is no conduction between drain and
source. Hence there is no current in the load and the condition is Open Switch
In order to drive the switch into Closed condition, a voltage is applied between gate and source such that:
VDS ≤ VGS - VTh.
This drives the MOSFET into the Ohmic Region. There is low resistance in the channel and for Closed Switch
RL
ID
D VDS
G
S
vi =
(a) (b)
Figure 5.21: MOSFET Application: (a) E-MOS as Switch; (b) D-MOS as Amplifier in Common Source
Configuration
5.5.2. MOSFET as an Amplifier
For application as an Amplifier, the D –MOSFET is used. There are three possible amplifier configurations:
• Common Drain
• Common Source
• Common Gate
The device is biased to operate in the active or saturation region with VDS > VGS - VTh.
For the common source amplifier (Figure 5.21(b)) the input signal is vgs and the output signal is id or vds.
Because the gate draws almost zero current (since the oxide insulates it from channel), the common source
amplifier has input impedance that is close to infinity. This is very desirable for a voltage amplifier.
The D-MOSFET can be biased with Q-point at VGS = 0 such that the positive cycle of the input signal drives
it to enhancement mode while the negative cycle drives it into the depletion mode.
5.5.3. MOSFET Small Signal Model

The MOSFET has an insulated gate. This is accommodated in the small signal model by having no connection
between the input and output ports. On the output, a voltage controlled current source represents the
dependence of the drain current on the gat – source voltage. Also, an output resistance represents the channel
modulation effect. The hybrid π small signal model is shown in Figure 5.22.
88
Figure 5.22: Hybrid π Small Signal Low Frequency Model of N-Channel E MOSFET
The model parameters are evaluated as:
The transconductance:
= −2 1− 5.21
For enhancement MOSFETs. The output resistance:

1
= = 5.22
Where λ is the channel modulation length and VM is the modulation voltage, also known as Early voltage, VA.
5.5.4. Practical applications of MOS Devices

MOSFET and MOS capacitor has many practical applications. The main mode of applications involve use of
the MOSFET as a switch or use of the MOS capacitor or MOSFET as a memory device. Applications include;
1. The MOS capacitor has applications other than as a component of the MOSFET. The key application is in
Charge Coupled Devices (CCD) where the capacitor is used as a light sensor for imaging applications. A
CCD (charge−coupled device) is an imaging device based on an array of MOS capacitors operating under
the deep-depletion condition, starved of inversion charge. Photo-generated carriers are collected in the
surface potential wells, and the collected charge packets are transferred in a serial manner to the charge-
sensing circuit located at the edge of the array.
2. CCD imagers have been replaced by CMOS imagers where cost, size, and power consumption are more
important than the best image quality. CMOS imagers integrate a charge-to voltage conversion circuit in
each sensing array element. In both types of imagers, colour sensing is achieved with separate sensing
elements for red, green, and blue in each pixel.
3. An alternative image sensor is the MOS image sensor, which uses MOS transistors. This is cheaper than
CCD but produces images of lower quality than CCD.
4. Touchscreens are large flat displays are made from thin film transistors (TFT). These are MOS transistors
fabricated out of polycrystalline silicon on insulating substrate such as glass.
5. Most semiconductor memory used in computers and other digital computational devices are made from
MOS technology. This includes dynamic ram (DRAM -which is very short term and needs to be refreshed
constantly), static RAM (SRAM – longer term but is not retained with power off) and longer term memory
like flash memory.
6. Power MOSFET are used in applications to deliver large power e.g. DC power supplies.
89
5.6. MOSFET Scaling
The MOSFET is very popular for use in integrated circuits (especially digital circuits). One major advantage
is the ability to shrink the size of the device. This is called scaling and it allows production of integrated
circuits that have more components and use less power per component.
1961: First 1978: Intel

Integrated 8086. Used in
Circuit, 2 first IBM PC.
Transistors 29000
Transistors
1993: Pentium; 1995: Pentium Pro; 2008: Core i7
1,180,235 5,500,000 Transistors Quad;
Transistors 2006: Core 2 Duo; 731,000,000
291,000,000 Transistors
Transistors
2013: ARM64 2017: Qualcomm 2018: Apple A12X Bionic

Mobile SoC Snapdragon 845 (octa-core ARM64 mobile
(System on (octa-core ARM64 SoC;
Chip); mobile SoC; 10,000,000,000 Transistors
1,000,000,000 5,300,000,000 For iPad 11 and 12.
Transistors
Figure 5.23: Evolution of Transistor Count in Integrated Circuits
The dimensions that are scaled are:
W = Width of Gate
L = Length of Gate
tox = thickness of Oxide
xj = depth of doping
The dimensions of each are multiplied by a factor 1/S, where S is the scaling factor. The supply voltage is
reduced by the same factor. The device has its area and power consumption reduced by a factor 1/S2.
Scaling is limited by associated problems known as short channel effects.
5.7. Comparison of FET with BJT

Comparison of some features between BJT, MOSFET, JFET, MESFET:
1. On General Characteristics:
a. BJT is a bipolar device (both holes and electrons are used in conduction). FET are unipolar devices (use
only one charge carrier, electrons for N channel and holes for P channel).
b. Conduction in FET is by drift while conduction in BJT is by diffusion.
2. In switching circuits:
a. BJT has lowest switching speed as a result of the need to remove minority carrier charge. This is
important for both digital circuits and power circuits.
b. BJT can however handle large currents and voltages. This is important for power circuits but not for
digital circuits.
90
c. FET devices have a higher OFF resistance and a lower ON resistance than BJT, which reduces power
losses in switching circuits for power applications.
d. MOSFET digital circuits can designed in complementary arrangement (CMOS) which has very low
power consumption.
e. BJT is current controlled while FET is voltage controlled. FET switches have simpler control circuits.
3. In amplifiers:
a. MOS amplifiers have higher input impedance than BJT amplifiers. This is desirable for voltage
amplifiers. MOSFET has the highest input impedance, due to the insulated gate.
b. BJT has lower output impedance than FET. This is again a desirable attribute for power amplifiers.
c. The high frequency performance of transistors is measured by the cut off frequency. The MESFET has
the highest cut off frequency and is used for microwave applications (frequencies in a few GHz). The
JFET has a cut off frequency than BJT but the MOSFET may have a lower cut off frequency than BJT.
4. Others: MOSFET are very suited for size scaling, which allows packing of many more devices in an
integrated circuit. This allows delivery of more complex applications and lower power consumption.
5.8. CMOS and BiCMOS Technology

CMOS circuits combine N-channel and P-Channel MOSFETs on the same device. They achieve digital logic
gates with very low power consumption. A cross section of CMOS device fabrication is shown in Figure
5.24(a). The Schematic circuit of a CMOS inverter is shown in Figure 5.24(b).
An analysis of the inverter will demonstrate that when the input is at 0Volts, the NMOS is OFF while the
PMOS is ON and the output is at voltage VDD. On the other hand, when input is VDD, the NMOS is ON while
the PMOS is OFF and the output is zero volts.
Because only one transistor is ON in any one logic state, the current flow from the power supply to ground is
very low and is equal to the leakage current of the device that is OFF. The almost zero current flow leads to
very low power consumption, which cannot be matched by devices using any other technology. Significant
current flow is only experience during the short transient period when the output changes from low to high
and vice versa. During this transition, the devices are temporarily both on.
(a) (b)
Figure 5.24: CMOS Technology: (a) Cross Section of NMOS and PMOS fabricated on same Substrate; (b)
CMOS Inverter
91
An analysis of the inverter will demonstrate that when the input is at 0Volts, the NMOS is OFF while the
PMOS is ON and the output is at voltage VDD. On the other hand, when input is VDD, the NMOS is ON while
the PMOS is OFF and the output is zero volts.
Because only one transistor is ON in any one logic state, the current flow from the power supply to ground is
very low and is equal to the leakage current of the device that is OFF. The almost zero current flow leads to
very low power consumption, which cannot be matched by devices using any other technology. Significant
current flow is only experience during the short transient period when the output changes from low to high
and vice versa. During this transition, the devices are temporarily both on.
It was noted that MOS devices have low output current and voltage limits when compared to the BJT. An
attempt to combine the advantages of the simple switching circuit with low power consumption of CMOS and
high power output of the BJT is called BiCMOS technology. The technology uses a CMOS input stage driving
a BJT output stage. It is applied in both digital and analogue integrated circuits.
Example:
The output characteristics of an N-Channel MOSFET are shown below.
a. Is the MOSFET Enhancement or Depletion type?
b. Estimate the threshold voltage, VTh.
Answer: (E-Type. There is no conduction with zero gate bias)

a. (At Saturation, VDS = VGS – VTh. Evaluating for different values of VGS: At VGS = 5V, VDS(Sat) = 3.6V,
hence VTh= 1.4V; At VGS = 4.5V, VDS(Sat) = 3.1V, hence VTh= 1.4V; At VGS = 4V, VDS(Sat) = 2.5V,
hence VTh= 1.5V; CONCLUSION: VTh ≈ 1.4V)
92
5.9. The MESFET
Transistors can achieve higher cut off frequencies if the transit time of carriers is short. For FET devices, only
one carrier is used. Electrons have a much higher mobility than holes and N-channel devices would have a
much higher transit time (hence much higher cut-off frequencies) than P-Channel devices.
The compound semiconductor, Gallium Arsenide (GaAs), which has an electron mobility more than 5 times
that of silicon. The transit time for electrons in GaAS would therefore be much higher than in silicon. There
was therefore interest in building FET devices using GAAs for igh frequency applications. Initial interest was
to build a metal oxide semiconductor (MOS) device out of GaAs. However, it is not possible to grow a stable
oxide out of GaAS.
The solution was to develop a device similar to the JFET but with a metal –semiconductor junction at the gate
instead of a PN junction. The result is the Metal, Semiconductor Field Effect Transistor, MESFET, first
proposed in 1966. The device structure is presented in Figure 5.25.
Figure 5.25: MESFET Structure

GaAs has a large band gap and low ni. The result is that the material has very high resistivity. GaAs MESFETs
are fabricated on a semiconducting GaAs substrate and have only one gate contact, unlike the Silicon JFET.
The metal contact at the gate is designed to have a very high Schottky barrier height in order to minimise the
gate current. A suitable metal for the gate is gold.
Example: What is the Schottky barrier height for a junction between gold and N-type GaAS, Nd = 1016cm-3?
Property Silicon GaAs Au
Relative Permittivity 11.9 13.1
Band Gap (eV) 1.12, Indirect 1.424, Direct
μp (cm2/V.s) 470 400
μn (cm2/V.s) 1500 8500
ni (cm-3) 1.0x1010 1.79x106
χ (eV) 4.05 4.07
Φ (eV) 5.1
The output characteristics of all field-effect transistors (FETs) are similar. They all have a linear region at low-
drain biases. As the bias increases, the output current eventually saturates, and at a sufficiently high voltage,
avalanche breakdown occurs at the drain.
The MESFET has significant speed advantages over the JFET and MOSFET:
1. The material in a MESFET is GaAs with higher electron mobility than silicon.
2. In a MOSFET, the drain source current Ids flows on an inversion channel at the surface of the
semiconductor. This further reduces the mobility of charge carriers. In a MESFET, Ids flows in the body
of the semiconductor and therefore the electron mobility is not degraded by surface scattering. This fact
further enhances GaAs MESFET’s speed advantage.
93
The speed advantages can be measured by the cut off frequency fT. For a given length, the silicon MOSFET
(N-type) has the lowest fT and the GaAs MESFET has an fT about three times higher than that of silicon.
MESFETs are usually depletion devices, which have a conducting channel at zero gate bias. The high
resistivity of GaAs would make it suitable for an enhancement mode devices, which have high resistance
under zero gate bias. However, this would require a positive gate voltage. The range of positive voltage that
can be applied without forward biasing the Schottky diode is very low. Hence enhancement mode MESFET
are not common.
Example:
16 -3
A junction is fabricated between gold and N-type GaAS with Nd = 10 cm ? (For Au, Φ = 5.1eV; For GaAs:
6 -3
χ = 4.07eV, Band Gap = 1.42eV, ni = 1.79x10 cm )
a. What is the work function of the GaAS?
b. What is the Schottky barrier height for the junction? Is it rectifying or Ohmic?
χs
φs
φm
Answer:
Φs = χs +Eg/2- (EF- EFi)
16 6
EF- EFi = (kT/q)ln(Nd/ni) = 0.0259 * ln(10 /1.79x10 )= 0.58eV
Φs = 4.07 + 0.71 – 0.58 = 4.2eV
ΦBN = Φm - χs = 5.1 – 4.07 = 1.03eV
The Majority carriers (electrons) will have a lower energy at the Fermi Level in the metal than at the edge of
the conduction band in the GaAS. Electrons will move from GaAS to metal until Fermi levels align and
equilibrium is achieved. At equilibrium, there will be a Schottky barrier which will oppose movement of
majority carriers from metal to GaAs to metal. There will also be a barrier (Φm - Φs =) opposing flow of
electrons from GaAs to metal, which can be reduced by biasing. The junction is rectifying.
94
Chapter 6. Optoelectronic Devices
6.1. Introduction
Optoelectronics is concerned with devices whose operations involve the emission or absorption of light.
Optoelectronic devices have many applications including:
1. As source of light in LED lighting.
2. In applications requiring coloured lights e.g. traffic lights, indicator lights, and video billboards.
3. Conversion of solar energy into electricity in solar cells.
4. Reading and writing information in optical storage like CD / DVD.
5. As sensors / transducers in control systems e.g. optical sensors detect the presence of a car or pedestrian at
an automated barrier and prevent the possibility of the barrier hitting them.
6. As components in an optical communication system.
A study of optoelectronics requires an understanding of the electromagnetic spectrum and the dual wave /
particle nature of light. It also requires understanding of the process of light emission and absorption in
semiconductors.
But first an overview of a major part of the application of optoelectronics – optical communication.
6.1.1. Overview of Optical Communication System
In traditional communication systems the information was carried by electrical signals in copper cables or
electromagnetic waves in air or space. In the last 30 years, the technique of transmitting information as optical
signals has become dominant. The essential component of optical communication systems is the support which
contains the optical signal and leads it from a source to a destination. This function is carried out by Optical
Fibres. Fibre optic communication systems offer a lot of advantages with respect to the conventional cable
facilities, that is:
1. Larger bandwidth, which allows for transmission of more information (e.g. more telephone signals and
internet data)
2. Higher immunity from electromagnetic noise.
3. No irradiation, i.e. no electromagnetic energy has to pass through people, plants and animals.
4. Smaller size.
5. Less attenuation; this enables links on longer distances without any intermediate amplification.
The general structure of an optical communication system is shown in Figure 6.1.
Figure 6.1: Fibre optic communication system

The main components are:
1. Optical-fibre cable
2. Electrical-optical interface and optical source / transmitter
3. Optical receiver / photodetector and optical-electrical interface.
4. For very long distances, an optical repeater (amplifier) may be required between the source and detector.
95
Fibre optic cables are not electronic devices and will not be covered here. The devices used as transmitters,
receivers and amplifiers are covered here. These include light emitting diodes (LED), Laser Diodes, Photo
Detectors, Photo Diodes and Photo Transmitters.
(a) (b)
Figure 6.2: (a) Structure of an optical fibre; (b) Multiple Fibre Cable
6.1.2. Electromagnetic Radiation
6.1.2.1. Introduction
An electromagnetic wave consists of a time varying electric field and a time varying magnetic field at right
angles to each other. The two fields are propagating in space in a direction perpendicular to the variation of
the fields (i.e. transverse waves), Figure 6.3.
Figure 6.3: Electromagnetic Wave

Electromagnetic waves propagate at the speed c, which is given by:
1
= = 6.1
√
Where μ and ε are the permeability and permittivity of the medium respectively. For free space vacuum) this
gives the speed of propagation as 2.998 x 108 ms-1. λ is the wavelength and ν is the frequency. This document
will also use the symbol f for frequency. Another important parameter related to waves is the wave number,
k. This is the number of complete oscillations per unit length.
2
= 6.2
6.1.2.2. Quantum Concepts

The quantum theory was developed in the early 20th century to explain some observed phenomenon that could
not be explained using classical theories of physics. The theory consisted of a number of postulates, two of
which are relevant to optoelectronics.
96
From classical mechanics, particles were expected to have momentum, while electromagnetic waves could
not have momentum. Observations such as Compton scattering led to a revision of this position. According to
de Broglie’s hypothesis, particles and radiation have a dual nature. Each particle has a wavelength, λ, related
to its momentum, p and each wave has momentum related to its wavelength. The relationship between
wavelength and momentum is given by:
ℎ
= 6.3
Where h is Plank’s constant. The wave nature of a particle is only observable if the wavelength is large enough
to interact with observable objects.
From6.2 and 6.3, the momentum of a wave is related to its wave number by:
ℎ
= 6.4
2
Classical mechanics also postulated that an electromagnetic wave could deliver energy in any quantity, so
long as the radiation was of sufficient intensity. While investigating blackbody radiation and photo-electric
emission respectively, Planck and Einstein found that the energy of electromagnetic waves comes in discrete
quanta (or packets, singular is quantum) called photons. It is not possible for an EM wave to deliver energy in
quantities less than the energy of one photon. The energy of one photon depends on the frequency of the EM
wave and is given by the Planck – Einstein relationship:
ℎ
=ℎ = 6.5
6.1.2.3. The Electromagnetic Spectrum

The full range of frequencies that electromagnetic waves can have is called the electromagnetic spectrum. The
spectrum is divided into categories covering different ranges of frequencies depending on the properties of
the waves in that range of frequencies.
By the early 20th century, it had become generally accepted that light is a form of electromagnetic radiation.
Light occupies a tiny segment of the electromagnetic spectrum known as the visible spectrum. Optical
electronics is concerned with the visible spectrum and the neighbouring bands of infra-red and ultra violet.
The range of wavelength, frequencies and photon energy for the electromagnetic spectrum is given in Table
6.1. An expanded view of the visible spectrum and neighbouring bands is given in Table 6.2.
Table 6.1: Electromagnetic Spectrum
Name Wavelength Frequency Photon Energy
Gamma ray < 0.01 nm > 10 x 1019Hz 100 kev - 300+ GeV
X - ray 0.01 - 10 nm 30 EHz - 30 PHz 120 eV - 120 keV
Ultraviolet 10 nm - 400 nm 30 PHz - 790 THz 3.2 eV - 124 eV
Visible 390 nm - 770 nm 769 THz - 389 THz 1.6 eV - 3.2 eV
Infrared 770 nm - 1 mm 405 THz - 300 GHz 1.24 meV -1.6 eV
Microwave 1 mm - 1 meter 300 GHz - 300 MHz 1.24 μeV - 1.24 meV
Radio 1 mm - km 300 GHz - 3 Hz 12.4 feV - 1.24 meV
97
Table 6.2: Visible Spectrum and Neighbouring Bands
Name Wavelength Frequency Photon Energy
Extreme infrared 1000 μm – 40 μm 0.3 THz – 7.5 THz 1.24 - 31meV
Far infrared 40 μm – 6 μm 7.5 THz – 50 THz 31 - 207meV
Medium Infrared 6 μm – 1.5 μm 50 THz – 200 THz 207 - 827meV
Near Infrared 1.5 μm – 0.77 μm 200 THz – 389 THz 0.827 - 1.61eV
Red 770 nm – 622 nm 389 THz – 482 THz 1.61 - 1.99eV
Orange 622 nm – 597 nm 482 THz – 502 THz 1.99 - 2.08eV
Yellow 597 nm – 577 nm 502 THz – 520 THz 2.08 - 2.15eV
Green 577 nm – 492 nm 520 THz – 609 THz 2.15 - 2.52eV
Blue 492 nm – 455 nm 609 THz – 659 THz 2.52 - 2.73eV
Violet 455 nm – 390 nm 659 THz – 769 THz 2.73 - 3.18eV
Near ultra-violet 390 nm – 300 nm 769 THz – 999 THz 3.18 - 4.13eV
Far ultra-violet 300 nm – 200 nm 1 PHz – 1.5 PHz 4.13 - 6.20eV
Extreme ultra-violet 200 nm – 10 nm 1.5 PHz – 30 PHz 6.20 - 124eV
Optical communication uses electromagnetic radiation with frequencies in the range of 700nm to 1.7μm, i.e.
in the near infra-red range. Radiation in the visible wavelengths are used for displays and applications like CD
/ DVD readers. Radiation in the ultra violet range is used in conjunction with phosphorescent materials to
produce white light for LED lighting.
6.1.3. Review of Energy Bands in Semiconductors
Electromagnetic waves are generated from materials as a result of a change in electron energy. Absorption of
electromagnetic waves results in a change in in electron energy. A review of the energy band theory of solids
is given here as a basis for the study of opto-electronic devices.
Also already established in Physical Electronics I, electrons propagate as electromagnetic waves. The location
and energy of an electron can be predicted by solution of the Schrödinger wave equation. The solution of this
equation gives the possibilities for the energy of an electron. This is summarised in Figure 6.4.
E E E ENERGY
n =4 Allowed Band
n =3
CONDUCTION BAND
Forbidden Band
EC
n =2
FORBIDDEN BAND Eg
EV
n =1 VALENCE BAND
(a) (b) (c) (d)

Figure 6.4: Possible Energies for (a) Free Electron; (b) Electron in an isolated Atom; (c) Electrons in a
Crystal; (d) Valence and Conduction Bands in a Crystal
1. For a free electron, i.e. an electron propagating in a region with no electromagnetic field, all values of
energy are allowed, Figure 6.4 (a).
98
2. For an electron bound by an electrostatic potential, e.g. an electron in an isolated atom, electron can only
have certain distinct values of energy, known as energy levels, Figure 6.4(b).
3. For an electron in a periodic potential (e.g. inside a crystal), there are bands of allowed energies separated
by bands of forbidden energies, Figure 6.4(c). Two allowed bands are of interest for determining the
properties of a solid, Figure 6.4(d). The highest energy band whose states are filled with electrons at 0K
is the valence band. The lowest energy band whose states are empty of electrons at 0K is the conduction
band. The difference in energy between the lowest energy in the conduction band (EC) and the highest
energy in the valence band (EV) is known as the band-gap energy, Eg.
6.1.3.1. Direct and Indirect Band-gap Semiconductors
For a free electron (propagating in a region where the potential energy is zero), the total energy is kinetic
energy, which can be expressed in terms of mass and momentum as:
ℎ
. .= = 6.6
2 8
A plot of Energy versus wave number is therefore a parabola, Figure 6.5(a). In three dimensions, k becomes
a wave vector, which is a combination of the different wavenumbers for each of the three dimensions:
= + +
In a crystal, an electron in the valence or conduction band interacts with a periodic array of atoms and there
are many possible wave solution for the electron. There will be different solutions for each crystal direction
and different solutions for the valence or conduction band. A plot of energy against wave vector in a crystal
is therefore a combination of many different parabola. The band-gap energy is the difference in energy
between the highest energy value of the electron waves in the valence band and the lowest value of energy for
the electron waves in the conduction band. There are two possibilities:
1. The highest energy in VB and lowest energy in CB can occur at the same value of wave number. This is a
direct band-gap material Figure 6.5(b). An example is gallium arsenide.
2. The highest energy in VB and lowest energy in CB can occur at different values of wave number. This is
an indirect band-gap material Figure 6.5(c). An example is silicon.
(a) (b) (c)
Figure 6.5: E – K Plot for (a) Free Electron; (b) Electrons in a Direct Bandgap Material; (c) Electrons in an
Indirect Band-gap Material
If two electrons, one in the valence band and one in the conduction band have the same value of wave number,
k, they also have the same momentum. If they have different values of wave number, they have different
values of momentum.
99
6.1.3.2. Shallow and Deep Impurity Levels
Semiconductor materials have two types of mobile charge carriers – electrons and holes. In an intrinsic (pure)
semiconductor, there is an equal number of electrons and holes. The conductivity of a semiconductor can be
enhanced by the addition of impurities called dopants. Donor impurities increase the number of free electrons
to make an N-type semiconductor while acceptor impurities increase the number of holes to make a P-type
semiconductors. Impurities can also be introduced unintentionally during the manufacturing process. These
will also be donor or acceptor.
Impurities in a semiconductor have an effect on the allowed energies of electrons and holes, as demonstrated
in Figure 6.6.
Si
Si
Free Electron
Si
Si
As
Si
Si
Si
(a) (b)
Figure 6.6: Arsenic Atom in Silicon Crystal: (a) Before Ionisation; (b) After Ionisation
Figure 6.6(a) is a two dimensional representation of the bonds in a silicon crystal where one silicon atom has
been replaced by an arsenic atom. Arsenic has five valence electrons. It uses four of the electrons to bond with
four neighbouring silicon atoms. One valence electron in the arsenic atom is not used in bonding. As long as
this electron is still held in orbit by the arsenic atom, it is not available to conduct electricity.
If however, the electron gains enough energy to break free from the arsenic atom and move freely within the
crystal, it will be available to conduct electricity. This situation is shown in Figure 6.6(b). The energy required
for the electron to break free from the arsenic atom is known as the ionisation energy of the dopant.
A conduction electron has energy whose value is within the conduction band of the semiconductor (≈EC). The
unbound electron in Figure 6.6(a) will therefore have energy equal to EC – Ionisation Energy. It is established
that for Group V impurities, the ionisation energy is much less than the band-gap energy, Eg. Therefore, before
ionisation, the donated electron has an energy that falls within the forbidden gap.
It can therefore be concluded that impurities in a semiconductor introduce allowed energy states in the
forbidden energy band. Donor impurities create donor levels, just below the edge of conduction band (i.e. EC).
Acceptor impurities create acceptor levels, just above the edge of the valence band (i.e. EV). These levels are
shown in Figure 6.7(a).
Conduction Band Ec
Donor Level Ed
Donor ionization energy
Acceptor ionization energy

Acceptor Level
Ea
Ev
Valence Band
(a) (c)
Figure 6.7: Impurity Level Concept for Silicon: (a) Donor and Acceptor Levels; (b) Shallow and Deep
Impurity Levels (Unless otherwise indicated, levels above mid-gap energy are Donor while levels below are
Acceptor)
100
Impurities that are used as dopants (i.e. Group V elements for donors and Group III elements for acceptors in
silicon) have ionisation energies that are ≤ 3kT (= 0.0777eV at T = 300K). The impurity levels are therefore
very close to the edge of the forbidden band. These impurity levels are known as Shallow Levels. Other
impurity elements e.g. transition metals have ionisation energies that are >3kT. The energy levels created by
these impurities are known as Deep Levels.
The impurity levels of different elements in silicon are shown in Figure 6.7(b). Impurities with shallow levels
can gain sufficient thermal energy at room temperature to meet the required ionisation energy. Shallow
impurities are therefore assumed to be 100% ionised. Deep impurities will not have sufficient thermal energy
at room temperature and are rarely ionised. They can however act as traps and capture electrons or holes. For
example, an electron may move from the conduction band to a deep acceptor level and be no longer available
for conduction. Similarly an electron can move from a deep donor level to the valence band and combine with
a hole (≡ a hole moves from valence band to a deep donor level).
If a captured electron leaves the acceptor and moves to the valence band (where it combines with a hole), the
acceptor level will have served as a Recombination Centre.
6.1.4. Light Absorption and Emission by Semiconductors
In a semiconductor at room, temperature, there are some electrons in the conduction band and some holes in
the valence band. Thermal generation of electrons and holes is continuous, but is balanced by recombination
to maintain the equilibrium defined by mass action law:
=
The intrinsic concentration, ni is a constant for a given temperature.
A semiconductor material can have electrons in the valence band excited by external source of energy so that
they cross the forbidden band and move to the conduction band, thus producing an electron hole pair. One
way in which this occurs is by absorption of photons of electromagnetic radiation e.g. visible light. Excess
electrons or holes can also be injected by an electric current.
When a semiconductor is excited giving rise to extra electron hole pairs, mass action law will require that
electrons and holes recombine in order to restore the balance. This recombination may result in the emission
of photons of electromagnetic radiation.
6.1.4.1. Light Absorption
Carrier generation due to light absorption occurs if the photon energy is large enough to raise an electron from
the valence band into an empty conduction band state, thereby generating one electron-hole pair. The photon
energy needs to be equal to or larger than the bandgap energy to satisfy this condition.
=ℎ ≥
The photon absorbed in this process and any excess energy, Eph - Eg, is added to the electron and the hole in
the form of kinetic energy. The electron moves from the top of the valence band to the bottom of the
conduction band. The process is shown in Figure 6.8.
When an electron – hole pair is generated in a direct band-gap semiconductor, the electron will have the same
value of k in the conduction band as it had in the valence band. For indirect band-gap semiconductors, the
electron will have a different value of k in the conduction band than the value it had in the valence band. Since
k = 2π/λ, and p = h/λ, the electron will have different momentum in the conduction band from what it had in
the valence band. Momentum must be conserved, and this is achieved by generation of lattice vibrations called
phonons. Photo-generation in indirect band-gap semiconductors is therefore less efficient in indirect band-gap
semiconductors than in direct band-gap semiconductors because extra energy is required to generate the lattice
vibrations.
101
(a) (b) (c)
Figure 6.8: Photo Generation of Electron Hole Pair (a) Energy Requirement; (b) Process in a Direct Band-
Gap Semiconductor; (c) Process in an Indirect Band-gap Semiconductor
Example: If a semiconductor is transparent to light with a wavelength longer than 0.87 μm, what is its band-
gap energy? (Answer: 1.42 eV).
6.1.4.2. Light Emission from Semiconductors
Once an electron-hole pair has been generated, the semiconductor will have excess holes and electrons because
the product np is now greater than ni2 for the particular temperature. The semiconductor is not at equilibrium.
Equilibrium will be restored by combination of the excess holes and electrons to reduce the carrier
concentrations to equilibrium levels (np = ni2). The process involves an electron moving from the bottom of
the conduction band to the top of the valence band where it recombines with a hole. The electron loses energy
equal to Eg. This energy will be released either as a photon of radiation or as lattice vibration (phonon). The
recombination is therefore termed as:
1. Radiative recombination – when the energy is released as a photon.
2. Non-radiative recombination – when the energy is released as lattice vibration.
Whether the recombination is radiative or non-radiative depends on the recombination mechanism. There are
three different mechanisms as presented in Figure 6.9.
Figure 6.9: Recombination Processes

1. Direct – recombination or Band-to-band recombination. This occurs when an electron moves from its
conduction band state into the empty valence band state associated with the hole. The process is different
for direct band-gap and indirect band-gap materials:
102
a. In direct band-gap materials, direct recombination takes place without change in k. The process is very
efficient and is usually radiative.
b. In indirect band-gap semiconductors, direct recombination would require a change in k. The electron
energy is therefore released as a lattice vibration (phonon) and is never radiative. The process is very
inefficient and rarely occurs.
2. Trap-assisted recombination. This occurs in a semiconductor which has deep impurity levels in the
forbidden band. In trap-assisted recombination, an electron in the conduction band falls into a trap. The
electron occupying the trap, in a second step, moves into the valence band and combines with a hole,
thereby completing the recombination process. One can envision this process as a two-step transition of
an electron from the conduction band to the valence band or as the annihilation of the electron and hole,
which meet each other in the trap. Once the trap is filled it cannot accept another electron. Trap assisted
recombination is usually not radiative, but in can be radiative in specific cases. Since band to band
recombination is very rare in indirect semiconductors, trap assisted recombination is usually the process
observed in those materials.
3. Auger recombination. This is a process in which an electron and a hole recombine in a band-to-band
transition, but now the resulting energy is given off to another electron or hole instead of being released
as a photon or phonon.
The band-gap energy and band-gap type of some selected materials is presented in Table 6.3. The frequency
of the emitted photon is given by the relationship:
=
ℎ
This equation can be modified to give the wavelength of the emitted photon as:
1.24
=
Where λ is in μm and Eg is in eV.
Table 6.3: Band-Gap Energy for Some Selected Materials

Material Eg (eV) , Type λ(nm) Material Eg (eV) , Type λ(nm)
AgCl 0.32 I 3875 InN 1.89 D
AgI 0.28 D 4429 InP 1.34 D
CdS 2.5 D 496 InSb 0.23 D
CdSe 1.8 D 689 PbS 0.3 D 4133
CdTe 1.48 D PbTe 0.25 I 4960
Diamond 5.4 I 230 Si 1.12 I
GaAs 1.42 D SiC 2.41 I
GaN 3.44 D TiO2 3 I 413
GaP 2.27 I ZnO 3.3 I 376
GaSb 0.75 D ZnS 3.75 D 331
Ge 0.66 I ZnSe 2.82 D
InAs 0.35 D ZnTe 2.39 D
Exercise:
1. Evaluate the wavelength of photon emitted in a direct recombination for the materials in Table 6.3. Indicate
the position of the radiation in the electromagnetic spectrum.
103
2. For application in lighting, LEDs would be required to give out white light. One way of achieving this is to
combine 3 LEDs with Red, Green and Blue Light. Identify whether there is any combination of materials
in Table 6.3 that can be used to generate white light.
6.1.4.3. Spontaneous and Stimulated Emission

When a semiconductor is excited such that np > ni2 electrons will move spontaneously (i.e. without any further
external intervention) from the conduction band to the valence band in order to combine with holes and restore
the mass action law balance. If the transition is radiative, the emission of radiation is known as spontaneous
emission.
A semiconductor can also emitted radiation by stimulation by an incident photon of electromagnetic radiation.
The incident photon causes an electron in the conduction band to move to the valence band and combine with
a hole. The energy lost by the electron is released as a photon that is of the same frequency and in phase with
the incident photon. This process is known as Stimulated Emission.
It should be noted that under normal circumstances, an incident photon is more likely to be absorbed by a
bound electron in the valence band and excite it to the conduction band. In order for stimulated emission to
occur, there must therefore be more electrons in the conduction band than in the valence band. This condition
is known as population inversion.
Figure 6.10: Summary of Band to Band Radiative Transitions: (a) Absorption; (b) Spontaneous Emission;
(c) Stimulated Emission; (d) Photon Received without Population Inversion; (e) Photon Received with
Population Inversion
6.2. Optical Sources

Optical Sources apply either spontaneous or stimulated emission to generate electromagnetic radiation. In
order to act as radiation sources, energy has to be supplied in the form of an electric current. This current
injects carriers in the semiconductor resulting in a situation where np > ni2. The excess carriers are removed
by recombination which results in emission of light. The process is called electroluminescence.
It should be noted that electroluminescence is only possible with direct band-gap materials. Silicon cannot
therefore be used to make optical sources.
6.2.1. The Light Emitting Diode (LED)
Under forward bias, a PN junction experiences carrier injection across the depletion region. Once they cross
the depletion region, the injected carriers undergo recombination, Figure 6.11(a).
104
For direct band-gap materials, this recombination is mainly radiative. Under normal circumstances, the
emitted photons are emitted in random directions. As a result, they get re-absorbed and re-emitted many times
inside the semiconductor and do not get out of the semiconductor, Figure 6.11(b).
(a) (b)
Figure 6.11: Light Emitting Diode: (a) Operating Principle; (b) Light Reflection at Surface for Normal
Diode Structure
6.2.1.1. LED Construction
A light emitting diode is specifically designed to ensure that the emitted photons get out of the semiconductor
and are directed in one desired direction. The structure of a typical LED is shown in Figure 6.12.
(a) (b)
(c)
Figure 6.12: LED Construction: (a) Cross-section of Semiconductor material; (b) LED Package – 3D View;
(c) 2D View of Domed Surface of LED
The structure has the following features:
1. Epitaxial construction to avoid crystal defects, which could create recombination centres.
2. The junction is near the surface to minimise absorption in the semiconductor.
3. The N-side is heavily doped to ensure that recombination occurs on the P-side which is nearer the surface
(the depletion region is mostly on the lightly doped side).
105
4. The device is package in a transparent dome with a high refractive index. The dome structure increases the
incident angle of radiation while the high refractive index ensures a high critical angle. Together, these
features minimise reflection back into the structure.
5. The metal interconnections are arranged away from the surface where light output is to exit the device.
6.2.1.2. LED Bandwidth & Characteristics
Theoretically, an LED will give out radiation at one frequency, determined by the band-gap energy, Eg of the
semiconductor. In practice however, it is noted that electrons have a maximum concentration at an energy
about kT/2 above EC while holes have maximum concentration at an energy kT/2 below EV. The energy in
band to band transition of electrons has a spread of:
∆ = ∆(ℎ ) ≈ 3
This energy spread will be manifested in the spread of frequencies of emitted photons, hence:
∆(ℎ ) = ∆ ≈ 3
Since
ℎ ℎ
= = =
ℎ
Then
ℎ
= =− =−
(ℎ ) (ℎ ) ℎ
And
∆ = ∆(ℎ ) = 3
ℎ ℎ
NOTE: The derivation of the equation for bandwidth of the emission from an LED applied here seems
strange, especially because h is not treated as a constant during differentiation. The actual variable is
electron energy, E. Once the final expression is derived, the resultant range of photon wavelengths can be
derived by substituting E = hν= hc/λ
The spread of output wavelength is shown in Figure 6.13(a) and Figure 6.13(b). The wavelength where peak
intensity is achieved increases with temperature due to reduction in band-gap energy.
The characteristics of voltage against current and light intensity against current are shown in Figure 6.13(c)
and Figure 6.13(d) respectively.
Light emitting diodes have a high forward voltage drop which depends on the LED material. Since LED colour
also depends on the material the forward drop varies with the colour, generally increasing as wavelength
reduces. The forward drop for a typical Red LED is about 1.5V. Once the voltage drop is reached, it remains
almost constant with current. The output light intensity increases proportionally with current.
Figure 6.13: LED Characteristics: (a) & (b) Light Intensity Against Wavelength; (c) Voltage against
Current; (d) Light Intensity against Current;
106
6.2.1.3. LED Efficiency
The efficiency of LED operation is a measure of the light energy produced as a fraction of the electrical energy
input. This can be expressed as the proportion of electron-hole recombination that result in photons of energy
transmitted outside the device. This measure is termed quantum efficiency. Efficiency is less than 100%
because not all recombination are radiative and not all emitted photons manage to exit the device. Quantum
efficiency therefore has two components, internal quantum efficiency and external quantum efficiency.
1. Internal quantum efficiency is the ratio of the radiative recombination to total (radiative + non-radiative)
recombination in the PN diode.

=
( + − )
2. External quantum efficiency is the ratio of generated photons that are emitted outside the semiconductor.
ℎ ℎ ℎ
=
ℎ
The total efficiency of an LED is the product of internal quantum efficiency and external quantum efficiency.
6.2.1.4. LED Materials
The construction of LEDs is done in such a way as to increase both internal and external quantum efficiency.
LED requires radiative recombination in a semiconductor. Indirect band-gap semiconductors are therefore not
suitable for LED manufacture. This eliminates the elemental semiconductors silicon and germanium.
Compound semiconductors are made from elements having a combined valence of 8. Thus a combination of
Group III and Group V elements (III – V semiconductors) e.g. GaAs, GaN, InAs, InN and II – VI
semiconductors e.g ZnS, CdTe.
Indirect band-gap materials may be used if there is a suitable impurity that could result in radiative trap assisted
recombination. An example is Gallium Phosphide (GaP) which demonstrates radiative recombination when
some nitrogen is added.
The material used in an LED depends on applications. The main applications are:
1. Transmitters for optical communications. This requires mainly infra-red LEDs.
2. Indicator lamps – requires mainly red LEDs.
3. High intensity traffic – Requires Red, Yellow and Blue LEDs.
4. Billboards – Requires Red, Yellow and Blue LEDs.
5. Flat panel and curved displays – Organic Light Emitting Diodes (OLED). These are made from some
organic polymers that have semiconductor properties.
6. Solid state lighting. LED lighting can be much more efficient in terms of energy use than incandescent and
even fluorescent lighting. This would require production of all three primary colours – red, green and blue.
Practical LEDs for lighting applications use a UV LED and a phosphor material that produces white light
when it absorbs UV radiation. OLEDs may also be used to produce solid state lighting. LED lighting can
theoretically achieve a luminous efficacy of 300 lumens per watt (commercially available lamps achieve
about 90 l/W). Linear fluorescent lamps are able to achieve 90 l/W while compact fluorescent lamps
achieve 70 l/W.
A calculation of wavelength of radiation from common III – V and II – VI semiconductors will quickly show
that there is no suitable material to produce some forms of EM radiation, e.g. blue LED. LED material is
normally specially designed by combining more than 2 elements to produce a material having a band-gap that
107
matches the wavelength of the desired radiation. When three elements are combined, this is a ternary
semiconductor. Four materials produce quaternary semiconductor.
Table 6.4: Binary and Ternary Semiconductor LED Materials
Material Eg (eV) λ (μm) Colour

InAs 0.36 3.44 Infra-Red
InP 1.36 0.91 Infra-Red
GaAs 1.42 0.87 Infra-Red
GaP 2.26 0.55 Green
AlP 2.43 0.51 Green
InxGa(1-x)N 2.7* 0.46 Blue
GaN 3.4 0.36 UV
*: The band-gap of ternary and quaternary semiconductors depends on the ratio of the elements, as
determined by the value of x. The band-gap quoted here is for a specific value of x.
Table 6.5: Ternary and Quaternary Semiconductor LED Materials
Colour Material Substrate Applications

Infrared InGaAsP InP Optical communication
Infrared-Red GaAsP GaAs Indicator lamps. Remote control
Red-Yellow AlInGaP GaA or GaP Optical communication. High-brightness traffic lights
Green-Blue InGaN GaN or sapphire High brightness signal lights. Video billboards
Blue-UV AlInGaN GaN or sapphire Solid-state lighting
Red-Blue Organic glass Displays
Examples:
1. The LED with characteristics in Figure 6.13(a) has a median wavelength of 665nm. What is the band-gap
of the material making the LED? Answer: Eg(eV) ≈1.24/λ(μm) = 1.24/0.665 = 1.86eV
2. What is the spectral width in wavelength for LEDs operating at a median wavelength of: (a) 850nm; (b)
1310nm; (c) 1550nm. What is the band-gap energy of the semiconductor material? Answer: Δλ = -
λ2*3kT/hc. kT = 4.143 x 10-21; hc = 1.986 x 10-25. 3kT/hc = 6.26 x 104. (a) Δλ = - (8.5x10-7)2 * 6.26 x 104
= 45nm; (b) Δλ = - (1.31x10-6)2 * 6.26 x 104 = 107nm; (c) Δλ = - (1.55x10-6)2 * 6.26 x 104 = 150nm;
6.2.2. Laser Diode

LED light output has a wide spectrum, which is not suitable for some applications like long distance optical
communication and reading of optical storage devices. Where light with very narrow spectrum is required,
lasers and laser diodes are used. While LEDs generate light by spontaneous emission, laser diodes generate
light by stimulated emission of radiation.
It was noted earlier that population inversion is a requirement for stimulated emission. Population inversion
can be achieved in a P-N junction in which both P and N regions are degenerately doped. A degenerately
doped semiconductor has Nd ≥ NC for N-type or Na ≥ NV for N-type. As a result in a degenerately doped N-
type semiconductor, all the states at EC are occupied by electrons and the Fermi Level, EF is above EC.
108
Similarly for a degenerately doped P-type semiconductor, EF is below EV and all the states at EV are occupied
by holes, i.e. there are no electrons at EV. A P-N junction made from such materials is shown in Figure 6.14.
Electrons
EC EF
EC
Holes Electrons Holes EC
EV EF EV
EF EC EV
EF
EV Population Inversion
(a) (b)
Figure 6.14: Population Inversion in P-N Junction: (a) Zero Bias; (b) Large Forward Bias
Under zero bias (Figure 6.14(a)), both the N-side and P-side have normal distribution of electron populations,
with more electrons occupying the lower energy levels. Under forward bias, the potential barrier at the junction
is lowered and carriers are injected into the depletion region. For a strong forward bias, the depletion region
will have electrons at EC and holes at EV, as in (Figure 6.14(b)). There is therefore population inversion.
Photons incident in this region will not absorbed but will instead stimulate emission of other photons. The
construction and characteristics of a laser diode are shown in Figure 6.15.
(a) (b)
Figure 6.15: Laser Diode: (a) Construction; (b) Light Intensity – Current Characteristic
Laser diodes generally emit light along the junction area. Mirrors are used to reflect generated light and direct
it towards the desired output. Laser diodes have a threshold current below which they operate as ordinary
LEDs with low intensity of output. Laser Diodes made from one semiconductor material (homo-junction)
have very high threshold current at room temperature and are rarely used. Hetero-junction devices are used
instead. Applications of laser diodes include CD / DVD reading and writing (red laser diode); Blue Ray DVD
reader / writer (blue laser diode); Transmitters in Fibre- Optic Communication (infra-red laser diode).
NC is the effective density of states of the conduction band while NV is the effective density of states of the
valence band.
109
6.3. Optical Detectors
Optical detectors convert electromagnetic radiation into electrical signals. They are applied as receivers in
optical communication and also as transducers for light detection and measurement. Optical detectors need to
achieve the following functions:
1. Allow electromagnetic radiation to penetrate the detector and generate electron-hole pairs. Ideally, the
carrier generation should be uniform throughout the detector.
2. Separate the generated carriers and prevent recombination.
3. In conjunction with an external circuit, use the carriers to generate an output current or voltage signal.
Optical detectors include photo-conductors, photodiodes and photo transistors. Optical detectors can use
indirect band-gap materials although the quantum efficiency will be less than for direct band-gap materials.
The only requirement is that the band-gap of the semiconductor must be less than or equal to the photon energy
of the radiation to be detected.
6.3.1. Photo-conductors
A photoconductor is a piece of semiconductor of length L, width W, and depth D, with an ohmic contacts at
either end, Figure 6.16.
Figure 6.16: Photoconductor: (a) Schematic; (b) In Circuit

A current is passed through the photoconductor. When light is incident on the conductor, it generates electron
hole pairs. This increases in number of carriers reduces the resistance of the photo-conductor. As a result, the
current through the device increases. Measurement of this current can be used to determine the intensity of
light that was incident on the semiconductor (intensity ≡ number of photons per unit time).
6.3.1.1. Carrier Generation under Steady Illumination
Consider a piece of semiconductor with equilibrium electron and hole concentrations of no and po respectively
where nopo = ni2. If the semiconductor is uniformly illuminated with e/m radiation with hν ≥ Eg. The radiation
will generate additional electron – hole pairs, which results in an additional concentration of n’ = p’. The total
concentration of electrons and holes therefore becomes;
= + ; = + with =
A steady light source will generate carriers at a constant rate of G per second. With generation of excess
carriers, the semiconductor is not at equilibrium since np > ni2. Recombination of holes and electrons will
start to try and restore the equilibrium. The rate of recombination is proportional to the excess carrier
concentration and is given by:
=−
Where τ is the excess carrier lifetime. This expression is valid for low level injection.
The rate of change of carrier concentration is the difference between recombination is given by:
110
= = = −
Now suppose the light source has been generating carriers at a constant rate of G per cm-3 per second for a
long time. A steady state is reached where the rate of generation is equal the rate of recombination, which
means the rate of change of carrier concentration is zero. Hence:
= − =0
And:
=
This expression is valid for low level injection.
6.3.1.2. Photoconductivity
The conductivity of a semiconductor with equilibrium electron and hole concentrations of no and po
respectively is given by:
= +
When light falls on the semiconductor, it generates additional electron – hole pairs, which results in an
additional concentration of n’ = p’. The conductivity therefore changes to:
= ( + ) +( + ) = +
Where σo is the equilibrium conductivity and σ’ is the photoconductivity.
If ohmic contacts are made on the semiconductor and it is connected across an emf source, the change in
conductivity can be identified by an increase in current in the circuit.
Such an arrangement can be suitable for detecting the presence or absence of light. However if an accurate
measurement of measurement of the level of illumination is required this simple arrangement will have the
following challenges:
1. The conductivity does not have a linear relationship with illumination. This is because the electron and hole
mobilities - μn and μp are different.
2. A linear illumination – conductivity relation, even for only one type of carrier, will only be achieved under
low level injection. This condition means that the concentration of majority carriers can only change by
10% from complete absence of illumination to maximum allowed illumination. This small change is not
suitable for accurate measurements.
Example: A piece of silicon is doped with acceptors to a concentration of 1 x 1015cm-3. It is steadily
illuminated by visible light such that it has a carrier generation rate, G = 1019cm-3s-1 throughout the
semiconductor. The illumination is applied for a long time. Assume τ = 10μs; ni = 1 x 1010, μn = 1400cm-2s-1;
μp = 460cm-2s-1.
a. Evaluate: no; po; σo; n’; p’; σ’; n; p; σ. Answer: po = Na = 1 x 1015cm-3; no = ni2/Na = 1 x 105cm-3; n’=
p’= Gτ = 1019 x 10-5 = 1014cm-3; n = no;+ n’≈ n’ = 1014cm-3; p = po;+ p’ = 1.1 x 1015cm-3.
b. Do low level injection conditions hold? Answer: Yes. p’ ≤ 0.1po is satisfied.
6.3.1.3. Unipolar Photoconductor
The two problems mentioned in the previous sub-section can be solved by having a semiconductor in which
the majority carriers have zero mobility.
The process by which is achieved is shown in Figure 6.17. Consider a P-Type semiconductor with acceptor
concentration Na. The semiconductor is also doped with deep donors to a concentration Nt.
111
Electron -
EC
Captured +
Hole
(a) (b) (c) V E

Figure 6.17: Energy Band Structure Showing Hole Capture by Deep Impurity: (a) Electron, Hole and Deep
Donor; (b) Movement of Electron from Donor Location; (c) Captured Hole
At room temperature, all the acceptors will be ionised a concentration, Na of holes and ni2/ Na of electrons.
Since the donors are deep, they will not be ionised at room temperature. The more likely occurrence is that
electrons from the deep donor sites will move to the valence band and combine with holes – those eliminating
the mobile holes. The deep donor positions will become positively charged but will not be mobile.
In other words, the deep donors will act as traps, capturing holes and making the immobile. The semiconductor
material will have only electrons as mobile charge carriers. Since electron concentration in a P-type material
is very low, conductivity of the material will be almost zero under no illumination. Since electrons are minority
carriers, their concentration can be increased by illumination up to 0.1 Na while maintaining low level injection
conditions. This allows a wide operating range for the sensor.
Example: A piece of silicon is doped with acceptors to a concentration of 1 x 1016cm-3 and a larger
concentration of deep donors. It is steadily illuminated by visible light such that it has a carrier generation
rate, G = 1020cm-3s-1 throughout the semiconductor. The illumination is applied for a long time. Assume τ =
10μs; ni = 1 x 1010, μn = 1100cm-2s-1; μp = 400cm-2s-1. Evaluate the conductivity without illumination and with
the given illumination.
Answer: All holes are captured by the deep donors, only electrons are available for conduction.
2 20 16 4 -3 -12 -1
Without illumination: no = ni /Na = 10 /10 = 10 cm ; σo = o n = 1.1 x 10 Scm ;
20 -5 15 -3 -1 -1
With illumination: n’ = Gτ = 10 * 10 = 10 cm ; σ = n( o + ’) = 1.1 x 10 Scm ; σ’ = σ - σo = 1.1 x
-1 -1 13
10 Scm ; 10 % Change
6.3.2. Photodiodes
In a PN junction at equilibrium, the energy bands on the P-side are higher than the bands on the N-side. If the
junction area is illuminated so that electron – hole pairs are generated in the region, the generated carriers will
tend to move towards the region where carrier energy is lower. This means the N-side for electrons and the P-
side for holes, Figure 6.19(a). This effectively separates the generated carriers and avoids recombination. It
should be noted that the direction of movement of the photo-generated carriers is in opposition to direction of
movement for a forward biased diode.
(a) (b) (c)

Figure 6.18: Photodiode Principle: (a) Carrier Separation in a PN Junction; (b) PN Photodiode Schematic
Cross-Section; (c) Photodiode in Circuit
112
A photodiode is a diode which has been constructed in such a way as to allow incident light to reach the
junction area, Figure 6.19(b). It has a thin highly doped P region and a Large N region. The thin P-region
allows light to reach the depletion region which is the desired area for generation of carriers.
In circuit, a PN photodiode is operated under reverse bias (Figure 6.19(c)) in order to match the direction of
carrier movement that will reduce the chances of recombination. Reverse bias causes the depletion region to
extend deep into the thickness of the N side of the device. When a photon of energy greater than the bandgap
is incident, it becomes absorbed and photo-generates a free electron hole pair (EHP) in the depletion layer.
The electric field present in the depletion layer pulls the EHP apart until they reach the neutral regions of the
device. Motion of the electrons photo-generated in the device by the electric field produces a photocurrent, Iph
in the device.
The total current in a diode is the sum of the phot-current and the current due to the biasing supply. The total
current is given by:
= −1 −
The I-V characteristic of the photodiode under constant illumination is shown in Figure 6.19(a). Since the
reverse current, IS is close to zero and almost constant, the current of a reverse biased photo-diode is the result
of photo current only. The device has reverse current even when voltage drop across the device is zero. The
characteristic looks like that of a normal diode shifted downwards by the photo-current.
A photodiode can also be used with zero bias, in which case it is said to operate in photovoltaic (as opposed
to photo-conduction) mode. All the current in photovoltaic mode is photo-current (there is no dark current).
Current
Iph Voltage
(a) (b)
Figure 6.19: (a) Photodiode Characteristic; (b) P-I-N Photodiode
When a photo-diode is to be used as a receiver in an optical communication system, the response time has to
match the high frequency of light in the communication system. This requires a thin depletion region. On the
other hand, a large depletion region is required to increase light absorption and therefore photo-generation of
carriers. One device that balances the conflicting requirements is the P-I-N Photodiode. This device has an
intrinsic region between heavily doped P and N regions. The intrinsic region presents a large area for
absorption of radiation, Figure 6.19(b).
113
6.3.3. The Photo-transistor
The photo transistor is an NPN BJT without a base connection. Instead the device is constructed in order to
allow incident light to easily reach the depletion regions, especially at the base – collector junctions, Figure
6.20.
(a) (b)
Figure 6.20: Phototransistor (a) Structure for Epitaxial BJT; (b) Symbol
Light incident on the B-C depletion region results in carrier photo-generation. The carriers are separated by
the P-N junctions with electrons moving into the collector and the holes into the base. This flow constitutes
the base current. The photo-electrons that move into the collector are extracted by the external biasing circuit.
The holes that move into the base are neutralised by injection of electrons form the N-type emitter. The
injection of electrons from the emitter results in transistor action. The total collector current is therefore an
amplified version of the photocurrent, which is given by βIph.
6.3.4. Efficiency of Photo-Detectors
The purpose of a photo-detector is to receive optical power and convert it into electron-hole pairs which can
be detected as a current or a voltage by an external circuit. Like optical sources, the performance of photo-
detectors can be measured in terms of optical efficiency.
The External Quantum Efficiency of a photo-detector is the number of electron-hole pairs generated and
collected by the external circuit per incident photon.

= =
ℎ
ℎ
Where Iph is the generated photo-current, q is the electronic charge, P is the incident power and hν is the energy
of a single photon.
The external quantum efficiency of a photo-detector is limited by a number of factors:
1. Reflection: Not all incident photons penetrate into the semiconductor. Some are blocked from reaching
the surface of the semiconductor while others are reflected back at the surface of the semiconductor. To
minimise reflection, the light receiving surface of a semiconductor is usually coated with an antireflection
coating.
2. Recombination: Some of the generated electron-hole pairs recombine and are therefore not detected by
the external circuit. In order to minimise the possibility of recombination, the following measures are taken
in the design:
a. Photo-detectors are designed to have an electric field which will separate the negatively charged
electrons from the positively charged holes. In photo-diodes and photo-transistors, this field is the
built-in field in the depletion region of a P-N junction, which is in many cases reverse biased to increase
the field. For photoconductors, the field is provide by an external DC power supply.
b. For Photo-diodes and Photo-transistors, the semiconductor layer where light is incident is made very
thin to ensure that light is absorbed in the depletion region, where the built-in field will separate the
114
carriers and avoid recombination. Photo-conductors conductors are made thin (D in Figure 6.16(a) is
small, in order for incident light to penetrate through the material and generate carriers uniformly.
3. Absorption: Incident photons that are absorbed into the semiconductor should ideally be absorbed when
they generate an electron-hole pair. In practice photons are able to travel some distance in the
semiconductor before they are absorbed. The Absorption Coefficient, α, is the light energy lost per unit
distance travelled in the semiconductor. The effects of the absorption coefficient affect the quantum
efficiency in the following ways:
a. The semiconductor material should be thick enough to allow absorption of most of the incident photons.
For example, if the thickness of the material is equal to the Penetration Depth, δ (δ = 1/ α), only a
fraction of 1/e (=63%) of the incident photons will be absorbed.
b. The absorption coefficient depends on the wavelength of the incident light. There is a small range of
wavelengths for which a given semiconductor achieves high quantum efficiency.
i. If the wavelength is too long, the photon energy will be smaller than the band-gap energy and the
radiation will pass right through the semiconductor without being absorbed (The semiconductor
material is transparent to light above a cut-off wavelength, λc, with Eg = hc/λc).
ii. If the Wavelength is too short, the light will be absorbed very first, e.g. before reaching the depletion
region. Generated electron-hole pairs therefore have a higher chance of recombining. Also, some
of the energy in these quick absorptions will be released as phonons (= quanta of lattice vibrations).
Items 2 and 4 above are measured by the internal quantum efficiency.
The Internal Quantum Efficiency of a photo-detector is the number of electron-hole pairs generated and
detected per photon absorbed into the device.
The external quantum efficiency incorporates the internal quantum efficiency.
6.4. Optical Amplifiers

When optical communication is to be transferred over long distances, it is necessary to have amplifiers (also
known as repeaters) at intervals along the optical transmission line. Optical amplifiers receive optical
messages at low power and re-transmit the same at high power (i.e. receive a few photons and transmit many
photons).
Since the message is encoded in the waveform, the repeater should produce exact copies of the received
photons. The appropriate device for this purpose is the laser diode. In the travelling wave semiconductor laser
(Figure 6.21), light is fed into the active region of the laser at one end. As it propagates through the laser, it
causes stimulated emission and is therefore amplified. A power supply is required to achieve population
inversion which is required for lasing operation.
Figure 6.21: Diode Laser as Optical Amplifier

115
6.5. Photovoltaic Devices
Consider a PN junction with an anode terminal on the P side and a cathode terminal on the N side. If light
with photon energy greater than or equal to the band-gap energy is incident on the junction area, electron-hole
pairs will be generated. If there is no external connection to the terminals, positively charged holes will
accumulate on the P side, next to the anode. At the same time, negatively charged electrons will accumulate
on the N side, next to the cathode. There will be a potential difference across the terminals. If the two terminals
are connected using a conductor, a current will flow. A PN junction can thus operate as an EMF source. The
process of converting light energy into electrical energy is known as the photovoltaic effect.
Solar cells use the photovoltaic effect to convert light from the sun into electrical energy. Solar cells have very
important applications in the provision of energy in areas where normal energy sources cannot be used e.g. on
satellites and in remote ground based locations. Solar cells are also considered as important sources of
renewable energy for general terrestrial applications. Solar energy is considered a renewable energy source
since it is not expected to be exhausted in the foreseeable future.
6.5.1. Solar Radiation

A blackbody is an object that absorbs all radiation incident upon it. The blackbody radiates energy with
characteristics that depend only on its temperature. The sun generates power through nuclear fusion reactions.
The solar irradiance (Ho in W/m2) is the power density incident on an object due to illumination from the sun.
At the sun's surface, the power density is that of a blackbody at about 6000K and the total power from the sun
is this value multiplied by the sun's surface area. However, at some distance from the sun, the total power
from the sun is now spread out over a much larger surface area and therefore the solar irradiance on an object
in space decreases as the object moves further away from the sun. The energy is also reduced by absorption
of by elements in the suns atmosphere. The solar energy just outside the earth’s atmosphere is termed AM0
(Air Mass = 0).
Figure 6.22: Comparison of spectral irradiation densities: black body radiation at 5800 K, AM0 Solar
irradiation just outside Earth’s Atmosphere; AM1.5 Solar irradiation at Earth’s Surface (for Central Europe)
116
In the atmosphere, solar radiation is further absorbed by the chemicals that make up the atmosphere, especially
water. The energy reaching the surface of the Earth after passing through the atmosphere is AM1 (Air Mass
= 1, at the equator).
The solar irradiance is an instantaneous power density in units of kW/m2. The solar irradiance varies
throughout the day from 0 kW/m2 at night to a maximum of about 1kW/m2. The solar irradiance is strongly
dependant on location and local weather. Solar irradiance measurements consist of global and/or direct
radiation measurements taken periodically throughout the day.
The solar insolation is the total amount of solar energy received at a particular location during a specified
time period, often in units of kWh/(m2 day). It is usually expressed as the peak solar insolation.
6.5.2. Working Principle of a Solar Cell

The term photovoltaic is derived from the combination of two terms: the photon, a ‘particle’ of light energy,
and the volt, a unit of electromotive force.
The working principle of solar cells is based on the photovoltaic effect, i.e. the generation of a potential
difference at the junction of two different materials in response to electromagnetic radiation. The photovoltaic
effect is closely related to the photoelectric effect, where electrons are emitted from a material that has
absorbed light with a frequency above a material-dependent threshold frequency.
The photovoltaic effect can be divided into three basic processes:
1. Generation of charge carriers due to the absorption of photons in the materials that form a junction.
2. Subsequent separation of the photo-generated charge carriers in the junction.
3. Collection of the photo-generated charge carriers at the terminals of the junction.
A solar cell is basically a semiconductor P-N junction designed to achieve the three functions.
Generation: Electron-hole pairs are generated in the depletion region of a PN junction through photo-
generation.
Separation: In the depletion region of a PN junction has a built-in electric field. This field separates the
generated electron-hole pairs. Electrons move to lower energy on the N-side while holes move to lower energy
(for holes) on the P side.
Collection: The charge carriers are extracted from the solar cells with electrical contacts so that they can
perform work in an external circuit.
The operation is summarised in Figure 6.23(a).
Voltage
VOC
Current
Illumination Halved
0.5ISC-1
ISC-1
(a) (b)
Figure 6.23: Solar Cell: (a) Operating Principle; (b) Characteristic
117
6.5.3. Solar Cell Characteristics
Light with energy equal to or exceeding the band-gap energy can generate electron-hole pairs in the depletion
region of the solar cell. The built-in electric field of the depletion region separates the carriers. Electrons move
to the N side while holes move to the P side. This creates an open circuit voltage, VOC.
If an external conductor (zero resistance) is connected across a PN junction under photo-excitation, a current
will flow. This is called the short circuit current, ISC. The current is proportional to light intensity, i.e. the
number of photons received. The short circuit current increases linearly with light intensity. The open circuit
voltage has a non-linear relationship with light intensity and peaks at about 0.6V.
If an external variable resistor is connected instead of a short circuit, the current can be varied between zero
(for open circuit) and ISC (for short circuit). The voltage across the solar cell will vary between VOC (for open
circuit) and zero (for short circuit). The I-V characteristics, shown in Figure 6.23(b) resemble those of a
photodiode.
When operating with positive voltage and negative current, the solar cell generates power. If a load resistor is
placed in the external circuit, power will be delivered to the resistor. The operating point will be the point on
the I-V characteristic where it intersects the line with the load line equation.
=
The power delivered to the load is given by:
=
at the operating point.
This is the area of the rectangle bounded by the operating point and the two axes. Figure 6.24 shows the I-V
characteristics of a solar cell with load lines for two values of load resistance, RL-1 and RL-2. The two operating
points are marked as P1 and P2 respectively. Also shown are the rectangles representing the product VI for
each operating point.
Voltage Vm VOC
RL-1
Current
RL-2 P1
Im P2
ISC
Figure 6.24: Solar Cell Power Output. P2 is the Maximum Power Output Point
There is a maximum size of rectangle that can fit in space under the characteristic for a given intensity of
radiation. The load resistance that results in the maximum size of rectangle will result in maximum power
transfer, where
=
It is clear from the characteristic that the maximum possible voltage is VOC while the maximum possible
current is ISC. However, no power is delivered when voltage is VOC or current is ISC. If a solar cell was
constructed with the I-V characteristics having a rectangular shape, it would be possible to deliver power equal
to VOCISC. A measure of how close the characteristic is to a rectangular shape is the Fill Factor, FF.
=
118
Typical fill factors range from 60 – 85%.
Controls for large scale solar farms usually include maximum power point tracking.
6.5.4. Solar Cell Construction
Conventional solar cells are built from a P-type silicon wafer, as sketched in Figure 6.25. The N-type layer on
the top of the P-wafer is much thinner than the wafer; it typically has a thickness of around 1 μm. Often, this
layer is called the emitter layer. The N-type layer is heavily doped for low resistivity and is very thin to allow
for passage of light. The ohmic contact to the N layer is in the form of metal fingers about 0.1mm wide and
0.05mm thick. This arrangement allows for thin connections that allow for illumination to pass through while
also the large number of fingers reduces the overall resistance of the contacts. The fingers are connected to a
common busbar for external connection. A transparent insulating anti-reflection coating about 60nm thick
covers the top silicon layer. The whole wafer has typically thicknesses in between 100 and 300 μm. The
bottom of the cell has a metal coating that makes ohmic contact with the P-type body of the silicon.
Figure 6.25: Solar Cell Construction

6.5.5. Solar Cell Efficiency
The efficiency of a solar cell is the percentage of solar energy incident on the cell that is converted to electric
energy and delivered to a load. Measured per second the incident solar energy is solar power and the efficiency
can be evaluated as:
× ×
=
Incident Solar Power
Solar cells have very low energy conversion efficiency. The main sources of energy loss are:
1) The part of the solar spectrum with photon energy less than the band-gap of the solar cell material. For a
typical silicon solar cell, this is equal to about 26% of total incident energy.
2) For photons of solar radiation with energy equal to or higher than the band-gap energy, each photon
generates one electron-hole pair (EHP) while the excess energy is lost as kinetic energy of the electron
(and eventually as heat). This accounts for 41% of the energy of this group of photons that is not converted
to electric energy. This is equivalent to 30% of the total incident solar energy.
3) The above two factors account for the largest loss in efficiency and are independent of the quality of the
material. Other factors that affect the efficiency depend on the quality of the material. These include:
a) Not all of the EHP generated in the depletion region are separated and collected. For crystalline silicon,
about 95% of EHP are collected. For polycrystalline silicon, only about 70% are collected. This leads
to a loss of another 3% or 13% (respectively) of total incident energy.
119
b) The recombination of generated EHP depends on the band-gap energy. This affects the open circuit
voltage, VOC (but not the short circuit current, ISC) and hence the maximum power output. VOC peaks
at a band-gap energy of 1.2 – 1.4eV. Materials with band-gap energy outside this range have lower
maximum power for the same number of EHP generated. For high quality silicon, the bandgap energy
reduces the maximum power to 60% while for low quality silicon, it is reduced to 50% of generated
EHP. This accounts for a loss of 17% and 15% of total incident power respectively.
c) Finally, the fill factor reduces the output power to 85% of maximum power for high quality silicon
and 70% of maximum power for low quality silicon.
The theoretical efficiency for pure crystalline silicon solar cells is about 21% while that of polycrystalline
silicon is about 12%.
Despite the low conversion efficiency, the most common material used for solar cells is polycrystalline silicon.
This material is selected because of availability of silicon and availability of fabrication processes for the
material which make it much cheaper than alternatives.
More efficient solar cells can be achieved by:
1) Use of solar concentrators to focus sunlight from a larger area onto a small solar cell (the solar cell is more
expensive than a glass lens).
2) Use of materials with direct band-gap e.g Gallium Arsenide (GaAS), Cadmium Sulphide (CdS), Cadmium
Telluride (CdTe).
3) Use of materials with band-gap between 1.2 and 1.4eV e.g. Gallium Arsenide (GaAS, Eg = 1.42eV) and
Cadmium Telluride (CdTe, Eg = 1.45eV).
4) Use of tandem solar cells with two types of materials a large bad-gap material at the top to absorb short
wavelengths and a small bandgap material below it to absorb longer wavelengths. Example – AlGaAs on
GaAs.
Crystalline GaAS solar cells have achieved efficiencies of 38% while Polycrystalline CdS solar cells have
achieved efficiencies of 20%. Tandem solar cells have achieved efficiencies above 30%. Efficiencies in
commercial solar cells are lower than the laboratory achieved maximum quoted here.
6.5.6. Solar PV Power Installations

For large scale power supply, many solar cells are connected together to form solar panels. Solar power is
only available during the day, when energy demand is usually not very high. Solar panels are therefore usually
connected to charge a battery. In a solar panel, solar cells are connected in series to achieve a desired voltage
(e.g. 14 – 20V for charging 12V Lead – Acid Battery). The series units are further connected in parallel to
achieve desired current.
120
Figure 6.26: Series and Parallel Connection of Solar Cells
The size of solar panel to be used depending on the energy to be supplied. It also depends on the solar energy
available in the area where installation is done. The combination of solar panel size and amount of storage
capacity in the batteries is selected to collect and store sufficient energy on a day with average solar irradiance
to supply the demand for a whole night and leave spare capacity in case the next few days are completely
overcast.
6.6. Summary: Optical Electronic Devices
A photo-cell is fundamentally a photo-diode used in photo-voltaic mode. The diode symbol is however not
used for the photo cell.
121
Appendix A. Electron and Hole Mobility for Silicon
Hole and Electron Mobility in Extrinsic Silicon at 300K
1600 μn
1500
1400 μp
1300
1200
1100
Mobility, cm2 / Vs
1000
900
800
700
600
500
400
300
200
100
0
14 15 16 17 18 19 20
Log (NA+ND); Total Dopant Concentration cm-3
Page 122 of 135

Appendix B. Reference Formulae
Planck-Einstein Relation / .
=ℎ = ; = μm ( )=
Photogeneration concentration, LLI ( )
Carrier Concentrations / Built-in ( ) ( )

Potential = ; = Φ = ln
Conductivity/ Einstein Relationship = + = ; =
Depletion width / One Sided 2 (Φ − ) 1 1 2 (Φ − )

Junction = + =
2 (Φ − ) 2 (Φ − )
Depletion width on P Side / N Side = =
( + ) ( + )
Diffussion Lengths: p in N / n in P = =
CE Current Gain, NPN (short /
= =
long base)
Sat. Current, JFET / MOSFET = 1+ = × ( − )

2
2
MOSFET Threshold Voltage = +2 ln + ln
LED Bandwidth ∆ =3
ℎ
Intrinsic
Symbol Description Value Property Intrinsic Si
GaAs
Relative
Electronic charge
q 1.602 x 10-19 C Permittivity 11.9 13.1
Permittivity of 8.859 x 10-14
εo vacuum F/cm Band Gap (eV) 1.12, Indirect 1.424, Direct
h Planck’s constant 6.626 x 10-34 J-s μp (cm2/V.s) 470 400
Boltzmann’s
k Constant 1.381 x 10-23 J/K μn (cm2/V.s) 1450 8500
Speed of light
c (vacuum) 2.998 x 108 m/s ni (cm-3) 1.0x1010 1.79x106
Thermal Voltage (T
=300K) 0.0259V χ (eV) 4.05 4.07
Radiation Ultra Violet Violet Blue Green Yellow Orange Red Infra-Red
λ(nm) 10 - 390 390–455 455–492 492–577 577–597 597–622 622–780 780 - 106
Page 123 of 135

Appendix C. Revision Questions
C.1. Metal Semiconductor Junctions
1. For PN junctions and metal semiconductor junctions:
a. State four possible transport mechanisms and give an example of where each can be
observed.
b. Discuss the similarities and differences between PN diode and Schottky Barrier Diode
2. Complete the following sentences by selecting the correct word from those in brackets:
a. A Schottky barrier blocks the flow of ____________(majority / minority) carriers from
____________ (metal / semiconductor) to ____________ (metal / semiconductor).
b. For junction between N-type semiconductor and metal, a Schottky barrier exists when
the energy of the ____________(majority / minority) carriers is ________ (higher /
lower) at the Fermi level in Metal than at the energy level ________ (EC / EV) in the
semiconductor.
c. For junction between P-type semiconductor and metal, a Schottky barrier exists when
the energy of the ____________(majority / minority) carriers is ________ (higher /
lower) at the Fermi level in metal than at the energy level ________ (EC / EV) in the
semiconductor.
d. An ohmic contact can be made when a Schottky barrier exists between a metal and a
semiconductor by ______ (heavily / lightly) doping the semiconductor so that the
transport mechanism becomes _________ (drift / diffusion / tunnelling).
3. With the help of I-V characteristics, differentiate between ohmic contacts and rectifying
contacts.
4. A junction is made between a metal with work function 4.8eV and N-type GaAs with doping
concentration of 1016 cm–3.
a. Evaluate the work function of the semiconductor.
b. Sketch the energy band diagram for a metal–semiconductor contact (including the
vacuum level) under no bias. Label clearly Φm, ΦBn and χSi on your sketch.
5. A junction is made between a metal with work function 4.55eV and N-type silicon with
doping concentration of 2x1016 cm–3. Evaluate:
a. The work function of the silicon
b. The theoretical barrier height.
c. The built-in potential
d. The depletion layer width.
6. A junction is made between a copper with work function 4.65eV and N-type silicon with
doping concentration of 3x1016 cm–3. Evaluate:
a. The work function of the silicon
b. The theoretical barrier height.
c. The built-in potential
d. The depletion layer width.
Page 124 of 135

7. A piece of silicon is doped with Nd = 1016cm-3. Metal contacts are to be made at the two ends
of the semiconductor with two of the metals in Table 6. The contacts are labelled A and B.
a. Which metal will form an ohmic contact with the silicon?
b. Which metal will form a rectifying contact with the silicon?
c. What is the circuit symbol for a rectifying contact?
d. What is the circuit symbol for an ohmic contact?
e. Sketch the circuit between contacts A and B and hence the I-V characteristics if:
i. Both A and B are ohmic contacts
ii. Both A and B are rectifying contacts
iii. A is an ohmic contact while B is a rectifying contact.
Table 6
Metal Cs Li Al Au
Work Function, eV 1.8 2.5 4.25 5.0
8. A tunnelling ohmic contact is formed between a metal and silicon when the width of the
depletion region is less than 2.5nm. Evaluate the minimum doping in N-silicon required to
achieve a tunnelling ohmic contact.
9. For a contact between metal and silicon with relatively heavy doping, transfer of charge will
be by both thermionic emission and tunnelling. The onset of tunnelling occurs when width
of the depletion region is less than 5nm. Evaluate the maximum doping in N-silicon
required to prevent tunnelling in a Schottky diode.
10. A silicon integrated circuit is to have both Schottky diodes and non-rectifying ohmic
contacts. The metal to be used for interconnection is tungsten with φm = 4.5eV. Determine
the range of doping allowed in order to achieve:
a. Schottky diode on N-silicon.
b. Ohmic contact on N-Silicon.
c. Schottky diode on P-silicon.
d. Ohmic contact on P-Silicon.
11. A Schottky diode is made between silicon with Nd = 1016cm-3 and gold with φm = 5.1eV.
The cross-sectional area of the junction is 1mm2.
a. Schottky diodes use only one type of carrier. What is the carrier in this case?
b. Determine the expected barrier height.
c. Determine the reverse saturation current of the diode.
d. Determine the diode current when the diode has a forward bias of 0.3V.
C.2. Bipolar Junction Transistor
12. Explain the following terms / statements:
a. Bipolar
b. Low level injection / High level injection.
c. Short base / long base.
d. Transistor action
e. Cut-off, active and saturation regions
Page 125 of 135

f. Early effect, breakdown voltage
g. Operating point
h. Small signal.
13. A silicon NPN transistor has the following parameters at 300K: Emitter width = 2μm; Base
width = 1.5μm; Collector width 4μm; NaB = 1017cm-3; NdE = 1019cm-3; NdC = 5 x 1015cm-3
and minority carrier lifetimes in emitter, base and collector of 10-8, 10-7and 10-6 s
respectively. The transistor is biased with VBE = 0.8V and VCE = 1.5V. Dopant
compensation has not been used in any of the regions. Evaluate the transistor β. State any
assumptions made.
14. Sketch the flow of charges in the NPN transistor. Hence define the terms emitter efficiency,
base transport factor, common base current gain, common emitter current gain.
15. A formula to estimate β for an NPN transistor is given in the formula table at the end of
this document. State:
a. The assumptions made about the effective widths of base and emitter in deriving this
formula.
b. What the formula would be if the assumptions were not true.
16. Explain the following features of a BJT, indicating the source of the feature inside the
structure:
a. Current gain, β, is low at low levels and high levels of collector current.
b. Output resistance is not infinite in saturation.
c. Current gain falls at high frequency.
17. The voltages at each transistor terminal (with respect to ground) are: VC = -0.7V, VB = 0V
and VE = 0.7V. The BJT is doped with NaB = 3 x 1016cm-3; NdE = 1019cm-3; NdC = 4 x 1015cm-
3
. Determine:
a. The transistor operating mode.
b. The minority carrier densities at each edge of the depletion regions (four answers
expected).
18. The voltages at each transistor terminal (with respect to ground) are: VC == 0V, VB = -3V
and VE = -3.7V. The BJT is doped with NaB = 3 x 1016cm-3; NdE = 1019cm-3; NdC = 4 x
1015cm-3. Determine:
expected).
19. The voltages at each transistor terminal (with respect to ground) are: VC = 0V, VB = 0.7V
and VE = 0.1V. The BJT is doped with NaB = 3 x 1016cm-3; NdE = 1019cm-3; NdC = 4 x 1015cm-
3
. Determine:
expected).
Page 126 of 135

20. Sketch the flow of charges that constitutes the currents in the NPN transistor. Hence define
the terms emitter efficiency, base transport factor, common base current gain, common
emitter current gain.
21. For an NPN BJT with β = 150 and biased at IC = 1mA, evaluate the values of gm and rπ.
22. For an NPN BJT with β = 50 - 100 and VA = 70V is biased at IC = 10mA. Evaluate the
values of gm, rπ and ro.
23. Two identical BJTs, A and B, are identical in dimensions and doping profiles. Transistor
A is NPN while transistor B is PNP. Indicate with reasons which of the device has:
a. The highest β.
b. The lowest transconductance, gm.
c. Largest ISC.
d. Highest cut off frequency.
24. The PNP transistor with characteristics in Figure 27 is biased with VCEQ = -8V and IBQ = -
300μA. Determine:
a. The transistor β
b. The Early voltage, VA.
c. The hybrid π equivalent circuit parameters (gm, rπ, ro).
Figure 27
25. For the circuit in Figure 28(a), VCC = 10V, VA = ∞, RC = 3kΩ, RB = 100kΩ, VBB = 3V and
the transistor has β = 100.
a. Determine the quiescent operating point.
b. Determine the hybrid π equivalent circuit parameters (gm, rπ, ro).
c. Sketch the hybrid π equivalent circuit for the complete circuit.
26. For the transistor circuit in Figure 28(a),
a. Determine the voltage gain.
b. Sketch the high frequency hybrid π equivalent circuit for the BJT.
Page 127 of 135

(a) (b)
Figure 28
27. Figure 28(b) shows the cross section of a BJT fabricated in silicon.
a. Label the terminals E, B, and C.
b. Explain the meaning and purpose of the region labelled n++ around the terminal on the
right.
c. Why is the P region having only a + superscript and not ++ like the N regions?
d. What's is the purpose of SiO2 at the top and on the sides of the structure?
C.3. Field Effect Transistors
28. Explain the following terms for MOS capacitor / MOSFET:
a. Accumulation
b. Depletion
c. Inversion
d. Enhancement vs Depletion
e. N-channel vs P-Channel
f. Ohmic region, saturation region, cut-off.
g. Channel modulation.
29. Figure 29(a) shows the cross section of a semiconductor device.
a. Identify the device in the figure.
b. Label the terminals of the device
c. Explain the meaning and purpose of the region labelled N+ around the terminal on the
right.
(a) (b)
Figure 29
30. Figure 29(b)shows a device fabricated in silicon.
a. Identify the device, giving reasons for your choice.
b. Label the terminals of the device.
c. Explain, with the help of sketches, how the device works
d. Sketch the output characteristics for the device, labelling the axes and identifying 3
operating regions.
Page 128 of 135

31. For the MOSFET, MESFET and JFET (all N-channel), arrange the devices in order of
increasing value of the following parameters, giving reasons for your ordering:
a. Gate current.
b. Cut off frequency.
32. State some advantages of FET over BJT. State some advantages of BJT over FET.
33. Name the three bias regimes of an MOS capacitor and explain what happens in the
semiconductor in each of these bias modes.
34. Determine the channel modulation voltage VM' for an N-channel MOSFET with the
following parameters: substrate impurity doping concentration Na = 2x1016cm-3, threshold
voltage Vth = 0.5 V, channel length L = 10μm, VGS = 1.5 V, and VDS = 5 V.
35. Distinguish between:
a. N-channel and P-channel MOSFET.
b. Enhancement and Depletion MOSFET.
c. Accumulation, depletion, inversion and pinch off in MOSFET channel.
d. Threshold voltage and pinch off voltage.
e. Channel length and channel modulation length.
36. An N-channel MOSFET has a channel width, W = 40μm, channel length, L = 2μm, oxide
thickness, tox = 10nm and relative permittivity of oxide, εr = 3.9. The mobility of electrons
in the inversion layer, μn = 500 cm2/(volt-sec). Determine the MOS constant, K.
37. The pinch-down voltage of a P-channel depletion MOSFET, Vp = 5V. The saturation
current, IDSS = -40mA. The MOSFET is operating in the saturation region with iD = -15mA.
Evaluate the gate to source voltage, vGS.
38. A MOS capacitor is fabricated on P-type Si substrate with a doping of 5 × 1016cm–3 and
with oxide thickness of 10nm and N+ poly-gate. The gate can be assumed to have work
function = electron affinity. Evaluate:
a. Cox
b. Vfb
c. Vth
39. For a MOS capacitor biased at threshold:
a. Sketch the potential profile across the device from gate contact to body contact.
b. Hence show that the threshold voltage, Vth is given by:
2
= +2 ln + ln
C.4. Opto-Electronic Devises

40. Explain with the help of diagrams radiative and non-radiative recombination. Indicate why
some materials do not experience radiative recombination.
41. Explain with the help of diagrams, the following terms:
a. Direct band-gap and indirect band-gap semiconductors.
b. Shallow and deep impurities.
Page 129 of 135

c. Electron capture / hole capture by deep traps.
d. Direct (or band to band) recombination, indirect (or trap assisted) recombination and
auger recombination. (State which is most likely to be radiative).
e. Radiative and non-radiative recombination.
f. Stimulated and spontaneous emission.
g. Population inversion.
h. Dark current vs light current
i. Photovoltaic mode vs photoconductive mode.
42. With reference to photo diodes:
a. With the sketch of an energy band diagram, describe the generation of a photocurrent in
a PN diode.
b. Indicate the photo-generated carriers and their direction of motion.
c. Explain why the photocurrent negative is compared to the forward bias current through
the same diode.
43. With reference to solar cells:
a. Explain the difference between a solar cell and a photodiode.
b. Explain why solar cells be more efficient if the sun where a laser rather than a black
body.
c. What limits the power conversion efficiency of a solar cell?
d. Sketch the characteristics of a solar cell and indicate the point where maximum power is
delivered.
44. Explain why silicon is not used to fabricate LEDs.
45. Explain why planar LEDs are generally inefficient and how the efficiency of an LED can
be improved beyond that of a planar LED.
46. State the range of band gaps for materials that can fabricate LEDs of colour: red, green,
blue, UV, IR.
47. Suppose the energy of electrons in a semiconductor has a spread of approximately 3/2kT
above EC. The energy of holes have a similar spread below EV.
a. What is the maximum possible spread of energies, dE for photons emitted as a result of
band to band recombination?
2
b. Hence show that the wavelength of light emitted by an LED has a spread of ∆ = 3 ℎ
48. Identify optoelectronic devices with applications in the following areas and briefly describe
the specific application and suitable device characteristics.
a. Domestic and commercial premises.
b. Telecommunications.
c. Instrumentation.
49. Consider a Schottky diode constructed from Copper (φm = 4.5eV) and silicon with φs =
4.25eV:
a. Is the conductivity of the silicon N-type or P-type?
b. Draw the energy band diagram for the junction under zero bias.
Page 130 of 135

c. Light with photon energy higher than silicon band-gap is used to illuminate the junction
area and generate electron-hole pairs:
i. If the diode is connected to an external circuit, in which direction would the resultant
photo-current flow?
ii. What is the maximum open circuit voltage for the device under illumination? (HINT:
At the maximum open circuit voltage, there is no movement of charge carriers,
therefore the built-in potential at the junction is balanced by the potential caused by
the photo-generated carriers).
50. Repeat the previous question for silicon with φs = 4.9eV.
51. A sample of silicon uniformly doped with 2 X 1016 cm-3 donors is illuminated by
penetrating light that generates 1020 hole-electron pairs per second per cm3 uniformly
throughout its bulk. The conductivity of the sample is found to increase by 1 percent (i.e.
from σo to 1.01σo) when it is illuminated for a long time. Assume You may use μn = 1450
cm2/V.s, μp = 470 cm2/V.s and ni = 1.0 X 1010cm-3.
a. Evaluate no, po and σo.
b. Evaluate n’, p’ and σ’.
c. Do low level injection conditions apply? Explain.
d. What is the minority carrier lifetime, τ?
e. If the illumination is removed after a long time, what happens to the conductivity of the
silicon sample?
52. A bar of silicon is doped with boron at 1015cm-3. It is illuminated by penetrating light that
generates 1020 hole-electron pairs per second per cm3 uniformly throughout its bulk. If τ =
10μs, determine no, po, n’, and p’.
53. For a typical silicon solar cell:
a. Sketch the cross-section of the device, and state the purpose of each component.
b. Sketch the I-V characteristics of indicating:
i. Open circuit voltage
ii. Short circuit current
iii. Maximum power transfer point.
(a) (b) (c)

Figure 30
54. Figure 30 shows the cross-section of three devices fabricated in silicon. The three devices
are photo-diode, P-I-N photodiode and solar cell.
a. Identify the three devices, giving reasons for your choice.
b. For each device, identify the features labelled with letters A – G and state the purpose of
each feature.
Page 131 of 135

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JOMO KENYATTA UNIVERSITY

SCHOOL OF ELECTRICAL, ELECTRONICS AND INFORMATION ENGINEERING

DEPARTMENT OF ELECTRICAL AND ELECTRONIC ENGINEERING

Figure 2.1: Parallel Plate Capacitor

Aside – Silicon Crystal Structures

Aside – Aluminium and Copper Crystal Structures

2.2. Review of Contacts and Contact Potential

The charge concentration for N-type extrinsic semiconductor:

The work function can be evaluated as:

And the work function:

2.2.2. Charge Movement at Junctions and Band Bending

2.3. Electrical Behaviour of Metal - Semiconductor Junctions

2.3.1. N Type Semiconductor – Metal Junction

2.3.1.2. Case 2: Φm < Φs

2.3.2. P-Type Semiconductor – Metal Junction

Figure 2.6: Work Function of Different Metals (Sze)

2.4. Schottky Diode Operation

Figure 2.7: Schottky Barrier Diode: Symbol and Construction Schematic

Table 2.3: Work Function of Silicon for Different Doping Concentrations

1.00E+15 0.30 4.31 1.00E+15 0.30 4.91

5.00E+15 0.34 4.27 5.00E+15 0.34 4.95

1.00E+16 0.36 4.25 1.00E+16 0.36 4.97

5.00E+16 0.40 4.21 5.00E+16 0.40 5.01

1.00E+17 0.42 4.19 1.00E+17 0.42 5.03

5.00E+17 0.46 4.15 5.00E+17 0.46 5.07

1.00E+18 0.48 4.13 1.00E+18 0.48 5.09

5.00E+18 0.52 4.09 5.00E+18 0.52 5.13

NPN BJT PNP BJT JUNCTION INSULATED GATE

JFET MESFET N-CHANNEL P-CHANNEL

Figure 3.2: Transistor Classification

3.2. Construction and Nomenclature

Lower Case Lower Case vce , ic AC values (small signal)

Lower Case Upper Case vCE , iC Combined AC & DC signals

Upper Case Upper Case VBE , IE DC signal values

Upper Case Upper Case VBEQ , ICQ DC Quiescent Values

Upper Case V Upper Case (Double) VBB , VCC DC Biasing Sources

Upper Case V Single Letter VB , VC, VE Terminal to Ground Voltage

3.3.1. Transistor Action

Figure 3.8: Supply Voltage Connections in Forward Active Region

Figure 3.9: Energy Band Structure in Forward Active Region

Figure 3.11: Transistor Current Components

3.5. BJT Minority Charge Distribution for Different Operating Regions

3.5.2. Active Region

Assume none of the regions has dopant compensation.

3.6. BJT Characteristics

3.6.2. BJT Characteristics

Figure 3.15: Circuit for Measuring CE Output Characteristics

Figure 3.18: The Early Effect

VA can be increased by selecting design parameters of the transistor that:

3.6.4. Biasing Voltages and Operating Region

Parameter Value (Volts)

Figure 3.21: BJT Changeover from Active Region to Saturation

3.6.5. Transistor Applications

3.7. DC Analysis of BJT Circuits

Figure 3.22: DC Analysis of BJT

3.8. The BJT as a Switch

CUT OFF SATURATION

Distance from BE Junction Distance from BE Junction

3.8.4. Parallel Operation

Figure 3.25: Parallel Operation of BJT – Guaranteed to Fail

(a) (b) (c)

3.10. AC Small Signal Models of Transistor Amplifier