2021 6 14

18:48:48
 ——
●

● ISA
●

Instruction-Set
Architecture ISA
ISA

●
2
 ●
——
●
●

● 3
——

4
 ——
●

●
5
 ●
——
●

● BCD
●

● 6
 ——
●

● r dmin
r+1
● r dmin
2r+1

7
● m

● x=xm-1xm-2…x0 y=ym-1ym-2…y0
d

8
9
 n k
●
1 2
2k≥n+k+1
2-4 3
5-11 4

n 12-26 5
27-57 6
k 58-120 7

k +3
1

10
● 2.5
1) 2+x=1.x6x5x4x3x2x1x0=1+0. x6x5x4x3x2x1x0
x=0. x6x5x4x3x2x1x0-1<-1/2
0. x6x5x4x3x2x1x0<1/2
x6=0 x5~x0
2) -1/2≤x=0. x6x5x4x3x2x1x0-1<-1/4
1/2<=0. x6x5x4x3x2x1x0<3/4
x6=1, x5=0 x4~x0

11
 ——
●
●
●
● ,
●
●
●

●
● ALU 2 1 2
3
● ALU 2 1 1
2
● ALU 2 1 0
1

12
 ——
● 3.17
1 [X] =00.01001 [Y] =11.01001
[X] +[Y] =11.10010
3 [X] =11.10011 [Y] =00.00101
[X] +[Y] =11.11000

13
 ——
●

● Cache
● Cache
● Cache- TA
h Cache TC TM
● Cache
● OPT FIFO LRU LFU
● Cache
●
14
 ——
●

● Cache
●

● Cache Cache

● 8
8
●

● LRU
●
15
 ——
●

● RZ NRZ NRZ1 FM PM MFM

● R
● R= /
●

● η= /
16
R η NRZ NRZ1 PM FM MFM

R 0 0 0.5 0.5 0.5

η 100% 100% 50% 50% 100%
● NRZ NRZ1 0 1
R=0 1
1 100%
●PM FM MFM 1 1
2 R=0.5

●PM FM 1
50% 17
CPU ——

a
6264 SRAM “ + ”
/
18
2
Cache Cache

19
2
●

● Cache
● 4 4 1
●

● 4 1
● 2 2
● Cache 4 Cache 4
● index
Cache
●
20
2
● CPU
011 10 011000 B

Cache 2
24

3
1 G “0” 2
E G “1”
A≠B E
A B E

21
4
Cache Cache

22
4

● CPU
0111 0 011000 B

Cache4 0
24

1 G “0” 2
E G “1”
A≠B E 3
A B E
23
8

24
● 4.25
● 1 9 1 10
● 1MB 20 10 1KB 1024 4 2
1024/2=512 Tag 9 2 1

25
● 4.25
● 2 ABCDEH
● (1010 1011 1)(1)(00 1101 1110)

● 157H 3 1
0 1
●

● (1)(00 1101 1110) 4DE H

● 2 12345H
● (0001 0010 0)(0)(11 0100 0101)

● 024H 0

26
 ● 4.26
● 1 1MB 20
1KB 10
10
10
4

10 +1 +1
+…

2 30 h +(1- h)(300+30)=32.7 h =99.1%

30 h +(1- h)300=32.7 h =99%
27
● 4.26
● 3 88888H
● 1000100010 0010001000
● 222H 1 Cache
01 0010001000 488H
● 56789H
● 0101011001 1110001001
● 159H 2 Cache
10 1110001001 B89H
● 4 Cache
●
28
 0 0
1 1 0001 287
0 1 23B

1 1 226 0 1 2A46

2 0 1 1 23B9

2 1 20D6
0 1 001A 86D
3 1 287
3 0 1 0
4 0
4 1 20D8
5 1 20D
5 1 20D6
6 1 235
6 0 0 0
7 1 2A4
7 1 23BA 1 1 001A 87E

● 4.38 0 1 0003 235

1 0
● 1 28 16 12
24 12 12 29
● 4.38
● 2 Tag 16 Index 3 5
● 3 00056A8H 0005H 20DH
20D6A8H
● (0010 0000 1101 0110) (101)(0 1000) Tag
20D6H Index 5 Cache 5 20D6H Tag
Cache Cache A8H
● 4 00356A8H 12 Index 1
Tag 15
● (Tag)(Index)( ) (0000 0000 0011 010)(1) (0110
1010 1000)
● Tag 001AH Index 1
● 4 TLB 1 “001AH”
87EH 87E6A8H

30
 ——
●

● ·
●

● CISC RISC

31
 ——
● Big-Endian Ordering

● Little-Endian Ordering

32 12345678H
1000H
5.1

1000 12 78
1001 34 56
1002 56 34
32
 —— .

●
. 指令 和 数据 混存在
鬰
●

● , 33
 —— .

● ,

三
, ,

● ,
,

● n 2 2n
●

●
34
CISC RISC

● CISC Complex Instruction Set Computer

● RISC Reduced Instruction Set Computer

35
CISC RISC

● CISC

正莲
●

● CPU
●

36
 CISC RISC
CISC
● CISC
● CISC
● CISC RISC
● CISC
● CISC
● RISC
●

RISC I VAX-11/780 M68000 Z80 PDP-11/70

C 1 1.0 0.8 0.9 1.2 0.9

C 2 1.0 0.6 - - 0.71

C 3 1.0 - 0.9 1.12 -

RISC I C 37
CISC RISC
RISC
●

些
● Machine Cycle
ALU

●
●

● LOAD STORE
●

●
38
CISC RISC
RISC
●

壹
●
● LOAD/STORE
●

● RISC
RISC CPI=1
●

● CPU
●

● 39
 ——
● 5.4 32

1 5 2 5 3 16

(?)

(?)
(?)

(?)

40
 ——
●
●

● 6 n3<=26-1
●

● 11 n2<=(26-n3)x 25-1
●
● 16
● n1<=((26-n3)x 25-n2)x25-1
●
● 32
● n0<=(((26-n3)x 25-n2)x25-n1) x 216
41
● 5.10

● 3 3 9 12 3
4 3 000~011
● 9 1 255
100000000~111111110
● 12 9 111111111 3 8
16
● 254 100000000~111111101
● 9 111111110 111111111 8 16
111111110000~111111111111

42
● 5.20

43
 ——
●

44
 ——
● CPU
●

●
-
●

✓
● CPU

飈 徽不改硬件
● CPU MIPS Flops CPI CPU
● MIPS
45
 CPU
● CPU
● _

● 1
_
● CPU 2

●
●
●
●

3
● RISC
4
●
46
●
47
 ——
●

E
●

● MOV JZ ADD STORE

48
1.
(3)
/
1(4 ) 2(4 ) 3(4 ) 4(3 ) 5
NOP 0000 NOP 0000 NOP 0000 NOP 000
R0in 0001 R0out 0001 ADD 0001 Mread 001
R1in 0010 R1out 0010 SUB 0010 Mwrite 010
…… …… AND 0011 IOread 011
R7in 1000 R7out 1000 OR 0100 IOwrite 100
IR in 1001 IRout 1001 SHL 0101
Yin 1010 Zout 1010 SHR 0110
ARin 1011 ARout 1011 ROL 0111
DRIin 1100 DRIout ROR 1000
DRSin 1100 PC+1 1001
1101 DRSout 1101 SP+1 1010
6.4
PCin PCout 1110 SP-1 1011
1110 SPout 1111 49
●

T1 AR←PC PCout ARin

ARout Mread
T2 DR←Memory[AR]
DRSin
●
T3 MOVPC←PC+I
R0, X IR←DR PC+1 DRIout IRin
MOV (R1), R0
ADD R1, R0
SUB R0, (X)
IN R0, P
JZ offs
POP R0
CALL (X) 50
●
1 MOV R0, X

AR←IR( )
T1 IRout ARin

ARout Mread
T2 DR←Memory[AR]
DRSin
T3 R0←DR DRIout R0in

51
●
2 MOV (R1), R0

T1 AR←R1 R1out ARin

T2 DR←R0 R0out DRIin
ARout DRSout
T3 Memory[AR]←DR
Mwrite

52
●
3 ADD R1, R0

T1 Y←R0 R0out Yin

T2 Z←R1+Y R1out ADD
T3 R1←Z Zout R1in

53
●
4 SUB R0, (X)

T1 AR←IR( ) IRout ARin

T2 DR←Memory[AR] ARout Mread DRSin
T3 AR←DR DRIout ARin
T4 DR←Memory[AR] ARout Mread DRSin
T5 Y←R0 R0out Yin
T6 Z←Y DR DRIout SUB
T7 R0←Z Zout R0in
54
●
5 IN R0, P

T1 AR←IR( ) IRout ARin

T2 DR←IO[AR] ARout IOread DRSin
T3 R0←DR DRIout R0in

55
●
6 JZ offs

ZF=1
IRout Yin
T1 Y←IR( )
PCout ADD
T2 Z←PC+Y
T3 Zout PCin
PC←Z

56
●
7 POP R0

T1 AR←SP SPout ARin

T2 DR←Memory[AR] ARout Mread DRSin
T3 R0←DR SP←SP+n DRIout R0in SP+1

57
●
8 CALL (X)

T1 SP←SP n DR←PC SP-1 PCout DRIin

T2 AR←SP SPout ARin
T3 Memory [AR]←DR ARout DRSout Mwrite
T4 AR←IR( ) IRout ARin
T5 DR←Memory[AR] ARout Mread DRSin
T6 PC←DR DRIout PCin

58
 ——

-
●

● VLIW

● IPC 1
● VLIW

59
 ——
● 7.13
● 10
9

R A
F

60
 ——
● 7.13
● I1 R1←A1+A2
● I2 R2←A3+A4
● I3 R3←A5+A6
● I4 R4←A7+A8
● I5 R5←A9+A10
● I6 R6←R1+R2
● I7 R7←R3+R4
● I8 R8←R5+R6
● I9 F←R7+R8
● t 61
 ——
● 1
S5 1 2 3 4 5 6 7 8 9

S4 1 2 3 4 5 6 7 8 9

S3 1 2 3 4 5 6 7 8 9

S2 1 2 3 4 5 6 7 8 9

S1 1 2 3 4 5 6 7 8 9

● 2 21 t

62
 ——
●

● BG

63
 ——
● I/O
●

● RISC-V I

I+4 RISC-V 32 4

● CPU DMA CPU

DMAC
● DMA CPU
64
This is OK

65