ESSENTIALS OF ELECTRONIC TESTING

FOR DIGITAL, MEMORY AND

MIXED-SIGNAL VLSI CIRCUITS
 FRONTIERS IN ELECTRONIC TESTING

Consulting Editor
Vishwani D. Agrawal

Books in the series:

Analog and Mixed-Signal Boundary-Scan: A Guide to the IEEE 1149.4

Test Standard
A. Osseiran
ISBN: 0-7923-8686-8
Design for At-Speed Test, Diagnosis and Measurement
B. Nadeau-Dosti
ISBN: 0-79-8669-8
Delay Fault Testing for VLSI Circuits
A. K-T. Cheng
ISBN: 0-7923-8295-1
Research Perspectives and Case Studies in System Test and Diagnosis
J.W. Sheppard, W.R. Simpson
ISBN: 0-7923-8263-3
Formal Equivalence Checking and Design Debugging
S.-Y. Huang, K.-T. Cheng
ISBN: 0-7923-8184-X
On-Line Testing for VLSI
M. Nicolaidis, Y. Zorian
ISBN: 0-7923-8132-7
Defect Oriented Testing for CMOS Analog and Digital Circuits
M. Sachdev
ISBN: 0-7923-8083-5
Reasoning in Boolean Networks: Logic Synthesis and Verification
Using Testing Techniques
W. Kunz, D. Stoffel
ISBN: 0-7923-9921-8
Introduction to IDDQTesting
S. Chakravarty, P.J. Thadikaran
ISBN: 0-7923-9945-5
Multi-Chip Module Test Strategies
Y. Zorian
ISBN: 0-7923-9920-X
Testing and Testable Design of High-Density Random-Access Memories
P. Mazumder, K. Chakraborty
ISBN: 0-7923-9782-7
From Contamination to Defects, Faults and Yield Loss
J.B. Khare, W. Maly
ISBN: 0-7923-9714-2
ESSENTIALS OF ELECTRONIC TESTING
FOR DIGITAL, MEMORY AND
MIXED-SIGNAL VLSI CIRCUITS

Michael L. Bushnell
Rutgers University

Vishwani D. Agrawal
Bell Labs, Lucent Technologies.

KLUWER ACADEMIC PUBLISHERS

NEW YORK, BOSTON, DORDRECHT, LONDON, MOSCOW
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To Margaret Kalvar for her patient understanding, love, and support, which makes
my work possible — MLB.
To the women in my life, Premlata, Prathima, Victoria and Chitra,
and to my son, Vikas — VDA.
TABLE OF CONTENTS

PREFACE xv

ABOUT THE AUTHORS xvii

I INTRODUCTION TO TESTING 1

1 INTRODUCTION 3
1.1 Testing Philosophy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 4
1.2 Role of Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6
1.3 Digital and Analog VLSI Testing . . . . . . . . . . . . . . . . . . . . 7
1.4 VLSI Technology Trends Affecting Testing . . . . . . . . . . . . . . . 9
1.5 Scope of this Book . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15

2 VLSI TESTING PROCESS AND TEST EQUIPMENT 17

2.1 How to Test Chips? . . . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.1.1 Types of Testing . . . . . . . . . . . . . . . . . . . . . . . . . 18
2.2 Automatic Test Equipment . . . . . . . . . . . . . . . . . . . . . . . 24
2.2.1 Advantest Model T6682 ATE . . . . . . . . . . . . . . . . . . 24
2.2.2 LTX Fusion ATE . . . . . . . . . . . . . . . . . . . . . . . . . . .. 28
2.2.3 Multi-Site Testing . . . . . . . . . . . . . . . . . . . . . . . . 29
2.3 Electrical Parametric Testing . . . . . . . . . . . . . . . . . . . . . . 30
2.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 34

3 TEST ECONOMICS AND PRODUCT QUALITY 35

3.1 Test Economics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1.1 Defining Costs . . . . . . . . . . . . . . . . . . . . . . . . . . 36
3.1.2 Production . . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
3.1.3 Benefit-Cost Analysis . . . . . . . . . . . . . . . . . . . . . . 41
3.1.4 Economics of Testable Design . . . . . . . . . . . . . . . . . . 42
3.1.5 The Rule of Ten . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.2 Yield . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.3 Defect Level as a Quality Measure . . . . . . . . . . . . . . . . . . . 47
3.3.1 Test Data Analysis . . . . . . . . . . . . . . . . . . . . . . . . 48
3.3.2 Defect Level Estimation . . . . . . . . . . . . . . . . . . . . . 50
viii TABLE OF CONTENTS

3.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53

4 FAULT MODELING 57
4.1 Defects, Errors, and Faults . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 Functional Versus Structural Testing . . . . . . . . . . . . . . . . . . 59
4.3 Levels of Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.4 A Glossary of Fault Models . . . . . . . . . . . . . . . . . . . . . . . 60
4.5 Single Stuck-at Fault . . . . . . . . . . . . . . . . . . . . . . . . . . . 70
4.5.1 Fault Equivalence . . . . . . . . . . . . . . . . . . . . . . . . 72
4.5.2 Equivalence of Single Stuck-at Faults . . . . . . . . . . . . . . 73
4.5.3 Fault Collapsing . . . . . . . . . . . . . . . . . . . . . . . . . 74
4.5.4 Fault Dominance and Checkpoint Theorem . . . . . . . . . . 75
4.5.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 78

II TEST METHODS 81

5 LOGIC AND FAULT SIMULATION 83

5.1 Simulation for Design Verification . . . . . . . . . . . . . . . . . . . . 83
5.2 Simulation for Test Evaluation . . . . . . . . . . . . . . . . . . . . . 88
5.3 Modeling Circuits for Simulation . . . . . . . . . . . . . . . . . . . . 91
5.3.1 Modeling Levels and Types of Simulators . . . . . . . . . . . 91
5.3.2 Hierarchical Connectivity Description . . . . . . . . . . . . . 93
5.3.3 Gate-level Modeling of MOS Networks . . . . . . . . . . . . . 94
5.3.4 Modeling Signal States . . . . . . . . . . . . . . . . . . . . . . 96
5.3.5 Timing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 98
5.4 Algorithms for True-Value Simulation . . . . . . . . . . . . . . . . . 101
5.4.1 Compiled-Code Simulation . . . . . . . . . . . . . . . . . . . 102
5.4.2 Event-Driven Simulation . . . . . . . . . . . . . . . . . . . . . 103
5.5 Algorithms for Fault Simulation . . . . . . . . . . . . . . . . . . . . . 105
5.5.1 Serial Fault Simulation . . . . . . . . . . . . . . . . . . . . . . . . . . . 106
5.5.2 Parallel Fault Simulation . . . . . . . . . . . . . . . . . . . . 107
5.5.3 Deductive Fault Simulation . . . . . . . . . . . . . . . . . . . 109
5.5.4 Concurrent Fault Simulation . . . . . . . . . . . . . . . . . . 113
5.5.5 Roth’s TEST-DETECT Algorithm . . . . . . . . . . . . . . . 116
5.5.6 Differential Fault Simulation . . . . . . . . . . . . . . . . . . 117
5.6 Statistical Methods for Fault Simulation . . . . . . . . . . . . . . . . 120
5.6.1 Fault Sampling . . . . . . . . . . . . . . . . . . . . . . . . . . 121
5.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125

6 TESTABILITY MEASURES 129

6.1 SCOAP Controllability and Observability . . . . . . . . . . . . . . . 131
6.1.1 Combinational SCOAP Measures . . . . . . . . . . . . . . . . 132
6.1.2 Combinational Circuit Example . . . . . . . . . . . . . . . . . 134
6.1.3 Sequential SCOAP Measures . . . . . . . . . . . . . . . . . . 140
TABLE OF CONTENTS ix

6.1.4 Sequential Circuit Example . . . . . . . . . . . . . . . . . . . 142

6.2 High-Level Testability Measures . . . . . . . . . . . . . . . . . . . . . 148
6.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150

7 COMBINATIONAL CIRCUIT TEST GENERATION 155

7.1 Algorithms and Representations . . . . . . . . . . . . . . . . . . . . 156
7.1.1 Structural vs. Functional Test . . . . . . . . . . . . . . . . . 156
7.1.2 Definition of Automatic Test-Pattern Generator . . . . . . . 157
7.1.3 Search Space Abstractions . . . . . . . . . . . . . . . . . . . . 158
7.1.4 Algorithm Completeness . . . . . . . . . . . . . . . . . . . . . 159
7.1.5 ATPG Algebras . . . . . . . . . . . . . . . . . . . . . . . . . 159
7.1.6 Algorithm Types . . . . . . . . . . . . . . . . . . . . . . . . . 160
7.2 Redundancy Identification (RID) . . . . . . . . . . . . . . . . . . . . 168
7.3 Testing as a Global Problem . . . . . . . . . . . . . . . . . . . . . . . 172
7.4 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 172
7.5 Significant Combinational ATPG Algorithms . . . . . . . . . . . . . 176
7.5.1 D-Calculus and D-Algorithm (Roth) . . . . . . . . . . . . . . 176
7.5.2 PODEM (Goel) . . . . . . . . . . . . . . . . . . . . . . . . . . 186
7.5.3 FAN (Fujiwara and Shimino) . . . . . . . . . . . . . . . . . . 192
7.5.4 Advanced Algorithms . . . . . . . . . . . . . . . . . . . . . . 197
7.6 Test Generation Systems . . . . . . . . . . . . . . . . . . . . . . . . . 204
7.7 Test Compaction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 205
7.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 206

8 SEQUENTIAL CIRCUIT TEST GENERATION 211

8.1 ATPG for Single-Clock Synchronous Circuits . . . . . . . . . . . . . 212
8.1.1 A Simplified Problem . . . . . . . . . . . . . . . . . . . . . . 214
8.2 Time-Frame Expansion Method . . . . . . . . . . . . . . . . . . . . . 214
8.2.1 Use of Nine-Valued Logic . . . . . . . . . . . . . . . . . . . . 216
8.2.2 Development of Time-Frame Expansion Methods . . . . . . . 218
8.2.3 Approximate Methods . . . . . . . . . . . . . . . . . . . . . . 222
8.2.4 Implementation of Time-Frame Expansion Methods . . . . . 222
8.2.5 Complexity of Sequential ATPG . . . . . . . . . . . . . . . . 225
8.2.6 Cycle-Free Circuits . . . . . . . . . . . . . . . . . . . . . . . . 225
8.2.7 Cyclic Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . 229
8.2.8 Clock Faults and Multiple-Clock Circuits . . . . . . . . . . . 231
8.2.9 Asynchronous Circuits . . . . . . . . . . . . . . . . . . . . . . 232
8.3 Simulation-Based Sequential Circuit ATPG . . . . . . . . . . . . . . 238
8.3.1 CONTEST Algorithm . . . . . . . . . . . . . . . . . . . . . . 239
8.3.2 Genetic Algorithms . . . . . . . . . . . . . . . . . . . . . . . . 246
8.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 248
x TABLE OF CONTENTS

9 MEMORY TEST 253

9.1 Memory Density and Defect Trends . . . . . . . . . . . . . . . . . . 255
9.2 Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 258
9.3 Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 259
9.3.1 Fault Manifestations . . . . . . . . . . . . . . . . . . . . . . . 259
9.3.2 Failure Mechanisms . . . . . . . . . . . . . . . . . . . . . . . 260
9.4 Memory Test Levels . . . . . . . . . . . . . . . . . . . . . . . . . . . 261
9.5 March Test Notation . . . . . . . . . . . . . . . . . . . . . . . . . . . 262
9.6 Fault Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 263
9.6.1 Diagnosis Versus Testing Needs . . . . . . . . . . . . . . . . . 265
9.6.2 Reduced Functional Faults . . . . . . . . . . . . . . . . . . . 266
9.6.3 Relation Between Fault Models and Physical Defects . . . . . 276
9.6.4 Multiple Fault Models . . . . . . . . . . . . . . . . . . . . . . 278
9.6.5 Frequency of Faults . . . . . . . . . . . . . . . . . . . . . . . 281
9.7 Memory Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 284
9.7.1 Functional RAM Testing with March Tests . . . . . . . . . . 284
9.7.2 Testing RAM Neighborhood Pattern-Sensitive Faults . . . . . 286
9.7.3 Testing RAM Technology and Layout-Related Faults . . . . . 294
9.7.4 RAM Test Hierarchy . . . . . . . . . . . . . . . . . . . . . . . 295
9.7.5 Cache RAM Chip Testing . . . . . . . . . . . . . . . . . . . . 296
9.7.6 Functional ROM Chip Testing . . . . . . . . . . . . . . . . . 300
9.7.7 Electrical Parametric Testing . . . . . . . . . . . . . . . . . . 301
9.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 306

10 DSP-BASED ANALOG AND MIXED-SIGNAL TEST 309

10.1 Analog and Mixed-Signal Circuit Trends . . . . . . . . . . . . . . . . 309
10.2 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 314
10.3 Functional DSP-Based Testing . . . . . . . . . . . . . . . . . . . . . 317
10.3.1 Concept . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 317
10.3.2 Mechanism of DSP-Based Testers . . . . . . . . . . . . . . . . 319
10.3.3 Waveform Synthesis . . . . . . . . . . . . . . . . . . . . . . . 320
10.3.4 Waveform Sampling and Digitization . . . . . . . . . . . . . . 322
10.4 Static ADC and DAC Testing Methods . . . . . . . . . . . . . . . . 322
10.4.1 Transmission vs. Intrinsic Parameters . . . . . . . . . . . . . 323
10.4.2 Uncertainty and Distortion in Ideal ADCs . . . . . . . . . . . 325
10.4.3 DAC Transfer Function Error . . . . . . . . . . . . . . . . . . 325
10.4.4 ADC Transfer Function Error . . . . . . . . . . . . . . . . . . 326
10.4.5 Flash ADC Testing Methods . . . . . . . . . . . . . . . . . . 327
10.4.6 DAC Testing Methods . . . . . . . . . . . . . . . . . . . . . . 332
10.5 Realizing Emulated Instruments Using Fourier Transforms . . . . . . 335
10.5.1 Fourier Voltmeter . . . . . . . . . . . . . . . . . . . . . . . . 345
10.5.2 Testing of Analog Devices Using Non-Coherent Sampling . . 350
10.5.3 Coherent Multi-Tone Testing . . . . . . . . . . . . . . . . . . 356
10.5.4 ATE Vector Operations . . . . . . . . . . . . . . . . . . . . . 364
TABLE OF CONTENTS xi

10.6 CODEC Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 366

10.6.1 Considerations for CODEC Performance Tests . . . . . . . . 369
10.6.2 CODEC Tests . . . . . . . . . . . . . . . . . . . . . . . . . . 372
10.7 Dynamic Flash ADC Testing FFT Technique . . . . . . . . . . . . . 376
10.8 Advanced Topics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 377
10.8.1 Event Digitization . . . . . . . . . . . . . . . . . . . . . . . . 377
10.8.2 Measuring Random Noise . . . . . . . . . . . . . . . . . . . . 380
10.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 382

11 MODEL-BASED ANALOG AND MIXED-SIGNAL TEST 385

11.1 Analog Testing Difficulties . . . . . . . . . . . . . . . . . . . . . . . . 386
11.2 Analog Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . 387
11.3 Levels of Abstraction . . . . . . . . . . . . . . . . . . . . . . . . . . . 389
11.4 Types of Analog Testing . . . . . . . . . . . . . . . . . . . . . . . . . 389
11.5 Analog Fault Simulation . . . . . . . . . . . . . . . . . . . . . . . . . 390
11.5.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . 391
11.5.2 DC Fault Simulation of Nonlinear Circuits . . . . . . . . . . . 391
11.5.3 Linear Analog Circuit AC Fault Simulation . . . . . . . . . . 395
11.5.4 Monte-Carlo Simulation . . . . . . . . . . . . . . . . . . . . . 397
11.6 Analog Automatic Test-Pattern Generation . . . . . . . . . . . . . . 397
11.6.1 ATPG Using Sensitivities . . . . . . . . . . . . . . . . . . . . 398
11.6.2 ATPG Using Signal Flow Graphs . . . . . . . . . . . . . . . . 406
11.6.3 Additional Methods . . . . . . . . . . . . . . . . . . . . . . . 413
11.7 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 413

12 DELAY TEST 417

12.1 Delay Test Problem . . . . . . . . . . . . . . . . . . . . . . . . . . . 417
12.2 Path-Delay Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 420
12.2.1 Test Generation for Combinational Circuits . . . . . . . . . . 424
12.2.2 Number of Paths in a Circuit . . . . . . . . . . . . . . . . . . 427
12.3 Transition Faults . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 428
12.4 Delay Test Methodologies . . . . . . . . . . . . . . . . . . . . . . . . 429
12.4.1 Slow-Clock Combinational Test . . . . . . . . . . . . . . . . . 429
12.4.2 Enhanced-Scan Test . . . . . . . . . . . . . . . . . . . . . . . 430
12.4.3 Normal-Scan Sequential Test . . . . . . . . . . . . . . . . . . 431
12.4.4 Variable-Clock Non-Scan Sequential Test ........... 432
12.4.5 Rated-Clock Non-Scan Sequential Test . . . . . . . . . . . . . 434
12.5 Practical Considerations in Delay Testing . . . . . . . . . . . . . . . 434
12.5.1 At-Speed Testing . . . . . . . . . . . . . . . . . . . . . . . . . 435
12.6 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 436

13 IDDQ TEST 439

13.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 439
13.2 Faults Detected by Tests . . . . . . . . . . . . . . . . . . . . . 441
13.3 Testing Methods . . . . . . . . . . . . . . . . . . . . . . . . . . 446
xii TABLE OF CONTENTS

13.3.1 Fault Coverage Metrics . . . . . . . . . . . . . . . . . . 446

13.3.2 Test Vector Selection from Stuck-Fault Vector Sets . . 448
13.3.3 Instrumentation Problems . . . . . . . . . . . . . . . . . . . . 451
13.3.4 Current Limit Setting . . . . . . . . . . . . . . . . . . . . . . 452
13.4 Surveys of Testing Effectiveness . . . . . . . . . . . . . . . . . 453
13.5 Limitations of Testing . . . . . . . . . . . . . . . . . . . . . . . 455
13.6 Delta Testing . . . . . . . . . . . . . . . . . . . . . . . . . . . 456
13.7 Built-In Current Testing . . . . . . . . . . . . . . . . . . . . . 458
13.8 Design for Testability . . . . . . . . . . . . . . . . . . . . . . . 460
13.9 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 460

III DESIGN FOR TESTABILITY 463

14 DIGITAL DFT AND SCAN DESIGN 465

14.1 Ad-Hoc DFT Methods . . . . . . . . . . . . . . . . . . . . . . . . . . 466
14.2 Scan Design . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 467
14.2.1 Scan Design Rules . . . . . . . . . . . . . . . . . . . . . . . . 469
14.2.2 Tests for Scan Circuits . . . . . . . . . . . . . . . . . . . . . . 471
14.2.3 Multiple Scan Registers . . . . . . . . . . . . . . . . . . . . . 474
14.2.4 Overheads of Scan Design . . . . . . . . . . . . . . . . . . . . 474
14.2.5 Design Automation . . . . . . . . . . . . . . . . . . . . . . . . . . 477
14.2.6 Physical Design and Timing Verification of Scan . . . . . . . 479
14.3 Partial-Scan Design . . . . . . . . . . . . . . . . . . . . . . . . . . . 479
14.4 Variations of Scan . . . . . . . . . . . . . . . . . . . . . . . . . . . . 483
14.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 485

15 BUILT-IN SELF-TEST 489

15.1 The Economic Case for BIST . . . . . . . . . . . . . . . . . . . . . . 490
15.1.1 Chip/Board Area Cost vs. Tester Cost . . . . . . . . . . . . . 492
15.1.2 Chip/Board Area Cost vs. System Downtime Cost . . . . . . 494
15.2 Random Logic BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
15.2.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 495
15.2.2 BIST Process . . . . . . . . . . . . . . . . . . . . . . . . . . . 496
15.2.3 BIST Pattern Generation . . . . . . . . . . . . . . . . . . . . 498
15.2.4 BIST Response Compaction . . . . . . . . . . . . . . . . . . . 512
15.2.5 Built-in Logic Block Observers . . . . . . . . . . . . . . . . . 519
15.2.6 Test-Per-Clock BIST Systems . . . . . . . . . . . . . . . . . . 521
15.2.7 Test-Per-Scan BIST Systems . . . . . . . . . . . . . . . . . . 521
15.2.8 Circular Self-Test Path System . . . . . . . . . . . . . . . . . 525
15.2.9 Circuit Initialization . . . . . . . . . . . . . . . . . . . . . . . 526
15.2.10 Device Level BIST . . . . . . . . . . . . . . . . . . . . . . . . 526
15.2.11 Test Point Insertion . . . . . . . . . . . . . . . . . . . . . . . 528
15.3 Memory BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 529
15.3.1 Definitions . . . . . . . . . . . . . . . . . . . . . . . . . . . . 530
TABLE OF CONTENTS xiii

15.3.2 March Test SRAM BIST . . . . . . . . . . . . . . . . . . . . 532

15.3.3 SRAM BIST with MISR . . . . . . . . . . . . . . . . . . . . . 534
15.3.4 Neighborhood Pattern Sensitive Fault Test DRAM BIST . . 536
15.3.5 Transparent Memory BIST Tests . . . . . . . . . . . . . . . . 539
15.3.6 Complex Examples . . . . . . . . . . . . . . . . . . . . . . . . 539
15.4 Delay Fault BIST . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 540
15.5 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 543

16 BOUNDARY SCAN STANDARD 549

16.1 Motivation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 550
16.1.1 Purpose of Standard . . . . . . . . . . . . . . . . . . . . . . . 552
16.2 System Configuration with Boundary Scan . . . . . . . . . . . . . . 553
16.2.1 TAP Controller and Port . . . . . . . . . . . . . . . . . . . . 553
16.2.2 Boundary Scan Test Instructions . . . . . . . . . . . . . . . . 557
16.2.3 Pin Constraints of the Standard . . . . . . . . . . . . . . . . 564
16.3 Boundary Scan Description Language . . . . . . . . . . . . . . . . . 569
16.3.1 BSDL Description Components . . . . . . . . . . . . . . . . . 570
16.3.2 Pin Descriptions . . . . . . . . . . . . . . . . . . . . . . . . . 571
16.4 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 572

17 ANALOG TEST BUS STANDARD 575

17.1 Analog Circuit Design for Testability . . . . . . . . . . . . . . . . . . 576
17.2 Analog Test Bus (ATB) . . . . . . . . . . . . . . . . . . . . . . . . . 576
17.2.1 Targeted Analog Faults . . . . . . . . . . . . . . . . . . . . . 577
17.2.2 Analog Test Access Port (ATAP) . . . . . . . . . . . . . . . . 579
17.2.3 Test Bus Interface Circuit (TBIC) . . . . . . . . . . . . . . . 580
17.2.4 Analog Boundary Module (ABM) . . . . . . . . . . . . . . . 583
17.2.5 Instructions for 1149.4 Standard . . . . . . . . . . . . . . . . 585
17.2.6 Other 1149.4 Standard Features . . . . . . . . . . . . . . . . 589
17.3 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 591

18 SYSTEM TEST AND CORE-BASED DESIGN 595

18.1 System Test Problem Defined . . . . . . . . . . . . . . . . . . . . . . 596
18.2 Functional Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 597
18.2.1 Microprocessor Test . . . . . . . . . . . . . . . . . . . . . . . 598
18.3 Diagnostic Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 598
18.3.1 Fault Dictionary . . . . . . . . . . . . . . . . . . . . . . . . . 599
18.3.2 Diagnostic Tree . . . . . . . . . . . . . . . . . . . . . . . . . . 600
18.3.3 A System Test Example . . . . . . . . . . . . . . . . . . . . . 602
18.4 Testable System Design . . . . . . . . . . . . . . . . . . . . . . . . . 604
18.5 Core-Based Design and Test-Wrapper . . . . . . . . . . . . . . . . . 606
18.6 A Test Architecture for System-on-a-Chip (SOC) . . . . . . . . . . . 607
18.7 An Integrated Design and Test Approach . . . . . . . . . . . . . . . 608
18.8 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 610
xiv TABLE OF CONTENTS

19 THE FUTURE OF TESTING 613

A CYCLIC REDUNDANCY CODE THEORY 615

A.1 Polynomial Multiplier . . . . . . . . . . . . . . . . . . . . . . . . . . 616
A.2 Polynomial Divider . . . . . . . . . . . . . . . . . . . . . . . . . . . . 617

B PRIMITIVE POLYNOMIALS OF DEGREE 1 TO 100 619

C BOOKS ON TESTING 621

C.1 General and Tutorial . . . . . . . . . . . . . . . . . . . . . . . . . . . 621
C.2 Analog and Mixed-Signal Circuit Test . . . . . . . . . . . . . . . . . 622
C.3 ATE, Test Programming, and Production Test . . . . . . . . . . . . 622
C.4 Board and MCM Test and Boundary Scan . . . . . . . . . . . . . . . 623
C.5 Built-In Self-Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
C.6 Delay Fault Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 624
C.7 Design for Testability . . . . . . . . . . . . . . . . . . . . . . . . . . 624
C.8 Fault Modeling . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
C.9 Fault Tolerance and Diagnosis . . . . . . . . . . . . . . . . . . . . . . 625
C.10 Formal Verification . . . . . . . . . . . . . . . . . . . . . . . . . . . . 625
C.11 High-Level Test and Verification . . . . . . . . . . . . . . . . . . . . 626
C.12 Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
C.13 Memory Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 626
C.14 Microprocessor Verification and Test . . . . . . . . . . . . . . . . . . 627
C.15 Semiconductor Defect Mechanisms . . . . . . . . . . . . . . . . . . . 627
C.16 System Test . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
C.17 Test Economics . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 627
C.18 Test Evaluation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
C.19 Test Generation . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
C.20 Periodicals . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 628
C.21 Conferences and Workshops . . . . . . . . . . . . . . . . . . . . . . . 629
C.22 Web Sites . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 629

BIBLIOGRAPHY 631

INDEX 671
PREFACE

The modern electronic testing has a forty year history. Test professionals hold
some fairly large conferences and numerous workshops, have a journal, and there
are over one hundred books on testing. Still, a full course on testing is offered only
at a few universities, mostly by professors who have a research interest in this area.
Apparently, most professors would not have taken a course on electronic testing
when they were students.
Other than the computer engineering curriculum being too crowded, the major
reason cited for the absence of a course on electronic testing is the lack of a suitable
textbook. For VLSI the foundation was provided by semiconductor device technol-
ogy, circuit design, and electronic testing. In a computer engineering curriculum,
therefore, it is necessary that foundations should be taught before applications. The
field of VLSI has expanded to systems-on-a-chip, which include digital, memory, and
mixed-signal subsystems. To our knowledge this is the first textbook to cover all
three types of electronic circuits.
We have written this textbook for an undergraduate “foundations” course on
electronic testing. Obviously, it is too voluminous for a one-semester course and a
teacher will have to select from the topics. We did not restrict such freedom because
the selection may depend upon the individual expertise and interests. Besides, there
is merit in having a larger book that will retain its usefulness for the owner even
after the completion of the course.
With equal tenacity, we address the needs of three other groups of readers.
The first group consists of engineers who, upon graduation, engage in any kind
of electronic hardware design, testing, or manufacturing project. Parts I and III
emphasize the needs of a design-oriented project and Parts I and II those of a test-
oriented project. The second group consists of students of a VLSI design course
who have not taken a course on testing. Parts I and III focus on their needs. The
third group, consisting of post-graduate and research students, will find a complete
coverage of topics with pointers to references where advanced material was omitted
for a lack of space. Figure 1.6 shows several ways to read this book.
At the 1999 International Test Conference during a panel discussion titled, “In-
creasing Test Coverage in a VLSI Design Course,” a panelist from the microelec-
tronics industry gave the wish-list as: test economics, classical semiconductor de-
fects, simple test pattern coverage, structured design for testability techniques (scan,
boundary scan, BIST) for system-on-a-chip design, automatic test equipment (con-
xvi PREFACE

straints and costs), and selected advanced topics ( and delay faults.) We kept
that list in mind while writing the book and we hope the teachers of VLSI design
and electronic testing courses will too.
We are all too familiar with incompleteness of software debugging and hardware
design verification. No “formal” method was used to verify the material in this book
either. Despite all efforts to remove errors, we cannot guarantee that the readers will
not find them. We will greatly appreciate the generosity of our readers if they inform
us about any errors. We will make such findings available to all readers through our
websites until the publisher gives us an opportunity to make corrections, with due
acknowledgment to those who have pointed them out.
We have taught a course on testing at Rutgers University for the past ten years.
Interaction with the students in the course and our master’s and doctoral students
had the greatest influence on our understanding of the subject. We would like to
thank them. Special mention should be made of the class of Spring 2000, which used
the draft and pointed out corrections and improvements. We are indebted to col-
leagues at Bell Labs and Rutgers for their advice and counsel. The enthusiasm and
support of the world-wide test professionals was exceptional. A partial list of those
we thank includes: Miron Abramovici, Prathima Agrawal, Mark Barber, Shawn
Blanton, Amy Bushnell, Tapan Chakraborty, Srimat Chakradhar, Xinghao Chen,
Dochan C. Choi, Rick Chruscial, Don Denburg, José de Sousa, Shaun Erickson,
David Fessler, Hideo Fujiwara, Paul Glick, John Hayes, Michael Hsiao, James Ja-
cob, Neil Kelly, Bill Kish, Kozo Kinoshita, Ken Lanier, Yuhai Ma, Pinaki Mazumder,
Cliff Miller, Karen Panetta, Janusz Rajski, Elizabeth Rudnick, Manoj Sachdev, Ke-
wal Saluja, Sharad Seth, and Lakshman Yagati. We thank our publisher Carl Harris
for always encouraging us to proceed ahead and for being patient through schedule
slips. We are thankful for the support of Al Aho, Dennis Ritchie, and Tom Szyman-
ski, research managers at Bell Labs, and David Daut and Jim Flanagan of Rutgers
University.
We also wish to thank the LTX Corporation, the Advantest Corporation, Sam-
sung Electronics Company, Ltd., IBM, and Lucent Technologies for their cooperation
in providing data for this book. In describing technical contributions we have tried
our best to cite correctly. From those who find their work incorrectly cited, we beg
forgiveness because such errors, caused by our ignorance, were unintentional.
We have corrected many errors found in the first printing. Students of our
class of Spring 2001 at Rutgers, especially, Xiao Liu, Shuo Sheng and Liang Zhang,
deserve thanks for pointing errors out. Many other readers whose help is grate-
fully acknowledged include Mike Balster and Gordon Robinson of Credence, Kanad
Chakraborty of Agere Systems, and Yong Kim of University of Wisconsin.
A complete set of lectures (powerpoint slides) based on this book can be obtained
from our websites.
Michael L. Bushnell Vishwani D. Agrawal
bushnell@caip.rutgers.edu va@agere.com
http://www-caip. rutgers.edu/ http://cm.bell-labs.com/
~bushnell/rutgers.html cm/cs/who/va
ABOUT THE AUTHORS

Michael L. Bushnell is a Full Professor and a Board of Trustees Research Fellow

in the Electrical and Computer Engineering Department at Rutgers University. He
received his B.S. degree at Massachusetts Institute of Technology in 1975, and his
M.S. degree in 1983 and his PhD degree in 1986, both from Carnegie Mellon Uni-
versity. He was selected in 1983 for the American Electronics Association Faculty
Development Program, he received the Outstanding Graduate Student Teaching
Award from Carnegie Mellon, and he was a Presidential Young Investigator of the
National Science Foundation of the United States. His current VLSI CAD research
interests are automatic digital, analog, and mixed-signal circuit test-pattern gen-
eration on serial and distributed computers, delay fault built-in self-testing, fault
simulation, synthesis for testability, and low-power design. He coauthored 78 papers.
His books on VLSI CAD are Efficient Branch and Bound Search with Application
to Computer Aided Design, Neural Models and Algorithms for Digital Testing, and
Design Automation. He holds 3 patents (2 more are pending) on BIST and test
generation methods. He is an Editorial Board Member of the Journal of Electronic
Testing: Theory and Applications. He served as the Program Co-Chair of India’s
annual International Conference on VLSI Design in 1995 and 1996.

Vishwani D. Agrawal is a Distinguished Member of Technical Staff in the Com-

puting Sciences Research Center of Bell Labs (R&D arm of Lucent Technologies),
Murray Hill, New Jersey, and a Visiting Professor of Electrical and Computer En-
gineering at Rutgers University, New Brunswick, New Jersey. He obtained his BSc
degree from the University of Allahabad, Allahabad, India, in 1960, BE (honours)
degree from the University of Roorkee, Roorkee, India, in 1964, ME degree from the
Indian Institute of Science, Bangalore, India, in 1966, and PhD degree in electrical
engineering from the University of Illinois, Urbana-Champaign, in 1971. His current
interests are testing, synthesis for testability, and parallel algorithms. He has pub-
lished over 200 papers and coauthored four books. He holds twelve U.S. patents on
testing, design for testability, and low-power design. He is the Editor-in-Chief of the
Journal of Electronic Testing: Theory and Applications and a past Editor-in-Chief
of the IEEE Design & Test of Computers magazine. He is the Consulting Editor
for the Frontiers in Electronic Testing book series of Kluwer Academic Publishers,
Boston. In 1985, he co-founded India’s annual International Conference on VLSI
Design. From 1989 to 1990, he served on the Board of Governors of the IEEE
xviii ABOUT THE AUTHORS

Computer Society, and in 1994, chaired the Fellow Selection Committee of that So-
ciety. He is a Fellow of the IEEE, a Fellow of the IETE (India), and a Member of
the ACM. He has received five Best Paper Awards. In 1993, he received the Distin-
guished Alumnus Award of the University of Illinois at Urbana-Champaign. In 1998,
he received the Harry H. Goode Memorial Award of the IEEE Computer Society for
“innovative contributions to the field of electronic testing.”