You are on page 1of 87

8 7 6 5 4 3 2 1

1. ALL INFORMATION COMPILED FOR USERS OF FORUM HTTP://WWW.MOBILEGSM.IN.UA

PCB 820-00863-09 X891 Intel Edition TOP MLB


D D

FD0401

C3928C3961C3901C3900C3908C3907C3996C3990C3994C3992C3991
R3041

C3041
C4125 *
R3901

C4196
FD0405

*
C4126
R3900 U4120

*
C3906

R3905 C4121

C3995 C4122
C3950

C4191
J3900
C3951
L4120 *

R3908

*
C3940

C3941
C4192
R3907

C4106
C3930

C3931 *
L4100
C3960

C3797
*
FL3995
C4105
*
C3993

C3718

C3796
R3802
C3925

*
U4100
C3710 *

CL0401

R4330 *
C3719 C3715 C3721

C4303

C3795
C4101

FL3903
*
C4102

C3717
FL4303
C3800
C4322
R3800

C3720
TP0543 TP0540FL4306

C3704
C3810 U3700 *
C4306 C3702

*
C4309

FL4305
C3750
C4307 C4308

C3722

*
J4300
*

C3700
L3700

C3798
FL4307 C4304

C4552

R4552
XW3700 C4305 C4302

DZ4310 *
C4330

C4592C4555C4556

R3820
R3811
R4310

R3803
*

C3709
C4495 C3701

J4500
C4324
C4320
FD0403 R3810

FL4556
C4494
R4400
R4308 PP0571
PP0570 *
C4497

C4310
FL4330 *

C4597
FD0412 C4410
C4326 C4491
R4309
C4594 FL4301

C4421 C4492 C4596 C4498


C4405
C4301

FL3901

L4401
C3909
C4300
C4493
XW4400 C4090 U4400

FL4001
FL4555 C4092

*
C4096
R4010 C4091

L4400
C4017
R4001

C4411
C4094

C
FL4650 R4005

C
R4007
R4617 C4006

XW4600
C4010

C4660
C4412

C4593

C4422

C4420

C4595

C4401
FL4640
C4050

J4000
C4007 C4496 C4490
FL4641
FL4642
C4051
*

DZ4641 C3790 * C4400


DZ4642

C4803

C4802
C4001 R4553

R3072
C4614

C4553
DZ4640

R3073
C4000 C4040 C4554 C4823
R4611
0

C4650 C2763 *
6

C4008 C4808 *
7

C4041 FL4554
2
C4613

C4617 C4812
W
X

C4824
C4825
C4061
C4601
C4060
C4600 C4030 C4809
C4028
J4600

*
C4618 C4031
R4000 C4822

C4801
FL4618

FL4619
R4601 C4805
2

C4093
0
8

R4600 C4814
4

C4701C4700
W

C4633
X

R4619 R4710
R4633 C4821 U4700
R4634 R4701
C4636

C4632

C4634 C4025 R4700

C4804
R4831
FL4003
C4631

Q3700

DZ4643 DZ4644

C4820C4813
C3622
PP0583
R3042C3042

C4811
FL4643 FL4644

C3600C3601

R3600
*
PP0582
*

C4630 SB0400

C2605
R1121
C4635

PP0541

*
R4003

*
*
R1101

R3620

C3620
U3620
PP0540

U3600

*
FD0420 R3110
R4800R4830
R4221

C3602
CL0400 C4817

C1852

C1832

C1840
FL4204

R3100

R1863

R1871

R1242

R1243

R1241

R1240

R1221

C1132

C1133

R1202

R1211

C1131

C1130

R1201

R1222

C1123

C1122

C1121

C1120

R1212

R1231

R1430

R1411

R1232

R1131

R1431

C4815

C1124

C1125

R1130

R1100

R1861

C3044

R3044
*
C2602

*
C2622
C3190 *
FL4200

PP0547 C1851 C1830


C4204

PP0502 R1500

*
L3100
FL4202 PP0542
C6486

C6485

U3100
*
C4203 C2630
R3601
R3801

C4200 C1842 J_INT_BOT


C2628

C2642

C1863

C2640

C2646

C2600

C2644
C4202 *
*

C1810

C2620

C2614

C2612

C2606
C6484 C2652 C2650 PP0545
PP0544
R4220 * R1420
C2629
C6483
C4220 PP0503
C2631 C2603 PP0514
C2609 C2634 R1421
R1464

C2645
FL6480 C3115
C4221
*

C1731
C6480 R1410 C3111 *
C1199
C1812
J4200

C1805
C4201

C2619
C1194
*

*
C6482 R1450 C3112
C2745

*
*

C1730
R4211

C2613
C1813

C2621

C1737
C2632
PP0587 R1194
*
*

FL6482 R1451
C4205 C3113 *

C1193

*
FL6464 R1150
*
C1191

C1861

C1192
C4211 C3114

X
PP0530

*
C1092

C2649
2
C6464 C1102 C1011

7
C4212 PP0531

0
5
C1750
*

C2710
C1781
0
C1198
FL1092

FL6462 XW2790 C1103

*
R4210
C1804

C1782
0

C3110
0

C2782

C2781
W
R1198

6
C1101

X
C6462 FL6411 *

7
C4210 C1093 C1760

C2615
1

1
W

3
C6460 C6411 C1100 Y1000
X

7
R4212

C1396
C1801

R1010
1
FL6400

XW2780
C1802

W
C1761

*
*

*
FL6460 R6410

X
*
C1763

C2780

C2641
FL6430
C6430 C6410 *
C1803 C1723

C1734
*

R1300

C1301
R1011C1010
J6400

R6421R6416R6418

R6432C6432
C1880

C6400
R1880 C1881 C1721
*
* R1460
R6431C6431 L2780

C2611
C6420
C1691

*
PP0546
FL6433
C6433 R1465
C1764

C1773

C1762

C1390
C6418
FL6454

FL6450 C1690 *
R0600

C1735
C6416

C2626
C6450 R1461

C2712

C2715

C2714
*

C6419 PP0562
X

C1702
511

SH0401
W

C6452 R0601
2
XW1701

C1394
7

U1000
C6421
7

*
XW0

FL6452 R1480
C1706

C1710

C1772
0

C1703 C1393

R2600C2610C2623

*
FL6413

*
CL0402 C6454 C1392 C2915

C1736
PP0590 C1811 *

C1870
C6466 C6413

C1295
*

PP0516
C1095C1090

C6465
PP0591 C6472
C1708

XW1870 C6471

R1602
C1705

C1709

C1793

R6465 PP0561 *
L2710
R6466

R1481

*
C6473 C1296
X

C1738
W
1

R6419 C6470 U2600 R1441

C1391
*

7
9
*

*
C1720C1722

R6420 PP0563 R5108R1440


C6493 * *

R1482
C6494 PP0515
C1711

C2635

*
R1623
C1713

C1704

C1792

* R1603

C2713

C2711

C2716
C3304
C4571 FL4572 PP0512 R1251 R1621
XW5785
XW5784

* FD0404

C1732
C3302 R1604

R1471
XW4570 C4572 R1250 R1620
*

C2601
* R1470
*

C3303 R1020

*
C4570 R4563 R1252 R1000
C1862

L6300

L6301
C6491 PP0564
*

C1860
R1622

C1490
C4563
FL4574FL5780

C1712

C1707

C1791

*
U1490

C2617

*
C4564 C6496 R1860 *

C1733

R1601C6300R6300R3061
*
C4573 L2711
*

U6110
C4575

C4574

C1290 *

C2643
J4530

C5785
XW6110

C1291
*
C1794
C6112 *

C5786
C6111
C4560C5781 PP0520

C1739
R5903
FL4561R4560

C2651
C5900 DZ5900

*
L2712

C1841
FL5703 *
C6117 U6300
*
C5784 L6110
0

C5703
3

*
PP0501
7

FL5783
2

C6110 R6116

C2618
C5700
W
X
R5901

*
C5783 SB0402

*
C1853
C2616
FL5700 C6100 *

B B

C6330
C4562

R1400
R1401
C5701

R0621

R0620

R0623
U6100

PP0560 *
U5900

R6210
*

R2604R1862C3071 R2601R3000 R3071 R1870


C1395 C1833 C2907 C2906 R1462 C1831 C1850

C6200

C6395

C6391
R5701 C5782 C2810
FL5782

C2624
PP0522 C5902
PP0592 R5700 C6390 C6311

R0622
FL5704 C2703 * *
C2702
C3553 R5902 *
C2813 *
C5704 C2705 C1843 C3390 *
XW5900

R6211

C6290
FD0410
J5700

C2772

C6210
PP0586
FL3553

L2810

L2811

C6312

*
C2647
C2724 *
C2700

L2770
C3530

U6200
L5720

*
*

R3530 C5702 C2811 *


C2704

C2850

C2992

C2851

C2991
*

*
C2706

C6292

C6291
*
DZ3530 FL5702 L2700

*
R3360
C3501

C3500

C2770

*
*
C2812

*
*

*
SH0400 C2701
R6200
L5740

L5710
*
C3540

*
C3020 C2865
XW2800

C2771
PP0504 PP0513 C2859 C2860 R3010 C2858 C2863

R3331
R3540 C2861 R3020 C2900
C5124 *
C5138 *
C2627 C5690 *
C5130

C5640
J3500

DZ3540

R3070R3011
C3520

C2741 *
L2703
XW2740
*
L5730

L5600
L5700
*

*
L2740
C5131 *
*

C5139 *
C5137 *
C5653
C5655

R3520 XW3041 C5641 *


C3343 *
L3341 *
L3340 *

C2742 *
C3342
PP0505
DZ3520 *
C3551 CL0403
*

C2637 C2636

C2909
C6490
C5651

C5621
*

PP0506
X

L2702 *
*
*

C3341
C5611
W

XW2991

R3551

C3045
3

C3510
C2790
0

C2855
L5100
4

C2913
C2743 *
X

C6495 *
C5660C5652
4

C3552 C5612C5631C5632C5654
W

C2792 *
*
X

3
W

C3511
0

*
3

L2720
4

C2856
R3552

R3045
0

R3316
4

C5650 *
5

L2790

*
C3550 C2744 *

C2990
C2854
L2701 * * C3316 C3317
C3391 *
C2852
U5600

C2791 *

C6497 C5691
R3370 FL3550

U2700

C3313C3314

C3312C3315
C2740 C2720

C3010
C5692

C3310
C3370
C5125
C3202

R3202

C3311
*

C2903
*

*
*

C5135

C2864

C3323

C3325

C3324
C2723 *
C5642

C2751
C6492

C3320
PP0521

*
L2730

L2750
*
DZ3300
C2910

*
C2911

C3201 L2741

C2866

*
R3074

C5645

Q3201 * XW2990 PP0500

*
R3201
*

C2722 *
* *

C2862
Q3200 C3322
C5128C5129C5142C5126

U3300
*
R3332
C2750

C2752
3 C3352

L2800

C3301
C3293

C2800C5127

*
C2970

C2971

C2857
C3305
0

FD0402 C2760C2730
7
*

C5134
3

R3330C2920

R3001 C3002
*
J3200

C3308R3062

C3307C3306
L2721 *
U5100
C3353C3292 XW

C3294 * XW3000
C2732 C3340

*
*

Y3000
Q3350

C3031
C3030

R3350

C3350
C3360
XW3200

L2760

FD0411 PP0550

*
X

*
*
W

C5136

C2901 C2981
*

*9

*
2

C3361

*
C2721

C2762

C2761

C2731

C2802

C2801
9

SB0401
5

C2914 C2980
*
C3351

A A

TITLE
APPLE PCBF, X891
THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED
TOP MLB
ORIG DIV DESIGNER DATE SCALE DRAWING NUMBER

KEN KIPLINGER 03/31/17 1:1


820-00863-09
TOP SIDE ASSEMBLY NOTICE OF PROPRIETARY PROPERTY
NOTES:
ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM THE INFORMATION CONTAINED HEREIN IS THE
TO STANDARDS AS DEFINED IN APPLE SPECIFICATION PROPRIETARY PROPERTY OF APPLE
080-2265 (FLEXIBLE PRINTED CIRCUIT BOARDS) OR
THE POSSESSOR AGREES TO THE FOLLOWING
062-0073 (MULTI- LAYER BOARDS) AS APPLICABLE.
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
(II) NOT TO REPRODUCE OR COPY IT
(III) NOT TO REVEAL OR PUBLISH IT

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
1. ALL INFORMATION COMPILED FOR USERS OF FORUM HTTP://WWW.MOBILEGSM.IN.UA

PCB 820-00869-06 X893 Intel Edition TOP MLB


D *

FD0403
D
L1405_KL1404_K

*
FD0413
C1404_KC1403_K

JUAT1_K
QUADP_K

L1401_KC1401_K L1402_K

FD0406

FD0415

R1402_K
R1404_K R1403_K

C1503_K
*

L1501_K
GLNA_K

L1700_K

L1701_K
TP0790

C1304_K
C1305_K
L1300_K

MHBLN_K
C1306_K
C1302_K
C1303_K
*
PP1648_K

R1302_K
LBLN_K
*

PP1618_K
PP1658_K

R1303_K
PP1625_K

R1406_K

R1405_K
GNSS_K
PP1604_K

GPOUAT_K C1405_K
C1402_K
*
PP1621_K PP1655_K

C1700_K

R1700_K

*
PP1623_K
PP1656_K

PP1622_K
C1701_K

PP1620_K

C1407_K
C7507_S
C1406_K

FL1400_K
C7515_S
R1500_K

C7511_S
PP1619_K PP7508_S

PP7507_S
C7518_S

R7508_S
* NFC_DCDC_S
C7516_S PP1624_K
Q7502_S

L7502_S
*
*
*
C7533_S
*
C7532_S
C7512_S * C7522_S
C7520_S PP7510_S
Q7501_S
C7531_S

*
L7503_S
C7514_S PP7505_S

*
C7530_S
C7510_S

C7506_S
C7517_S *

C7521_S
L7500_S C7523_S PP7514_S PP7504_S

C C
C7503_S
C7526_S

PP7503_S

PP7506_S
T7500_S PP0700
PP1612_K
*
PP0704
PP1635_K
PP1611_K
PP7509_S
PP7511_S
L7501_S

NFC_S

R203_K
R0630
C200_K
R5001

C5015
C7513_S

*
C7502_S *

C5027

C5026

*
C7505_S C3412 PP1633_K
C5016 EPROM_K
TP7505_S
R501_K

L5000
J_INT_TOP C5018
PP7513_S

C3441

C3440

C3411
R209_K PP7512_S
C512_K
R204_K
R7502_S
C7504_S

C3418

C3416

C3419

R207_K
U5000
*

C518_K
TP7506_S PP1657_K

C510_K
C513_K *

C516_K
C5000
C5001

C5019
TP0720
R3407 C5029 C519_K
C3404 C505_K *
R3450

C3455 C3451

C5012
*
C523_K C508_K
C509_K * * L503_K
XW500_K

*
PP0702

C520_K
C3406 C5025 *

TP0721
C3456 C3452 PP0703

X
W
C500_K
U3400

5
C5011

0
XW3402C3415

C522_K

4
D3400 C501_K

_
K
C3454 C3453 XW503_K
PP1602_K
C5024 *

L500_K
C506_K
PP1634_K PP0701
C5530 C3403
C3402

BBPMU_K
*
*

C3413
PP1613_K
XW3401

D3401 XW501_K
0

PP1609_K
MC_K

L502_K

C514_K
0

C5008 *
PP1601_K
4

C503_K
3

PP1610_K
W

C3443

C3444
R3408
R3422

C3442
X

*
PP1642_K
C3417
C3445
C3405

*
*

PP1641_K
*

R3401

*
C5006 *

C504_K
*
*
U5530

D3403

*
*
C5028
R1604_K

C515_K
R3420
R3421

C511_K
R1610_K
C434_K

*
C441_K C400_K C417_K C517_KC419_K
C439_K
C201_K
C426_K C404_K
C413_K

L501_K
C521_K
R208_K

R1608_K C415_K
PP1614_K

C502_K
D3402 R1609_K

K
C437_K PP1643_K

_
PP1640_K

2
0
R401_K

5
W
C428_K

X
C401_K
C3461 C403_K
C3407

C429_K PP1607_K PP1603_K


C4934
C420_K R206_K C4926 C4929
C4925 C4922
C3462 C440_K C409_K
PP1600_K

C4914
C433_K
PP1628_K
R3406

C3463 PP1661_K
R400_K TP0730
PP1627_K

C421_K
C3464 C300_K

U4900
FD0405 C3465
C425_K
U_BB_K C301_K
R3460

C423_K
C431_K
C427_K
C3466 C422_K

*
C418_K PP1660_K
FD0414
C4927
C414_K
PP1605_K
R201_K
C303_K

C4928 C4930
TCXO_K

R1616_K TP0731

C4909
R302_K C406_K
PP1606_K
R1617_K C412_K PP1615_K
R202_K
*

C4904 *

R1613_K C407_K

L4900
R1614_K
C402_K
R1615_K C4932 *

C4907
R1607_K

*
*

R200_K C4903 *

R7702_W *
*
C7709_W

R300_K
R7711_W

C7711_W

R7600_W

C7603_W

C7600_W

C7601_W

R1605_K

R1606_K

R1611_K

R1612_K

R1602_K

R1603_K

R1601_K
C405_K

C430_K

C432_K

W5BPF_W *
R205_KC438_KC410_K
C408_K
C4931

*
C436_K C411_K C416_K
C435_K

C424_K
*

R1600_K

*
C507_K
C7608_W

TP0708
C7607_W

PP7616_W PP7623_W
* PP7622_W
C7602_W C4905 *
*

PP7621_W
PP7620_W
PP7630_W
TP0713
PP7624_W
PP7631_W

J_DEBUG_K
PP7603_W
PP7609_W
R7700_W

C7708_W PP7626_W
PP7607_W
* C7705_W *
L7704_W
PP7600_WPP7617_W
PP7605_W

B
*

PP7608_W

B
PP7611_WPP7606_W
ET_K
W25DI_W

UWLAN_W PP7619_W
PP7628_W
PP7604_W
PP7601_W

PP7625_W
PP7629_W PP7627_W
PP7610_W
*

TP0709
PP7618_W
L7600_W
C7701_W

FD0401 PP7613_W
W2BPF_W
*
TP0702 PP7612_W

PP7615_W
FD0410
L7701_W
L7700_W *
R7703_W

TP0705
TP0703

PP7614_W
TP0701
*

C7604_W *
C7716_W

*
C721_K

C722_K

C723_K

W2XSW_W
XW701_K

* C7606_W *
C7609_W *
C7611_W *
C7612_W C720_K TP0752
TP0715 TP0714 TP0700
TP0710
TP0764
XW3043

TP0761 TP0780
PP1608_K TP0754
TP0755 TP0751
TP0763
PP1631_K
TP0750
PP1630_K
PP1632_K
PP1629_K PP1647_K
R5807 FL5809 PP1646_K TP0706 TP0522
TP0753
C5807 C5809
R1200_K

R1201_K

C5945_K
C645_K
C616_K

C907_K

R615_K
C626_K

C631_K

R607_K

C622_K

C621_K

C624_K

R616_K
C629_K

C634_K

C636_K

FL5806 FL5810
C605_K
C607_K

C611_K

R604_K

C603_K

C602_K

R614_K

C610_K

* XW600_K
* C600_K
C623_K *
*

C5806 C5810 C604_K *


TP0707 TP0515
C1601_K
C1200_K

C1201_K

C650_KC642_KC633_K
*
*

R605_K
C615_K
*

FL5800 FL5802 VTCXO_K


C601_K

C5800 C5802
C1202_K

C637_K
C5860

C620_K

FL5805 FL5895
R5801

C612_K

TP0768
C5805 C5895 FL601_K
*

R1202_K

C1204_K
C606_K

R606_K

C5844
*

C5804
C617_K

R602_K PP1616_K
R5844 FL5804 C5890 PP1617_K
TP0766
C1203_K
C641_K

C639_K

C635_K

C5845
*

R603_K

C5803
J5800

XCVR1_K

DZ1609_K
XCVR0_K

FL5890
C613_K

DSM_K

FL5845 FL5803
C640_K *

C5891 FL5896
C638_K

C628_K

R5845
C649_K

PP1654_K
TP0760
C608_KC609_K

PP1653_K
C5850 C5896 FL5894
C643_K C644_K
C627_K R610_K
R609_K

FL5850 C5894 PP1651_K


FL5893
C5893 UATCP_K
*

PP1652_K
TP0762
C5847
*
FL5891

FL5847
*
TP0759
C5842
*
FL1101_K

*
C1106_K

C1104_K

C1108_K
L903_K

L902_K

C908_K
*

R5842 C5892
DZ1606_K
FL5840

TP0758
L1030_K

L1001_K

L1027_K

R1000_K

L1006_K

L1003_K

L1007_K

L1011_K

L1005_K
C619_K

R601_K

C614_K

C5840
C632_K

C5820
*

FL600_K
*

L1004_K * L1016_K *

R5820 C5841 * C1001_K


L1021_K
L1023_K
L1000_K
L1024_K
L1017_K
* * * *
TP0756
R600_K

C630_K

C909_KC1112_K
L1015_K
FL5841

R3043
*

*
L1010_K
C5821
C3043 L1008_K L1012_K
L1009_K
L1013_K C905_K C906_KC900_K TP0771
*

R5821 DZ1608_K
FD0404
L1018_K
DZ1600_K

C1600_K
*

TP0757
*
*

C625_K
J_SIM_K

L1019_K
DZ1607_K*

TP0772
FD0412
GSMDI_K
*
L1025_K
C809_K

C810_K

*
L1014_K
DZ1605_K
FL1100_K
C1109_K

C1111_K

TP0767
TDDPA_K

L1020_K
*

C1107_K
C804_K

C806_K
*

C1105_K
L1026_K
JLAT1_K

SWTX1_K

*
LATCP_K

C7712_W

R7701_W
C903_K *
MHBPA_K

LBPA_K

C813_KC904_K

C7703_W
*

* PP1650_K
R1100_K
C902_K

L901_K

L1100_K C1100_K
PP1649_K
C1103_K
C1705_K

C1706_K

R801_K
*

C812_K
R800_K

*
*

C801_K
C1704_K

L803_K
LATDI_K

C815_K
C805_K

C800_K

*
C1703_K
C808_K
GSMPA_K

L1703_K
C1707_K

C1708_K

C1710_K

C1711_K

L1702_K

XW800_K
C811_KC807_K
*
*

C803_K

FL1102_K
*
C1114_K
C901_K

L900_K

A
SB0400 C1115_K

A
GPOLAT_K *
C1116_K L800_K
*
C1102_K

C1101_K
R1102_K
R1101_K FD0402

FD0411

TITLE
APPLE PCBF, X893
THIS IS THE PROPERTY OF APPLE AND IT MUST BE RETURNED
MLB BOT
ORIG DIV DESIGNER DATE SCALE DRAWING NUMBER

TIM REID 04/06/17 1:1


820-00869-06
TOP SIDE ASSEMBLY NOTICE OF PROPRIETARY PROPERTY
NOTES:
ARTWORK VIEWED FROM COMPONENT SIDE. PCB SHALL CONFORM THE INFORMATION CONTAINED HEREIN IS THE
TO STANDARDS AS DEFINED IN APPLE SPECIFICATION PROPRIETARY PROPERTY OF APPLE
080-2265 (FLEXIBLE PRINTED CIRCUIT BOARDS) OR
THE POSSESSOR AGREES TO THE FOLLOWING
062-0073 (MULTI- LAYER BOARDS) AS APPLICABLE.
(I) TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
(II) NOT TO REPRODUCE OR COPY IT
(III) NOT TO REVEAL OR PUBLISH IT

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
9 0008409760 ENGINEERING RELEASED 2017-04-05

X891/X893 MLB Top: EVT


LAST_MODIFICATION=Mon Apr 3 13:03:06 2017
D D
PAGE CSA CONTENTS SYNC DATE PAGE CSA CONTENTS SYNC DATE
1 1 TABLE OF CONTENTS 46 61 I/O: Accessory Buck test_mlb 10/17/2016
2 2 SYSTEM:BOM Tables test_mlb 10/13/2016 47 62 I/O: USB PD test_mlb 10/13/2016
3 4 SYSTEM: Mechanical Components 48 63 I/O: Hydra test_mlb 10/13/2016
4 5 SYSTEM: Testpoints (Top) test_mlb 10/13/2016 49 64 I/O: B2B Dock test_mlb 10/13/2016
5 6 BOOTSTRAPPING test_mlb 10/13/2016 50 65 I/O: Interposer (Bottom) test_mlb 10/13/2016
6 10 SOC: JTAG,USB,XTAL test_mlb 10/17/2016 51 80 RADIOS 06/04/2015
7 11 SOC: PCIE test_mlb 10/17/2016
8 12 SOC: MIPI & ISP test_mlb 10/13/2016
9 13 SOC: LPDP test_mlb 10/13/2016
10 14 SOC: Serial test_mlb 10/17/2016
11 15 SOC: GPIO & UART test_mlb 10/13/2016
12 16 SOC: AOP test_mlb 10/17/2016
13 17 SOC: Power (1/3) test_mlb 10/17/2016
14 18 SOC: Power (2/3) test_mlb 10/17/2016
15 19 SOC: Power (3/3) test_mlb 10/17/2016
16 26 NAND test_mlb 10/13/2016
C 17 27 SYSTEM POWER: PMU Bucks (1/4) test_mlb 10/13/2016 C
18 28 SYSTEM POWER: PMU Bucks (2/4) test_mlb 10/13/2016
19 29 SYSTEM POWER: PMU LDOs (3/4) test_mlb 10/13/2016
20 30 SYSTEM POWER: PMU (4/4) test_mlb 11/01/2016
21 31 SYSTEM POWER: Boost test_mlb 10/13/2016
22 32 SYSTEM POWER: B2B Battery test_mlb 10/13/2016
23 33 SYSTEM POWER: Charger test_mlb 10/13/2016
24 34 SYSTEM POWER: Iktara
25 35 SYSTEM POWER: B2B Cyclone + Button test_mlb 10/13/2016
26 36 SENSORS test_mlb 10/13/2016
27 37 CAMERA: PMU (1/2) test_mlb 10/13/2016
28 38 CAMERA: PMU (2/2) test_mlb 10/13/2016
29 39 CAMERA: B2B Wide (WY) test_mlb 10/13/2016
30 40 CAMERA: B2B Tele (MT) test_mlb 10/13/2016
31 41 CAMERA: Strobe Drivers test_mlb 10/13/2016
32 42 CAMERA: B2B FCAM test_mlb 10/13/2016
33 43 CAMERA: B2B Strobe + Hold Button test_mlb 10/13/2016
34 44 PEARL: Power test_mlb 10/13/2016
B 35 45 PEARL: B2B Romeo + Juliet test_mlb 10/13/2016
B
36 46 PEARL: B2B Rosaline + Misc test_mlb 10/13/2016
37 47 AUDIO: CODEC (1/2) test_mlb 10/13/2016
38 48 AUDIO: CODEC (2/2) test_mlb 10/13/2016
39 49 AUDIO: Speaker Amp Bottom 08/25/2015
40 50 AUDIO: Speaker Amp Top 08/25/2015
41 51 ARC: Driver test_mlb 10/13/2016
42 56 CG: Power Supplies - Touch & Display test_mlb 10/13/2016
43 57 CG: B2B Display test_mlb 10/13/2016
44 58 CG: B2B Orb & Touch 08/25/2015
45 59 I/O: Overvoltage Cut-Off Circuit sync 01/10/2017

A BOM:639-04583 (Ultimate) DRAWING TITLE


TABLE OF CONTENTS A
BOM:639-03409 (Extreme) SCH,MLB,TOP,X891
DRAWING NUMBER SIZE

051-02221 D
MCO:056-04077 TABLE_5_HEAD
Apple Inc. REVISION

9.0.0
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION NOTICE OF PROPRIETARY PROPERTY: BRANCH

051-02221 1 SCH,MLB_TOP,X891 SCH NO COMMON


TABLE_5_ITEM

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
TABLE_5_ITEM

820-00863 1 PCB,MLB_TOP,X891 PCB NO COMMON I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
1 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 1 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

EEEE Codes Global Ferrites Soft-Term Cap Sub BOMs


TABLE_5_HEAD TABLE_ALT_HEAD TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_CRITICAL_HEAD

PART NUMBER CRITICAL PART# COMMENT


TABLE_5_ITEM TABLE_5_ITEM

825-7691 1 EEEE FOR (MLB_TOP,639-04583,ULTIMATE) EEEE_J2WJ NO ULTIMATE TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

685-00155 1 SUBBOM,MLB,TOP,CAP,TYPICAL,X891 SUBBOM_CAP CRITICAL COMMON


TABLE_5_ITEM
155S00194 155S0610 BOM_TABLE_ALTS ALL FERR BD, 150OHM, TDK 155S0610 FERR BD, 150OHM, 01005
825-7691 1 EEEE FOR (MLB_TOP,639-03409,EXTREME) EEEE_HP26 NO EXTREME TABLE_ALT_ITEM

155S00200 155S0610 BOM_TABLE_ALTS ALL FERR BD, 150OHM, TY Agnes Input


TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

D D
SOC
TABLE_5_ITEM

138S00159 4 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA C2970,C2971,C2980,C2981 CRITICAL SOFT_CAP


TABLE_5_ITEM

138S0831 4 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C2970,C2971,C2980,C2981 CRITICAL TYPICAL_CAP

TABLE_5_HEAD

Agnes Output
PART#

339S00358
QTY

1
DESCRIPTION

SKYE+3GB, B0, M, DEV


REFERENCE DESIGNATOR(S)

U1000
CRITICAL

CRITICAL
BOM OPTION

COMMON
TABLE_5_ITEM

Global R/C Alternates TABLE_ALT_HEAD


PART#

138S00159
QTY

9
DESCRIPTION

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA
REFERENCE DESIGNATOR(S)

C2900,C2901,C2903,C2906,C2907,C2910,C2911,C2913,C2914
CRITICAL

CRITICAL
BOM OPTION

SOFT_CAP
TABLE_5_HEAD

TABLE_5_ITEM

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


TABLE_CRITICAL_HEAD

PART NUMBER CRITICAL PART# COMMENT


TABLE_5_ITEM

TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: TABLE_ALT_ITEM TABLE_CRITICAL_ITEM
138S0831 9 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C2900,C2901,C2903,C2906,C2907,C2910,C2911,C2913,C2914 CRITICAL TYPICAL_CAP
PART NUMBER
118S0764 118S0717 BOM_TABLE_ALTS ALL RES, 3.92K, 0.1%, 0201 118S0717 RES, 3.92K, 0.1%, 0201

339S00359 339S00358 BOM_TABLE_ALTS U1000 DDR-H,3G, B0


TABLE_ALT_ITEM

138S0648 138S0652 BOM_TABLE_ALTS ALL CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO


TABLE_ALT_ITEM

138S0652 CAP,X5R,4.7UF,6.3V,0.65MM,0402
TABLE_CRITICAL_ITEM

Sensors
TABLE_5_HEAD

TABLE_ALT_ITEM

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

339S00360 339S00358 BOM_TABLE_ALTS U1000 DDR-S-20,3G, B0 138S0739 138S0706 BOM_TABLE_ALTS ALL CAP,CER,X5R,0.22UF,20%,6.3V,20% 138S0706 CAP,CER,X5R,0.22UF,20%,6.3V,20% TABLE_5_ITEM

TABLE_ALT_ITEM

339S00361 339S00358 BOM_TABLE_ALTS U1000 DDR-S-18,3G, B0


TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

138S00159 2 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA C3602,C3622 CRITICAL SOFT_CAP


132S0436 132S0400 BOM_TABLE_ALTS ALL CAP,CER,X5R,0.22UF,20%,6.3V,01005 132S0400 CAP,CER,X5R,0.22UF,20%,6.3V,01005 TABLE_5_ITEM

TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

138S0831 2 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C3602,C3622 CRITICAL TYPICAL_CAP


138S00049 138S0831 BOM_TABLE_ALTS ALL CAP,CER,X5R,2.2UF,20%,6.3V,0201 138S0831 CAP,CER,X5R,2.2UF,20%,6.3V,0201

NAND RCAM B2Bs


TABLE_5_HEAD

Ultimate Global Inductors TABLE_ALT_HEAD


PART#

138S00159

138S0831
QTY

3
DESCRIPTION

CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA

CAP,TYPICAL,2.2UF,6.3V,0201,MURATA
REFERENCE DESIGNATOR(S)

C3909,C3925,C4025

C3909,C3925,C4025
CRITICAL

CRITICAL

CRITICAL
BOM OPTION

SOFT_CAP

TYPICAL_CAP
TABLE_5_ITEM

TABLE_5_ITEM

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


TABLE_CRITICAL_HEAD

TABLE_5_HEAD

PART NUMBER CRITICAL PART# COMMENT


PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM

152S00710 152S00617 BOM_TABLE_ALTS ALL IND,MLD,0.1UH,20%,6.1A,29MOHM,H=.65,1608


TABLE_ALT_ITEM

152S00617 IND,MLD,0.1UH,20%,6.1A,29MOHM,H=.65,1608
TABLE_CRITICAL_ITEM

Strobe B2B
335S00287 1 HYNIX, 3DV3, ULTIMATE U2600 CRITICAL ULTIMATE TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

152S00712 152S00620 BOM_TABLE_ALTS ALL IND,MLD,0.1UH,20%,7.2A,17MOHM,H=0.8,2012 152S00620 IND,MLD,0.1UH,20%,7.2A,17MOHM,H=0.8,2012

C C
TABLE_5_ITEM

TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

138S00159 1 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA C4303 CRITICAL SOFT_CAP


PART NUMBER
152S00713 152S00621 BOM_TABLE_ALTS ALL IND,MLD,0.47UH,20%,3.5A,53MO,H=.65,2012 152S00621 IND,MLD,0.47UH,20%,3.5A,53MO,H=.65,2012 TABLE_5_ITEM

TABLE_ALT_ITEM
TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

138S0831 1 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C4303 CRITICAL TYPICAL_CAP


335S00284 335S00287 BOM_TABLE_ALTS U2600 TOSHIBA, 1Z, ULTIMATE
152S00714 152S00622 BOM_TABLE_ALTS ALL IND,MLD,1.0UH,20%,2.1A,100MO,H=.65,2012 152S00622 IND,MLD,1.0UH,20%,2.1A,100MO,H=.65,2012
TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

335S00285 335S00287 BOM_TABLE_ALTS U2600 TOSHIBA, BICS3, ULTIMATE


TABLE_ALT_ITEM

152S00716 152S00626 BOM_TABLE_ALTS ALL IND,MLD,1.5UH,20%,1.1A,160MO,H=.65,2012 152S00626 IND,MLD,1.5UH,20%,1.1A,160MO,H=.65,2012 Audio


TABLE_ALT_ITEM TABLE_CRITICAL_ITEM TABLE_5_HEAD

TABLE_ALT_ITEM

335S00286 335S00287 BOM_TABLE_ALTS U2600 SANDISK, BICS3, ULTIMATE


152S00717 152S00631 BOM_TABLE_ALTS ALL IND,MLD,1.0UH,20%,2.5A,78MO,H=0.8,2012 152S00631 IND,MLD,1.0UH,20%,2.5A,78MO,H=0.8,2012 PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_ALT_ITEM TABLE_CRITICAL_ITEM TABLE_5_ITEM

TABLE_ALT_ITEM

335S00288 335S00287 BOM_TABLE_ALTS U2600 SAMSUNG, 3DV4, ULTIMATE


152S00718 152S00632 BOM_TABLE_ALTS ALL IND,MLD,1.0UH,20%,3.2A,60MO,H=0.8,2016 152S00632 IND,MLD,1.0UH,20%,3.2A,60MO,H=0.8,2016 138S00159 2 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA C4809,C4805 CRITICAL SOFT_CAP
TABLE_ALT_ITEM TABLE_CRITICAL_ITEM TABLE_5_ITEM

152S00720 152S00640 BOM_TABLE_ALTS ALL IND,MLD,0.47UH,3.8A,55MO,H=0.65MM,2012 152S00640 IND,MLD,0.47UH,3.8A,55MO,H=0.65MM,2012 138S0831 2 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C4809,C4805 CRITICAL TYPICAL_CAP

Extreme 152S00721 152S00641 BOM_TABLE_ALTS ALL IND,MLD,0.47UH,4A,48MO,H=0.8MM,2012


TABLE_ALT_ITEM

TABLE_ALT_ITEM
152S00641 IND,MLD,0.47UH,4A,48MO,H=0.8MM,2012
TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM
Pearl B2B
TABLE_5_HEAD 152S00715 152S00623 BOM_TABLE_ALTS ALL IND,MLD,1UH,3.6A,60MO,H=0.8MM,2016 152S00623 IND,MLD,1UH,3.6A,60MO,H=0.8MM,2016 TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

TABLE_5_ITEM 152S00653 152S00651 BOM_TABLE_ALTS ALL IND,1.2UH,3A,2016,0.65Z 152S00651 IND,1.2UH, 3A, 2016, 0.65Z TABLE_5_ITEM

335S00240 1 HYNIX, 3DV3, EXTREME U2600 CRITICAL EXTREME TABLE_ALT_ITEM TABLE_CRITICAL_ITEM


138S00159 1 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA C4613 CRITICAL SOFT_CAP
152S00649 152S00650 BOM_TABLE_ALTS L3340,L3341 IND,0.47UH,6.6A,3225,0.8Z 152S00650 IND,0.47UH,6.6A,3225,0.8Z TABLE_5_ITEM

138S0831 1 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C4613 CRITICAL TYPICAL_CAP


TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


PART NUMBER
Acorn
335S00228

335S00247
335S00240

335S00240
BOM_TABLE_ALTS

BOM_TABLE_ALTS
U2600

U2600
TOSHIBA, BICS3, EXTREME

SANDISK, BICS3, EXTREME


TABLE_ALT_ITEM

TABLE_ALT_ITEM

TABLE_ALT_ITEM
XTAL Alternate TABLE_ALT_HEAD
PART#

138S00160
QTY

2
DESCRIPTION

CAP,SOFT-TERM,10UF,10V,0402,MURATA
REFERENCE DESIGNATOR(S)

C5641,C5653
CRITICAL

CRITICAL
BOM OPTION

SOFT_CAP
TABLE_5_HEAD

TABLE_5_ITEM

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


TABLE_CRITICAL_HEAD TABLE_5_ITEM

335S00276 335S00240 BOM_TABLE_ALTS U2600 SAMSUNG, 3DV4, EXTREME


PART NUMBER CRITICAL PART# COMMENT 138S0979 2 CAP,TYPICAL,10UF,10V,0402,MUR/KYO C5641,C5653 CRITICAL TYPICAL_CAP
TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

Global Capacitors
197S0612 197S0446 BOM_TABLE_ALTS Y1000 XTAL, 24M, 1612 197S0446 XTAL, 24M, 1612
CODEC
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_5_ITEM

B B
TABLE_ALT_HEAD TABLE_CRITICAL_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
138S00160 2 CAP,SOFT-TERM,10UF,10V,0402,MURATA C4811,C4808 CRITICAL SOFT_CAP
PART NUMBER TABLE_5_ITEM

Multi-Vendor Criticals
TABLE_CRITICAL_ITEM

TABLE_ALT_ITEM

138S00149 0402-3T,10.5uF@1V 138S0979 2 CAP,TYPICAL,10UF,10V,0402,MUR/KYO C4811,C4808 CRITICAL TYPICAL_CAP


138S00148 138S00149 BOM_TABLE_ALTS ALL 0402-3T,10.5uF@1V, Kyocera

138S00150 138S00149 BOM_TABLE_ALTS ALL 0402-3T,10.5uF@1V, SEMCO


TABLE_ALT_ITEM

Ansel
TABLE_CRITICAL_HEAD TABLE_CRITICAL_HEAD TABLE_5_HEAD

TABLE_ALT_ITEM

CRITICAL PART# COMMENT CRITICAL PART# COMMENT PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
138S00151 138S00149 BOM_TABLE_ALTS ALL 0402-3T,10.5uF@1V, TY
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_5_ITEM

377S0106 SUPPR,TRANS,VARISTOR,12V,33PF,01005 132S0288 CAP,CER,X5R,0.1UF,10%,16V,0201 138S00160 1 CAP,SOFT-TERM,10UF,10V,0402,MURATA C3710 CRITICAL SOFT_CAP


TABLE_ALT_HEAD TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM TABLE_5_ITEM

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
PART NUMBER
197S0446 XTAL,24MHZ,30PPM,9.5PF,60 OHM MAX,1612 132S0275 CAP,CER,X5R,470PF,10%,10V,01005 138S0979 1 CAP,TYPICAL,10UF,10V,0402,MUR/KYO C3710 CRITICAL TYPICAL_CAP
TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

TABLE_ALT_ITEM

138S00144 0402,16uF@1V 155S0576 FERR BD,10 OHM,50%,750MA,0.07 DCR,01005 132S0249 CAP,CER,X7R,220PF,10%,10V,01005


138S00143 138S00144 BOM_TABLE_ALTS ALL 0402,16uF@1V, Kyocera
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

TABLE_ALT_ITEM

138S00163 138S00144 BOM_TABLE_ALTS ALL 0402,16uF@1V, Taiyo


155S00168 FLTR,NOISE,65 OHMZ,3.4OHM,0.7-2GHZ,0605 132S0245 CAP,CER,X5R,0.01UF,10%,6.3V,01005 TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


PART NUMBER
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

138S0979 CAP,CER,X5R,10UF,20%,10V,0402,H=0.65MM 132S00093 CAP,X5R,0.022UF,20%,6.3V,01005 TABLE_ALT_ITEM

TABLE_ALT_HEAD TABLE_CRITICAL_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

685-00156 685-00155 BOM_TABLE_ALTS SUBBOM_CAP SUBBOM,MLB,TOP,CAP,SOFT,X891


PART NUMBER
138S0692 CAP,CER,X5R,1UF,20%,6.3V,0201 132S00025 CAP,CER,X5R,0.047UF,20%,6.3V,01005
TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

TABLE_ALT_ITEM

138S00139 0201,3uF@1V 138S0683 CAP,CER,X5R,1UF,10%,25V,0402 132S00008 CAP,CER,0.1UF,10%,50V,X7R,0402


138S00138 138S00139 BOM_TABLE_ALTS ALL 0201,3uF@1V, Kyocera
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

TABLE_ALT_ITEM

138S00164 138S00139 BOM_TABLE_ALTS ALL 0201,3uF@1V, Taiyo


138S0652 CAP,CER,X5R,4.7UF,20%,6.3V,H=0.65MM,0402 131S0883 CAP,CER,NP0/C0G,220PF,2%,50V,0201
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

138S00070 CAP,X5R,4.7UF,20%,25V,0402 131S0804 CAP,CER,27PF,5%,C0G,25V,0201


TABLE_ALT_HEAD TABLE_CRITICAL_HEAD

TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
PART NUMBER
138S00014 CAP,CER,1UF,20%,16V,X5R,0201,H=0.39MM 131S0307 CAP,CER,NP0/C0G,100PF,5%,16V,01005
TABLE_CRITICAL_ITEM

TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

TABLE_ALT_ITEM

138S00146 0402,5.1uF@3V 132S0664 CAP,CER,0.047UF,10%,25V,X5R,0201 131S0225 CAP,CER,NP0/C0G,15PF,5%,16V,01005


138S00145 138S00146 BOM_TABLE_ALTS ALL 0402,5.1uF@3V, Kyocera
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

TABLE_ALT_ITEM

138S00165 138S00146 BOM_TABLE_ALTS ALL 0402,5.1uF@3V, Taiyo


132S0663 CAP,CER,X5R,1UF,10%,25V,0402 131S0223 CAP,CER,NP0/C0G,27PF,5%,16V,01005
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

TABLE_ALT_HEAD TABLE_CRITICAL_HEAD
132S0534 CAP,CER,X5R,0.1UF,10%,25V,0201 131S0220 CAP,CER,NP0/C0G,12PF,5%,16V,01005

A PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

PART NUMBER
TABLE_ALT_ITEM

138S00141 0201,1.1uF@3V
TABLE_CRITICAL_ITEM
132S0436 CAP,CER,X5R,0.22UF,20%,6.3V,01005
TABLE_CRITICAL_ITEM
131S0216 CAP,CER,NP0/C0G,47PF,5%,16V,01005
TABLE_CRITICAL_ITEM
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE
138S00140 138S00141 BOM_TABLE_ALTS ALL 0201,1.1uF@3V, Kyocera 132S0396 CAP,CER,X5R,1000PF,10%,10V,01005 131S00053 CAP,CER,C0G,220PF,5%,10V,01005

138S00142 138S00141 BOM_TABLE_ALTS ALL 0201,1.1uF@3V, SEMCO


TABLE_ALT_ITEM

132S0316 CAP,CER,X5R,0.1UF,20%,6.3V,01005
TABLE_CRITICAL_ITEM

118S00068 RES,MF,1.3 MOHM,1%,200PPM,1/20W,0201


TABLE_CRITICAL_ITEM

SYSTEM:BOM Tables
DRAWING NUMBER SIZE
TABLE_ALT_ITEM TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

138S00166 138S00141 BOM_TABLE_ALTS ALL 0201,1.1uF@3V, Taiyo 132S0304 CAP,CER,X5R,0.22UF,20%,6.3V,0201 117S0055 RES,MF,1/20W,2M OHM,5,0201,SMD 051-02221 D
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM Apple Inc. REVISION
132S0296 CAP,CER,X5R,1000PF,10%,6.3V,01005 107S0257 THERMISTOR,NTC,10K OHM,1%,B=3435,01005
TABLE_CRITICAL_ITEM
9.0.0
132S0318 CAP,CER,X5R,820PF,10%,10V,01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
2 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 2 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

FIDUCIALS
FD0401
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY

CL0400 FD0402
2.10R1.60-NSP FID
0P5SQ-CROSS-NSP
D
1
1
ROOM=ASSEMBLY
D
FD0403
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY

FD0404
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY

FD0420
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY

FD0405
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY

FD0410
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY

FD0411
FID
C 0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY
C
FD0412
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY

CRITICAL
SB0400
STDOFF-2.9OD1.4ID-0.77H-SM CL0401
1 2.10R1.60-NSP
1

CRITICAL
SB0402
STDOFF-MLB-TUBE
1

CL0402
2.10R1.60-NSP
1

B B
CRITICAL
1
SH0401
SM

SHLD-EMI-HARD-X891

CL0403
2.10R1.60-NSP
1
CRITICAL

1
SH0400
CRITICAL SM

SB0401
STDOFF-2.9OD1.4ID-0.77H-SM SHIELD-EMI-TOP-X891
1

A A
PAGE TITLE

SYSTEM: Mechanical Components


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
4 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 3 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Test Points Probe Points


POWER SOC Debug Sensors
TP0540
P2MM-NSM PP0500 PP0540 PP0582
PP_ROMEO_DENSE_ANODE SM P2MM-NSM P2MM-NSM P2MM-NSM
1
D
35 34 PP ROOM=TEST
20 6 IN
AP_TO_PMU_TEST_CLKOUT 1
SM
PP 26 12 IN
SPI_AOP_TO_IMU_SCLK 1
SM
PP 41 37 IN
PDM_CODEC_TO_ARC_CLK 1
SM
PP
D
TP0543
P2MM-NSM
ROOM=TEST ROOM=TEST ROOM=TEST

35 34
PP_ROMEO_CATHODE 1
SM
ROOM=TEST
PP0501
P2MM-NSM
PP0541
P2MM-NSM
PP0583
P2MM-NSM
PP
BOARD_ID0 1
SM SPI_AOP_TO_IMU_MOSI 1
SM
PDM_CODEC_TO_ARC_DATA 1
SM
11 5 IN PP 26 12 IN PP 41 37 IN PP
ROOM=TEST ROOM=TEST ROOM=TEST

PP0502
P2MM-NSM
PP0542
P2MM-NSM
32 8
AP_TO_FCAM_SHUTDOWN_L 1
SM
26 12
SPI_IMU_TO_AOP_MISO 1
SM
IN PP IN PP
ROOM=TEST ROOM=TEST
PP0503
P2MM-NSM
SM
8 IN
AP_DEBUG3 1
PP
ROOM=TEST
PP0504
P2MM-NSM
PP0544
P2MM-NSM
PP0586
P2MM-NSM
SM SM SM
11 IN
DFU_STATUS 1
PP 26 12 IN
ACCEL_GYRO_TO_AOP_DATARDY 1
PP 47 10 IN
AP_BI_CCG2_SWDIO 1
PP
ROOM=TEST ROOM=TEST
ROOM=TEST

PP0505 PP0545
P2MM-NSM
PP0587
P2MM-NSM
P2MM-NSM ACCEL_GYRO_TO_AOP_INT SM SM
SM 1 AP_TO_CCG2_SWCLK 1
20 11 6 IN
PMU_TO_AP_PRE_UVLO_L 1
PP
26 12 IN PP 47 10 IN PP
ROOM=TEST ROOM=TEST
ROOM=TEST
PP0546
PP0506
P2MM-NSM COMPASS_TO_AOP_INT
P2MM-NSM
1
SM
SM 49 25 12 IN PP
AP_TO_PMU_SOCHOT_L 1
20 6 IN PP

ROOM=TEST
ROOM=TEST

PP0547
P2MM-NSM
SOC I2C1_AOP PP0590
SOC CPU/GPU 26 12 IN
PHOSPHORUS_TO_AOP_INT 1
SM
PP
ROOM=TEST 50 49 41 25 12 IN I2C1_AOP_SCL
P2MM-NSM
1
SM
PP

C XW0510
ROOM=TEST
C
SHORT-10L-0.05MM-SM PP0591
17 13
PP_GPU 1 2 PP_GPU_LVCC 50
Hydra VBUS PP0550
50 49 41 25 12 IN
I2C1_AOP_SDA
P2MM-NSM
1
SM
PP
ROOM=TEST
XW0511
SHORT-10L-0.05MM-SM
P2MM-NSM
SM
PP_CPU_PCORE 1 2 PP_CPU_PCORE_LVCC 48 23
HYDRA_TO_TIGRIS_VBUS1_VALID_L 1
17 13 50 IN PP
ROOM=TEST

PP0512
P2MM-NSM
20 13 IN
AP_CPU_PCORE_SENSE 1
SM
PP
ROOM=TEST
NAND PP0560
CCG2 PP0592
PP0513
P2MM-NSM P2MM-NSM P2MM-NSM
SM
SM SWD_AP_BI_NAND_SWDIO 1
SM CCG2_TO_SMC_INT_L 1
20 13 IN
AP_VDD_GPU_SENSE 1
PP
16 12 IN PP
47 10 IN PP
ROOM=TEST ROOM=TEST
ROOM=TEST
PP0514 PP0561
P2MM-NSM
P2MM-NSM SM
TP_SOC_SENSE 1
SM
50 16 12 IN
SWD_AOP_TO_MANY_SWCLK 1
PP
13 IN PP
ROOM=TEST
ROOM=TEST
PP0515 PP0562
P2MM-NSM
P2MM-NSM SM
TP_VSS_CPU_SENSE 1
SM
16 10 5 IN
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2 1
PP
15 IN PP
ROOM=TEST
ROOM=TEST
PP0516 PP0563
P2MM-NSM
P2MM-NSM SM
TP_VSS_SENSE 1
SM
16 IN
NAND_ANI1_VREF 1
PP
15 IN PP
ROOM=TEST
ROOM=TEST
PP0564
P2MM-NSM
SM
B NAND_ANI0_VREF 1
B
PMU PP0520
16 IN PP
ROOM=TEST

14 12 IN
AOP_TO_DDR_SLEEP1_READY
P2MM-NSM
1
SM
PP
Rigel
ROOM=TEST PP0570
PP0521
P2MM-NSM CAMPMU_TO_RIGEL_ENABLE
P2MM-NSM
1
SM
SM 34 28 IN PP
20 10 IN
SPMI_PMU_BI_PMGR_SDATA 1
PP ROOM=TEST
ROOM=TEST PP0571
P2MM-NSM
PP0522
P2MM-NSM 34 20 8 IN
RIGEL_TO_ISP_INT 1
SM
PP
SM ROOM=TEST
48 20 6 IN
PMU_TO_AP_HYDRA_ACTIVE_READY 1
PP
ROOM=TEST

PCIE Refclk PP0530


P2MM-NSM
SM
16 7 IN
90_PCIE_AP_TO_NAND_REFCLK_P 1
PP
ROOM=TEST

PP0531
P2MM-NSM
SM
16 7 IN
90_PCIE_AP_TO_NAND_REFCLK_N 1
PP
ROOM=TEST

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

SYSTEM: Testpoints (Top)


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
5 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 4 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

BOOTSTRAPPING:BOARD REV
BOARD ID
BOOT CONFIG
R0623
BOARD_REV3 1
1.00K 2 PP1V8_IO
11 OUT 6 7 8 10 14 16 17 27 28 29 30
32 34 35 43
5%
1/32W
MF
01005
ROOM=SOC

R0622 NOSTUFF
BOARD_REV2 1
1.00K 2
11 OUT
5%
1/32W
MF
01005
ROOM=SOC

R0621
BOARD_REV1 1
1.00K 2
11 OUT

C 5%
1/32W C
MF
01005
ROOM=SOC
SELECTED -->
R0620
BOARD_REV0 1
1.00K 2
11 OUT
5%
1/32W
MF
01005
ROOM=SOC

BOARD_ID4 No connect
11 OUT
CKPLUS_WAIVE=SINGLE_NODENET

On mlb_bot
50 10 OUT
BOARD_ID3
CKPLUS_WAIVE=SINGLE_NODENET

B 11 OUT
PP1V8_IO
MAKE_BASE=TRUE SELECTED -->
B

11 OUT
PP1V8_IO

D221 Baseband Selected on RF Board


No connect
11 4 OUT
BOARD_ID0

SELECTED -->
No connect
16 10 4 OUT
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2

A R0601 SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016


A
SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1 1
4.7K 2
PAGE TITLE
16 10 OUT
1%
BOOTSTRAPPING
1/32W DRAWING NUMBER SIZE
MF
01005 051-02221 D
ROOM=SOC Apple Inc. REVISION
R0600 NOSTUFF 9.0.0
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0 1
4.7K 2
16 10 OUT NOTICE OF PROPRIETARY PROPERTY: BRANCH
1%
1/32W
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
evt-1
MF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
01005
ROOM=SOC I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 5 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SOC - USB, JTAG, XTAL VDD11_XTAL:1.06-1.17V @ 2mA MAX


VDD18_USB: 1.62V - 1.98V @ 20mA MAX
PP1V8_IO 5 7 8 10 14 16 17 27 28 29 30
32 34 35 43

1 C1090
0.1UF
20%
2 6.3V
X5R-CERM
D 01005
ROOM=SOC
D
FL1092
240-OHM-25%-0.20A-0.9DCR
PP1V8_XTAL 1 2
01005
1 C1092 ROOM=SOC
1 C1093
0.1UF 4UF
20%
2 6.3V
20%
2 6.3V
USB Reference
X5R-CERM CER-X5R
01005 0201
ROOM=SOC ROOM=SOC

6
AP_USB_REXT
3.14-3.46V @ 12mA MAX
1
PP3V3_USB 19
R1000
200
1%
1/32W
1 C1095 MF
0.1UF 2 01005
ROOM=SOC
20%
2 6.3V
X5R-CERM
01005
ROOM=SOC

(Analog)
0.765V - 0.84V @ 5mA MAX
PP0V8_SOC_FIXED_S1 7 8 9 13 14 17

VDD18_XTAL AU28

VDD33_USB AN14

VDD_FIXED_USB AN15
VDD18_USB AP14
VDD12_UH1_HSIC0 AT7
C C
OMIT_TABLE

U1000
TMIT78B0-C4
WLCSP
SYM 1 OF 16
ROOM=SOC

BA4 UH1_HSIC0_DATA
CRITICAL
ANALOGMUX_OUT AT27 AP_TO_PMU_AMUX_OUT 20
NC OUT
AY4 UH1_HSIC0_STB
NC

USB_DP AY6 90_USB_AP_DATA_P BI 48


MAKE_BASE=TRUE GND AT8 BA6 90_USB_AP_DATA_N
JTAG_SEL USB_DM BI 48

AV6 JTAG_TRST*
NC
AT9 JTAG_TDO
NC
AT12 JTAG_TDI USB_VBUS AV7 USB_VBUS_DETECT 23
NC IN
48 BI
SWD_DOCK_BI_AP_SWDIO AT10 JTAG_TMS
48
SWD_DOCK_TO_AP_SWCLK AT13 JTAG_TCK USB_ID AW6
IN NC
R1020
1
10K 2 PMU_TO_SYSTEM_COLD_RESET_R_L AU7 COLD_RESET*
5% USB_REXT AU8 AP_USB_REXT
1/32W 48 20 4 IN
PMU_TO_AP_HYDRA_ACTIVE_READY AT34 CFSB
6

MF
PMU_TO_SYSTEM_COLD_RESET_L 01005 AV5 CFSB_AON
20 IN AT22 PMU_TO_AP_THROTTLE_PCORE_L
B 20 4
AP_TO_PMU_TEST_CLKOUT V2 TST_CLKOUT
CPU_TRIGGER0
CPU_TRIGGER1 AW21 PMU_TO_AP_THROTTLE_ECORE_L
IN 20

20
B
OUT IN

16 OUT
AP_TO_NAND_RESET_L AF34 SSD_RESET* GPU_TRIGGER0 AD2 PMU_TO_AP_THROTTLE_GPU0_L IN 20

GPU_TRIGGER1 AD3 PMU_TO_AP_THROTTLE_GPU1_L


16 OUT
AP_TO_NAND_FW_STRAP AG38 SSD_BFH
IN 20

SOCHOT1 A30 AP_TO_PMU_SOCHOT_L


MAKE_BASE=TRUE GND W5 HOLD_RESET
OUT 4 20

DROOP B31 PMU_TO_AP_PRE_UVLO_L


GND W4 TESTMODE
IN 4 11 20

WDOG AW5 AP_TO_PMU_WDOG_RESET OUT 20

XI0 BA28 XTAL_AP_24M_IN


XO0 BA27 XTAL_AP_24M_OUT NOSTUFF
1
R1010 ROOM=SOC
511K
1%
1/32W
Y1000
1.60X1.20MM-SM
MF
2 01005
R1011 24.000MHZ-30PPM-9.5PF-60OHM
ROOM=SOC
1
1.00K 2 SOC_24M_O 1 3
5%
1/32W 2 4
MF
01005
1 C1010 1 C1011
ROOM=SOC
12PF 12PF
5% 5%
2 16V
CERM 2 16V
CERM
01005
ROOM=SOC
01005
ROOM=SOC

A SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016
A
PAGE TITLE

SOC: JTAG,USB,XTAL
DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
10 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 6 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SOC - PCIE INTERFACES

D
(Analog)
VDD12_PCIE_REFBUF:1.08V - 1.26V @ 30mA MAX D
R1198 1.62V - 1.98V @ 81mA MAX
PP1V2_SOC 1
0.00 2 PP1V2_SOC_PCIE_REFBUF PP1V8_IO
19 14 13 9 5 6 7 8 10 14 16 17 27 28 29
30 32 34 35 43
0%
PCIe BB CLKREQ PU on BB domain 1/32W
MF
1 C1198 1 C1199
01005 0.1UF 4UF
PCIe Clock Request Pull-Ups ROOM=SOC
20%
2 6.3V
20%
2 6.3V
(Analog)
X5R-CERM CER-X5R VDD_FIXED_PCIE_REFBUF:0.765V - 0.84V @ 9mA MAX
29 28 27 17 16 14 10 8 7 6 5
PP1V8_IO 01005 0201
43 35 34 32 30 ROOM=SOC ROOM=SOC
VDD_FIXED_PCIE_ANA:0.765V - 0.84V @ 131mA MAX
R1100 1 R1130 1 PP0V8_SOC_FIXED_S1 6 8 9 13 14 17
100K 100K
5% 5%
1/32W
MF
1/32W
MF R1194
1 C1193 1 C1192 1 C1191
01005 2 01005 2 0.00 0.1UF 1.0UF 4UF
ROOM=SOC ROOM=SOC PP0V8_SOC_FIXED_PCIE_REFBUF 1 2
20% 20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R 2 6.3V
CER-X5R
PCIE_NAND_BI_AP_CLKREQ_L 0% 01005 0201-1 0201
16 7 1 C1194 1/32W

VDD18_PCIE AM29
VDD18_PCIE AM31

VDD_FIXED_PCIE_REFBUF AM27
VDD12_PCIE_REFBUF AN26

VDD_FIXED_PCIE_ANA AN30
VDD12_PCIE_REFBUF AP26

VDD_FIXED_PCIE_ANA AP29
VDD_FIXED_PCIE_ANA AP31

VDD_FIXED_PCIE_REFBUF AP27
ROOM=SOC ROOM=SOC ROOM=SOC
PCIE_WLAN_BI_AP_CLKREQ_L MF
50 7 0.1UF 01005
20% ROOM=SOC
2 6.3V
X5R-CERM
01005
ROOM=SOC

PCIe Reset Pull-Downs


50 7 PCIE_AP_TO_WLAN_RESET_L
50 7 PCIE_AP_TO_BB_RESET_L
16 7 PCIE_AP_TO_NAND_RESET_L
R1101 1 R1121 1 R1131 1
100K 100K 100K
5% 5% 5%
1/32W 1/32W 1/32W
MF MF MF ROOM=SOC
01005 2 01005 2 01005 2
U1000
C ROOM=SOC ROOM=SOC ROOM=SOC

TMIT78B0-C4 C
WLCSP
SYM 2 OF 16

16 7 PCIE_NAND_BI_AP_CLKREQ_L AL38 PCIE_CLKREQ0* PCIE_CLKREQ3* AJ36 PCIE_WLAN_BI_AP_CLKREQ_L 7 50


BI BI

16 4 90_PCIE_AP_TO_NAND_REFCLK_P AW27 PCIE_REF_CLK0_P PCIE_REF_CLK3_P AY24 90_PCIE_AP_TO_WLAN_REFCLK_P 50


OUT OUT
16 4 90_PCIE_AP_TO_NAND_REFCLK_N AV27 PCIE_REF_CLK0_N PCIE_REF_CLK3_N BA24 90_PCIE_AP_TO_WLAN_REFCLK_N 50
OUT OUT

PCIE LINK 3
0.22UF 2 1 C1100 C1130 1 2
0.1UF
6.3V 20% GND_VOID
AV29 BA36 90_PCIE_WLAN_TO_AP_RXD_C_P GND_VOID 20% 6.3V 90_PCIE_WLAN_TO_AP_RXD_P
16 IN
90_PCIE_NAND_TO_AP_RXD_P 01005 X5R 90_PCIE_NAND_TO_AP_RXD_C_P PCIE_RX0_P PCIE_RX3_P X5R-CERM 01005 IN 50

16 IN
90_PCIE_NAND_TO_AP_RXD_N ROOM=SOC
90_PCIE_NAND_TO_AP_RXD_C_N AW29 PCIE_RX0_N PCIE_RX3_N AY36 90_PCIE_WLAN_TO_AP_RXD_C_N ROOM=SOC
90_PCIE_WLAN_TO_AP_RXD_N IN 50
2 1 C1101 C1131 1 2
PCIE LINK 0

0.22UF 0.1UF
6.3V 20% GND_VOID GND_VOID 20% 6.3V
01005 X5R X5R-CERM 01005
ROOM=SOC ROOM=SOC

0.22UF 2 1 C1102 C1132 1 2


0.1UF
6.3V 20% GND_VOID
AY30 AV35 90_PCIE_AP_TO_WLAN_TXD_C_P GND_VOID 20% 6.3V 90_PCIE_AP_TO_WLAN_TXD_P
16 OUT
90_PCIE_AP_TO_NAND_TXD_P 01005 X5R 90_PCIE_AP_TO_NAND_TXD_C_P PCIE_TX0_P PCIE_TX3_P X5R-CERM 01005 OUT 50

16 OUT
90_PCIE_AP_TO_NAND_TXD_N ROOM=SOC
90_PCIE_AP_TO_NAND_TXD_C_N BA30 PCIE_TX0_N PCIE_TX3_N AW35 90_PCIE_AP_TO_WLAN_TXD_C_N ROOM=SOC
90_PCIE_AP_TO_WLAN_TXD_N OUT 50
0.22UF 2 1 C1103 AJ37 AH36 PCIE_AP_TO_WLAN_RESET_L C1133 1 2
0.1UF
6.3V 20% GND_VOID 16 7 OUT
PCIE_AP_TO_NAND_RESET_L PCIE_PERST0* PCIE_PERST3* OUT 7 50 GND_VOID 20% 6.3V
01005 X5R X5R-CERM 01005
ROOM=SOC ROOM=SOC

LINK0 LINK3
90_PCIE_AP_TO_BB_REFCLK_P 50
OUT
90_PCIE_AP_TO_BB_REFCLK_N 50
OUT

1 C1124 1 C1125
AL37 AK37 PCIE_BB_BI_AP_CLKREQ_L 4.7PF 4.7PF
B NC PCIE_CLKREQ1* PCIE_CLKREQ2* BI 50
+/-0.1PF
2 16V
+/-0.1PF
2 16V
B
AW26 PCIE_REF_CLK1_P PCIE_REF_CLK2_P AV25 NP0-C0G NP0-C0G
NC 01005 01005
AY26 PCIE_REF_CLK1_N PCIE_REF_CLK2_N AW25 ROOM=SOC ROOM=SOC
NC

PCIE LINK 2
C1120 1 2 0.1UF
AV31 BA34 90_PCIE_BB_TO_AP_RXD_C_P GND_VOID 20% 6.3V 90_PCIE_BB_TO_AP_RXD_P
NC PCIE_RX1_P PCIE_RX2_P X5R-CERM 01005 IN 50
AW31 PCIE_RX1_N PCIE_RX2_N AY34 90_PCIE_BB_TO_AP_RXD_C_N ROOM=SOC 90_PCIE_BB_TO_AP_RXD_N 50
NC IN
C1121 1 2 0.1UF
GND_VOID 20% 6.3V
X5R-CERM 01005
ROOM=SOC

C1122 1 2 0.1UF
AY32 AV33 90_PCIE_AP_TO_BB_TXD_C_P GND_VOID 20% 6.3V
NC PCIE_TX1_P PCIE_TX2_P X5R-CERM 01005 90_PCIE_AP_TO_BB_TXD_P OUT 50
BA32 PCIE_TX1_N PCIE_TX2_N AW33 90_PCIE_AP_TO_BB_TXD_C_N ROOM=SOC
90_PCIE_AP_TO_BB_TXD_N 50
NC OUT

AK38 AJ38 PCIE_AP_TO_BB_RESET_L C1123 1 2 0.1UF


NC PCIE_PERST1* PCIE_PERST2* OUT 7 50 GND_VOID 20% 6.3V
X5R-CERM 01005
LINK1 LINK2 ROOM=SOC

AU30 PCIE_EXT_REF_CLK_P
AT30 PCIE_EXT_REF_CLK_N

PCIE_REXT AU32 AP_PCIE_RCAL


1
A R1150
1%
200 SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016
A
PAGE TITLE
1/32W
MF
2 01005ROOM=SOC SOC: PCIE
DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
11 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 7 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SOC - MIPI & ISP INTERFACES ISP I2C0


29 28 27 17 16 14 10 8 7 6 5
PP1V8_IO
43 35 34 32 30

1 1
R1201 R1202
1.00K 1.00K
5% 5%
1/32W 1/32W
MF MF
(Analog) 2 01005 2 01005
MIPI Lane & Polarity Swapping 0.765V - 0.84V @ 40mA MAX 1.62V - 1.98V @ 10mA MAX
ROOM=SOC ROOM=SOC

17 14 13 9 7 6
PP0V8_SOC_FIXED_S1 PP1V8_IO 5 6 7 8 10 14 16 17 27 28 29 30
29 8 I2C0_ISP_SCL
32 34 35 43
8 I2C0_ISP_SDA

D C1290 1 C1291 1 1 C1295 1 C1296


29
D
0.1UF 2.2UF 2.2UF 0.1UF
20% 20% 20% 20%
6.3V 6.3V 2 6.3V 2 6.3V
X5R-CERM 2 X5R-CERM 2 X5R-CERM X5R-CERM
01005
ROOM=SOC
0201
ROOM=SOC
0201
ROOM=SOC
01005
ROOM=SOC
ISP I2C1

G12
G14
PP1V8_IO

F11
F13
29 28 27 17 16 14 10 8 7 6 5
43 35 34 32 30

1 1
R1211 R1212

VDD_FIXED_MIPI

VDD18_MIPI
1.00K 1.00K
5% 5%
1/32W 1/32W
MF MF
2 01005
ROOM=SOC
2 01005
ROOM=SOC

30 8 I2C1_ISP_SCL
8 I2C1_ISP_SDA
U1000 30

TMIT78B0-C4
WLCSP
SYM 3 OF 16
90_MIPI_JULIET_TO_AP_DATA0_P 90_MIPI_JULIET_TO_AP_DATA0_P I2C0_ISP_SCL
35

35
BI
90_MIPI_JULIET_TO_AP_DATA0_N
MAKE_BASE
MAKE_BASE 90_MIPI_JULIET_TO_AP_DATA0_N
B12
A12
MIPI0C_DPDATA0
MIPI0C_DNDATA0
ROOM=SOC
ISP_I2C0_SCL
ISP_I2C0_SDA
W35
V38 I2C0_ISP_SDA
OUT 8 29

8 29
ISP I2C2
BI BI
Juliet MIPI

PP1V8_IO
29 28 27 17 16 14 10 8 7 6 5
35 IN
90_MIPI_JULIET_TO_AP_DATA1_P MAKE_BASE 90_MIPI_JULIET_TO_AP_DATA1_P B14 MIPI0C_DPDATA1 ISP_I2C1_SCL W36 I2C1_ISP_SCL OUT 8 30
43 35 34 32 30

1 1
35 IN
90_MIPI_JULIET_TO_AP_DATA1_N MAKE_BASE 90_MIPI_JULIET_TO_AP_DATA1_N A14 MIPI0C_DNDATA1 ISP_I2C1_SDA Y36 I2C1_ISP_SDA BI 8 30 R1221 R1222
1.00K 1.00K
5% 5%
35 IN
90_MIPI_JULIET_TO_AP_CLK_N MAKE_BASE 90_MIPI_JULIET_TO_AP_CLK_N A13 MIPI0C_DPCLK ISP_I2C2_SCL Y34 I2C2_ISP_SCL OUT 8 32
1/32W 1/32W
MF MF
35 IN
90_MIPI_JULIET_TO_AP_CLK_P MAKE_BASE 90_MIPI_JULIET_TO_AP_CLK_P B13 MIPI0C_DNCLK ISP_I2C2_SDA Y38 I2C2_ISP_SDA BI 8 32 2 01005 2 01005
ROOM=SOC ROOM=SOC

MIPI0C_REXT D12 MIPI0C_REXT


C 8

8 MIPI1C_REXT
D13 MIPI1C_REXT
ISP_I2C3_SCL AA37
AB38
I2C3_ISP_SCL
I2C3_ISP_SDA
OUT 8 28 31 34 35
32 8 I2C2_ISP_SCL C
ISP_I2C3_SDA BI 8 28 31 34 35
32 8 I2C2_ISP_SDA

32
90_MIPI_FCAM_TO_AP_DATA0_N MAKE_BASE 90_MIPI_FCAM_TO_AP_DATA0_N B17 MIPI1C_DPDATA0
BI
32 BI
90_MIPI_FCAM_TO_AP_DATA0_P MAKE_BASE 90_MIPI_FCAM_TO_AP_DATA0_P A17 MIPI1C_DNDATA0 R1240
33.2 AP_TO_WIDE_CLK
ISP I2C3
FCAM MIPI

1 2 OUT 29

32
90_MIPI_FCAM_TO_AP_DATA1_N MAKE_BASE 90_MIPI_FCAM_TO_AP_DATA1_N B15 MIPI1C_DPDATA1 SENSOR_INT AB36 RIGEL_TO_ISP_INT 4 20 34 1%
IN IN
1/32W
32 IN
90_MIPI_FCAM_TO_AP_DATA1_P MAKE_BASE 90_MIPI_FCAM_TO_AP_DATA1_P A15 MIPI1C_DNDATA1 MF PP1V8_IO
01005 29 28 27 17 16 14 10 8 7 6 5
43 35 34 32 30
ROOM=SOC
1 1
32 IN
90_MIPI_FCAM_TO_AP_CLK_P MAKE_BASE 90_MIPI_FCAM_TO_AP_CLK_P A16 MIPI1C_DPCLK
SENSOR0_CLK U38 AP_TO_WIDE_CLK_R R1241 R1231 R1232
90_MIPI_FCAM_TO_AP_CLK_N MAKE_BASE 90_MIPI_FCAM_TO_AP_CLK_N B16 MIPI1C_DNCLK 33.2 1.00K 1.00K
32 IN
SENSOR1_CLK R38 AP_TO_TELE_CLK_R 1 2 AP_TO_TELE_CLK OUT 30
5% 5%
1/32W 1/32W
43 BI
90_MIPI_AP_TO_DISPLAY_DATA0_P A10 MIPID_DPDATA0 SENSOR2_CLK R37 AP_TO_FCAM_JULIET_RIGEL_CLK_R 1% MF MF
90_MIPI_AP_TO_DISPLAY_DATA0_N B10
1/32W 2 01005 2 01005
43 BI MIPID_DNDATA0 MF ROOM=SOC ROOM=SOC
01005
ROOM=SOC
90_MIPI_AP_TO_DISPLAY_DATA1_P 90_MIPI_AP_TO_DISPLAY_DATA1_P B9 I2C3_ISP_SCL
43 OUT
90_MIPI_AP_TO_DISPLAY_DATA1_N
MAKE_BASE
90_MIPI_AP_TO_DISPLAY_DATA1_N A9
MIPID_DPDATA1
V34 AP_TO_JULIET_SHUTDOWN_L
R1242 35 34 31 28 8

8 I2C3_ISP_SDA
43 OUT MAKE_BASE MIPID_DNDATA1 SENSOR0_RST OUT 35
1
33.2 2 AP_TO_FCAM_JULIET_CLK
35 34 31 28
Display MIPI

SENSOR1_RST U35 AP_TO_TELE_SHUTDOWN_L OUT 30


OUT 32 35

1%
43 OUT
90_MIPI_AP_TO_DISPLAY_DATA3_P MAKE_BASE 90_MIPI_AP_TO_DISPLAY_DATA3_P A7 MIPID_DPDATA2 SENSOR2_RST AB34 AP_TO_WIDE_SHUTDOWN_L OUT 29 1/32W
MF
43
90_MIPI_AP_TO_DISPLAY_DATA3_N MAKE_BASE 90_MIPI_AP_TO_DISPLAY_DATA3_N B7 MIPID_DNDATA2 SENSOR3_RST AC37 01005
OUT NC AP_TO_FCAM_SHUTDOWN_L ROOM=SOC
SENSOR4_RST AA35 4 32
OUT
43 OUT
90_MIPI_AP_TO_DISPLAY_DATA2_N MAKE_BASE 90_MIPI_AP_TO_DISPLAY_DATA2_N A6 MIPID_DPDATA3 R1243
90_MIPI_AP_TO_DISPLAY_DATA2_P 90_MIPI_AP_TO_DISPLAY_DATA2_P B6 1
33.2 2 AP_TO_RIGEL_CLK
43 OUT MAKE_BASE MIPID_DNDATA3 OUT 34

1%
AP_DEBUG3 1/32W
43 OUT
90_MIPI_AP_TO_DISPLAY_CLK_N MAKE_BASE 90_MIPI_AP_TO_DISPLAY_CLK_N A8 MIPID_DPCLK SENSOR0_ISTRB V36
OUT 4 MF
01005
43
90_MIPI_AP_TO_DISPLAY_CLK_P MAKE_BASE 90_MIPI_AP_TO_DISPLAY_CLK_P B8 MIPID_DNCLK SENSOR1_ISTRB U36 ROOM=SOC
OUT NC

AP_TO_MANY_BSYNC AA3 U37


B 50 28 21 20 12

43
OUT
DISPLAY_TO_AP_ALIVE AB4
DISP_TOUCH_BSYNC0
DISP_TOUCH_BSYNC1
SENSOR0_XSHUTDOWN
SENSOR1_XSHUTDOWN T37
NC
ISP_TO_DISPLAY_FLASH_INT 43
B
IN OUT

AB6 DISP_TOUCH_EB
NC

8
MIPID_REXT D11 MIPID_REXT

AA4 DISP_I2C_SCL
NC
AA5 DISP_I2C_SDA
NC

Y4 DISP_POL
NC

MIPI Reference
MIPI0C_REXT 8
MIPI1C_REXT 8
MIPID_REXT 8
A A
R12501 R12511 R12521
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

PAGE TITLE
200 200 200
1%
1/32W
1%
1/32W
1%
1/32W
SOC: MIPI & ISP
MF MF MF DRAWING NUMBER SIZE
01005 2 01005 2 01005 2
ROOM=SOC ROOM=SOC ROOM=SOC 051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
12 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 8 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SOC - LPDP
(Analog)
VDD_FIXED_PLL_LPDP 0.765V - 0.84V @ 3mA MAX
VDD12_PLL_LPDP 1.14V - 1.26V @ 10mA MAX VDD_FIXED_LPDP_TX 0.765V - 0.84V @ 16mA MAX
VDD12_LPDP 1.14V - 1.26V @ 72mA MAX VDD_FIXED_LPDP_RX 0.765V - 0.84V @ 30mA MAX
PP1V2_SOC PP0V8_SOC_FIXED_S1
19 14 13 7 6 7 8 9 13 14 17

1 C1390 1 C1391 1 C1392 1 C1393 1 C1394 1 C1395 1 C1396 D


D 20%
2.2UF
20%
2.2UF
20%
0.1UF 0.01UF
10% 5%
15PF 2.2UF
20%
2.2UF
20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R 2 16V
NP0-C0G-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201 0201 01005 01005 01005 0201
ROOM=SOC
0201
ROOM=SOC
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC

Desense for Wifi frequencies

G16
G18
F15
F17
F16
VDD12_LPDP_TX M9

VDD_FIXED_PLL_LPDP R9

VDD_FIXED_LPDP_TX P9
VDD12_PLL_LPDP T9
VDD12_LPDP_RX

VDD_FIXED_LPDP_RX
29
90_LPDP_WIDE_TO_AP_D0_P A26 LPDPRX_RX_D0_P LPDP_TX0P M3
IN NC
90_LPDP_WIDE_TO_AP_D0_N B26 LPDPRX_RX_D0_N LPDP_TX0N M4
29 IN
U1000 NC
TMIT78B0-C4
WLCSP
SYM 4 OF 16
29
90_LPDP_WIDE_TO_AP_D1_P A25 LPDPRX_RX_D1_P LPDP_TX1P L4
IN NC
C 29 IN
90_LPDP_WIDE_TO_AP_D1_N B25 LPDPRX_RX_D1_N LPDP_TX1N L5
NC C

29
90_LPDP_WIDE_TO_AP_D2_P A24 LPDPRX_RX_D2_P LPDP_TX2P K3
IN NC
29
90_LPDP_WIDE_TO_AP_D2_N B24 LPDPRX_RX_D2_N LPDP_TX2N K4
IN NC

30
90_LPDP_TELE_TO_AP_D0_P A21 LPDPRX_RX_D3_P LPDP_TX3P J4
IN NC
30
90_LPDP_TELE_TO_AP_D0_N B21 LPDPRX_RX_D3_N LPDP_TX3N J5
IN NC

30 IN
90_LPDP_TELE_TO_AP_D1_P A20 LPDPRX_RX_D4_P
30 IN
90_LPDP_TELE_TO_AP_D1_N B20 LPDPRX_RX_D4_N

30
90_LPDP_TELE_TO_AP_D2_P A19 LPDPRX_RX_D5_P LPDP_AUX_P G4
IN NC
30
90_LPDP_TELE_TO_AP_D2_N B19 LPDPRX_RX_D5_N LPDP_AUX_N G5
IN NC

LPDP_CAL_DRV_OUT H3
NC
LPDP_CAL_VSS_EXT H6
NC
29 BI
LPDP_WIDE_BI_AP_AUX D21 LPDPRX_AUX_D0_P
D20 LPDPRX_AUX_D1_P EDP_HPD Y6
NC NC
D19 Y2
B 30
LPDP_TELE_BI_AP_AUX
NC
D17
LPDPRX_AUX_D2_P
LPDPRX_AUX_D3_P
DP_WAKEUP NC B
BI
D16 LPDPRX_AUX_D4_P
NC
D15 LPDPRX_AUX_D5_P
NC

MAKE_BASE=TRUE GND A22 LPDPRX_BYP_CLK_P


GND B22 LPDPRX_BYP_CLK_N

17 14 13 9 8 7 6
PP0V8_SOC_FIXED_S1 B23 LPDPRX_RCAL_P

R1300 1
300
1%
1/32W
MF
01005-1 2
ROOM=SOC AP_LPDPRX_RCAL_NEG A23 LPDPRX_RCAL_N

C1301 1
100PF D18 LPDPRX_EXT_C
5% NC
16V
NP0-C0G 2
01005
ROOM=SOC

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

SOC: LPDP
DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
13 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 9 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SOC - SERIAL INTERFACES 29 28 27 17 16 14 10 8 7 6 5


43 35 34 32 30
AP I2C0
PP1V8_IO

R1400 1 R1401 1
2.2K 2.2K
5% 5%
1/32W 1/32W
MF MF
01005 2 01005 2
ROOM=SOC ROOM=SOC

49 46 20 10
I2C0_AP_SCL
49 46 20 10
I2C0_AP_SDA

D D
AP I2C1
PP1V8_IO
R1460 29 28 27 17 16 14 10 8 7 6 5
43 35 34 32 30

I2S_AP_TO_CODEC_MCLK1 33.2 I2S_AP_TO_CODEC_MCLK1_R AV23 AG3 I2C0_AP_SCL


38 OUT
1 2
I2S_AP_TO_CODEC_ASP3_BCLK AW23
I2S0_MCK
U1000 I2C0_SCL
AG2 I2C0_AP_SDA
OUT 10 20 46 49 R1410 1 R1411 1
1% 38 OUT I2S0_BCLK I2C0_SDA BI 10 20 46 49 2.2K 2.2K
1/32W
I2S_AP_TO_CODEC_ASP3_LRCLK AT24 TMIT78B0-C4 5% 5%
MF 38 OUT I2S0_LRCK WLCSP 1/32W 1/32W
01005 MF MF
ROOM=SOC 38 IN
I2S_CODEC_ASP3_TO_AP_DIN AT25 I2S0_DIN I2C1_SCL AD38 I2C1_AP_SCL OUT 10 33 49 01005 01005
I2S_AP_TO_CODEC_ASP3_DOUT SYM 6 OF 16 I2C1_AP_SDA ROOM=SOC 2 ROOM=SOC 2
38 AT26 I2S0_DOUT I2C1_SDA AD36 10 33 49
OUT BI
ROOM=SOC I2C1_AP_SCL
49 33 10

I2C2_SCL A34 I2C2_AP_SCL OUT 10 50 49 33 10


I2C1_AP_SDA
AH34 I2S1_MCK I2C2_SDA B34 I2C2_AP_SDA 10 50
NC BI
AG36
NC
NC
AG35
I2S1_BCLK
I2S1_LRCK I2C3_SCL AC36 I2C3_AP_SCL OUT 10 42 50
AP I2C2
AH38 I2S1_DIN I2C3_SDA AC38 I2C3_AP_SDA 10 42 50 29 28 27 17 16 14 10 8 7 6 5
PP1V8_IO
NC BI 43 35 34 32 30
AG37 I2S1_DOUT
NC
SMC_I2CM0_SCL AY16 I2C0_SMC_SCL OUT 10 21 22 23 47 50
R1420 1 R1421 1
R1464 AW16 I2C0_SMC_SDA 2.2K 2.2K
SMC_I2CM0_SDA BI 10 21 22 23 47 50 5% 5%
I2S_AP_TO_SPKRAMP_TOP_MCLK 1
33.2 2 I2S_AP_TO_SPKRAMP_TOP_MCLK_R AT35 1/32W 1/32W
50 OUT I2S2_MCK MF MF
AT36 AT20 I2C1_SMC_SCL 01005 2 01005 2
1%
NC I2S2_BCLK SMC_I2CM1_SCL OUT 10 48 ROOM=SOC ROOM=SOC
1/32W
MF AP_BI_CCG2_SWDIO AR36 I2S2_LRCK SMC_I2CM1_SDA AU20 I2C1_SMC_SDA
01005
47 4 BI IN 10 48
I2C2_AP_SCL
ROOM=SOC AP_TO_CCG2_SWCLK AR34 I2S2_DIN
50 10
47 4 OUT I2C2_AP_SDA
38 IN
CODEC_TO_AP_INT_L AR35 I2S2_DOUT SMC_UART0_RXD AW19 CCG2_TO_SMC_INT_L IN 4 47
50 10

SMC_UART0_TXD AW15 IKTARA_TO_SMC_INT IN 50

AG4 AL6
AP I2C3
NC I2S3_MCK SEP_SPI0_SCLK NC PP1V8_IO
I2S_BB_TO_AP_BCLK AG5 I2S3_BCLK SEP_SPI0_MISO AM5 29 28 27 17 16 14 10 8 7 6 5

C 50

50
OUT

OUT
I2S_BB_TO_AP_LRCLK AH2 I2S3_LRCK SEP_SPI0_MOSI AM4
NC
PMU_TO_SEP_DOUBLE_CLICK_DET IN 20
43 35 34 32 30

R1430 1 R1431 1 C
50 IN
I2S_BB_TO_AP_DIN AH6 I2S3_DIN 2.2K 2.2K
I2S_AP_TO_BB_DOUT AH4 5% 5%
50 OUT I2S3_DOUT 1/32W 1/32W
AL2 CKPLUS_WAIVE=I2C_PULLUP I2C4_AP_SCL MF MF
SEP_I2C_SCL 10 01005 01005
I2C4_AP_SDA ROOM=SOC 2 ROOM=SOC 2
SEP_I2C_SDA AM3 CKPLUS_WAIVE=I2C_PULLUP 10

50 42 10
I2C3_AP_SCL
I2C3_AP_SDA
16 5 4 IN
SPI_S4E_TO_AP_MISO_BOOT_CONFIG2 AV22 SPI0_MISO
50 42 10

R1465 SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1 BA21 SPI0_MOSI


16 5 OUT
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0 1
0.00 2
16 5 OUT
SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0_R BA22 SPI0_SCLK SMC I2C
0% BOARD_ID3 AU22 SPI0_SSIN
1/32W
50 5 IN
48 47 46 38 22 20 17 14 12 10
PP1V8_S2
MF 50 49
01005
ROOM=SOC
SPI_RACER_TO_AP_MISO AU23 R1482 R1440 1 R1441 1
50 IN SPI1_MISO 2.2K 2.2K
R1461 SPI_AP_TO_RACER_MOSI AY22 AV21 SPMI_PMGR_TO_PMU_SCLK_R 1
0.00 2 SPMI_PMGR_TO_PMU_SCLK 5% 5%
50 OUT SPI1_MOSI SPMI_SCLK OUT 20 1/32W 1/32W
SPI_AP_TO_RACER_SCLK 1
0.00 2 SPI_AP_TO_RACER_SCLK_R AW22 AW20 SPMI_PMU_BI_PMGR_SDATA MF MF
50 OUT SPI1_SCLK SPMI_SDATA BI 4 20 0% 01005 2 01005 2
1/32W ROOM=SOC ROOM=SOC
0% 50 OUT
SPI_AP_TO_RACER_CS_L AT23 SPI1_SSIN MF
1/32W 01005
MF ROOM=SOC 50 47 23 22 21 10
I2C0_SMC_SCL
01005 DWI_CLK AE36
ROOM=SOC NC 50 47 23 22 21 10
I2C0_SMC_SDA
DWI_DO AF36
38 IN
SPI_CODEC_TO_AP_MISO AE4 SPI2_MISO NC
R1462 38 OUT
SPI_AP_TO_CODEC_MOSI AE2 SPI2_MOSI PP1V8_S2
SPI_AP_TO_CODEC_SCLK 1
0.00 2 SPI_AP_TO_CODEC_SCLK_R AD5 48 47 46 38 22 20 17 14 12 10
38 OUT SPI2_SCLK 50 49

0% 38 OUT
SPI_AP_TO_CODEC_CS_L AE6 SPI2_SSIN R1481 R1450 1 R1451 1
1/32W 0.00 AP_TO_RACER_REF_CLK
MF
01005
1 2 OUT 50 4.7K 4.7K
5% 5%
ROOM=SOC 0% 1/32W 1/32W
1/32W MF MF
AE38 SPI3_MISO MF 01005 2 01005 2
NC CLK24M_OUT AV19 AP_TO_RACER_REF_CLK_R 01005 ROOM=SOC ROOM=SOC
AE35
B NC
AF38
SPI3_MOSI
SPI3_SCLK AP_TO_NAND_SYS_CLK_R
ROOM=SOC
48 10
I2C1_SMC_SCL B
NC NAND_SYS_CLK BA20
AE37 SPI3_SSIN 48 10
I2C1_SMC_SDA
NC
R1480
1
0.00 2 AP_TO_NAND_SYS_CLK
SPI: Route as Daisy-Chain. No T's Allowed 0%
OUT 16
AP I2C4
1/32W
MF 29 28 27 17 16 14 10 8 7 6 5
PP1V8_IO
Place series terminations close to SoC Pins 01005 43 35 34 32 30
ROOM=SOC
R1470 1 R1471 1
4.7K 4.7K
5% 5%
1/32W 1/32W
MF MF
01005 01005 2
ROOM=SOC 2 ROOM=SOC

10
I2C4_AP_SCL
10
I2C4_AP_SDA

29 28 27 17 16 14 10 8 7 6 5
PP1V8_IO
43 35 34 32 30

C1490
A1

1
0.47UF VCC
20%
2 6.3V
X5R
01005
ROOM=SOC U1490
B1 SCL WLCSP SDA A2 I2C4_AP_SDA
A OMIT_TABLE I2C4_AP_SCL
10

10 SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016
A
PAGE TITLE
VSS
TABLE_5_HEAD
ROOM=SOC
CRITICAL
SOC: Serial
B2

DRAWING NUMBER SIZE


PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
051-02221 D
Apple Inc.
TABLE_5_ITEM

335S00234 1 WLCSP U1490 CRITICAL COMMON REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


TABLE_ALT_HEAD

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
PART NUMBER
THE POSESSOR AGREES TO THE FOLLOWING: PAGE

335S00233 335S00234 BOM_TABLE_ALTS U1490 U1490


TABLE_ALT_ITEM

I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
14 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 10 OF 51
8 7 6 5 4 3 2 . 1
8 7 6 5 4 3 2 1

D D

SOC - GPIO INTERFACES


U1000
TMIT78B0-C4
WLCSP
SYM 5 OF 16 NOSTUFF
AP_TO_DISPLAY_RESET_L AL4 ROOM=SOC
43 OUT
T35
GPIO_0
TMR32_PWM0 D28 PMU_TO_AP_PRE_UVLO_L IN 4 6 20
R1500
NC GPIO_1 C30 JULIET_PMU_TO_RIGEL_STROBE_R 1
200K 2 JULIET_PMU_TO_RIGEL_STROBE
AP_TO_CAMPMU_RESET_L R36 TMR32_PWM1 OUT 34 35
28 OUT GPIO_2 A28 WLAN_TO_AP_TIME_SYNC
AP_TO_NFC_DEV_WAKE P38 TMR32_PWM2 IN 50 1%
50 OUT GPIO_3 1/32W
MF
AP_TO_BB_COREDUMP R35 GPIO_4 01005
50 OUT
UART0_RXD AF3 UART_AP_DEBUG_RXD ROOM=SOC
AP_TO_BB_RESET_L N37 GPIO_5
IN 48
50 OUT
UART0_TXD AF2 UART_AP_DEBUG_TXD 48
L37 GPIO_6
OUT
NC
AP_TO_BB_IPC_GPIO1 K38 GPIO_7
50 OUT
UART1_CTS* P34 UART_BT_TO_AP_CTS_L 50
K34 GPIO_8
IN
NC UART1_RTS* L36 UART_AP_TO_BT_RTS_L
CAMPMU_TO_AP_IRQ_L L35 GPIO_9
OUT 50
28 IN
UART1_RXD P36 UART_BT_TO_AP_RXD
AP_TO_GNSS_WAKE D33 GPIO_10
IN 50
50 OUT
UART1_TXD M37 UART_AP_TO_BT_TXD 50
C34 GPIO_11
OUT
NC
AP_TO_BT_WAKE D32 GPIO_12
C 50

50
OUT

OUT
AP_TO_SPKRAMP_TOP_RESET_L D29 GPIO_13
UART2_CTS* B28
B29
UART_GNSS_TO_AP_CTS_L
UART_AP_TO_GNSS_RTS_L
IN 50 C
B33 UART2_RTS* OUT 50
NC GPIO_14 C28 UART_GNSS_TO_AP_RXD
AP_TO_NFC_FW_DWLD_REQ A32 UART2_RXD IN 50
50 OUT GPIO_15 B30 UART_AP_TO_GNSS_TXD
P6 UART2_TXD OUT 50
NC GPIO_16
AP_TO_RACER_RESET_L P4 GPIO_17
50 OUT
UART3_CTS* D30 UART_NFC_TO_AP_CTS_L
BOARD_ID0 R4 GPIO_18
IN 50
5 4 IN
UART3_RTS* B32 UART_AP_TO_NFC_RTS_L
SPKRAMP_TOP_TO_AP_INT_L R3 GPIO_19
OUT 50
50 IN
UART3_RXD C32 UART_NFC_TO_AP_RXD
PMU_TO_AP_BUTTON_VOL_UP_L R2 GPIO_20
IN 50
20 IN
UART3_TXD D31 UART_AP_TO_NFC_TXD
50 OUT
AP_TO_BBPMU_RADIO_ON_L T5 GPIO_21
OUT 50

AP_TO_WLAN_DEVICE_WAKE T4 GPIO_22
50 OUT
UART4_CTS* K36 UART_WLAN_TO_AP_CTS_L 50
T3 GPIO_23
IN
NC UART4_RTS* M35 UART_AP_TO_WLAN_RTS_L 50
T2 GPIO_24
OUT
NC UART4_RXD N36 UART_WLAN_TO_AP_RXD
PP1V8_IO U6 GPIO_25
IN 50
5 IN
UART4_TXD N35 UART_AP_TO_WLAN_TXD
50 48 20 IN
PMU_HYDRA_TO_AP_FORCE_DFU U4 GPIO_26
OUT 50

DFU_STATUS U2 GPIO_27
4 OUT
UART6_RXD AF5 UART_ACCESSORY_TO_AP_RXD
PP1V8_IO V5 GPIO_28
IN 48
5 IN
UART6_TXD AF4 UART_AP_TO_ACCESSORY_TXD
5 IN
BOARD_ID4 V4 GPIO_29
OUT 48

20
AP_TO_PMU_AMUX_SYNC V3 GPIO_30
IN
UART7_RXD R5
50
AP_TO_BB_TIME_MARK AJ3 GPIO_31 NC
OUT
UART7_TXD P2
50 IN
BB_TO_AP_RESET_DETECT_L AJ4 GPIO_32 NC
AJ5 GPIO_33
NC
5 IN
BOARD_REV3 AJ6 GPIO_34
5 IN
BOARD_REV2 AK3 GPIO_35
5 IN
BOARD_REV1 AK4 GPIO_36
5 IN
BOARD_REV0 AK5 GPIO_37

B B
20 IN
PMU_TO_AP_BUTTON_POWER_KEY_L AB2 REQUEST_DFU1
20 IN
PMU_TO_AP_BUTTON_VOL_DOWN_L AC4 REQUEST_DFU2

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

SOC: GPIO & UART


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
15 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 11 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SOC - AOP 1.8V @ 15mA MAX


48 47 46 38 22 20 17 14 12 10
50 49
PP1V8_S2
1 C1690 1 C1691
4UF 0.1UF
20% 20%
2 6.3V
CER-X5R 2 6.3V
X5R-CERM
0201 01005

D
ROOM=SOC ROOM=SOC
D

AP13
AP15
AP17
AP19
VDDIO18_AOP
VDDIO18_AOP
VDDIO18_AOP
VDDIO18_AOP
AOP_TO_DDR_SLEEP1_READY AT11 AON_DDR_RESET*
14 4 OUT
U1000
AU14 TMIT78B0-C4
NC AOP_FUNC_0 WLCSP
AU13 AOP_FUNC_1 SYM 7 OF 16
NC AOP_PDM_CLK0 BA16 CODEC_TO_AOP_GPIO1
ACCEL_GYRO_TO_AOP_DATARDY AW10 AOP_FUNC_2
ROOM=SOC IN 38
26 4 BI
AOP_PDM_DATA0 AW18 CODEC_TO_AOP_GPIO2
SPI_AOP_TO_ACCEL_GYRO_CS_L AW11 IN 38

AOP I2C Pull-Ups 26

26 4
IN

OUT
ACCEL_GYRO_TO_AOP_INT AT16
AOP_FUNC_3
AOP_FUNC_4 SPI SCM
AOP_PDM_DATA1 AW17
NC
PP1V8_S2 10 12 14 17 20 22 38 46 47 48 26 IN
SPI_AOP_TO_PHOSPHORUS_CS_L AV11 AOP_FUNC_5 RT_CLK32768 BA18 PMU_TO_AOP_CLK32K IN 20
49 50
PHOSPHORUS_TO_AOP_INT AY10 AOP_FUNC_6
1
R1620 1
R1621 1
R1622 1
R1623
26 4 OUT
AOP_SWD_TCK_OUT AV20 SWD_AOP_TO_MANY_SWCLK
35 IN
ROMEO_TO_AOP_B2B_DETECT AV12 AOP_FUNC_7
OUT 4 16 50

1.00K 1.00K 1.00K 1.00K RACER_TO_AOP_INT_L AY11


5% 5% 5% 5% 50 IN AOP_FUNC_8 AY17 SWD_AOP_BI_RACER_SWDIO
1/32W 1/32W 1/32W 1/32W AOP_TO_CODEC_RESET_L AU16 AOP_SWD_TMS0 BI 50
MF MF MF MF 38 OUT AOP_FUNC_9 AT21 SWD_AOP_BI_BB_SWDIO
2 01005 2 01005 2 01005 2 01005 AP_TO_MANY_BSYNC AV16 AOP_SWD_TMS1 BI 50
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC 50 28 21 20 8 IN AOP_FUNC_10 AC5 SWD_AP_BI_NAND_SWDIO
AT17 SWD_TMS2 BI 4 16
I2C1_AOP_SCL NC AOP_FUNC_11 AC2
4 12 25 41 49 50
PMU_TO_AOP_IRQ_L AV13 SWD_TMS3 NC
I2C1_AOP_SDA 20 OUT AOP_FUNC_12
4 12 25 41 49 50
AOP_TO_SPKRAMP_BOT_ARC_RESET_L AW12 AOP_FUNC_13
I2C0_AOP_SCL 50 41 IN
AOP_I2CM0_SCL BA9 I2C0_AOP_SCL
12 36
SPKRAMP_BOT_ARC_TO_AOP_INT_L AV14 AOP_FUNC_14 OUT 12 36
I2C0_AOP_SDA 50 41 OUT
AOP_I2CM0_SDA AV9 I2C0_AOP_SDA
12 36
38 OUT
AOP_TO_CODEC_CLP_EN AW13 AOP_FUNC_15 AOP_PDM_CLK4 BI 12 36

49 41 38 OUT
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT AU17 AOP_FUNC_16 AOP_I2CM1_SCL AV10 I2C1_AOP_SCL OUT 4 12 25 41 49 50

C 36 IN
PROX_BI_AP_AOP_INT_L AV15
AY13
AOP_FUNC_17
I2C0 SCM
AOP_I2CM1_SDA AW9 I2C1_AOP_SDA BI 4 12 25 41 49 50 C
NC AOP_FUNC_18
50 IN
HALL3_TO_AOP_IRQ_L BA11 AOP_FUNC_19
36 IN
ALS_TO_AOP_INT_L AV17 AOP_FUNC_20
R1603 NC
BA10 AOP_FUNC_21
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK 1
49.9 2 COMPASS_TO_AOP_INT AT18
50 49 41 38 IN 49 25 4 IN AOP_FUNC_22 I2C1 SCM
1% 50 IN
HALL2_TO_AOP_IRQ_L AW14 AOP_FUNC_23
1/32W
MF I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_R AV18 AOP_FUNC_24
01005
ROOM=SOC
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_R BA12 AOP_FUNC_25
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN AY14
R1604 50 41 38 IN AOP_FUNC_26
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK 1
49.9 2
50 49 41 38 IN
1%
1/32W
MF
01005
ROOM=SOC
26 4 IN
SPI_IMU_TO_AOP_MISO AW7 AOP_SPI_MISO
R1601 26 4 OUT
SPI_AOP_TO_IMU_MOSI AU10 AOP_SPI_MOSI
SPI_AOP_TO_IMU_SCLK 1
49.9 2 SPI_AOP_TO_IMU_SCLK_R AV8
26 4 OUT AOP_SPI_SCLK
1%
1/32W
MF 50 IN
UART_BB_TO_AOP_RXD AT14 AOP_UART0_RXD DOCK_ATTENTION BA17 HYDRA_TO_NUB_INT IN 48
01005
UART_AOP_TO_BB_TXD AY8 AOP_UART0_TXD
ROOM=SOC 50 OUT
DOCK_CONNECT AY19 HYDRA_TO_NUB_DOCK_CONNECT IN 48

50 OUT
AOP_TO_WLAN_CONTEXT_A BA8 AOP_UART1_RXD
50 OUT
AOP_TO_WLAN_CONTEXT_B AW8 AOP_UART1_TXD

50 IN
UART_RACER_TO_AOP_RXD AU11 AOP_UART2_RXD
50 OUT
UART_AOP_TO_RACER_TXD AT15 AOP_UART2_TXD

I2S_AOP_TO_CODEC_ASP2_BCLK BA14
B R1602
38

38
OUT
I2S_CODEC_ASP2_TO_AOP_DIN AT19
AOP_I2S0_BCLK
AOP_I2S0_DIN
B
IN
I2S_AOP_TO_CODEC_MCLK2 1
33.2 2 I2S_AOP_TO_CODEC_MCLK2_R AU19
38 OUT AOP_I2S0_MCK
1% 38 OUT
I2S_AOP_TO_CODEC_ASP2_LRCLK BA15 AOP_I2S0_LRCK
1/32W
MF
01005 38 OUT
I2S_AOP_TO_CODEC_ASP2_DOUT BA13 AOP_I2S0_DOUT
ROOM=SOC

A SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016
A
PAGE TITLE

SOC: AOP
DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
16 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 12 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SOC - CPU, GPU & SOC RAILS


1.06V @ 11.0A MAX
0.8V @ 6A MAX
0.575V @ 2.7A MAX
17 4
PP_CPU_PCORE
C1702 1 C1703 OMIT
1.06V @ 18.3A MAX
4UF 4UF 0.8V @ 10.6A MAX 0.765V @ 4.9A MAX
20%
2 4V
20%
2 4V
XW1701
SHORT-20L-0.05MM-SM 0.575V @ 3.4A MAX 0.635V @ 2.6A MAX
X5R X5R
0201 0201 2 1 BUCK0_FB
ROOM=SOC ROOM=SOC OUT 17
PP_GPU PP_SOC_S1
D ROOM=SOC
OMIT
4 17

OMIT
17
D
1
1 C1730 1 C1731 XW1731
1 C1760 1 C1761 XW1760
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC 4UF 4UF SHORT-20L-0.05MM-SM
4UF 4UF SHORT-20L-0.05MM-SM
20% 20% 20% 20%
C1704 C1705 C1706 C1707 2 4V
X5R 2 4V
X5R
1
ROOM=SOC
2 BUCK1_FB OUT 17 2 4V
X5R 2 4V
X5R
1 2 BUCK2_FB OUT 17

14UF 14UF 14UF 14UF 0201


ROOM=SOC
0201
ROOM=SOC
0201 0201 ROOM=SOC
20% 20% 20% 20% AA14 F25 NO_XNET_CONNECTION ROOM=SOC ROOM=SOC NO_XNET_CONNECTION
4V
X5R
4V
X5R
4V
X5R
4V
X5R AA16 U1000 J16
0402-D2X-1 0402-D2X-1 0402-D2X-1 0402-D2X-1 AB11 TMIT78B0-C4 F31
1 3 1 3 1 3 1 3 WLCSP
AB13 G20 ROOM=SOC ROOM=SOC ROOM=SOC
SYM 8 OF 16
2 4 2 4 2 4 2 4 AB15
ROOM=SOC G22 C1762 C1763 C1764
AB17 G24 14UF 14UF 14UF
AB19 G26 20% 20% 20%
4V 4V 4V
AC20 J28 X5R X5R X5R
0402-D2X-1 0402-D2X-1 0402-D2X-1
AD15 H11 1 3 1 3 1 3
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC AE14 H15
C1708 C1709 C1710 C1711 C1712 C1713 AF20
VDD_CPU
H19
ROOM=SOC
C1732
ROOM=SOC
C1733
ROOM=SOC
C1734
ROOM=SOC
C1735
ROOM=SOC
C1736 2 4 2 4 2 4
14UF 14UF 14UF 14UF 14UF 14UF AG9 H23
20% 20% 20% 20% 20% 20% 14UF 14UF 14UF 14UF 14UF
4V 4V 4V 4V 4V 4V AG15 H31 20% 20% 20% 20% 20%
X5R X5R X5R X5R X5R X5R 4V 4V 4V 4V 4V
0402-D2X-1 0402-D2X-1 0402-D2X-1 0402-D2X-1 0402-D2X-1 0402-D2X-1 AH10 J12 X5R X5R X5R X5R X5R
1 3 1 3 1 3 1 3 1 3 1 3 0402-D2X-1 0402-D2X-1 0402-D2X-1 0402-D2X-1 0402-D2X-1
AH12 J18 1 3 1 3 1 3 1 3 1 3
VDD_GPU AA9 G13
2 4 2 4 2 4 2 4 2 4 2 4 AH14 J22
2 4 2 4 2 4 2 4 2 4 AA18 U1000 J20
AH16 J24 TMIT78B0-C4
AA22 L19
AH18 J26 WLCSP
AA24 M13
AH20 J30 SYM 9 OF 16
AA28 M15
L16 ROOM=SOC
ROOM=SOC ROOM=SOC ROOM=SOC
AA30 M21
K17
K29 C1737 C1738 C1739 AB21 N10
14UF 14UF 14UF AB25 N12
C L12
L18
20%
4V
20%
4V
20%
4V AB27 N16 C
X5R X5R X5R AC22 N18
L22 0402-D2X-1 0402-D2X-1 0402-D2X-1
1 3 1 3 1 3 AC24 N29
L28
AC28 P13
M23 2 4 2 4 2 4 AC30 P15
0.7V @ 75mA MAX L24
AD9 P19
N22
19
PP0V7_VDD_LOW_S2 AD21 P21
N24
OMIT AD25 P25
1 C1750 N28
XW1790 AD27 P27
4UF SHORT-20L-0.05MM-SM
20% AD29 R10
2 6.3V 2 1 BUCK11_FB OUT 18 20
CER-X5R AE22 R12
0201
ROOM=SOC AM15 ROOM=SOC
AE24 R16
1.01V @ 2.1A MAX AM17 1.06V @ 4.3A MAX
AE28 R18
0.735V @ 0.6A MAX AM19 0.8V @ 2.8A MAX
AF25 R22
AM21 0.575V @ 1.4A MAX
17
PP_CPU_SRAM VDD_LOW
PP_CPU_ECORE AF27 R24
AN16 18
ROOM=SOC ROOM=SOC
AG22 R28
AN18
C1772 C1773 AN20
ROOM=SOC
C1791
ROOM=SOC
C1792
ROOM=SOC
C1793
1 C1794 AG24 T13
14UF 14UF 4UF AG28 T15
20% 20% 14UF 14UF 14UF 20%
4V 4V 20% 20% 20% 2 4V AH25 VDD_SOC T19
X5R X5R AA12 AA10 4V 4V 4V X5R
0402-D2X-1 0402-D2X-1 X5R X5R X5R 0201
ROOM=SOC
AH27 T21
1 3 AB18 U10 0402-D2X-1 0402-D2X-1 0402-D2X-1
1 3 1 3 1 3 AJ16 T25
AC9 U12 1 3
VDD_CPU_SRAM VDD_ECPU AJ18 T27
2 4 AC14 V13
2 4 2 4 2 4 2 4 AJ22 U16
AE20 V15
AJ24 U18
AF14 Y13
AJ28 U22
1.06V @ 1.1A MAX U14 Y15
(Analog) AK13 U24
B 0.80V @ 0.63A MAX
0.675V @ 0.19A MAX
20 4 OUT
AP_CPU_PCORE_SENSE AH21 VDD_CPU_SENSE 0.8V @ 6mA MAX
0.8V @ 6mA MAX
AK15 U28 B
AK19 U30
0.8V @ 10mA MAX
PP_GPU_SRAM AK21 V19
17
PP0V8_SOC_FIXED_S1 6 7 8 9 14 17
ROOM=SOC ROOM=SOC
AK25 V21
N26
C1781 C1782 H13
AK27 V25
14UF 14UF AL12 V27
20% 20% H17
4V 4V VDD_FIXED_CPU W14 AL16 W18
X5R X5R H21
0402-D2X-1 0402-D2X-1 (Analog) AL18 W22
1 3 H25 VDD_FIXED_PLL_GPU K21
1 3 1.2V @ 7mA MAX (CPU) AL22 W24
K11 VDD_FIXED_PLL_SOC L20
1.2V @ 7mA MAX (GPU) AL24 W28
2 4 K19 1.2V @ 20mA MAX (SOC)
2 4 VDD_GPU_SRAM AL28 W30
K23 VDD12_PLL_CPU W16 PP1V2_SOC 7 9 14 19
AL30 Y19
G30 VDD12_PLL_GPU L21
M29 VDD12_PLL_SOC M20
1 C1720 1 C1721 1 C1722 1 C1723 AM13 Y25
0.1UF 0.1UF 0.1UF 4UF AM25 Y21
20% 20% 20% 20%
20 4 OUT
AP_VDD_GPU_SENSE N23 VDD_GPU_SENSE 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
CER-X5R
AN12 Y27
01005 01005 01005 0201 AN22 P23
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
VDD_SOC_SENSE TP_SOC_SENSE 4
AN24 OUT

F22

A SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016
A
PAGE TITLE

SOC: Power (1/3)


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
17 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 13 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SOC - POWER SUPPLIES


DDR IMPEDANCE CONTROL
18 14
PP0V6_VDDQL_S1
0.6V @ 262mA MAX
18 14
PP0V6_VDDQL_S1
1 1 1 1 1 1
R1860 R1861 R1862 R1863 R1870 R1871
D 1 C1830 1 C1831 1 C1832 1 C1833 1%
240
1%
240
1%
240
1%
240
1%
240
1%
240 D
4UF 4UF 4UF 4UF 1/32W 1/32W 1/32W 1/32W 1/32W 1/32W
20% 20% 20% 20% MF MF MF MF MF MF
2 4V
X5R 2 4V
X5R 2 4V
X5R 2 4V
X5R 01005
2ROOM=SOC 2 01005 01005
2ROOM=SOC 01005
2ROOM=SOC 01005
2ROOM=SOC 01005
2ROOM=SOC
0201 0201 0201 0201 ROOM=SOC
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
AD1 DDR0_RREF AP5 DDR0_RREF
Place caps on SoC Corners AF1 U1000 DDR1_RREF AN35 DDR1_RREF
AH1 TMIT78B0-C4 E5 DDR2_RREF
WLCSP DDR2_RREF
0.8V @ 0.9A MAX AK9 VDDQL_DDR0 H35 DDR3_RREF
DDR3_RREF
PP0V8_SOC_FIXED_S1 AP9 SYM 11 OF 16
9 8 7 6
17 14 13
AT1 ROOM=SOC
ROOM=SOC
C1801 AV1
14UF AA20 V17
20% AOP_TO_DDR_SLEEP1_READY
4V
X5R AA26 U1000 V23 DDR0_RET* AR5
IN 4 12

0402-D2X-1 TMIT78B0-C4 DDR1_RET* AM35


1 3 AB9 V29
WLCSP AD39 DDR2_RET* E3
AB23 W20
SYM 10 OF 16 AF31 DDR3_RET* G35
2 4 AB29 W26
ROOM=SOC AF39
AC26 Y9
AK31 VDDQL_DDR1
AD23 Y17
AP39
AD31 Y23 PP1V2_LPADC 19 DDR0_ZQ
AT39 DDR0_ZQ AJ2
AE26 Y29
1 C1870 AV39 DDR3_ZQ N38 DDR3_ZQ
1 C1802 1 C1803 1 C1804 1 C1805 AF23
2.2UF OMIT
4UF 4UF 4UF 4UF AF29 20%
20%
2 4V
20%
2 4V
20%
2 4V
20%
2 4V AG26 LPADC_REF_P BA19 2 6.3V
X5R-CERM XW1870
SHORT-20L-0.05MM-SM
X5R X5R X5R X5R 0201
0201 0201 0201 0201 AH23 LPADC_REF_M AY20 ROOM=SOC LPADC_GND 1 2
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC D1 DDR0_SYS_ALIVE AP6 SYSTEM_ALIVE 16 20 23
AH29 ROOM=SOC
IN
(Analog) F1 DDR1_SYS_ALIVE AM34
AJ14 0.8V @ 8mA MAX F9 DDR2_SYS_ALIVE E4
C AJ20
AJ26
VDD_FIXED_PLL_DDR0 AK11
AJ29
PP0V8_SOC_FIXED_S1 6 7 8 9 13 14 17
H1
VDDQL_DDR2 DDR3_SYS_ALIVE H34 C
VDD_FIXED_PLL_DDR1 K9
AK17 VDD_FIXED_PLL_DDR2 D8
T1
AK23 VDD_FIXED_PLL_DDR3 R29
V1
AL14
C4
AL20 VDDQL Voltage Sense -> NC 1.8V @ 200mA MAX
AL26
AB3 PP1V8_S2 10 12 14 17 20 22 38 46 47 48
AM11 49 50
AB37
AM23 VDD_FIXED
D39 AW3
1 C1840 1 C1841 1 C1842 1 C1843
AP11 2.2UF 2.2UF 2.2UF 2.2UF
F39 AW37 20% 20% 20% 20%
AP21 2 6.3V 2 6.3V 2 6.3V 2 6.3V
K31 VDD1 B3 X5R-CERM X5R-CERM X5R-CERM X5R-CERM
AP24 0201 0201 0201 0201
P31 B37 ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
F19 VDDQL_DDR3
P39 Y3
F23
T39 Y37
M11
V39
M17 AA2
N14 AA38
N20 1.06V - 1.17V @ (Inc in VDD2) AC39
P11 AH39
42 19 17 14
PP1V1_S2 AR6 VDDIO11_RET_DDR0
P17 AJ1
AN34 VDDIO11_RET_DDR1
P29 AK39
E6 VDDIO11_RET_DDR2
R14 AM1
(Analog) G34 VDDIO11_RET_DDR3
R20 1.2V @ 16mA MAX AN39
R26 AP1
19 13 9 7
PP1V2_SOC AJ11 VDDIO12_PLL_DDR0
T11 AV2 1.06V - 1.17V @2.2A MAX
AK29 VDDIO12_PLL_DDR1
T17 AV37
0.875V @ 0.8A MAX D9 VDDIO12_PLL_DDR2 PP1V1_S2 14 17 19 42
T23 VDD2 AW2
B T31 0.730V @ 0.51A MAX T29 VDDIO12_PLL_DDR3 AW38 1 C1850 1 C1851 1 C1852 1 C1853 B
U20 0.600V @ 0.35A MAX C2 4UF 4UF 4UF 4UF
20% 20% 20% 20%
U26 17
PP_DCS_S1 AJ10 C3 2 4V 2 4V 2 4V 2 4V
X5R X5R X5R X5R
AP10 VDD_DCS_DDR0 C38 0201 0201 0201 0201
1 C1860 1 C1861 1 C1862 1 C1863 D38 ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
4UF 4UF 4UF 4UF
20% 20% 20% 20% AE30 H39
2 4V
X5R 2 4V
X5R 2 4V
X5R 2 4V
X5R AK30 VDD_DCS_DDR1 J1
0201
ROOM=SOC
0201
ROOM=SOC
0201
ROOM=SOC
0201
ROOM=SOC K39
F10 M1
Place caps on SoC Corners L10 N39
VDD_DCS_DDR2
A4 P1
U1000 DCS Voltage Sense -> NC
1.8V @ 5.3mA MAX (CPU) W1
TMIT78B0-C4 1.8V @ 1.1mA MAX (GPU) K30
1.8V @ 60mA MAX WLCSP 1.8V @ 3.3mA MAX (SOC)
SYM 12 OF 16
R30 VDD_DCS_DDR3
34 32
27 17
8 7 6 5
PP1V8_IO AP23 ROOM=SOC VDD18_TSADC_CPU0 T12 PP1V8_IO 5 6 7 8 10 14 16 17 27 28 29 30
16 14 10 32 34 35 43
30 29 28 AP25 VDDIO18_GRP1 VDD18_TSADC_CPU1 AF21
43 35 1 C1810 1 C1811 1 C1812 1 C1813 VDD18_TSADC_CPU2 AJ9
26UF 4UF 4UF 4UF
20% 20% 20% 20% VDD18_TSADC_CPU3 Y16
2 4V 2 6.3V 2 6.3V 2 6.3V AB31
X5R CER-X5R CER-X5R CER-X5R
0402-0.1MM 0201 0201 0201 V31 VDDIO18_GRP2 VDD18_TSADC_GPU0 G21
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
Y31
VDD18_TSADC_SOC0 AJ12
F21 VDD18_TSADC_SOC1 AD30
D23 VDDIO18_GRP3 VDD18_TSADC_SOC2 J31

VDD18_EFUSE1 H12
AF9 AT6 1.8V @ 1mA MAX
VDD18_EFUSE2
A V9 VDDIO18_GRP4 VDD18_FMON AN13 PP1V8_IO 5 6 7 8 10 14 16 17 27 28 29 30
32 34 35 43
R1880 1.8V
300
@ 1mA MAX SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016
A
VDD18_LPOSC AN19 PP1V8_LPOSC_S2 1 2 PP1V8_S2 10 12 14 17 20 22 38 46 47 48
PAGE TITLE
49 50

1 C1880 1 C1881 5%
1/32W
SOC: Power (2/3)
MF DRAWING NUMBER SIZE
56PF 0.47UF 01005
5%
2 25V
20%
2 6.3V
ROOM=SOC 051-02221 D
NP0-C0G-CERM
01005
X5R
01005
Apple Inc. REVISION
ROOM=SOC ROOM=SOC
9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
18 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 14 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

SOC - POWER SUPPLIES


A1 AE29 AL34 AU29 BA39 G2 M19 U21
A2 U1000 AE31 AL35 U1000 AU3 C1 U1000 G3 M2 U1000 U23
A3 TMIT78B0-C4 AE34 AL36 TMIT78B0-C4 AU4 C5 TMIT78B0-C4 G6 M5 TMIT78B0-C4 U25
WLCSP WLCSP WLCSP WLCSP
A5 AE39 AL39 AU5 C6 G11 M6 U27
A11 SYM 13 OF 16 AF6 AM2 SYM 14 OF 16 AU6 C7 SYM 15 OF 16 G15 M22 SYM 16 OF 16 U29
ROOM=SOC ROOM=SOC ROOM=SOC ROOM=SOC
D A18 AF15 AM6 AU9 C8 G17 M24 U31 D
A27 AF22 AM12 AU31 C9 G19 M28 U34
A29 AF24 AM14 AU33 C10 G23 M34 U39
A31 AF26 AM16 AU34 C11 G25 M36 V6
A33 AF28 AM18 AU35 C12 G31 M38 V14
A35 AF30 AM20 AU36 C13 G36 M39 V16
A36 AF35 AM22 AU37 C14 G37 N1 V18
A37 AF37 AM24 AU38 C15 G38 N2 V20
A38 AG1 AM26 AU39 C16 G39 N3 V22
A39 AG6 AM28 AV3 C17 H2 N4 V24
AA1 AG14 AM30 AV4 C18 H4 N5 V26
AA6 AG20 AM36 AV24 C19 H5 N6 V28
AA11 AG23 AM37 AV26 C20 H14 N9 V30
AA13 AG25 AM38 AV28 C21 H16 N11 V35
AA15 AG27 AM39 AV30 C22 H18 N13 V37
AA17 AG29 AN1 AV32 C23 H20 N15 W2
AA19 AG34 AN2 AV34 C24 H22 N17 W3
AA21 AG39 AN3 AV36 C25 H24 N19 W6
AA23 AH3 AN4 AV38 C26 H26 N21 W9
AA25 AH5 AN5 AW1 C27 H30 N25 W13
AA27 AH9 AN6 AW4 C29 H36 N27 W15
AA29 AH11 AN11 AW24 C31 H37 N34 W17
AA31 AH13 AN17 AW28 C33 H38 P3 W19
AA34 AH15 AN21 AW30 C35 J2 P5 W21
AA36 AH17 AN23 AW32 C36 J3 P10 W23
AA39 AH19 AN25 AW34 C37 J6 P12 W25
AB1 AH22 AN29 AW36 C39 J11 P14 W27
C AB5 AH24 AN31 AW39 D10 J17 P16 W29 C
AB10 AH26 AN36 AY1 D14 J19 P18 W31
AB12 AH28 AN37 AY2 D2 J21 P20 W34
AB14 AH35 AN38 AY3 D3 J23 P22 W37
AB16 AH37 AP2 AY5 D4 J25 P26 W38
AB20 AJ13 AP3 AY7 D5 J27 P28 W39
AB22 VSS VSS AJ15 AP4 VSS VSS AY9 D6 VSS VSS J29 P30 VSS Y1
AB24 AJ17 AP12 AY12 D7 J34 P35 Y5
AB26 AJ19 AP16 AY15 D22 J35 P37 Y14
AB28 AJ21 AP18 AY18 D24 J36 R1 Y18
AB30 AJ23 AP20 AY21 D25 J37 R6 Y20
AB35 AJ25 AP22 AY23 D26 J38 R11 Y22
AB39 AJ27 AP28 AY25 D27 J39 R13 Y24
AC1 AJ34 AP34 AY27 D34 K1 R15 Y26
AC3 AJ35 AP35 AY28 D35 K2 R17 Y28
AC6 AJ39 AP36 AY29 D36 K5 R19 Y30
AC15 AK1 AP37 AY31 D37 K6 R21 Y35
AC21 AK2 AP38 AY33 E1 K10 R23 Y39
AC23 AK6 AR1 AY35 E2 K12 R25
VSS_CPU_SENSE AG21 TP_VSS_CPU_SENSE 4
AC25 AK10 AR2 AY37 E34 K16 R27 OUT

AC27 AK12 AR3 AY38 E35 K18 R31 VSS_SENSE P24 TP_VSS_SENSE OUT 4
AC29 AK14 AR4 AY39 E36 K20 R34
AC31 AK16 AR37 B1 E37 K22 R39
AC34 AK18 AR38 B2 E38 K24 T6
AC35 AK20 AR39 B4 E39 K28 T10
NC <- DDR Vss V Sense
AD4 AK22 AT2 B5 F12 K35 T14
B AD6 AK24 AT3 B11 F14 K37 T16 B
AD14 AK26 AT4 B18 F18 L1 T18
AD20 AK28 AT5 B27 F2 L2 T20
AD22 AK34 AT28 B35 F3 L3 T22
AD24 AK35 AT29 B36 F4 L6 T24
AD26 AK36 AT31 B38 F5 L9 T26
AD28 AL1 AT32 B39 F6 L11 T28
AD34 AL3 AT33 BA1 F20 L17 T30
AD35 AL5 AT37 BA2 F24 L23 T34
AD37 AL11 AT38 BA3 F26 L29 T36
AE1 AL13 AU1 BA5 F30 L34 T38
AE3 AL15 AU2 BA7 F34 L38 U1
AE5 AL17 AU12 BA23 F35 L39 U3
AE9 AL19 AU15 BA25 F36 M10 U5
AE15 AL21 AU18 BA26 F37 M12 U9
AE21 AL23 AU21 BA29 F38 M14 U11
AE23 AL25 AU24 BA31 G1 M16 U13
AE25 AL27 AU25 BA33 M18 U15
AE27 AL29 AU26 BA35 U17
AL31 AU27 BA37 U19
BA38

A SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016
A
PAGE TITLE

SOC: Power (3/3)


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
19 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 15 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

391mA MAX
28 27 17 16 14 10 8 7 6 5
43 35 34 32 30 29
PP1V8_IO
S4E NAND
1 C2626 1 C2610
4UF 0.1UF
20% 20%
2 4V
X5R 2 6.3V
X5R-CERM
0201
ROOM=NAND
01005
ROOM=NAND

D D
1 C2629 1 C2630
18UF 18UF
20% 20%
2 6.3V
CER-X5R 2 6.3V
CER-X5R
0402-0.1MM
ROOM=NAND
0402-0.1MM
ROOM=NAND

1 C2624 1 C2641 1 C2643 1 C2645 1 C2647


4UF 4UF 4UF 4UF 4UF
20% 20% 20% 20% 20%
2 4V
X5R 2 4V
X5R 2 4V
X5R 2 4V
X5R 2 4V
X5R
0201 0201 0201 0201 0201
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND

1 C2611 1 C2617 1 C2623 1 C2612


220PF 100PF 68PF 47PF
5% 5% 5% 5%
2 10V
C0G-CERM 2 16V
NP0-C0G
6.3V
2 NP0-C0G 2 16V
CERM
01005 01005 01005 01005
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND

932mA MAX
19
PP0V9_NAND
1 C2602 1 C2605 1 C2600 1 C2601
26UF 26UF 4UF 4UF
20% 20% 20% 20%
2 4V
X5R 2 4V
X5R 2 4V
X5R 2 4V
X5R
0402-0.1MM 0402-0.1MM 0201 0201
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
C 1100mA MAX (1us peak power) C
PP3V0_NAND 19

1 C2622 1 C2627 1 C2640 1 C2642 1 C2644 1 C2646


1 C2613 1 C2616 1 C2619 1 C2621
18UF 18UF 18UF 18UF
4UF 4UF 4UF 4UF 4UF 4UF 20% 20% 20% 20%
20% 20% 20% 20% 20% 20% 2 6.3V 2 6.3V 2 6.3V 2 6.3V
2 4V
X5R 2 4V
X5R 2 4V
X5R 2 4V
X5R 2 4V
X5R 2 4V
X5R
CER-X5R
0402-0.1MM
CER-X5R
0402-0.1MM
CER-X5R
0402-0.1MM
CER-X5R
0402-0.1MM
0201 0201 0201 0201 0201 0201 ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND

1 C2603 1 C2606 1 C2609 1 C2614 1 C2620 1 C2628 1 C2649 1 C2650 1 C2651 1 C2652
220PF 220PF 100PF 68PF 47PF 22PF 4UF 4UF 4UF 4UF
5% 5% 5% 5% 5% 5% 20% 20% 20% 20%
2 10V
C0G-CERM 2 10V
C0G-CERM 2 16V
NP0-C0G
6.3V
2 NP0-C0G 2 16V
CERM 2 16V
CERM 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 2 6.3V
CERM-X5R
01005 01005 01005 01005 01005 01005 0201
ROOM=NAND
0201
ROOM=NAND
0201
ROOM=NAND
0201
ROOM=NAND
ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND ROOM=NAND

1 C2615 1 C2618 1 C2631 1 C2632 1 C2634 1 C2635 1 C2636 1 C2637


22PF 47PF 68PF 100PF 220PF 220PF 220PF 100PF
5% 5% 5% 5% 5% 5% 5% 5%
16V
2 CERM 2 16V 2 6.3V 2 16V 2 10V 2 10V 2 10V 2 16V
CERM NP0-C0G NP0-C0G C0G-CERM C0G-CERM C0G-CERM NP0-C0G
4 OUT
NAND_ANI1_VREF 01005
ROOM=NAND
01005
ROOM=NAND
01005
ROOM=NAND
01005
ROOM=NAND
01005
ROOM=NAND
01005
ROOM=NAND
01005 01005
ROOM=NAND ROOM=NAND
4 OUT
NAND_ANI0_VREF
NC

ANI0_VREF G12

E10

E12

L12
PCI_AVDD_CLK_2 M9

G6
G8

G4
PCI_AVDD_CLK_1 N6

PCI_VDD_1 N8

R6
R8

N2

D3

R2

VDD_PLL R4
E2

K9

P9
T5

VPP F3
AVDD18_PLL L2

L6
L8
PCI_AVDD_H J6

PCI_VDD_2 J8

ANI1_VREF J4

J2
VDD

VDDIO

VCC
B B

U2600
THGBX7G8D2LLFXG
10 IN
AP_TO_NAND_SYS_CLK M3 CLK_IN WFLGA EXT_D0/BOOT0 B3 PMU_TO_NAND_LOW_BATT_BOOT_L IN 20
ROOM=NAND EXT_D1/BOOT1 C4 AP_TO_NAND_FW_STRAP
90_PCIE_AP_TO_NAND_REFCLK_P K11 PCIE_REFCLK_P BOMOPTION=OMIT_TABLE IN 6
7 4 IN
CRITICAL EXT_D2/BOOT2/SPINAND_SCLK B5 SPI_AP_TO_S4E_SCLK_BOOT_CONFIG0
90_PCIE_AP_TO_NAND_REFCLK_N J12 PCIE_REFCLK_M IN 5 10
7 4 IN
EXT_D3/SWD_UID0/SPINAND_MISO C6 SPI_S4E_TO_AP_MISO_BOOT_CONFIG2 OUT 4 5 10

7
PCIE_NAND_BI_AP_CLKREQ_L P5 PCIE_CLKREQ_N EXT_D4/UART_RX B7
BI NC
EXT_D5/SWD_UID1/SPINAND_MOSI C8 SPI_AP_TO_S4E_MOSI_BOOT_CONFIG1
PCIE_NAND_RESREF H7 PCI_RESREF
IN 5 10

EXT_D6/UART_TX B9
NC
1
R2604 7 IN
90_PCIE_AP_TO_NAND_TXD_P M11 PCIE_RX0_P EXT_D7/SPF B11 SYSTEM_ALIVE IN 14 20 23

3.01K 90_PCIE_AP_TO_NAND_TXD_N N12 PCIE_RX0_M


1%
7 IN
EXT_NCE/PERST* E8 PCIE_AP_TO_NAND_RESET_L IN 7
1/32W
MF SWD_AP_BI_NAND_SWDIO
2 01005 EXT_NRE/JTAG_TMS D7 BI 4 12
ROOM=NAND
EXT_NWE/JTAG_TCK E6 SWD_AOP_TO_MANY_SWCLK
7 OUT
90_PCIE_NAND_TO_AP_RXD_P R12 PCIE_TX0_P IN 4 12 50

7 OUT
90_PCIE_NAND_TO_AP_RXD_N T11 PCIE_TX0_M EXT_RNB/JTAG_TDO E4

EXT_CLE/JTAG_TDI D5 NC

EXT_ALE/JTAG_SEL D9

DROOP_N T3
AP_TO_NAND_RESET_L L4 RESET*
6 IN
WP_N G2 PP1V8_IO 5 6 7 8 10 14 16 17 27 28 29 30
32 34 35 43
A Board trace <= 0.2Ohm
G10 TRST*
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
NAND_ZQ_C K3 ZQ_C PAGE TITLE

NAND_ZQ_N
CKPLUS_WAIVE=MISS_P_DIFFPAIR
C10 ZQ_N NAND
DRAWING NUMBER SIZE
1 1
R2600 R2601 051-02221 D
100
0.1%
300
0.1% Apple Inc. REVISION
1/32W 1/32
MF
01005
MF
01005
VSS 9.0.0
2ROOM=NAND 2ROOM=NAND NOTICE OF PROPRIETARY PROPERTY: BRANCH

evt-1
A2
A4
A6
A8
A10
A12
B1
B13
C2
C12
D1
D11
D13
F1
F5
F7
F9
F11
F13
H1
H3
H5
H9
H11
H13
J10
K1
K5
K7
K13
L10
M1
M5
M7
M13
N4
N10
P1
P3
P7
P11
P13
R10
T1
T7
T9
T13
U2
U4
U6
U8
U10
U12
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
26 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 16 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CRITICAL

L2740 U2700 L2700


1UH-20%-3.2A-0.06OHM D2422B0 1UH-20%-3.2A-0.06OHM
WLCSP 0.625V - 1.06V
PP1V1_S2 2 1 BUCK4_LX0 V11 L17 1 2 PP_CPU_PCORE
42 19 14 SYM 2 OF 5 BUCK0_LX0 4 13
W11 ROOM=PMU BUCK0_LX0 L18
PIWA20160H-SM BUCK4_LX0 PIWA20160H-SM
1 C2745 1 C2744 1 C2743 1 C2742 1 C2741 1 C2740 ROOM=PMU Y11
CRITICAL
ROOM=PMU 1 C2700 1 C2701 1 C2702 1 C2703 1 C2704 1 C2705
26UF 26UF 26UF 26UF 26UF 220PF CRITICAL 220PF 26UF 26UF 26UF 26UF 26UF
20%
2 4V
20%
2 4V
20%
2 4V
20%
2 4V
20%
2 4V
5%
2 10V
L2701 5%
2 10V
20%
2 4V
20%
2 4V
20%
2 4V
20%
2 4V
20%
2 4V
X5R X5R X5R X5R X5R C0G-CERM CRITICAL 0.47UH-20%-3.3A-0.053OHM C0G-CERM X5R X5R X5R X5R X5R
0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM 01005 01005 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU L2741 N16 BUCK0_LX1 1 2
4.9A MAX
BUCK4

ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU

13.8A MAX
0.47UH-20%-3.3A-0.053OHM N17 PIWA2012FE-SM

BUCK0
(Place in TTS) BUCK0_LX1 ROOM=PMU
1 2 BUCK4_LX1 V9 N18
W9
D
PIWA2012FE-SM
ROOM=PMU Y9
BUCK4_LX1 CRITICAL

L2702 1 C2706 D
0.1UH-20%-6.1A-0.031OHM 26UF
OMIT 20%
R16 BUCK0_LX2 1 2 2 4V
XW2740
SHORT-20L-0.05MM-SM
R17 PINA1608-SM
X5R
0402-0.1MM
BUCK0_LX2 ROOM=PMU ROOM=PMU
2 1 BUCK4_FB T8 BUCK4_FB R18
ROOM=PMU CRITICAL

L2703
L2750 0.1UH-20%-6.1A-0.031OHM
1UH-20%-2.5A-0.052OHM U16 BUCK0_LX3 1 2

14 13 9 8 7 6
PP0V8_SOC_FIXED_S1 2 1 BUCK5_LX0 V3 BUCK0_LX3 U17 PINA1608-SM
W3 U18 ROOM=PMU
PIWA20160H-SM BUCK5_LX0
1 C2752 1 C2751 1 C2750 ROOM=PMU Y3
1.7A MAX
BUCK5

26UF 26UF 220PF


20% 20% 5%
2 4V
X5R 2 4V
X5R
10V
2 C0G-CERM OMIT
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
01005
ROOM=PMU XW2750
SHORT-20L-0.05MM-SM BUCK0_FB R13 BUCK0_FB IN 13
2 1 BUCK5_FB T4 BUCK5_FB
ROOM=PMU CRITICAL
CRITICAL L2710 0.67V - 0.92V
L2760 1UH-20%-3.6A-0.062OHM 1.03V for overdrive only
1UH-20%-2.4A-0.06OHM A15 BUCK1_LX0 1 2 PP_GPU 4 13
PP1V25_S2 2 1 BUCK6_LX0 H1 BUCK1_LX0 B15 0806
27 19
H2 BUCK6_LX0 ROOM=PMU 1 C2710 1 C2711 1 C2712 1 C2713 1 C2714 1 C2715
1.2A MAX
BUCK6

PIWA2016FE-SM
1 C2763 1 C2762 1 C2761 1 C2760 ROOM=PMU 220PF 26UF 26UF 26UF 26UF 26UF

13.8A MAX
15UF 15UF 15UF 220PF L2711 5%
2 10V
20%
2 4V
20%
2 4V
20%
2 4V
20%
2 4V
20%
2 4V

BUCK1
20% 20% 20% 5% OMIT 0.47UH-20%-4A-0.048OHM C0G-CERM X5R X5R X5R X5R X5R
2 6.3V
X5R 2 6.3V
X5R 2 6.3V
X5R 2 10V
C0G-CERM XW2760
SHORT-20L-0.05MM-SM
A13 BUCK1_LX1 1 2
01005
ROOM=PMU
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
0402-0.1MM-1 0402-0.1MM-1 0402-0.1MM-1 01005
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU 2 1 BUCK6_FB H4 BUCK6_FB B13 PIWA20120H-SM CRITICAL
BUCK1_LX1
C (Place Close to Ansel) ROOM=PMU C13 ROOM=PMU

CRITICAL
C
0.80V - 1.06V L2770 L2712 1 C2716
1UH-20%-2.5A-0.052OHM 0.1UH-20%-7.2A-0.018OHM 26UF
20%
13
PP_CPU_SRAM 2 1 BUCK7_LX0 W16 A11 BUCK1_LX2 1 2 2 4V
X5R
PIWA20160H-SM W17 BUCK7_LX0 B11 PINA2012-SM 0402-0.1MM
C2772 C2771 C2770 BUCK1_LX2
2.1A MAX

1 1 1
BUCK7

ROOM=PMU W18 C11 ROOM=PMU ROOM=PMU


26UF 26UF 220PF
20% 20% 5%
2 4V 2 4V 2 10V OMIT
X5R X5R C0G-CERM
0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
01005
ROOM=PMU XW2770
SHORT-20L-0.05MM-SM
2 1 BUCK7_FB W14 BUCK7_FB A9
NC
ROOM=PMU BUCK1_LX3 B9
NC
CRITICAL
C9
NC
0.80V - 0.92V L2780
1UH-20%-2.5A-0.078OHM
13
PP_GPU_SRAM 2 1 BUCK8_LX0 A17
PIWA20120H-SM B17 BUCK8_LX0 BUCK1_FB F15 BUCK1_FB
1 C2782 1 C2781 1 C2780 ROOM=PMU
IN 13
1.2A MAX
BUCK8

26UF 26UF 220PF OMIT


20% 20% 5% CRITICAL
2 4V
X5R 2 4V
X5R 2 10V
C0G-CERM XW2780
SHORT-20L-0.05MM-SM L2720
0402-0.1MM 0402-0.1MM 01005 0.67V/0.80V
ROOM=PMU ROOM=PMU
ROOM=PMU 2 1 BUCK8_FB E17 BUCK8_FB
1UH-20%-3.2A-0.06OHM
V5 BUCK2_LX0 1 2 PP_SOC_S1

4.9A MAX
ROOM=PMU 13

BUCK2
CRITICAL BUCK2_LX0 W5 PIWA20160H-SM
L2790 Y5 ROOM=PMU 1 C2720 1 C2721 1 C2722 1 C2723 1 C2724
1UH-20%-2.1A-0.1OHM 220PF 26UF 26UF 26UF 26UF
CRITICAL 5% 20% 20% 20% 20%
BUCK9_LX 2 10V 2 4V 2 4V 2 4V 2 4V
14
PP_DCS_S1 2 1 A6 L2721 C0G-CERM
01005
X5R
0402-0.1MM
X5R
0402-0.1MM
X5R
0402-0.1MM
X5R
0402-0.1MM
B6 BUCK9_LX0 0.47UH-20%-3.3A-0.053OHM
B 1 C2792 1 C2791 1 C2790
PIWA2012FE-SM ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
B
BUCK9

ROOM=PMU V7
1.2A MAX

BUCK2_LX1 1 2
26UF 26UF 220PF OMIT (Place in TTS)
20% 20% 5% W7 PIWA2012FE-SM
2 4V
X5R 2 4V
X5R 2 10V
C0G-CERM XW2790
SHORT-20L-0.05MM-SM
BUCK2_LX1
Y7 ROOM=PMU
0402-0.1MM 0402-0.1MM 01005
ROOM=PMU ROOM=PMU ROOM=PMU 1 2 BUCK9_FB F4 BUCK9_FB
ROOM=PMU

BUCK2_FB T7 BUCK2_FB 13
IN

L2730
1UH-20%-2.4A-0.06OHM
F1 BUCK3_LX0 1 2 PP1V8_S2 10 12 14 20 22 38 46 47
BUCK3_LX0 F2 PIWA2016FE-SM
48 49 50

1.7A MAX
BUCK3
ROOM=PMU 1 C2730 1 C2731 1 C2732
OMIT 220PF 15UF 15UF
5% 20% 20%
XW2730
SHORT-20L-0.05MM-SM
2 10V
C0G-CERM 2 6.3V
X5R 2 6.3V
X5R
01005
ROOM=PMU
0402-0.1MM-1 0402-0.1MM-1
BUCK3_FB G4 BUCK3_FB 1 2 ROOM=PMU ROOM=PMU

ROOM=PMU

C1
VBUCK3_SW C2

A A2 PP1V8_IO SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016


A
5 6 7 8 10 14 16 27 28 29 30 32
34 35 43 PAGE TITLE
BUCK3_SW1 B1
SYSTEM POWER: PMU Bucks (1/4)
SWITCH OUTPUTS

B2
DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

BUCK3_SW2 D1 PP1V8_TOUCH_RACER_S2 42 50
9.0.0
D2 PP1V8_IMU_S2 NOTICE OF PROPRIETARY PROPERTY: BRANCH
BUCK3_SW3 25 26 49
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
27 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 17 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
CRITICAL
U2700 L2800
D2422B0 1UH-20%-2.1A-0.1OHM
WLCSP
19
VDD_MAIN_SNS P7 VDD_MAIN_SNS SYM 3 OF 5
A4 BUCK10_LX 1 2 PP0V6_VDDQL_S1 14
IN
BUCK10_LX0

1.2A MAX
BUCK10
ROOM=PMU B4 PIWA2012FE-SM
45 43 42 41 34 31 27 23 21 19
50 46
PP_VDD_MAIN E5 VDD_MAIN_1 ROOM=PMU 1 C2800 1 C2801 1 C2802
K5 VDD_MAIN_2 220PF 26UF 26UF
5% 20% 20%
1 C2850 1 C2851 1 C2852 R7 VDD_MAIN_3 OMIT 2 10V
C0G-CERM 2 4V
X5R 2 4V
X5R

BAT/USB
18UF 18UF 18UF U14 VDD_MAIN_4 XW2800 01005 0402-0.1MM
ROOM=PMU
0402-0.1MM
ROOM=PMU
20% 20% 20% ROOM=PMU
L14 SHORT-20L-0.05MM-SM
2 6.3V 2 6.3V 2 6.3V VDD_MAIN_5 E4
CER-X5R
0402-0.1MM
CER-X5R
0402-0.1MM
CER-X5R
0402-0.1MM F14 BUCK10_FB BUCK10_FB 2 1
VDD_MAIN_6
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU

CRITICAL
M15
M16 L2810
1 C2854 1 C2855 1 C2856 1 C2857 1 C2858 1UH-20%-3.2A-0.06OHM
M17 VDD_BUCK0_01
4UF 4UF 4UF 4UF 4UF G17 BUCK11_LX0 1 2 PP_CPU_ECORE 13
20% 20% 20% 20% 20% M18 BUCK11_LX0
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
G18 PIWA20160H-SM
CERM-X5R
0201
CERM-X5R
0201
CERM-X5R
0201
CERM-X5R
0201
CERM-X5R
0201 ROOM=PMU 1 C2810 1 C2811 1 C2812 1 C2813
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU T15 220PF 26UF 26UF 26UF
CRITICAL 5% 20% 20% 20%

3.0A MAX
BUCK11
T16 2 10V 2 4V 2 4V 2 4V
T17 VDD_BUCK0_23 L2811 C0G-CERM
01005
X5R
0402-0.1MM
X5R
0402-0.1MM
X5R
0402-0.1MM
0.47UH-20%-4A-0.048OHM ROOM=PMU
ROOM=PMU ROOM=PMU ROOM=PMU
T18
J17 BUCK11_LX1 1 2
1 C2859 1 C2860 1 C2861 1 C2862 1 C2863 BUCK11_LX1 J18 PIWA20120H-SM
4UF 4UF 4UF 4UF 4UF A14 ROOM=PMU
20% 20% 20% 20% 20%
2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V B14
CERM-X5R CERM-X5R CERM-X5R CERM-X5R CERM-X5R
C 0201
ROOM=PMU
0201
ROOM=PMU
0201
ROOM=PMU
0201
ROOM=PMU
0201
ROOM=PMU
C14
D14
VDD_BUCK1_01 C
BUCK11_FB J15 BUCK11_FB 13 20
A10 IN

1 C2864 1 C2865 1 C2866 B10


4UF 4UF 4UF C10 VDD_BUCK1_23
20% 20% 20%
2 6.3V 2 6.3V 2 6.3V D10
CERM-X5R CERM-X5R CERM-X5R
0201 0201 0201
ROOM=PMU ROOM=PMU ROOM=PMU V6
W6
VDD_BUCK2
Y6

BUCK INPUT
E1
E2 VDD_BUCK3

V10
W10 VDD_BUCK4
Y10

V2
W2
VDD_BUCK5
Y2

J1
J2 VDD_BUCK6

Y15
B Y16
B
VDD_BUCK7
Y17

B18
C18 VDD_BUCK8

A7
B7 VDD_BUCK9

A3
B3 VDD_BUCK10

H17
H18 VDD_BUCK11

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

SYSTEM POWER: PMU Bucks (2/4)


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
28 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 18 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

43 42 41 34 31 27 23 21 19 18
PP_VDD_MAIN
50 46 45
OMIT

XW2990 1 C2990 1 C2991 1 C2992


SHORT-20L-0.05MM-SM 18UF 18UF 18UF
18 OUT
VDD_MAIN_SNS 2 1 20% 20% 20%
2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R
ROOM=PMU 0402-0.1MM 0402-0.1MM 0402-0.1MM
OMIT ROOM=PMU ROOM=PMU ROOM=PMU

XW2991
SHORT-20L-0.05MM-SM
20 OUT
PMU_PRE_UVLO_DET 2 1
ROOM=PMU

D D

50 38 34 27 21 19
PP_VDD_BOOST
OMIT_TABLE OMIT_TABLE

XW2995
OMIT 1 C2970 1 C2971
SHORT-20L-0.05MM-SM
2.2UF 2.2UF
20% 20%
20 OUT
PMU_LDO5_UVLO_DET 2 1 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
ROOM=PMU 0201 0201
ROOM=CAM_PMU ROOM=CAM_PMU

U2700
C D2422B0 C
WLCSP
PP_VDD_MAIN K4 VDD_LDO0 SYM 1 OF 5 VLDO0 K3 PP2V5_LDO0_S2
U2700 43 42 41 34 31 27 23 21 19 18
50 46 45
PP_VDD_BOOST N4 VDD_LDO1
ROOM=PMU
VLDO1 N3 PP3V3_USB
19

LDO1
D2422B0 50 38 34 27 21 19 6

WLCSP M4 VDD_LDO2 VLDO2 M3 PP1V8_AUDIO_VA_S2 38 41 50 LDO2


A1 SYM 5 OF 5 K17 42 17 14
PP1V1_S2 R5 VDD_LDO3 VLDO3 P5 PP3V0_CONVOY LDO3
A12 ROOM=PMU K18 OMIT_TABLE OMIT_TABLE N1 N2 PP0V7_VDD_LOW_S2
VDD_LDO4 VLDO4 LDO4
A16 L16 C2980 1 C2981 1
V1 VDD_LDO5 VLDO5 U1 PP3V0_NAND
13

LDO5
2.2UF 2.2UF 16
A18 L6 20% 20% W1 VDD_LDO5
6.3V 6.3V
A5 M7 X5R-CERM 2 X5R-CERM 2 L1 VDD_LDO6 VLDO6 L2 PP_ACC_VAR 46 48 LDO6
0201 0201
A8 M11 ROOM=PMU ROOM=PMU K1 VDD_BYPASS VBYPASS K2
B12 N7

LDO INPUT
B16 N15 M1 VDD_LDO7 VLDO7 M2 PP3V0_S2 36 45 47 48 50 LDO7
B5 N8 R2 VDD_LDO8 VLDO8 P2 PP0V9_NAND 16 LDO8
B8 N9 M6 VDD_LDO9 VLDO9 N6 PP1V8_ALWAYS 20 23 LDO9
C12 P10 R6 VDD_LDO10
C15 P11 27 17
PP1V25_S2 R4 VDD_LDO11
C16 P15 L4 VDD_LDO12 VLDO10 P6 PP3V0_DISPLAY 43 LDO10
C17 P16 R3 VDD_LDO13 VLDO11 P4 PP1V2_SOC 7 9 13 14 LDO11
C3 P17 T1 L3 LDO12

LDO
VDD_LDO14 VLDO12 NC
C4 P18 VLDO13 P3 PP1V2_CODEC_S2 38 LDO13
M5 VDD_VBUF
C5 P8 VLDO14 T2 PP1V0_DISPLAY_DVDD 43 LDO14
C6 P9 19
PP2V5_LDO0_S2 J4 VCC_LDOG
C7 R15
C8 R8 E14 VPP_OTP
D11 T3 PMU_VSS_RTC
20
D12 T5
B D13 T6 B
D15 T9
D16 U10 VBUF_1V2 N5 PP1V2_LPADC 14 VBUF_1V2
D17 VSS VSS U11 T14 TP_DET
NC
D18 U12 OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
D8 U15 1 C2901 1 C2906 1 C2909 1 C2911 1 C2913
D9 U3 VPUMP D3 PMU_VPUMP 2.2UF 2.2UF 1.0UF 2.2UF 2.2UF
20% 20% 20% 20% 20%
E11 U4 2 6.3V 2 6.3V 2 6.3V 6.3V
2 X5R-CERM 2 6.3V
X5R-CERM X5R-CERM X5R X5R-CERM
E12 U5 0201 0201 0201-1 0201 0201
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
E13 U6
E18 U7 OMIT_TABLE OMIT_TABLE
OMIT_TABLE OMIT_TABLE OMIT_TABLE
E3 U8 1 C2920 1 C2900 1 C2903 1 C2907 1 C2910 1 C2914 1 C2915
F16 U9 47NF 2.2UF 2.2UF 2.2UF 2.2UF 2.2UF 0.22UF
20% 20% 20% 20% 20% 20% 20%
F17 V12 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V 2 6.3V
X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R-CERM X5R
F18 V15 01005 0201 0201 0201 0201 0201 01005-1
ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU ROOM=PMU
F3 V16
F5 V17
G1 V18
G15 V4 VPUMP: 10nF min. @4.6V
G16 V8
G2 N12
G3 W12
G5 W15
H16 W4
H3 W8

A H5
J13
Y1
Y12 SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE
J14 Y13
J16 Y14 SYSTEM POWER: PMU LDOs (3/4)
J5 DRAWING NUMBER SIZE
Y18
K14 Y4 051-02221 D
K16 Y8
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
29 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 19 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
Ansel AMUX R3010
1
200K 2
CRITICAL
CAMPMU_TO_PMU_AMUX 20 28
U2700 1%
1/20W
1 C3071 D2422B0
WLCSP
MF
201
1000PF ROOM=PMU
10% AP_TO_PMU_WDOG_RESET P13
RESET_IN1 SYM 4 OF 5
2 10V
6 IN
IREF R10 PMU_IREF
X5R
01005 48 IN
HYDRA_TO_PMU_HOST_RESET P12
RESET_IN2
ROOM=PMU
C3010
ROOM=PMU AP_TO_PMU_SOCHOT_L N13 0.22UF
RESET_IN3

RESETS
6 4 IN
VREF R9 PMU_VREF 1 2

REFS
20 6 OUT
PMU_TO_SYSTEM_COLD_RESET_L R12
RESET*
H15 SHDN 20%
NC 6.3V
COLD_RESET & SYSTEM_ALIVE X5R
0201
ROOM=PMU

PP1V8_S2 10 12 14 17 22 38 46 47 48 49
50

1 1
R3061 R3062 48 6 4
PMU_TO_AP_HYDRA_ACTIVE_READY M12 ACTIVE_RDY
PMU_TO_AP_PRE_UVLO_L
PRE_UVLO M14
OUT
100K 100K OUT 4 6 11
5% 5% PMU_TO_AOP_CLK32K G6 SLEEP_32K
1/32W 1/32W 12 OUT
MF MF PMU_TO_TOUCH_CLK32K_RESET_L H6 OUT_32K
2 01005
ROOM=PMU
2 01005
ROOM=PMU
R3000 50 OUT
VDROOP0 P14 PMU_TO_AP_THROTTLE_PCORE_L OUT 6
100

COMPARATOR
SYSTEM_ALIVE 14 16 20 23 23 20 16 14
SYSTEM_ALIVE 1 2 SYSTEM_ALIVE_R K13 SYS_ALIVE VDROOP1 E16 PMU_TO_AP_THROTTLE_GPU0_L 6
OUT OUT
PMU_TO_SYSTEM_COLD_RESET_L 6 20 1% 50 28 21 12 8 IN
AP_TO_MANY_BSYNC M13 FORCE_SYNC VDROOP11 L15 PMU_TO_AP_THROTTLE_ECORE_L OUT 6
1/32W PMU_TO_SEP_DOUBLE_CLICK_DET
MF L12 DBL_CLICK_DET
01005
10 OUT
VDROOP0_DET R14 AP_CPU_PCORE_SENSE
PMU_TO_AOP_IRQ_L N14 IRQ* IN 4 13
ROOM=PMU 12 OUT
VDROOP1_DET E15 AP_VDD_GPU_SENSE IN 4 13

49 46 10
I2C0_AP_SCL M8 SCL VDROOP11_DET K15
BUCK11_FB 13 18
IN IN
I2C0_AP_SDA L8 SDA
49 46 10 BI
PRE_UVLO_DET L13 PMU_PRE_UVLO_DET
SPMI_PMGR_TO_PMU_SCLK K7 SCLK
IN 19
10 IN
LDO5_UVLO_DET U2 PMU_LDO5_UVLO_DET
C 10 4 OUT
SPMI_PMU_BI_PMGR_SDATA L7 SDATA
IN 19
C
NTCs IBAT T11
NC
VBAT T10
FOREHEAD NTC NC
HYDRA_TO_PMU_USB_BRICK_ID PP1V8_ALWAYS 19

ADC
BRICK_ID1 N11 20 48 20 23
IN
6
AP_TO_PMU_AMUX_OUT D4 AMUX_A0 BRICK_ID2 N10 1
R3074 NOSTUFF
IN NC
1 D5 AMUX_A1 ADC_IN R11 ACORN_TO_PMU_ADC 20 42 31.6K
OMIT NC IN
CAMPMU_TO_PMU_AMUX D6 AMUX_A2
1%
1/32W
C3041 1
R3041 FOREHEAD_NTC XW3041 28 20 IN
D7 AMUX_A3
MF
100PF SHORT-20L-0.05MM-SM NC BUTTON1 G14 BUTTON_VOL_DOWN_L 2 01005
5% 10KOHM-1% FOREHEAD_NTC_RETURN 1 2 F9 AMUX_A4 BUTTON_POWER_KEY_L IN 25
ROOM=PMU
16V 2 NC BUTTON2 H14
NP0-C0G 01005 ROOM=PMU 48 20
HYDRA_TO_PMU_USB_BRICK_ID F10 AMUX_A5 BUTTON_VOL_UP_L
IN 33
01005 IN
BUTTON3 F13

BUTTONS
ROOM=PMU 25
2 E6 IN

AMUX
ROOM=PMU
NC AMUX_A6 G13 BUTTON_RINGER_A
ACC_BUCK_TO_PMU_AMUX E7 BUTTON4 IN 25
46 IN AMUX_A7
50 OUT
PMU_AMUX_AY E8 AMUX_AY BUTTONO1 K6 PMU_TO_AP_BUTTON_VOL_DOWN_L OUT 11

BUTTONO2 J7 PMU_TO_AP_BUTTON_POWER_KEY_L
1
R3011 ACORN_TO_PMU_ADC F6 AMUX_B0
OUT 11
42 20
BUTTONO3 J6 PMU_TO_AP_BUTTON_VOL_UP_L
200K 11 IN
AP_TO_PMU_AMUX_SYNC G7 AMUX_B1
OUT 11

REAR CAMERA NTC 1%


1/32W 43
DISPLAY_TO_PMU_AMUX G8 AMUX_B2 R3073
IN
MF TOUCH_TO_AMUX_PP1V8 F7 F11 PMU_TO_NFC_EN_R 1
100 2 PMU_TO_NFC_EN
1 2 01005 50 IN AMUX_B3 GPIO1 OUT 50

OMIT ROOM=PMU
50 20
PMU_TO_WLAN_CLK32K E9 AMUX_B4 GPIO2 F12 PMU_TO_AP_THROTTLE_GPU1_L OUT 6 5%
RIGEL_TO_ISP_INT 1/32W
XW3042 E10 G9 TIGRIS_TO_PMU_INT_L
C3042 1 R3042 REAR_CAMERA_NTC SHORT-20L-0.05MM-SM
34 8 4 IN
AP_TO_PMU_TEST_CLKOUT F8
AMUX_B5 GPIO3
G10 WLAN_TO_PMU_HOST_WAKE
IN 23 MF
01005
100PF 10KOHM-1% RCAM_NTC_RETURN 1 2 6 4 IN AMUX_B6 GPIO4 IN 50 ROOM=PMU
5% H7 AMUX_B7 GPIO5 G11 NFC_TO_PMU_HOST_WAKE 50
16V 2 01005 NC IN
NP0-C0G
01005 2 ROOM=PMU
ROOM=PMU
50 OUT
PMU_AMUX_BY H8 AMUX_BY GPIO6 G12
NC
R3072
ROOM=PMU H9 PMU_TO_GNSS_EN_R 1
100 2 PMU_TO_GNSS_EN
GPIO7 OUT 50

20
FOREHEAD_NTC T12 TDEV1 GPIO8 H10 PMU_TO_WLAN_CLK32K OUT 20 50 5%
1/32W
20
REAR_CAMERA_NTC T13 TDEV2 GPIO9 H11 PMU_TO_BT_REG_ON OUT 50 MF
01005
RADIO_PA_NTC U13 H12 BT_TO_PMU_HOST_WAKE
B TDEV3 GPIO10
B

GPIO
50 50

NTC
IN ROOM=PMU

20
AP_NTC V13 TDEV4 GPIO11 J8 CODEC_TO_PMU_WAKE IN 38
CHARGER_NTC W13 J9
20
PMU_TCAL V14
TDEV5 GPIO12
J10
NC R3071
TCAL GPIO13 NC 1
20.0K 2 PMU_HYDRA_TO_AP_FORCE_DFU
GPIO14 J11 PMU_TO_WLAN_REG_ON BI 11 48
50
1 C3020 1
R3020 PMU_VSS_RTC R1 XTAL1 GPIO15 J12 PMU_TO_BB_USB_VBUS_DETECT
OUT 50
5%
1/32W
100PF 3.92K 20 19 OUT 50

XTAL
MF
5% TCXO_PMU_32K P1 XTAL2 GPIO16 K8 01005
RADIO PA NTC on MLB Bottom 2 16V
NP0-C0G
0.1%
1/20W K9
NC
PMU_TO_AP_FORCE_DFU_R ROOM=PMU
01005 MF GPIO17
ROOM=PMU
2 0201
PMU_VDD_RTC L5 VDD_RTC GPIO18 K10 PMU_TO_CCG2_RESET_L OUT 47
R3070
ROOM=PMU
K11 PMU_TO_BBPMU_RESET_R_L 1
1.00K 2 PMU_TO_BBPMU_RESET_L
GPIO19 OUT 50
PMU_VDD_REF J3 VDD_REF GPIO20 K12 PMU_TO_NAND_LOW_BATT_BOOT_L OUT 16 5%
1/32W
L9 BB_TO_PMU_PCIE_HOST_WAKE_L
R3001 1 C3030 1 C3031 GPIO21
L10 PMU_TO_IKTARA_EN_EXT_1P8V
IN 50 MF
01005
PP1V8_ALWAYS 1
0.00 2 PP1V8_ALWAYS_XO 0.22UF 1UF GPIO22 OUT 50 ROOM=PMU
23 20 19
20% 20% GPIO23 L11 PMU_TO_BOOST_EN OUT 21
0% 2 6.3V 2 6.3V M9
1/32W X5R X5R GPIO24 PMU_TO_DISPLAY_PANICB OUT 43
AP NTC MF ROOM=PMU
0201 0201
M10
01005 1 C3002 ROOM=PMU ROOM=PMU GPIO25 NC
0.1UF
3

20% FAULT_OUT* H13 PMU_TO_IKTARA_RESET_L 50


1 OUT
OMIT 2 6.3V
X5R-CERM
VDD

C3044 1
R3044 AP_NTC XW3044 01005
ROOM=PMU Y3000
100PF SHORT-20L-0.05MM-SM 32.768KHZ-10PPM
5%
16V 2
10KOHM-1% AP_NTC_RETURN 1 2 CSP
NP0-C0G 01005 ROOM=PMU
1 NC CLKOUT 2
01005 ROOM=PMU
NC CRITICAL
ROOM=PMU 2
ROOM=PMU
GND
4

PMU_VSS_RTC
A CHARGER NTC
20 19

SYNC_MASTER=test_mlb SYNC_DATE=11/01/2016
A
1 PAGE TITLE
ROOM=PMU

1
OMIT
SHORT-20L-0.05MM-SM SYSTEM POWER: PMU (4/4)
I609 XW3000 DRAWING NUMBER SIZE

C3045 1
R3045 CHARGER_NTC XW3045 2 OMIT 051-02221 D
100PF
CHARGER_NTC_RETURN
SHORT-20L-0.05MM-SM Apple Inc. REVISION
5% 10KOHM-1% 1 2
16V
NP0-C0G 2 01005 ROOM=PMU
9.0.0
01005 ROOM=PMU NOTICE OF PROPRIETARY PROPERTY: BRANCH
ROOM=PMU 2
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
30 OF 80
NOTE:100PF CAPS ARE THE SAMPLING CAPS FOR PMU ADC III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
SHEET

IV ALL RIGHTS RESERVED 20 OF 51


8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

Boost Enable Pull


21 20
PMU_TO_BOOST_EN
1
R3100
511K
1%
1/32W
MF
2 01005
ROOM=BOOST

BOOST
C C
45 43 42 41 34 31 27 23 19 18
PP_VDD_MAIN 353S01124
50 46

1 C3190 1 ROOM=BOOST
18UF When VDD_MAIN < 3.4, boosts to 3.4
20% Otherwise tracks VDD_MAIN
2 6.3V
CER-X5R L3100
0402-0.1MM 0.47UH-20%-4A-0.048OHM A3 VIN VOUT B3 PP_VDD_BOOST 19 27 34 38 50
ROOM=BOOST PIWA20120H-SM
A4 VIN U3100 VOUT B4
SN61280E
1 C3110 1 C3111 1 C3112 1 C3113 1 C3114 1 C3115
2 C3 SW 18UF 18UF 18UF 18UF 18UF 220PF
CSP 20% 20% 20% 20% 20% 5%
SYS_BOOST_LX C4 SW 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 10V
C0G-CERM
ROOM=BOOST 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM 01005
21 20 IN
PMU_TO_BOOST_EN A1 EN CRITICAL ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST ROOM=BOOST

I2C0_SMC_SCL B2
R3110 50 47 23 22 10 IN SCL
I2C0_SMC_SDA 1
39.2 2 I2C0_SMC_SDA_BOOST C2
50 47 23 22 10 BI SDA
1%
1/32W B1 VSEL
MF
01005
ROOM=BOOST C1 BYP*

50 28 20 12 8 IN
AP_TO_MANY_BSYNC A2 GPIO
PGND
AGND

D2
D3
D4

D1
B B

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

SYSTEM POWER: Boost


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
31 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 21 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

BATTERY CONNECTOR
Rcpt: 516S00232 <-- This one on MLB Gas gauge I2C level translator
Plug: 516S00233
Q3200

SYM_VER_1
RV1C002UN
SM
ROOM=B2B_BATTERY
CRITICAL
XW3200 R3202
SHORT-20L-0.05MM-SM I2C0_SMC_BI_GG_SDA_CONN I2C0_SMC_BI_GG_SDA 33 I2C0_SMC_SDA

S
D
1 2

2
23 OUT
VBATT_SENSE 2 1 CKPLUS_WAIVE=I2C_PULLUP
BI 10 21 23 47 50

5%
C ROOM=B2B_BATTERY
PLACE_NEAR=J3200:2mm J3200
1 C3202
56PF
1/32W
MF C
NO_XNET_CONNECTION=1 01005
B2B-BATT-RCPT 5%

G
ROOM=B2B_BATTERY
F-ST-SM 2 25V
NP0-C0G-CERM

1
9 01005
ROOM=B2B_BATTERY
5 6

PP_BATT_VCC 1 3 PP1V8_S2 10 12 14 17 20 38 46 47 48 49
50 23 50
2 4
1 C3292 1 C3293 1 C3294
56PF 330PF 220PF 7 8
5% 10% 10%
2 25V 2 16V 2 10V

1
NP0-C0G-CERM CER-X7R X7R-CERM 10

G
01005 01005 01005
ROOM=B2B_BATTERY ROOM=B2B_BATTERY ROOM=B2B_BATTERY ROOM=B2B_BATTERY
R3201
I2C0_SMC_TO_GG_SCL_CONN I2C0_SMC_TO_GG_SCL 2
33 1 I2C0_SMC_SCL IN 10 21 23 47 50

2
D
CKPLUS_WAIVE=I2C_PULLUP

S
5%
1 C3201 1/32W
MF
56PF 01005
5%

SYM_VER_1
Q3201 2 25V
NP0-C0G-CERM
ROOM=B2B_BATTERY

RV1C002UN 01005
ROOM=B2B_BATTERY
SM
ROOM=B2B_BATTERY
CRITICAL

B B

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

SYSTEM POWER: B2B Battery


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
32 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 22 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

TIGRIS2 CHARGER

D D

PP_VDD_MAIN
18 19 21 27 31 34 41 42 43 45
46 50

TIGRIS_PMID1
1 C3390 1 C3391
18UF 18UF
20% 20%
DZ3300 K 1 C3310 1 C3311 1 C3312 1 C3313 1 C3314 1 C3315 2 6.3V
CER-X5R 2 6.3V
CER-X5R
BZT52C20LP R3316 1 4.7UF 4.7UF 220PF 220PF 220PF 220PF 0402-0.1MM 0402-0.1MM
DFN10062 50K C3316 1 C3317 1 20%
2 25V
20%
25V
2 CER-X5R
5%
2 25V
5%
2 25V
5%
2 25V
5%
2 25V
ROOM=CHARGER ROOM=CHARGER

A 1% 4.7UF 4.7UF CER-X5R


0402 0402
COG
01005
COG
01005
COG
01005
COG
01005
1/32W 20% 20%
MF 25V 2 25V 2 ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER
01005 2 X5R X5R
ROOM=CHARGER
0402 0402
ROOM=CHARGER ROOM=CHARGER

C TIGRIS_PMID2
TIGRIS_LDO
C
1 C3320 1 C3322 1 C3323 1 C3324 1 C3325

C2
D2
A2
B2

E2

VDD_MAIN5 F2
4.7UF
20% 5%
220PF
5%
220PF
5%
220PF
5%
220PF 1 C3360 1 C3361

VDD_MAIN
VDD_MAIN
VDD_MAIN
VDD_MAIN
VDD_MAIN
2 25V 2 25V
COG 2 25V
COG 2 25V
COG 2 25V
COG
220PF 4UF
CER-X5R 10% 20%
0402 01005 01005 01005 01005 10V
2 X7R-CERM 2 6.3V

A2
A3
B1
B2
B3
ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER CERM-X5R
01005 0201 CRITICAL
ROOM=CHARGER ROOM=CHARGER S
Q3350
PP_VBUS1_E75 CSD68841W
49 A1
G BGA
1 C3301 1 C3302 1 C3303 1 C3304 A6 PMID1 LDO H3 C3340 ROOM=CHARGER

1UF 220PF 220PF 220PF U3300 0.047UF


10% 5% 5% 5% B6 PMID1 H4 TIGRIS_BOOT 1 2 D
2 25V
X5R 2 25V
COG 2 25V
COG 2 25V
COG C6 SN2500A1YEWR BOOT
402 01005 01005 01005 PMID1 WCSP

C1
C2
C3
ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER D6 PMID1 ROOM=CHARGER
BUCK_SW A7 10%
CRITICAL 25V
E6 PMID1 BUCK_SW B7 X5R
0201 CRITICAL CRITICAL
BUCK_SW C7 ROOM=CHARGER
F6 PMID2
BUCK_SW D7
NO_XNET_CONNECTION L3340 L3341
50
PP_VBUS2_IKTARA G6 PMID2
0.47UH-6.8A-0.046OHM 0.47UH-6.8A-0.046OHM
BUCK_SW E7
H6 PMID2 TIGRIS_LX 1 2 TIGRIS_LX_MID 1 2
1 C3305 1 C3306 1 C3307 1 C3308 BUCK_SW F7
3225 3225
10%
1UF
5%
220PF
5%
220PF
5%
220PF A5 VBUS1 BUCK_SW G7 ROOM=CHARGER ROOM=CHARGER
C3341 1 C3342 1 C3343 1
2 25V 2 25V
COG 2 25V
COG 2 25V
COG
B5 VBUS1 BUCK_SW H7 220PF 220PF 330PF
X5R 5% 5% 10%
402 01005 01005 01005 C5 10V 10V 16V
ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER
VBUS1
BATT A1 C0G-CERM 2 C0G-CERM 2 CER-X7R 2
D5 VBUS1 01005 01005 01005
BATT B1 ROOM=CHARGER ROOM=CHARGER ROOM=CHARGER
E5 VBUS1
BATT C1
F5 VBUS2 BATT D1
G5 VBUS2 BATT E1 PP_BATT_VCC 22 50

B 20 19
PP1V8_ALWAYS H5 VBUS2
BATT_SNS F1 VBATT_SENSE B
I2C0_SMC_SDA F3 SDA
IN 22
1 C3350 1 C3351 1 C3352 1 C3353
1
R3330
50 47 22 21 10 BI
ACT_DIODE A3 TIGRIS_ACTIVE_DIODE 330PF 4UF 4UF 220PF
50 47 22 21 10
I2C0_SMC_SCL G2 SCL 10% 20% 20% 5%
2 16V 2 6.3V 2 6.3V 2 10V
IN
100K NOSTUFF CER-X7R CERM-X5R CERM-X5R C0G-CERM
5% SYSTEM_ALIVE F4 G3
1/32W
MF
20 16 14 IN SYS_ALIVE HDQ_HOST
G4
R33501 01005
ROOM=CHARGER
0201
ROOM=CHARGER
0201
ROOM=CHARGER
01005
ROOM=CHARGER

2 01005 HYDRA_TO_TIGRIS_VBUS1_VALID_L B4 VBUS1_VALID* HDQ_GAUGE 100K


ROOM=CHARGER 48 4 IN 5%
B3 VBUS2_VALID* 1/32W
R3331 R3360 MF
01005 2
TIGRIS_TO_PMU_INT_L 1
100 2 TIGRIS_TO_PMU_INT_R_L E3 INT* A4 PP_VBUS1_E75_RVP_R 2
10 1 PP_VBUS1_E75_RVP ROOM=CHARGER
20 OUT AUX1 45 47 48

1% 5%
1/32W TIGRIS_VBUS_DETECT C4 VBUS1_DET NC0 D3 1/32W
MF G1 MF
01005 NC1 01005
ROOM=CHARGER
D4 TEST ROOM=CHARGER
NC2 H1
R3332 23
BATTERY_NTC E4 NTC NC3 H2
USB_VBUS_DETECT 1
30.1K 2
6 OUT
1% GND AGND
1/32W
MF
A8
C8
D8
E8
F8
G8
H8

B8

01005
ROOM=CHARGER

BATTERY NTC
A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

1
I251
OMIT SYSTEM POWER: Charger
C3370 1
R3370 BATTERY_NTC XW3370
SHORT-20L-0.05MM-SM
DRAWING NUMBER

051-02221
SIZE

D
100PF 23
Apple Inc.
5%
16V
10KOHM-1% BATTERY_NTC_RETURN 1 2 REVISION
NP0-C0G 2 01005 ROOM=CHARGER 9.0.0
01005 ROOM=CHARGER
ROOM=CHARGER 2 NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
33 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 23 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C C

Iktara Components on MLB Bottom

B B

A A
PAGE TITLE

SYSTEM POWER: Iktara


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
34 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 24 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Cyclone + Button Connnector


Rcpt: 516S00289 <-- This one on MLB
Plug: 516S00290

J3500
Cyclone Filtering AA36D-S04VA1
F-ST-SM
D 25
BUTTON_VOL_DOWN_CONN_L 9 10 D
50
IKTARA_COIL2 IKTARA_COIL2 25 25
IKTARA_COIL2 5 PWR
6
MAKE_BASE=TRUE
1 C3500 1 C3501 BUTTON_VOL_UP_CONN_L 1 2 COMPASS_TO_AOP_INT_BTN_CONN
220PF 220PF 25
BUTTON_RINGER_A_CONN I2C1_AOP_TO_COMPASS_SCL_BTN_CONN
25
2% 2% 25
3 4 25
2 50V
C0G 2 50V
C0G
0201 0201
ROOM=B2B_BUTTON ROOM=B2B_BUTTON
25
IKTARA_COIL1 7 PWR
8 I2C1_AOP_BI_COMPASS_SDA_BTN_CONN 25

25
PP1V8_IMU_COMPASS_BTN_CONN 11 12

ROOM=B2B_BUTTON

50
IKTARA_COIL1 IKTARA_COIL1 25
MAKE_BASE=TRUE
1 C3510 1 C3511
220PF 220PF
2% 2%
2 50V
C0G 2 50V
C0G
0201 0201
ROOM=B2B_BUTTON ROOM=B2B_BUTTON

C C
BUTTONS
R3520
BUTTON_RINGER_A 1
100 2 BUTTON_RINGER_A_CONN
20 OUT 25

5%
C3520 1 1/32W 1
27PF
5%
MF
01005 DZ3520
6.3V 2 ROOM=B2B_BUTTON 0201
NP0-C0G 5.5V-6.2PF
0201 ROOM=B2B_BUTTON
ROOM=B2B_BUTTON 2

R3530
BUTTON_VOL_DOWN_L 1
100 2 BUTTON_VOL_DOWN_CONN_L
20 OUT 25

5%
C3530 1 1/32W
MF
1 DZ3530
220PF 01005 12V-33PF
01005-1
5% ROOM=B2B_BUTTON ROOM=B2B_BUTTON
10V 2 2
C0G-CERM
01005
ROOM=B2B_BUTTON

R3540
BUTTON_VOL_UP_L 1
100 2 BUTTON_VOL_UP_CONN_L
20 OUT 25

B 5%
1/32W 1 DZ3540 B
C3540 1 MF
01005 12V-33PF
220PF ROOM=B2B_BUTTON
01005-1
5% 2 ROOM=B2B_BUTTON
10V 2
C0G-CERM
01005
ROOM=B2B_BUTTON

Compass (Button Flex Location)


FL3550
150OHM-25%-200MA-0.7DCR
49 26 17
PP1V8_IMU_S2 2 1 PP1V8_IMU_COMPASS_BTN_CONN 25
01005
ROOM=B2B_DOCK 1 C3550
220PF
5%
2 10V
C0G-CERM
01005
ROOM=B2B_DOCK
R3551
I2C1_AOP_SCL 2
0.00 1 I2C1_AOP_TO_COMPASS_SCL_BTN_CONN
50 49 41 12 4 IN 25
CKPLUS_WAIVE=I2C_PULLUP
0%
1/32W
MF
1 C3551
01005 56PF
ROOM=B2B_DOCK 5%
2 25V
NP0-C0G-CERM
01005
ROOM=B2B_DOCK
R3552
I2C1_AOP_SDA 2
0.00 1 I2C1_AOP_BI_COMPASS_SDA_BTN_CONN
50 49 41 12 4 BI 25
CKPLUS_WAIVE=I2C_PULLUP
0%
A 1/32W
MF
01005
1 C3552
56PF SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
ROOM=B2B_DOCK 5% PAGE TITLE
2 25V
NP0-C0G-CERM
01005 SYSTEM POWER: B2B Cyclone + Button
FL3553 ROOM=B2B_DOCK DRAWING NUMBER SIZE
150OHM-25%-200MA-0.7DCR 051-02221 D
49 12 4 OUT
COMPASS_TO_AOP_INT 2 1 COMPASS_TO_AOP_INT_BTN_CONN 25
Apple Inc. REVISION
01005
ROOM=B2B_DOCK 1 C3553 9.0.0
220PF NOTICE OF PROPRIETARY PROPERTY: BRANCH
5%
2 10V
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
evt-1
C0G-CERM THE POSESSOR AGREES TO THE FOLLOWING: PAGE
01005
ROOM=B2B_DOCK I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
35 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 25 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
Graphite - Accel & Gyro Magnesium - Compass
(On Dock or Button Flex)
APN: 338S00304

PP1V8_IMU_S2 17 25 26 49

49 26 25 17
PP1V8_IMU_S2 OMIT_TABLE
1 C3600 1 C3601 1 C3602
0.1UF 0.1UF 2.2UF
20% 20% 20%
1 2 6.3V 2 6.3V 2 6.3V
R3601 X5R-CERM
01005
X5R-CERM
01005
X5R-CERM
0201
100K
5% ROOM=CARBON ROOM=CARBON ROOM=CARBON
1/32W
MF

16
01005 2

1
ROOM=CARBON

VDDIO
VDD

CRITICAL
U3600
BMI262BB
LGA
12 IN
SPI_AOP_TO_ACCEL_GYRO_CS_L 5 CSB ROOM=CARBON
SCLK 2 SPI_AOP_TO_IMU_SCLK IN 4 12 26
15 SM
MOSI 3 SPI_AOP_TO_IMU_MOSI IN 4 12 26

12 4 OUT
ACCEL_GYRO_TO_AOP_DATARDY 6 INT MISO 4 SPI_IMU_TO_AOP_MISO OUT 4 12 26
ACCEL_GYRO_TO_AOP_INT 7 MOTION_INT
C 12 4 OUT
C
GND
GND
GND
GND
GND
GND
GND
8
9
10
11
12
13
14

CARBON_REGOUT

1
R3600
0.00
0%
1/32W
MF
2 01005
ROOM=CARBON

B B

Phosphorus
BOSCH (APN:338S00188)
ST (APN:338S00230)

49 26 25 17
PP1V8_IMU_S2 PP1V8_IMU_S2 17 25 26 49
OMIT_TABLE
1 C3620 1 C3622
0.1UF 2.2UF
R36201 20%
2 6.3V
X5R-CERM
20%
2 6.3V
X5R-CERM
100K 01005 0201
5% ROOM=PHOSPHORUS ROOM=PHOSPHORUS
1/32W
MF
01005 2
A ROOM=CARBON
A
8

SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016

VDD VDDIO PAGE TITLE


ROOM=PHOSPHORUS
U3620 SENSORS
SPI_AOP_TO_IMU_MOSI BMP284AA SPI_IMU_TO_AOP_MISO
26 12 4 3 SDI LGA SDO 5 4 12 26 DRAWING NUMBER SIZE
IN OUT
SPI_AOP_TO_IMU_SCLK 4 SCK CRITICAL
051-02221 D
26 12 4 IN
IRQ 7 PHOSPHORUS_TO_AOP_INT Apple Inc.
12 IN
SPI_AOP_TO_PHOSPHORUS_CS_L 2 CS* OUT 4 12
REVISION
GND 9.0.0
1

NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
36 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 26 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Camera PMU
45 43 42 41 34 31 23 21 19 18
PP_VDD_MAIN
50 46

D 1 C3790 See 2831115 for C3791 removal CRITICAL


D
18UF
20%
2 6.3V
CER-X5R U3700 CRITICAL
0402-0.1MM D2462
ROOM=CAM_PMU
WLCSP L3700
SYM 1 OF 4
1UH-20%-2.5A-0.078OHM
J7 VDD_BUCK9 ROOM=CAM_PMU
BUCK9_LX0 H7 CAMPMU_BUCK_LX0 1 2 PP2V85_VAR_CAM_VCM_PVDD 29
J8 VDD_BUCK9 BUCK9_LX0 H8 PIWA20120H-SM
BUCK9_FB H5 ROOM=CAM_PMU
1 C3700 1 C3701 1 C3702
18UF 18UF 330PF
20% 20% 10%
XW3700
SHORT-20L-0.05MM-SM
2 6.3V
CER-X5R 2 6.3V
CER-X5R 2 16V
CER-X7R
VCC MAIN BUCKS
0402-0.1MM 0402-0.1MM 01005
CAMPMU_BUCK_FB 1 2 ROOM=CAM_PMU ROOM=CAM_PMU ROOM=CAM_PMU

ROOM=CAM_PMU
OMIT

C5 VDD_MAIN
E2 VDD_MAIN
G4 VDD_MAIN

U3700
D2462
WLCSP
C 50 38 34 21 19
PP_VDD_BOOST A1 VDD_LDO4_17 SYM 2 OF 4
VLDO4 B2
PP2V85_FCAM_AVDD 32 C
H2 VDD_LDO9 VLDO9 J2
PP_CAM_WIDE_ADC 29
1 C3795 1 C3796 PP1V1_CAM_TELE_JULIET_DVDD 35
4UF
20%
4UF
20%
1 C3704 1 C3709
2 6.3V
CERM-X5R 2 6.3V
CERM-X5R 20%
2.2UF 2.2UF
20%
Q3700
0201 0201 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
DMN1017UCP3
ROOM=CAM_PMU ROOM=CAM_PMU 0201 0201 X3-DSN1010-3
ROOM=CAM_PMU ROOM=CAM_PMU

PP1V25_S2 B6 VDD_LDO10 VLDO10 A6


PP1V1_CAM_TELE_DVDD

S
2

3
19 17 30
B5 VDD_LDO15 VLDO15 A5
PP1V1_FCAM_DVDD 32
1 C3797 1 C3798
4UF 4UF OMIT_TABLE

G
20%
2 4V
20%
2 4V
1 C3710 1 C3715 ROOM=CAM_PMU
X5R X5R 10UF 2.2UF

1
0201 0201 20% 20% CRITICAL
ROOM=CAM_PMU ROOM=CAM_PMU LDO INPUT LDO OUTPUT 2 10V
X5R-CERM 2 6.3V
X5R-CERM CAMPMU_TELE_DVDD_DISABLE_L
0402-0.1MM 0201 IN 28
ROOM=CAM_PMU ROOM=CAM_PMU

A2 VDD_LDO4_17 VLDO17 B1
PP2V85_CAM_TELE_AVDD 30 35
B4 VDD_LDO18 VLDO18 A4
PP1V1_CAM_WIDE_DVDD 29

1 C3717 1 C3718
2.2UF 2.2UF
20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201
ROOM=CAM_PMU
0201
ROOM=CAM_PMU

B3 VDD_LDO19 VLDO19 A3 PP1V8_HAWKING 33


A7 VDD_LDO20_21 VLDO20 B8
PP2V85_CAM_WIDE_AVDD 29
B B
1 C3719 1 C3720
2.2UF 2.2UF
20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201
ROOM=CAM_PMU
0201
ROOM=CAM_PMU

A8 VDD_LDO20_21 VLDO21 B7 PP3V3_SVDD 28 29 30 35


H1 VDD_LDO22 VLDO22 G1 PP_CAM_TELE_ADC 30

1 C3721 1 C3722
2.2UF 2.2UF
20% 20%
2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
0201
ROOM=CAM_PMU
0201
ROOM=CAM_PMU
For GPIO pullups only
30 29 28 17 16 14 10 8 7 6 5 PP1V8_IO H3 VBUCK3 BUCK3_SW1 J3
43 35 34 32 NC

SW INPUT SW OUTPUT
J4 VPUMP
NC

ON_BUF F2 CAMPMU_ON_BUF
C3750 1
0.22UF
20%
6.3V 2
X5R
01005
ROOM=CAM_PMU

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

CAMERA: PMU (1/2)


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
37 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 27 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Pull Downs
AP_TO_CAMPMU_RESET_L 11 28

1
R3801
100K
5%
1/32W
MF
2 01005
ROOM=CAM_PMU

D D

PP3V3_SVDD 27 29 30 35

1
R3820
100K
5%
U3700 1/32W
MF
D2462 01005
2 ROOM=CAM_PMU
WLCSP
R3802 35 34 31 8 IN
I2C3_ISP_SCL E8 SCL
SYM 3 OF 4
GPIO1 F6 CAMPMU_TO_STROBE_DRIVER_HWEN OUT 31
I2C3_ISP_SDA 1
33.2 2 I2C3_ISP_SDA_U3700 F8 E6
35 34 31 8 BI SDA I2C GPIO2 NC
1% GPIO3 D7
NC
1/32W
MF R3803 GPIO4 E4
NC
CAMPMU_TO_AP_IRQ_L 01005
1
49.9 2 CAMPMU_TO_AP_IRQ_R_L D8 D4
11 OUT IRQ* GPIO5 NC
1% GPIO6 D3 CAMPMU_TO_RIGEL_ENABLE 4 34
1/32W D6 CRASH*
OUT
MF NC RESET
GPIO9 F7 PP1V8_IO MAKE_BASE=TRUE PP1V8_IO 5 6 7 8 10 14 16 17 27 29 30 32
34 35 43
01005
28 11 IN
AP_TO_CAMPMU_RESET_L F5 RESET_IN GPIO10 F3 AP_TO_MANY_BSYNC IN 8 12 20 21 50
R3811
G3 YOGI_TO_RIGEL_STATUS_R 1
10K 2 YOGI_TO_RIGEL_STATUS
GPIO11 IN 34 36

CAMPMU_VREF C1 VREF GPIO12 G2 CAMPMU_TELE_DVDD_DISABLE_L OUT 27 5%


1/32W
GPIO15 E3 MAMA_BEAR_BI_RIGEL_STATUS_R MF
CAMPMU_IREF D1 IREF 01005
C E1 REFERENCE GPIO
ROOM=CAM_PMU C
CAMPMU_VRTC VRTC R3810
1
1 C3800 R3800 1 C3810 1
10K 2 MAMA_BEAR_BI_RIGEL_STATUS IN 34 35
0.22UF 200K 0.1UF 5%
20% 1% 20%
1/32W 1/32W
2 6.3V MF 2 6.3V J5 TDEV1 MF
X5R X5R NC 01005
01005 2 01005 01005 G5 TDEV2 ROOM=CAM_PMU
ROOM=CAM_PMU ROOM=CAM_PMU ROOM=CAM_PMU NC TEMPERATURE
C6 TCAL
NC

AMUX_AY C8 CAMPMU_TO_PMU_AMUX OUT 20

ATM E7

U3700
B D2462
WLCSP
B
C2 SYM 4 OF 4 G6
VSS VSS
C3 VSS VSS G7
C4 VSS VSS G8
C7 VSS VSS H4
D2 VSS VSS H6
D5 VSS VSS J1
E5 VSS VSS J6
F1 VSS VSS F4

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

CAMERA: PMU (2/2)


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
38 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 28 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Power Filtering
Wide Camera
Rcpt: 516S00313
Connector
<-- This one on MLB FL3901
33-OHM-25%-1500MA
Plug: 516S00314 PP2V85_VAR_CAM_VCM_PVDD 1 2
27 PP_CAM_VCM_PVDD_CONN 29 30
OMIT_TABLE
0201
ROOM=B2B_WIDE_RCAM
1 C3909
J3900 2.2UF
AA26DK-S026VA1 20%
F-ST-SM 2 6.3V
X5R-CERM
31
0201
29
PP1V1_CAM_WIDE_DVDD_CONN 27 28 PP1V1_CAM_WIDE_DVDD_CONN 29 FL3995 ROOM=B2B_WIDE_RCAM

10-OHM-750MA
D 1 2 30 28 27 17 16 14 10 8 7 6 5
PP1V8_IO 1 2 PP1V8_CAM_WIDE_VDDIO_CONN 29
D
43 35 34 32
90_LPDP_WIDE_TO_AP_D0_CONN_N GND_VOID 3 4 01005-1
29
90_LPDP_WIDE_TO_AP_D0_CONN_P GND_VOID 5 6 LPDP_WIDE_BI_AP_AUX_CONN ROOM=B2B_WIDE_RCAM
1 C3995 1 C3996
29 29
0.1UF 220PF
7 8 I2C0_ISP_BI_WIDE_RCAM_OIS_SDA_CONN 29
20% 5%
90_LPDP_WIDE_TO_AP_D1_CONN_N GND_VOID 9 10 I2C0_ISP_TO_WIDE_RCAM_OIS_SCL_CONN 2 6.3V
X5R-CERM 2 10V
C0G-CERM
29 29 01005 01005
29
90_LPDP_WIDE_TO_AP_D1_CONN_P GND_VOID 11 12 WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN 29 30
ROOM=B2B_WIDE_RCAM ROOM=B2B_WIDE_RCAM

13 14 AP_TO_WIDE_SHUTDOWN_CONN_L 29 35 30 29 28 27
PP3V3_SVDD
29
90_LPDP_WIDE_TO_AP_D2_CONN_N GND_VOID 15 16 WIDE_TO_TELE_SYNC_J3900_CONN 30

29
90_LPDP_WIDE_TO_AP_D2_CONN_P GND_VOID 17 18 PP1V8_CAM_WIDE_VDDIO_CONN 29 29 27
PP2V85_CAM_WIDE_AVDD
19 20 PP_CAM_VCM_PVDD_CONN 29 30 29 27
PP_CAM_WIDE_ADC
29
AP_TO_WIDE_CLK_CONN 21 22 PP3V3_SVDD 27 28 29 30 35 30 29 PP_CAM_VCM_PVDD_CONN
23 24 PP2V85_CAM_WIDE_AVDD
25 26 PP_CAM_WIDE_ADC
27 29
1 C3990 1 C3991 1 C3992 1 C3994
27 29
220PF 220PF 220PF 220PF
5% 5% 5% 5%
29 30 2 10V
C0G-CERM 2 10V
C0G-CERM 2 10V
C0G-CERM 2 10V
C0G-CERM
01005 01005 01005 01005
32 ROOM=B2B_WIDE_RCAM ROOM=B2B_WIDE_RCAM ROOM=B2B_WIDE_RCAM ROOM=B2B_WIDE_RCAM

ROOM=B2B_WIDE_RCAM

FL3903
33-OHM-25%-1500MA
27
PP1V1_CAM_WIDE_DVDD 1 2
PP1V1_CAM_WIDE_DVDD_CONN 29
OMIT_TABLE NOSTUFF
0201
ROOM=B2B_TELE_CAM 1 C3925 1 C3993 1 C3928
2.2UF 220PF 15PF
20% 5% 5%
2 6.3V
X5R-CERM 2 10V
C0G-CERM 2 16V
NP0-C0G-CERM
0201 01005 01005
ROOM=B2B_TELE_RCAM ROOM=B2B_WIDE_RCAM ROOM=B2B_WIDE_RCAM

C ISP I2C C
LPDP Filters
R3900 C3930
I2C0_ISP_SCL 1
0.00 2 I2C0_ISP_TO_WIDE_RCAM_OIS_SCL_CONN
8 IN 29 0.1UF
0%
CKPLUS_WAIVE=I2C_PULLUP
90_LPDP_WIDE_TO_AP_D0_P 1 2 90_LPDP_WIDE_TO_AP_D0_CONN_P
1/32W
MF
1 C3900 9 BI
ROOM=B2B_WIDE_RCAM GND_VOID=TRUE
29

01005 56PF 20%


ROOM=B2B_WIDE_RCAM
5% 6.3V
2 25V
NP0-C0G-CERM
X5R-CERM
01005
01005
ROOM=B2B_WIDE_RCAM
C3931
R3901 90_LPDP_WIDE_TO_AP_D0_N
0.1UF
1 2 90_LPDP_WIDE_TO_AP_D0_CONN_N
I2C0_ISP_SDA 1
0.00 2 I2C0_ISP_BI_WIDE_RCAM_OIS_SDA_CONN 9 BI 29
8 BI 29 ROOM=B2B_WIDE_RCAM GND_VOID=TRUE
CKPLUS_WAIVE=I2C_PULLUP 20%
0%
1/32W 6.3V
MF
01005
1 C3901 X5R-CERM
01005
ROOM=B2B_WIDE_RCAM
56PF
5%
2 25V
NP0-C0G-CERM
C3940
01005 0.1UF
ROOM=B2B_WIDE_RCAM
9 IN
90_LPDP_WIDE_TO_AP_D1_P 1 2 90_LPDP_WIDE_TO_AP_D1_CONN_P 29
ROOM=B2B_WIDE_RCAM GND_VOID=TRUE
20%
6.3V
X5R-CERM
01005

C3941
0.1UF
9 IN
90_LPDP_WIDE_TO_AP_D1_N 1 2 90_LPDP_WIDE_TO_AP_D1_CONN_N 29
GND_VOID=TRUE
ROOM=B2B_WIDE_RCAM
20%
B 6.3V
X5R-CERM
01005
B
C3950
0.1UF
9 IN
90_LPDP_WIDE_TO_AP_D2_P 1 2 90_LPDP_WIDE_TO_AP_D2_CONN_P 29
ROOM=B2B_WIDE_RCAM GND_VOID=TRUE

IO Filters 20%
6.3V
X5R-CERM
01005

R3905 C3951
49.9 0.1UF
8
AP_TO_WIDE_CLK 1 2 AP_TO_WIDE_CLK_CONN 29 9
90_LPDP_WIDE_TO_AP_D2_N 1 2 90_LPDP_WIDE_TO_AP_D2_CONN_N 29
IN IN
NOSTUFF GND_VOID=TRUE
1%
1/32W
MF
1 C3906 ROOM=B2B_WIDE_RCAM
20%
6.3V
01005 56PF X5R-CERM
ROOM=B2B_WIDE_RCAM 5% 01005
2 25V
NP0-C0G-CERM
01005 C3960
ROOM=B2B_WIDE_RCAM
0.1UF
LPDP_WIDE_BI_AP_AUX 1 2 LPDP_WIDE_BI_AP_AUX_CONN
9 BI 29

20%
6.3V
1 C3961
X5R-CERM 56PF
01005 5%
ROOM=B2B_WIDE_RCAM
2 25V
NP0-C0G-CERM
R3907 01005
AP_TO_WIDE_SHUTDOWN_L 1
0.00 2 AP_TO_WIDE_SHUTDOWN_CONN_L
ROOM=B2B_WIDE_RCAM
8 IN 29

0%
1/32W
MF
1 C3907
01005 220PF
ROOM=B2B_WIDE_RCAM 5%
2 10V
C0G-CERM
A 01005
ROOM=B2B_WIDE_RCAM
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

R3908
CAMERA: B2B Wide (WY)
DRAWING NUMBER SIZE
WIDE_AND_TELE_TO_STROBE_DRIVER_STROBE 0.00 WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN
31 OUT
1 2 29 30 051-02221 D
0% Apple Inc.
1/32W
MF
1 C3908 REVISION

9.0.0
01005 220PF
ROOM=B2B_WIDE_RCAM
5% NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 10V
C0G-CERM
01005 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
evt-1
ROOM=B2B_WIDE_RCAM
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
39 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 29 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Tele Camera Connector


Rcpt: 516S00313 <-- This one on MLB
Plug: 516S00314
Power Filtering
ROOM=B2B_TELE_RCAM
FL4001
J4000 10-OHM-750MA
AA26DK-S026VA1 PP1V8_IO PP1V8_CAM_TELE_VDDIO_CONN
F-ST-SM 29 28 27 17 16 14 10 8 7 6 5
1 2 30
31 43 35 34 32
01005-1
30
PP1V1_CAM_TELE_DVDD_CONN 27 28 PP1V1_CAM_TELE_DVDD_CONN 30 ROOM=B2B_TELE_RCAM
1 C4017 1 C4096
D 20%
0.1UF
5%
220PF D
30
90_LPDP_TELE_TO_AP_D0_CONN_N GND_VOID 1 2 2 6.3V
X5R-CERM 2 10V
C0G-CERM
30
90_LPDP_TELE_TO_AP_D0_CONN_P GND_VOID 3 4 01005 01005
ROOM=B2B_TELE_RCAM ROOM=B2B_TELE_RCAM
5 6 LPDP_TELE_BI_AP_AUX_CONN 30 PP3V3_SVDD
30
90_LPDP_TELE_TO_AP_D1_CONN_N GND_VOID 7 8 WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN 29 30
35 30 29 28 27

30
90_LPDP_TELE_TO_AP_D1_CONN_P GND_VOID 9 10 I2C1_ISP_TO_TELE_RCAM_OIS_SCL_CONN 30 PP2V85_CAM_TELE_AVDD
11 12 I2C1_ISP_BI_TELE_RCAM_OIS_SDA_CONN 30
35 30 27
PP_CAM_TELE_ADC
30
90_LPDP_TELE_TO_AP_D2_CONN_N GND_VOID 13 14 30 27

90_LPDP_TELE_TO_AP_D2_CONN_P GND_VOID 15 16 AP_TO_TELE_SHUTDOWN_CONN_L 30 29 PP_CAM_VCM_PVDD_CONN


30 30

30
AP_TO_TELE_CLK_CONN 17 18 WIDE_TO_TELE_SYNC_J4000_CONN 30
1 C4090 1 C4091 1 C4092 1 C4094
19 20 PP3V3_SVDD 27 28 29 30 35
220PF 220PF 220PF 220PF
5% 5% 5% 5%
21 22 PP1V8_CAM_TELE_VDDIO_CONN 30 2 10V 2 10V 2 10V 2 10V
C0G-CERM C0G-CERM C0G-CERM C0G-CERM
30 27 PP_CAM_TELE_ADC 23 24 01005 01005 01005 01005
ROOM=B2B_TELE_RCAM ROOM=B2B_TELE_RCAM ROOM=B2B_TELE_RCAM ROOM=B2B_TELE_RCAM
35 30 27 PP2V85_CAM_TELE_AVDD 25 26

30 29 PP_CAM_VCM_PVDD_CONN 29 30 PP_CAM_VCM_PVDD_CONN 29 30
32 FL4003
33-OHM-25%-1500MA
27
PP1V1_CAM_TELE_DVDD 1 2
PP1V1_CAM_TELE_DVDD_CONN 30
OMIT_TABLE NOSTUFF
0201
R4003 1 ROOM=B2B_TELE_CAM 1 C4025 1 C4093 1 C4028
20K 2.2UF 220PF 15PF
1% 20% 5% 5%
2 6.3V 2 10V 2 16V
ISP I2C 1/32W
MF
01005 2
ROOM=B2B_TELE_CAM
X5R-CERM
0201
ROOM=B2B_TELE_RCAM
C0G-CERM
01005
ROOM=B2B_TELE_RCAM
NP0-C0G-CERM
01005
ROOM=B2B_TELE_RCAM

R4000
0.00
C 8 IN
I2C1_ISP_SCL 1 2 I2C1_ISP_TO_TELE_RCAM_OIS_SCL_CONN
CKPLUS_WAIVE=I2C_PULLUP
30 C
0%
1/32W
MF
01005
1

5%
C4000
56PF
LPDP
ROOM=B2B_TELE_RCAM
2 25V
NP0-C0G-CERM
01005 C4030
ROOM=B2B_TELE_RCAM
0.1UF
90_LPDP_TELE_TO_AP_D0_P 1 2 90_LPDP_TELE_TO_AP_D0_CONN_P
R4001 9 BI
GND_VOID
30

I2C1_ISP_SDA 1
0.00 2 I2C1_ISP_BI_TELE_RCAM_OIS_SDA_CONN
ROOM=B2B_TELE_RCAM
20%
8 BI 30
6.3V
0% CKPLUS_WAIVE=I2C_PULLUP X5R-CERM
1/32W
MF
1 C4001 01005
56PF
01005
ROOM=B2B_TELE_RCAM
5% C4031
2 25V
NP0-C0G-CERM 0.1UF
01005 9 BI
90_LPDP_TELE_TO_AP_D0_N 1 2 90_LPDP_TELE_TO_AP_D0_CONN_N 30
ROOM=B2B_TELE_RCAM
ROOM=B2B_TELE_RCAM
GND_VOID
20%
6.3V
X5R-CERM
01005

C4040
0.1UF
9 OUT
90_LPDP_TELE_TO_AP_D1_P 1 2 90_LPDP_TELE_TO_AP_D1_CONN_P 30
ROOM=B2B_TELE_RCAM
GND_VOID
20%
6.3V
X5R-CERM
01005

C4041
0.1UF
9 OUT
90_LPDP_TELE_TO_AP_D1_N 1 2 90_LPDP_TELE_TO_AP_D1_CONN_N 30
ROOM=B2B_TELE_RCAM
GND_VOID
20%
B 6.3V
X5R-CERM B
IO Filters 01005

C4050
0.1UF
90_LPDP_TELE_TO_AP_D2_P 1 2 90_LPDP_TELE_TO_AP_D2_CONN_P
R4005 9 OUT
ROOM=B2B_TELE_RCAM
30

AP_TO_TELE_CLK 1
49.9 2 AP_TO_TELE_CLK_CONN 20% GND_VOID
8 IN 30
6.3V
1% NOSTUFF X5R-CERM
1/32W
MF
1 C4006 01005
56PF
01005
ROOM=B2B_TELE_RCAM
5% C4051
2 25V
NP0-C0G-CERM 0.1UF
01005 9 OUT
90_LPDP_TELE_TO_AP_D2_N 1 2 90_LPDP_TELE_TO_AP_D2_CONN_N 30
ROOM=B2B_TELE_RCAM
ROOM=B2B_TELE_RCAM GND_VOID
20%
6.3V
X5R-CERM
01005
R4007
AP_TO_TELE_SHUTDOWN_L 1
0.00 2 AP_TO_TELE_SHUTDOWN_CONN_L C4060
8 IN 30

0%
0.1UF
1/32W
MF
1 C4007 9 OUT
LPDP_TELE_BI_AP_AUX 1 2 LPDP_TELE_BI_AP_AUX_CONN 30

01005 220PF
ROOM=B2B_TELE_RCAM
5%
2 10V
ROOM=B2B_TELE_RCAM
20%
6.3V
1 C4061
C0G-CERM
01005
X5R-CERM 56PF
01005 5%
ROOM=B2B_TELE_RCAM
2 25V
NP0-C0G-CERM
01005
ROOM=B2B_TELE_RCAM

30 29 BI
WIDE_AND_TELE_TO_LED_DRIVER_STROBE_EN_CONN
1 C4008
220PF
5%
2 10V
C0G-CERM
A 01005
ROOM=B2B_TELE_RCAM SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

R4010
CAMERA: B2B Tele (MT)
DRAWING NUMBER SIZE
WIDE_TO_TELE_SYNC_J3900_CONN 0.00 WIDE_TO_TELE_SYNC_J4000_CONN
29 IN
1 2 30 051-02221 D
0% Apple Inc.
1/32W
MF
1 C4010 REVISION

9.0.0
01005 220PF
ROOM=B2B_TELE_RCAM
5% NOTICE OF PROPRIETARY PROPERTY: BRANCH
2 10V
C0G-CERM
01005 THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
evt-1
ROOM=B2B_TELE_RCAM
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
40 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 30 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D
LED STROBE DRIVERS (NEON)
APN:353S00558
I2C Address (7-bit): 0x63

45 43 42 41 34 27 23 21 19 18
PP_VDD_MAIN PP_LED1_BOOST_OUT
50 46

C4191 1 C4192 1
1 1 C4105 1 C4106
18UF 220PF
20%
6.3V 2
5%
10V 2
CRITICAL 220PF 18UF
5% 20%
CER-X5R
0402-0.1MM
C0G-CERM
01005 L4100 2 10V
C0G-CERM 2 6.3V
CER-X5R
ROOM=STROBE ROOM=STROBE
1UH-20%-3.6A-0.062OHM U4100 01005 0402-0.1MM
0806 ROOM=STROBE ROOM=STROBE
ROOM=STROBE
LM3566
DSBGA
A2 IN
ROOM=STROBE2
OUT C1
2
CRITICAL
LED_DRIVER1_LX B1 SW LED1 D3
PP_STROBE_COOL_WIDE_LED 33

31 28
CAMPMU_TO_STROBE_DRIVER_HWEN C2 HWEN
IN
INT 300K PD

31 29
WIDE_AND_TELE_TO_STROBE_DRIVER_STROBE B2 STROBE LED2 D1
PP_STROBE_WARM_ZOOM_LED 33
IN
INT 300K PD

BB_TO_STROBE_DRIVER_GSM_BURST_IND D2 TX INT
1 C4102 1 C4101
50 36 31 IN 300K PD
220PF 220PF
35 34 31 28 8 BI
I2C3_ISP_SDA A3 SDA 5% 5%
I2C3_ISP_SCL B3 SCL STROBE_MODULE_NTC 2 10V 2 10V
35 34 31 28 8 IN TORCH/TEMP C3 31 33
C0G-CERM
01005
C0G-CERM
01005
ROOM=STROBE ROOM=STROBE
GND

A1
C C

APN:353S00868
I2C Address (7-bit): 0x67

PP_LED2_BOOST_OUT
C4196 1
1
1 C4125 1 C4126
18UF 220PF 18UF
20% CRITICAL 5% 20%
6.3V 2 2 10V 2 6.3V
CER-X5R C0G-CERM CER-X5R
0402-0.1MM L4120 01005 0402-0.1MM
ROOM=STROBE2
1UH-20%-3.6A-0.062OHM U4120 ROOM=STROBE ROOM=STROBE2

0806 LM35662
ROOM=STROBE2
DSBGA
A2 IN
ROOM=STROBE2
OUT C1
2
CRITICAL
LED_DRIVER2_LX B1 SW LED1 D3
PP_STROBE_COOL_ZOOM_LED 33

31 28
CAMPMU_TO_STROBE_DRIVER_HWEN C2 HWEN
IN
INT 300K PD

31 29 WIDE_AND_TELE_TO_STROBE_DRIVER_STROBE B2 STROBE LED2 D1


PP_STROBE_WARM_WIDE_LED 33
IN
INT 300K PD

BB_TO_STROBE_DRIVER_GSM_BURST_IND D2 TX INT
1 C4122 1 C4121
50 36 31 IN 300K PD
220PF 220PF
35 34 31 28 8 BI
I2C3_ISP_SDA A3 SDA 5% 5%
I2C3_ISP_SCL B3 SCL STROBE_MODULE_NTC 2 10V 2 10V
35 34 31 28 8 IN TORCH/TEMP C3 31 33
C0G-CERM
01005
C0G-CERM
01005
ROOM=STROBE2 ROOM=STROBE2
GND
B B

A1

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

CAMERA: Strobe Drivers


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
41 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 31 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

NEW HAMPSHIRE POWER FCAM Connector


FL4200 Rcpt: 516S00244 <-- This one on MLB
10-OHM-750MA Plug: 516S00245
43 35
16 14 10 8 7 6 5
PP1V8_IO 1 2 PP1V8_FCAM_VDDIO_CONN 32
34 30 29 28 27 17
01005-1
ROOM=B2B_FCAM
1 C4200 1 C4201 J4200
0.1UF BB35K-RA18-3A
20% 220PF F-ST-SM
2 6.3V
X5R-CERM
5%
01005 2 10V
C0G-CERM 23
01005
ROOM=B2B_FCAM
ROOM=B2B_FCAM
32
PP1V1_FCAM_DVDD_CONN 19 20

D FL4202 D
1 2
10-OHM-750MA
PP1V1_FCAM_DVDD 90_MIPI_FCAM_TO_AP_DATA0_P 3 4 I2C2_ISP_TO_FCAM_SAVAGE_SCL_CONN
1 2 PP1V1_FCAM_DVDD_CONN 8 BI 32 35
27 32
8 BI
90_MIPI_FCAM_TO_AP_DATA0_N 5 6 I2C2_ISP_BI_FCAM_SAVAGE_SDA_CONN 32 35
01005-1
7 8 PP1V8_FCAM_VDDIO_CONN
ROOM=B2B_FCAM
1 C4202 1 C4203 90_MIPI_FCAM_TO_AP_CLK_P 9 10
32

0.1UF 220PF 8 OUT


20% 5% 8 90_MIPI_FCAM_TO_AP_CLK_N 11 12 PP2V85_FCAM_AVDD_CONN 32
2 6.3V 2 10V
OUT
X5R-CERM
01005
C0G-CERM
01005
13 14 AP_TO_FCAM_SHUTDOWN_CONN_L 32
ROOM=B2B_FCAM
ROOM=B2B_FCAM
8 90_MIPI_FCAM_TO_AP_DATA1_P 15 16 FCAM_TO_JULIET_SYNC_J4200 32
OUT
90_MIPI_FCAM_TO_AP_DATA1_N 17 18 AP_TO_FCAM_CLK_CONN
FL4204 8 OUT 32

10-OHM-750MA
21 22
27
PP2V85_FCAM_AVDD 1 2 PP2V85_FCAM_AVDD_CONN 32
24
01005-1
ROOM=B2B_FCAM
1 C4204 1 C4205 ROOM=B2B_FCAM
0.1UF 220PF
20% 5%
2 6.3V
X5R-CERM 2 10V
C0G-CERM
01005 01005
ROOM=B2B_FCAM ROOM=B2B_FCAM

FCAM I/O
R4210
AP_TO_FCAM_JULIET_CLK 1
0.00 2 AP_TO_FCAM_CLK_CONN
35 8 IN 32

0%
1 C4210 1/32W
MF
C 5%
56PF
ROOM=B2B_FCAM
01005 C
2 25V
NP0-C0G-CERM
01005
ROOM=B2B_FCAM

R4211
AP_TO_FCAM_SHUTDOWN_L 1
0.00 2 AP_TO_FCAM_SHUTDOWN_CONN_L
8 4 IN 32

0%
1/32W
MF
1 C4211
01005 220PF
ROOM=B2B_FCAM
5%
2 10V
C0G-CERM
01005
ROOM=B2B_FCAM

R4212
FCAM_TO_JULIET_SYNC_J4530 1
0.00 2 FCAM_TO_JULIET_SYNC_J4200
35 OUT 32

0%
1/32W
MF
1 C4212
01005 100PF
ROOM=B2B_FCAM
5%
2 16V
NP0-C0G
01005
ROOM=B2B_FCAM

ISP I2C2
R4220
I2C2_ISP_SCL 1
0.00 2 I2C2_ISP_TO_FCAM_SAVAGE_SCL_CONN
8 IN 32 35

B 0%
1/32W 1 C4220
CKPLUS_WAIVE=I2C_PULLUP
B
MF
01005 56PF
ROOM=B2B_FCAM
5%
2 25V
NP0-C0G-CERM
01005
ROOM=B2B_FCAM

R4221
I2C2_ISP_SDA 1
0.00 2 I2C2_ISP_BI_FCAM_SAVAGE_SDA_CONN
8 BI 32 35

0% CKPLUS_WAIVE=I2C_PULLUP
1/32W
MF
1 C4221
01005 56PF
ROOM=B2B_FCAM
5%
2 25V
NP0-C0G-CERM
01005
ROOM=B2B_FCAM

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

CAMERA: B2B FCAM


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
42 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 32 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

HAWKING
C4300 Strobe Connector
0.22UF Rcpt: 516S00267 <-- This one on MLB
37 OUT
HAWKING_TO_CODEC_AIN5_N 1 2 GND 33 Plug: 516S00268
10%
6.3V
CER-X5R J4300
01005 AA36D-S010VA1
ROOM=B2B_STROBE F-ST-SM
15 16

C4301 FL4301 D
D 0.22UF 150OHM-25%-200MA-0.7DCR
11 PWR 12 PP_STROBE_COOL_WIDE_LED
37 OUT
HAWKING_TO_CODEC_AIN5_P 1 2 HAWKING_TO_CODEC_AIN5_C_P 1 2 HAWKING_TO_CODEC_AIN5_P_CONN 33
31 33

01005 SIGNAL
10%
6.3V
CKPLUS_WAIVE=MISS_N_DIFFPAIR
ROOM=B2B_STROBE
1 C4302 33
REARMIC2_TO_CODEC_AIN2_CONN_P 1 2 I2C1_AP_BI_MIC2_SDA 33
CER-X5R 56PF 33
REARMIC2_TO_CODEC_AIN2_CONN_N 3 4 I2C1_AP_TO_MIC2_SCL 33
01005 5%
ROOM=B2B_STROBE 2 25V
NP0-C0G-CERM 33
PP_CODEC_TO_REARMIC2_BIAS_CONN 5 6 PP1V8_HAWKING_CONN 33
01005 38
REARMIC2_TO_CODEC_BIAS_FILT_RET 7 8 HAWKING_TO_CODEC_AIN5_P_CONN 33
ROOM=B2B_STROBE
BUTTON_POWER_KEY_CONN_L 9 10 STROBE_MODULE_NTC_CONN
FL4303 33 33

150OHM-25%-200MA-0.7DCR PWR
PP_STROBE_WARM_ZOOM_LED 13 14 PP_STROBE_WARM_WIDE_LED
27
PP1V8_HAWKING 1 2 PP1V8_HAWKING_CONN 33
33 31 31 33

OMIT_TABLE
01005
ROOM=B2B_STROBE
1 C4303 1 C4304
2.2UF 220PF 33 31
PP_STROBE_COOL_ZOOM_LED 17 18 PP_STROBE_COOL_ZOOM_LED 31 33
20% 5%
2 6.3V
X5R-CERM 2 10V
C0G-CERM
0201 01005 ROOM=B2B_STROBE
ROOM=B2B_STROBE ROOM=B2B_STROBE

33
GND

MIC2 (ANC REF) GND


FL4305
150OHM-25%-200MA-0.7DCR
MAKE_BASE=TRUE
38
PP_CODEC_TO_REARMIC2_BIAS 2 1 PP_CODEC_TO_REARMIC2_BIAS_CONN 33
01005
ROOM=B2B_STROBE
1 C4305
220PF
5%
2 10V
C0G-CERM
C 01005
ROOM=B2B_STROBE C
FL4306
150OHM-25%-200MA-0.7DCR
37 OUT
REARMIC2_TO_CODEC_AIN2_P 2 1 REARMIC2_TO_CODEC_AIN2_CONN_P 33
01005
ROOM=B2B_STROBE
1 C4306
56PF
5%
2 25V
NP0-C0G-CERM
01005
ROOM=B2B_STROBE

FL4307
150OHM-25%-200MA-0.7DCR
37 OUT
REARMIC2_TO_CODEC_AIN2_N 2 1 REARMIC2_TO_CODEC_AIN2_CONN_N 33
01005
ROOM=B2B_STROBE
1 C4307
56PF
5%
2 25V
NP0-C0G-CERM
01005
Power Key Button ROOM=B2B_STROBE

R4310
BUTTON_POWER_KEY_L 100
1 2 BUTTON_POWER_KEY_CONN_L
20 OUT

C4310
27PF
1 5%
1/32W
MF
1
33

Strobe Filtering
5%
6.3V
01005
ROOM=B2B_STROBE
DZ4310
NP0-C0G 2 5.5V-6.2PF PP_STROBE_WARM_ZOOM_LED
0201 0201 31 33
ROOM=B2B_STROBE ROOM=B2B_STROBE
2
C4320 1
220PF
B 5%
10V 2 B
C0G-CERM
01005
ROOM=B2B_STROBE

R4308
PP_STROBE_COOL_WIDE_LED I2C1_AP_SCL 1
0.00 2 I2C1_AP_TO_MIC2_SCL
31 33 49 10 IN 33

0%
C4322 1 1/32W
MF
1 C4308
220PF 01005 56PF
5% ROOM=B2B_STROBE
5%
10V
C0G-CERM 2 2 25V
NP0-C0G-CERM
01005 01005
ROOM=B2B_STROBE
ROOM=B2B_STROBE

PP_STROBE_WARM_WIDE_LED 31 33
R4309
I2C1_AP_SDA 2
0.00 1 I2C1_AP_BI_MIC2_SDA
C4324 1 49 10 IN
0%
33

220PF
5%
1/32W
MF
1 C4309
10V
C0G-CERM 2 01005 56PF
ROOM=B2B_STROBE
5%
01005
ROOM=B2B_STROBE
2 25V
NP0-C0G-CERM
01005
ROOM=B2B_STROBE

PP_STROBE_COOL_ZOOM_LED 31 33

C4326 1
220PF
5%
10V
C0G-CERM 2
A 01005
ROOM=B2B_STROBE
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
FL4330 PAGE TITLE

STROBE_MODULE_NTC
150OHM-25%-200MA-0.7DCR
1 2 STROBE_MODULE_NTC_CONN
CAMERA: B2B Strobe + Hold Button
31 OUT 33 DRAWING NUMBER SIZE
01005 051-02221 D
R4330 1 ROOM=B2B_STROBE
1 C4330 Apple Inc. REVISION
27K 220PF
0.5%
1/32W 5% 9.0.0
MF 2 10V
C0G-CERM NOTICE OF PROPRIETARY PROPERTY: BRANCH
01005 2
ROOM=B2B_STROBE
01005
ROOM=B2B_STROBE
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
43 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 33 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Rigel Driver 45 43 42 41 31 27 23 21 19 18
50 46
PP_VDD_MAIN
1 C4497 C4494 1
18UF 4UF
20% 20%
6.3V 6.3V
2 CER-X5R CERM-X5R 2
0402-0.1MM 0201
ROOM=RIGEL ROOM=RIGEL

C4493 1
4UF
20%
6.3V
CERM-X5R 2
D 0201
ROOM=RIGEL
D

C4492 1
4UF
20%
6.3V
CERM-X5R 2
0201
ROOM=RIGEL

C4491 1
4UF
Terminate @ Cap via on VDD_MAIN plane. 20%
6.3V
OMIT CERM-X5R 2
0201
XW4400
SHORT-20L-0.05MM-SM
ROOM=RIGEL

2 1 PP_RIGEL_VINCORE
ROOM=RIGEL
C4490 1
1.0UF
20%
10V
X5R-CERM 2
0201-1
ROOM=RIGEL

PP1V8_IO
C 29 28 27 17 16 14 10 8 7 6 5
43 35 32 30
PP_VANA
C
50 38 27 21 19
PP_VDD_BOOST
1 C4495 1 C4496 1 C4498
1.0UF 1.0UF 4UF
20% 20% 20%
10V 10V
2 6.3V

VINSUA A10

VINSDA F10
2 X5R-CERM 2 X5R-CERM

VCC4 G9
VCC3 G2

VIN_LVT H8

VDDIO C5

VANA H4

VINVCORE2 H5

VINSDB E2

VINSUB A3
VINSUB A2
VINSUB A1

VINSUA A9
VINSUA A8

VINSDA E9
VINCORE F5

VINSDB F2
VINSDB F1

VINSDA F9
CERM-X5R
0201-1 0201-1 0201
ROOM=RIGEL ROOM=RIGEL ROOM=RIGEL

PP_RIGEL_BUCK_BOOST_A
35 4
PP_ROMEO_CATHODE K4 VK VBBOUTA H10 1 C4400 1 C4401
K5 VK VBBOUTA J10 4.7UF 220PF
K6 VK VBBOUTA K10 L4400 20%
16V
2 X5R
5%
2 10V
CRITICAL 0.47UH-20%-4A-0.048OHM C0G-CERM
K7 0402 01005
K8
VK U4400 VLXA D10 RIGEL_VLXA 1 2 ROOM=RIGEL ROOM=RIGEL
VK STB600B0 D9 PIWA20120H-SM
VLXA
ROMEO_TO_RIGEL_VCSEL_NTC G4 NTC
WLCSP
ROOM=RIGEL VLXA E10
1 C4405 ROOM=RIGEL
35 IN 4.7UF
20%
C4 B10
OTPHV VCXA
B9
2 16V
X5R 1 C4420
D4 VCXA RIGEL_VCXA 0402
ROOM=RIGEL 0.01UF
TAMP 10%
BOOSTSDA E8 RIGEL_BOOSTSDA 2 6.3V
28 4
CAMPMU_TO_RIGEL_ENABLE B3 ENA
X5R
01005
IN
BULKSDA D8 RIGEL_BULKSDA ROOM=RIGEL
36 28 BI
YOGI_TO_RIGEL_STATUS C8 XEF1
35 28
MAMA_BEAR_BI_RIGEL_STATUS C7 XEF0 BULKSDB D3 RIGEL_BULKSDB
BI
B8 THROT BOOSTSDB E3 RIGEL_BOOSTSDB
JULIET_PMU_TO_RIGEL_STROBE A4 STROBE
1 C4421
35 11 IN
VCXB B1 RIGEL_VCXB 0.01UF
B B7 TESTMODE VCXB B2 1 C4410
10%
2 6.3V
X5R B
4.7UF 01005
B5 TESTMODE2 VLXB D1 20% ROOM=RIGEL L4401
VLXB D2 2 16V
X5R 0.47UH-20%-4A-0.048OHM
B6 TEST
VLXB E1 RIGEL_VLXB 0402
ROOM=RIGEL 1 2
AP_TO_RIGEL_CLK A7 MCLK PIWA20120H-SM
8 IN
VBBOUTB J1 ROOM=RIGEL 1 C4411 1 C4412
20 8 4
RIGEL_TO_ISP_INT B4 INT VBBOUTB J2 4.7UF 220PF
OUT 20% 5%
J3 PP_RIGEL_BUCK_BOOST_B
R4400 35 31 28 8 IN
I2C3_ISP_SCL A5 SCL
VBBOUTB 16V
2 X5R
0402
2 10V
C0G-CERM
01005
I2C3_ISP_SDA 1
33.2 2 I2C3_ISP_SDA_U4400 A6 H9 ROOM=RIGEL ROOM=RIGEL
35 31 28 8 IN SDA IOUT0
1% IOUT0 K9
1/32W G5 PD0
MF IOUT0 J9 PP_ROMEO_DENSE_ANODE 4 35
01005 G6 PD1
IOUT1 H1
RIGEL_LSCP H7 LSCP
IOUT1 H2
C4422 1 IOUT1 H3 PP_ROMEO_SPARSE_ANODE 35
0.01UF
10% IOUT2 K1
6.3V
X5R 2 IOUT2 K2
01005
ROOM=RIGEL IOUT2 K3 PP_ROSALINE_ANODE 36

IOUT3 G1 PP_ROMEO_A_ANODE 35

IOUT4 G10 PP_ROMEO_B_ANODE


GNDCORE4
GNDCORE3
GNDCORE2

35
GNDCORE
PGNDK
PGNDK
PGNDK
PGNDK
PGNDK

PGNDB
PGNDB

PGNDA
PGNDA
GNDD

GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
GNDS
J8
J7
J6
J5
J4

G8
G3
H6

F6

C6

G7
E6
F8
E5
F3
D7
D6
D5
C3

C2
C1

C9
C10
A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

PEARL: Power
DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
44 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 34 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Romeo Connector
Romeo Power Filtering Rcpt: 516S00267
Plug: 516S00268
<-- This one on MLB

PP_ROMEO_B_ANODE
35 34

35 34
PP_ROMEO_A_ANODE J4500
35 34 4
PP_ROMEO_DENSE_ANODE AA36D-S010VA1
PP_ROMEO_SPARSE_ANODE F-ST-SM
35 34 PP_ROMEO_DENSE_ANODE 15 16 PP_ROMEO_DENSE_ANODE 4
35 34 4
PP_ROMEO_CATHODE 35 34 4 34 35

D 35 30 29 28 27
PP3V3_SVDD D
35 34 4
PP_ROMEO_CATHODE 11 PWR 12 PP_ROMEO_CATHODE 4 34 35

1 C4592 1 C4593 1 C4594 1 C4595 1 C4596 1 C4597 35 34


PP_ROMEO_B_ANODE 1 SIGNAL 2
220PF 220PF 220PF 220PF 220PF 220PF 35 34
PP_ROMEO_A_ANODE 3 4 I2C3_ISP_TO_MAMA_BEAR_SCL_CONN 35
5% 5% 5% 5% 5% 5%
2 10V 2 10V 2 10V 2 10V 2 10V 2 10V 5 6 MAMA_BEAR_BI_RIGEL_STATUS_CONN 35
C0G-CERM C0G-CERM C0G-CERM C0G-CERM C0G-CERM C0G-CERM
01005 01005 01005 01005 01005 01005 35
ROMEO_TO_AOP_B2B_DETECT_CONN 7 8 ROMEO_TO_RIGEL_VCSEL_NTC_CONN 35
ROOM=B2B_PEARL ROOM=B2B_PEARL ROOM=B2B_PEARL ROOM=B2B_PEARL ROOM=B2B_PEARL ROOM=B2B_PEARL
35
I2C3_ISP_BI_MAMA_BEAR_SDA_CONN 9 10 PP3V3_SVDD 27 28 29 30 35

PP_ROMEO_CATHODE PWR PP_ROMEO_CATHODE 4


Romeo I/O 35 34 4
13 14 34 35

FL4554 ROOM=B2B_PEARL
150OHM-25%-200MA-0.7DCR 35 34
PP_ROMEO_SPARSE_ANODE 17 18 PP_ROMEO_SPARSE_ANODE 34 35

12 OUT
ROMEO_TO_AOP_B2B_DETECT 1 2 ROMEO_TO_AOP_B2B_DETECT_CONN 35
01005
1 C4554
ROOM=B2B_PEARL 220PF
5%
2 10V
C0G-CERM
01005

FL4555
ROOM=B2B_PEARL
ISP I2C3
150OHM-25%-200MA-0.7DCR R4552
ROMEO_TO_RIGEL_VCSEL_NTC 1 2 ROMEO_TO_RIGEL_VCSEL_NTC_CONN I2C3_ISP_SCL 1
0.00 2 I2C3_ISP_TO_MAMA_BEAR_SCL_CONN
34 OUT 35 34 31 28 8 IN 35
CKPLUS_WAIVE=I2C_PULLUP
01005 0%
1 C4555 1/32W
MF
1 C4552
ROOM=B2B_PEARL 220PF 01005 56PF
5% ROOM=B2B_PEARL 5%
2 10V
C0G-CERM 2 25V
NP0-C0G-CERM
C 01005
ROOM=B2B_PEARL
01005
ROOM=B2B_PEARL C
FL4556
150OHM-25%-200MA-0.7DCR R4553
MAMA_BEAR_BI_RIGEL_STATUS 1 2 MAMA_BEAR_BI_RIGEL_STATUS_CONN I2C3_ISP_SDA 1
0.00 2 I2C3_ISP_BI_MAMA_BEAR_SDA_CONN
34 28 IN 35 34 31 28 8 BI 35
01005 0% CKPLUS_WAIVE=I2C_PULLUP
ROOM=B2B_PEARL
1 C4556 1/32W
MF
1 C4553
220PF 01005 56PF
5% ROOM=B2B_PEARL 5%
2 10V
C0G-CERM 2 25V
NP0-C0G-CERM
01005 01005
ROOM=B2B_PEARL ROOM=B2B_PEARL

Juliet Connector
Juliet Power and I/O Rcpt: 516S00244
Plug: 516S00245
<-- This one on MLB

B R4560 B
AP_TO_JULIET_SHUTDOWN_L 0.00 AP_TO_JULIET_SHUTDOWN_L_CONN
J4530
8 IN
1 2 35 BB35K-RA18-3A
F-ST-SM
0%
1/32W
MF
1 C4560 23
01005 220PF
ROOM=B2B_PEARL 5% 35
PP1V1_JULIET_DVDD_CONN 19 20
2 10V
C0G-CERM
01005
ROOM=B2B_PEARL 1 2 JULIET_PMU_TO_RIGEL_STROBE_CONN 35
90_MIPI_JULIET_TO_AP_DATA0_P 3 4 FCAM_TO_JULIET_SYNC_J4530
FL4561 8
90_MIPI_JULIET_TO_AP_DATA0_N 5 6 PP2V85_JULIET_AVDD_CONN
32 35

150OHM-25%-200MA-0.7DCR 8 35
7 8
AP_TO_FCAM_JULIET_CLK 1 2 AP_TO_JULIET_CLK_CONN
32 8 IN 35
8
90_MIPI_JULIET_TO_AP_CLK_P 9 10 PP1V8_JULIET_VDDIO_CONN 35
01005
XW4570 C4562 1
ROOM=B2B_PEARL 8
90_MIPI_JULIET_TO_AP_CLK_N 11 12 AP_TO_JULIET_SHUTDOWN_L_CONN 35

SHORT-01005 56PF 13 14 I2C2_ISP_BI_FCAM_SAVAGE_SDA_CONN BI 32


PP1V1_JULIET_DVDD_CONN 5%
27
PP1V1_CAM_TELE_JULIET_DVDD 1 2 35
25V
NP0-C0G-CERM 2 8
90_MIPI_JULIET_TO_AP_DATA1_P 15 16 I2C2_ISP_TO_FCAM_SAVAGE_SCL_CONN IN 32
01005 90_MIPI_JULIET_TO_AP_DATA1_N 17 18 AP_TO_JULIET_CLK_CONN
ROOM=B2B_PEARL
1 C4570 1 C4571 ROOM=B2B_PEARL 8 35

0.1UF 220PF
20% 5% 21 22
2 6.3V
X5R-CERM 2 10V
C0G-CERM R4563 24
01005 01005 0.00
ROOM=B2B_PEARL JULIET_PMU_TO_RIGEL_STROBE 1 2 JULIET_PMU_TO_RIGEL_STROBE_CONN ROOM=B2B_PEARL
FL4572 ROOM=B2B_PEARL 34 11 OUT
0%
35

10-OHM-750MA 1/32W 1 C4563


PP2V85_CAM_TELE_AVDD 1 2 PP2V85_JULIET_AVDD_CONN MF
01005 220PF
30 27 35
ROOM=B2B_PEARL 5%
01005-1 2 10V
ROOM=B2B_PEARL
1 C4572 1 C4573 C0G-CERM
01005
0.1UF 220PF ROOM=B2B_PEARL
20% 5%
2 6.3V
X5R-CERM 2 10V
C0G-CERM
A FL4574
01005
ROOM=B2B_PEARL
01005
ROOM=B2B_PEARL
SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE
10-OHM-750MA
43 34 32 30
27 17 16 14
7 6 5
PP1V8_IO 1 2 PP1V8_JULIET_VDDIO_CONN 35 35 32
FCAM_TO_JULIET_SYNC_J4530 PEARL: B2B Romeo + Juliet
10 8 IN
DRAWING NUMBER SIZE
29 28 01005-1
ROOM=B2B_PEARL
1 C4574 1 C4575 1 C4564 051-02221 D
0.1UF
20% 5%
220PF
5%
220PF Apple Inc. REVISION

2 6.3V
X5R-CERM 2 10V
C0G-CERM 2 10V
C0G-CERM 9.0.0
01005 01005 01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH
ROOM=B2B_PEARL
ROOM=B2B_PEARL ROOM=B2B_PEARL
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
45 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 35 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

AOP I2C Yogi Signals Rosaline + Misc Connector


FL4650 Rcpt: 516S00325 <-- This one on MLB
R4600 150OHM-25%-200MA-0.7DCR Plug: 516S00326
I2C0_AOP_SCL 1
0.00 2 I2C0_AOP_TO_PROX_ALS_YOGI_SCL_CONN 36 YOGI_TO_RIGEL_STATUS 1 2 YOGI_TO_RIGEL_STATUS_CONN 36
12 IN 34 28 BI
0%
1/32W 1 C4600
CKPLUS_WAIVE=I2C_PULLUP
01005
1 C4650 ROOM=B2B_PEARL
J4600
MF AA26DK-S028VA1
01005 56PF ROOM=B2B_PEARL 220PF OMIT
F-ST-SM
ROOM=B2B_PEARL 5%
2 25V
5%
2 10V
XW4600
SHORT-20L-0.05MM-SM 33
NP0-C0G-CERM C0G-CERM
01005 01005 38
FRONTMIC3_TO_CODEC_BIAS_FILT_RET 1 2 29 30
ROOM=B2B_PEARL ROOM=B2B_PEARL

D 36 FRONTMIC3_TO_CODEC_AIN3_CONN_N 1 2 FRONTMIC3_TO_CODEC_AIN3_CONN_P 36
D
R4601 36 PP3V0_YOGI_PROX_ALS_CONN 3 4 PP_CODEC_TO_FRONTMIC3_BIAS_CONN 36
I2C0_AOP_SDA 1
0.00 2 I2C0_AOP_BI_PROX_ALS_YOGI_SDA_CONN 5 6 YOGI_TO_RIGEL_STATUS_CONN
12 BI 36 36

0%
CKPLUS_WAIVE=I2C_PULLUP
7 8 PROX_BI_AP_AOP_INT_CONN_L
1/32W
MF
1 C4601 9 10 I2C0_AOP_BI_PROX_ALS_YOGI_SDA_CONN
36

01005 56PF 36

ROOM=B2B_PEARL 5% 11 12 I2C0_AOP_TO_PROX_ALS_YOGI_SCL_CONN 36
2 25V
NP0-C0G-CERM 13 14 ALS_TO_AOP_INT_CONN_L
01005 36
ROOM=B2B_PEARL 15 16
36 34 PP_ROSALINE_ANODE 17 18 PP_ROSALINE_ANODE 34 36
BB_TO_STROBE_DRIVER_GSM_BURST_IND_CONN 36
SPEAKER2 36 COIL_TO_SPKRAMP_TOP_VSENSE_POS_CONN
19
21
20
22 COIL_TO_SPKRAMP_TOP_VSENSE_NEG_CONN 36
23 24
SPKRAMP_TOP_TO_COIL_OUT_NEG 25 26 SPKRAMP_TOP_TO_COIL_OUT_NEG
SPKRAMP_TOP_TO_COIL_OUT_POS 50 36 36 50
50 36 IN
36 CODEC_AOUT_TO_HAC_CONN_P 27 28 CODEC_AOUT_TO_HAC_CONN_N 36
1 C4635 1 C4630
C4631 1
10%
820PF
5%
220PF 50 36 SPKRAMP_TOP_TO_COIL_OUT_POS 31 32 SPKRAMP_TOP_TO_COIL_OUT_POS 36 50
220PF 2 10V
X5R 2 10V
C0G-CERM
34
5% ROOM=B2B_PEARL
10V 01005 01005
C0G-CERM 2 ROOM=B2B_PEARL ROOM=B2B_PEARL
01005
ROOM=B2B_PEARL

50 36 IN
SPKRAMP_TOP_TO_COIL_OUT_NEG
1 C4636 1 C4632
820PF 220PF
10% 5%
2 10V
X5R 2 10V
C0G-CERM
01005 01005
C ROOM=B2B_PEARL ROOM=B2B_PEARL
C
R4633
COIL_TO_SPKRAMP_TOP_VSENSE_POS 1
0.00 2 COIL_TO_SPKRAMP_TOP_VSENSE_POS_CONN PP_ROSALINE_ANODE
50 OUT 36 34 36
NOSTUFF
0%
C4633 1 1/32W
MF
1 C4660
220PF 01005 220PF
5% ROOM=B2B_PEARL
5%
10V 2 10V
2 C0G-CERM
C0G-CERM
01005 01005
ROOM=B2B_PEARL ROOM=B2B_PEARL

R4634
PROX & ALS POWER 50 OUT
COIL_TO_SPKRAMP_TOP_VSENSE_NEG
NOSTUFF
1
0.00
0%
2 COIL_TO_SPKRAMP_TOP_VSENSE_NEG_CONN 36

C4634 1 1/32W
MF
220PF 01005
5% ROOM=B2B_PEARL
10V
C0G-CERM 2

MIC3 01005
ROOM=B2B_PEARL

FL4640
150OHM-25%-200MA-0.7DCR
38
PP_CODEC_TO_FRONTMIC3_BIAS 1 2 PP_CODEC_TO_FRONTMIC3_BIAS_CONN 36
01005
ROOM=B2B_PEARL 1 DZ4640
6.8V-100PF
R4611 01005
ROOM=B2B_PEARL
PP3V0_S2 1
0.00 2
PP3V0_YOGI_PROX_ALS_CONN 2
48 47 45 19 36
50 OMIT_TABLE
0%
B 1/32W
MF
1 C4613 1 C4614 B
01005 2.2UF
20% 5%
220PF FL4641
ROOM=B2B_PEARL
2 6.3V 2 10V
150OHM-25%-200MA-0.7DCR
X5R-CERM C0G-CERM
0201 01005 37 OUT
FRONTMIC3_TO_CODEC_AIN3_N 1 2 FRONTMIC3_TO_CODEC_AIN3_CONN_N 36
ROOM=B2B_PEARL ROOM=B2B_PEARL
01005
ROOM=B2B_PEARL 1 DZ4641
6.8V-100PF
01005
ROOM=B2B_PEARL
2

PROX/ALS I/O FL4642


R4617 150OHM-25%-200MA-0.7DCR
PROX_BI_AP_AOP_INT_L 1
240 2
PROX_BI_AP_AOP_INT_CONN_L FRONTMIC3_TO_CODEC_AIN3_P 2 1 FRONTMIC3_TO_CODEC_AIN3_CONN_P
12 BI 36 37 OUT 36

1% 01005
1/32W
MF
1 C4617 ROOM=B2B_PEARL
1 DZ4642
01005 220PF 6.8V-100PF
01005
ROOM=B2B_PEARL 5% ROOM=B2B_PEARL
10V
2 C0G-CERM 2
01005
ROOM=B2B_PEARL

FL4618 FL4643
150OHM-25%-200MA-0.7DCR 150OHM-25%-200MA-0.7DCR
ALS_TO_AOP_INT_L 2 1 ALS_TO_AOP_INT_CONN_L CODEC_AOUT_TO_HAC_P 1 2 CODEC_AOUT_TO_HAC_CONN_P
12 OUT 36 37 OUT 36
01005 01005
ROOM=B2B_PEARL
1 C4618 ROOM=B2B_PEARL 1 DZ4643
220PF 6.8V-100PF
01005
5% ROOM=B2B_PEARL
2 10V
C0G-CERM 2
01005
ROOM=B2B_PEARL

A FL4619 NOSTUFF FL4644 SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016


A
150OHM-25%-200MA-0.7DCR PAGE TITLE
150OHM-25%-200MA-0.7DCR CODEC_AOUT_TO_HAC_N
50 31 IN
BB_TO_STROBE_DRIVER_GSM_BURST_IND 1 2 BB_TO_STROBE_DRIVER_GSM_BURST_IND_CONN 36 37 OUT
2
01005
1 CODEC_AOUT_TO_HAC_CONN_N 36 PEARL: B2B Rosaline + Misc
01005
1 ROOM=B2B_PEARL
1 DZ4644 DRAWING NUMBER

051-02221
SIZE

D
ROOM=B2B_PEARL R4619 6.8V-100PF
01005 Apple Inc.
0.00 ROOM=B2B_PEARL REVISION
0% 2
1/32W
MF
9.0.0
2 01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH
ROOM=B2B_PEARL THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
46 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 36 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CALLAN AUDIO CODEC (ANALOG INPUTS & OUTPUTS)

D D
U4700
CS42L75
WLCSP
SYM 1 OF 3
49 IN
LOWERMIC1_TO_CODEC_AIN1_P K3 AIN1+ CRITICAL AOUT+ K8 CODEC_AOUT_TO_HAC_P OUT 36
LOWERMIC1_TO_CODEC_AIN1_N L3 ROOM=CODEC L8 CODEC_AOUT_TO_HAC_N
49 IN AIN1- AOUT- OUT 36

33 IN
REARMIC2_TO_CODEC_AIN2_P K4 AIN2+
33 IN
REARMIC2_TO_CODEC_AIN2_N L4 AIN2-

36 IN
FRONTMIC3_TO_CODEC_AIN3_P K6 AIN3+
36 IN
FRONTMIC3_TO_CODEC_AIN3_N L6 AIN3-

49 IN
LOWERMIC4_TO_CODEC_AIN4_P K5 AIN4+
49 IN
LOWERMIC4_TO_CODEC_AIN4_N L5 AIN4-

C C
33 IN
HAWKING_TO_CODEC_AIN5_P G3 AIN5+
33 IN
HAWKING_TO_CODEC_AIN5_N G2 AIN5-

F3 AIN6+
NC
G4 AIN6-
NC

F4 AIN7+
NC
NC
E3 AIN7- C4700
100PF
1 2

5%
16V
NP0-C0G
C2
R4700 01005
NC AIN8+
1
20.0 2
ROOM=CODEC
90_MIKEYBUS_DATA_P 48
D3 AIN8-
BI
NC 5%
1/32W
MF
B8 DMIC1_CLK DP E1 90_MIKEYBUS_CODEC_DATA_P 01005
NC ROOM=CODEC
D8 DMIC1_DATA DN F1 90_MIKEYBUS_CODEC_DATA_N
NC

NC
E11 DMIC2_CLK MIKEYBUS_REFERENCE
R4701
E10 MBUS_REF G1 IN 49 20.0 90_MIKEYBUS_DATA_N
B NC DMIC2_DATA 1
5%
2 BI 48
B
D10 DMIC3_CLK 1/32W
NC
NC
D9 DMIC3_DATA 1
R4710
MF
01005 C4701
100 ROOM=CODEC 100PF
E9 DMIC4_CLK 5% 1 2
NC 1/32W
F8 DMIC4_DATA MF
NC 5%
2 01005
ROOM=CODEC 16V
NP0-C0G
50 OUT
PDM_CODEC_TO_SPKRAMP_TOP_CLK B11 PDMOUT1_CLK 01005
ROOM=CODEC
50 OUT
PDM_CODEC_TO_SPKRAMP_TOP_DATA B10 PDMOUT1_DATA

41 4 OUT
PDM_CODEC_TO_ARC_CLK A10 PDMOUT2_CLK
41 4 OUT
PDM_CODEC_TO_ARC_DATA B9 PDMOUT2_DATA
F10 PDMOUT3_CLK
NC
F9 PDMOUT3_DATA
NC

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

AUDIO: CODEC (1/2)


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
47 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 37 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

CALLAN AUDIO CODEC (POWER & I/O)

D D

50 41 19
PP1V8_AUDIO_VA_S2
OMIT_TABLE
1 C4809
2.2UF
20%
2 6.3V
X5R-CERM
0201
ROOM=CODEC

CODEC_AGND 38

48 47 46 38 22 20 17 14 12 10
PP1V8_S2
50 49

PP_VDD_BOOST
R4800 1
50 34 27 21 19 100K
5%
OMIT_TABLE 1/32W
MF
1 C4812 1 C4814 1 C4805 01005 2
0.1UF 0.1UF 2.2UF ROOM=CODEC
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
U4700
X5R-CERM X5R-CERM X5R-CERM CS42L75
01005 01005 0201 12
AOP_TO_CODEC_RESET_L J4 RESET* WLCSP JTAG_TMS E7
ROOM=CODEC ROOM=CODEC ROOM=CODEC IN NC
SYM 3 OF 3 JTAG_TCK D7
NC
JTAG_TDI E8
48 47 46 38 22 20 17 14 12 10
PP1V8_S2 NC
50 49 JTAG_TDO F7
OMIT_TABLE CODEC_TO_PMU_WAKE H3 WAKE* NC
1 C4811 1 C4813 1 C4815 20 OUT

10UF 0.1UF 0.1UF 10 OUT


CODEC_TO_AP_INT_L D4 INT*
ROOM=CODEC
20% 20% 20% CRITICAL
2 10V
X5R-CERM 2 6.3V
X5R-CERM 2 6.3V
X5R-CERM
C 0402-0.1MM
ROOM=CODEC
01005
ROOM=CODEC
01005
ROOM=CODEC
PP1V2_CODEC_S2 10 IN
SPI_AP_TO_CODEC_CS_L
SPI_AP_TO_CODEC_SCLK
C7
A7
CS* C
10 IN CCLK
1 C4817 1 C4821 SPI_AP_TO_CODEC_MOSI C8 MOSI
1.0UF 1.0UF 10 IN
SPI_CODEC_TO_AP_MISO B7

VD_FILT G11
20% 20% MISO

VD C1
VL_SW A2

VD_FILT B1

VL A9

VA K2
10

VP_MBUS F2
VP L9
2 6.3V 2 6.3V

VA J1
VA J2
OUT
X5R
0201-1
X5R
0201-1
R4830
ROOM=CODEC ROOM=CODEC
CODEC_TO_SPKRAMP_BOT_ARC_MCLK 33.2 I2S_AP_TO_CODEC_MCLK1 A4
50 41 OUT
1 2 10 IN MCLK1_IN TSTI G10
1% 12 IN
I2S_AOP_TO_CODEC_MCLK2 B4 MCLK2_IN TSTI J3
1/32W
MF CODEC_TO_SPKRAMP_BOT_ARC_MCLK_R A5 MCLK_OUT TSTI J5
01005
C4803 PP_CODEC_TO_LOWERMIC1_BIAS K11
ROOM=CODEC
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK A6
4.7UF 49 MIC1_BIAS 50 49 41 12 OUT ASP1_SCLK
49 IN
LOWERMIC1_TO_CODEC_BIAS_FILT_RET 1 2 LOWERMIC1_BIAS_FILT_IN K10 MIC1_BIAS_FILT
CRITICAL
ROOM=CODEC
R4831 50 49 41 12 OUT
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK C6 ASP1_LRCK/FSYNC
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT 49.9 I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_R
20% U4700 49 41 12 IN
1 2 B5 ASP1_SDIN
6.3V CS42L75 1% 50 41 12 OUT
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN B6 ASP1_SDOUT
X5R-CERM1 WLCSP 1/32W
402
ROOM=CODEC MF
SYM 2 OF 3 01005
I2S_AOP_TO_CODEC_ASP2_BCLK C4
C4804 PP_CODEC_TO_REARMIC2_BIAS J11 CODEC_LP_FILTP 1 C4820
ROOM=CODEC 12 IN
I2S_AOP_TO_CODEC_ASP2_LRCLK D5
ASP2_SCLK
4.7UF 33 MIC2_BIAS LP_FILT+ D1 12 IN ASP2_LRCK/FSYNC
REARMIC2_TO_CODEC_BIAS_FILT_RET J10 CODEC_LP_FILTN 0.1UF I2S_AOP_TO_CODEC_ASP2_DOUT D6
33 IN
1 2 REARMIC2_BIAS_FILT_IN MIC2_BIAS_FILT LP_FILT- D2 20% 12 IN ASP2_SDIN
2 6.3V
X5R-CERM 12
I2S_CODEC_ASP2_TO_AOP_DIN C5 ASP2_SDOUT
20% OUT
6.3V 01005
ROOM=CODEC
X5R-CERM1
402
ROOM=CODEC 10 IN
I2S_AP_TO_CODEC_ASP3_BCLK C11 ASP3_SCLK
I2S_AP_TO_CODEC_ASP3_LRCLK C9
C4801 PP_CODEC_TO_FRONTMIC3_BIAS K9
10 IN
I2S_AP_TO_CODEC_ASP3_DOUT C10
ASP3_LRCK/FSYNC
4.7UF 36 MIC3_BIAS 10 IN ASP3_SDIN
36
FRONTMIC3_TO_CODEC_BIAS_FILT_RET 1 2 FRONTMIC3_BIAS_FILT_IN J9 MIC3_BIAS_FILT 10
I2S_CODEC_ASP3_TO_AP_DIN D11 ASP3_SDOUT
IN OUT

20% H4 DIGLDO_PULLDN GNDA F5


6.3V
X5R-CERM1 H5 DIGLDO_EN GNDA G5
402
B ROOM=CODEC
GNDA G6 B
C4802 PP_CODEC_TO_LOWERMIC4_BIAS H9 NC
A3 SW1_CLK GNDA G7
4.7UF 49 MIC4_BIAS C3 H1
LOWERMIC4_TO_CODEC_BIAS_FILT_RET 1 2 LOWERMIC4_BIAS_FILT_IN H8 NC SW1_SD GNDA
49 IN MIC4_BIAS_FILT H2
GNDA
20% B3 SW2_CLK GNDA H6
6.3V NC
X5R-CERM1
402
1 C4823 1 C4824 NC
B2 SW2_SD GNDA H7
ROOM=CODEC
1.0UF 1.0UF OMIT_TABLE GNDA J6
20% 20%
2 6.3V 2 6.3V CODEC_TO_AOP_GPIO1 E6 J7
X5R
0201-1
X5R
0201-1 NC
H11 MIC5_BIAS FILT+ K1 CODEC_FILTP 1 C4808 12 OUT
CODEC_TO_AOP_GPIO2 E5
GPIO1 GNDA
J8
H10 10UF 12 GPIO2 GNDA
FILT- L2
ROOM=CODEC ROOM=CODEC OUT
NC MIC5_BIAS_FILT 20% E4
2 10V AOP_TO_CODEC_CLP_EN F6 GNDA
X5R-CERM 12 IN CLP_EN
0402-0.1MM
ROOM=CODEC

1 C4822 1 C4825
1.0UF 1.0UF
20% 20% G8 MIC6_BIAS
2 6.3V 2 6.3V NC
X5R X5R G9 MIC6_BIAS_FILT
0201-1 0201-1 NC
ROOM=CODEC ROOM=CODEC

GNDD GNDP
A1
A8
A11
E2
F11

K7
L1
L7
L10
L11

A XW4802
SHORT-10L-0.1MM-SM SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
2 1 38 CODEC_AGND PAGE TITLE

ROOM=CODEC AUDIO: CODEC (2/2)


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
48 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 38 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C C

South Speaker Amplifier on MLB Bottom

B B

A SYNC_DATE=08/25/2015 A
PAGE TITLE

AUDIO: Speaker Amp Bottom


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
49 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 39 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C C

North Speaker Amplifier on MLB Bottom

B B

A SYNC_DATE=08/25/2015 A
PAGE TITLE

AUDIO: Speaker Amp Top


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
50 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 40 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Pull Downs
AOP_TO_SPKRAMP_BOT_ARC_RESET_L 12 41 50

1
R5108
100K
5%
1/32W
MF
2 01005
ROOM=ARC_CTRL
ARC DRIVER
D D

APN: 338S00296
I2C ADDRESS: 1000 001x
0x82

45 43 42 34 31 27 23 21 19 18
PP_VDD_MAIN PP1V8_AUDIO_VA_S2 19 38 41 50
50 46

C5130 1 C5131 1 C5125 1 1 C5127 1 C5134


18UF 18UF 4UF 0.1UF 2.2UF
20% 20% 20% 20% 20%
6.3V 2 6.3V 2 6.3V 2 2 6.3V 2 6.3V
CER-X5R CER-X5R CERM-X5R X5R-CERM X5R-CERM
0402-0.1MM 0402-0.1MM 0201 01005 0201
ROOM=ARC_CTRL ROOM=ARC_CTRL ROOM=ARC_CTRL ROOM=ARC_CTRL ROOM=ARC_CTRL

C C

A5

F5
CRITICAL
L5100 VP VA
1.2UH-20%-3A-0.11OHM
ARC1_LX A2 A1 PP_ARC1_VBOOST
1 2
B2
SW U5100 VBST_B
B1
MEFE2016T-SM SW CS35L26C-A1 VBST_B
ROOM=ARC_CTRL
D6 WLCSP C1
1 C5126 1 C5135 1 C5137 1 C5124 1 C5138 1 C5139
50 49 25 12 4 BI
I2C1_AOP_SDA SDA VBST_A 220PF 0.1UF 10UF 10UF 10UF 10UF
ROOM=ARC_CTRL D1 5% 10% 20% 20% 20% 20%
I2C1_AOP_SCL E6 VBST_A 2 10V
C0G-CERM 2 16V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM
50 49 25 12 4 IN SCL CRITICAL 01005 0201 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM
ROOM=ARC_CTRL ROOM=ARC_CTRL ROOM=ARC_CTRL ROOM=ARC_CTRL ROOM=ARC_CTRL ROOM=ARC_CTRL
SPKRAMP_BOT_ARC_TO_AOP_INT_L A7
50 12 BI INT*
AOP_TO_SPKRAMP_BOT_ARC_RESET_L A6
50 41 12 IN RESET*
F6
ALIVE/SYNC ISNS+
F1 ARC1_ISENSE_POS
1 C5128
NC E1 0.01UF
E5 ISNS- ARC1_ISENSE_NEG 10%
50 41 38 19
PP1V8_AUDIO_VA_S2 PP1V8_AUDIO_VA_S2 AD0/PDM_CLK1 2 6.3V
X5R
MAKE_BASE=TRUE 01005
CODEC_TO_SPKRAMP_BOT_ARC_MCLK B7 ROOM=ARC_CTRL
50 38 IN MCLK
E2 SOLENOID1_TO_ARC1_VSENSE_POS
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK C7 VSNS+ IN 49
50 49 38 12 IN SCLK E3 SOLENOID1_TO_ARC1_VSENSE_NEG
VSNS- IN 49
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK C6
50 49 38 12 IN LRCK/FSYNC
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN D7
50 38 12 IN SDIN D2 ARC1_TO_SOLENOID1_OUT_POS
OUT+ 49
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT B6 C2 ARC1_TO_SOLENOID1_OUT_NEG
49 38 12 OUT SDOUT OUT- 49

PDM_CODEC_TO_ARC_CLK F7
PDM_CLK0
37 4 IN
E7 F4
C5129 1 1 C5142
PDM_CODEC_TO_ARC_DATA ARC1_FILT 470PF 470PF
B 37 4 IN
D5
PDM_DATA0 FILT+
F3
10%
10V 2
10%
2 10V
B
PDM_DATA1 AD1 X5R X5R
GNDP GNDA 1 C5136 01005
ROOM=ARC_CTRL
01005
ROOM=ARC_CTRL
2.2UF
20%

A3
A4
B3
B4
C3
C4
C5
D3
D4

B5
E4
F2
2 6.3V
X5R-CERM
0201
ROOM=ARC_CTRL

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

ARC: Driver
DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
51 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 41 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Acorn PMU

D D

U5600 Charge Pump 1 Caps


LM3373A1YKA
DSBGA
PP1V1_S2 A1 VJ ROOM=ACORN VC B1 PP1V1_RACER
19 17 14
LOAD SWITCH
50
1 C5611
C 1 C5691
4UF
1 C5692
0.1UF
A2 VK LDO1 VA C1 PP3V5_RACER 50
0.22UF
20% C
20% 20% 42 ACORN_CP1_CAP1_POS 2 6.3V
X5R
2 6.3V
CERM-X5R 2 6.3V
X5R-CERM
PP_CP1_OUT_ACORN A4 VL CP1 C1+ B2 ACORN_CP1_CAP1_POS 42
1 C5642 42 ACORN_CP1_CAP1_NEG 01005
ROOM=ACORN
0201 01005 CRITICAL C1- B3 ACORN_CP1_CAP1_NEG 4UF
ROOM=ACORN ROOM=ACORN 1 C5650 1 C5651 42
20%
2 6.3V ACORN_CP1_CAP2_POS
220PF 4UF CERM-X5R 42
5% 20% C2+ A3 ACORN_CP1_CAP2_POS 0201 ACORN_CP1_CAP2_NEG
2 16V
C0G 2 6.3V
CERM-X5R C2- C3 ACORN_CP1_CAP2_NEG
42
ROOM=ACORN
42
1 C5612
01005 0201 42
0.22UF
ROOM=ACORN ROOM=ACORN 20%
PP5V45_BOOST2_ACORN H4 VG PP5V25_TOUCH_VDDH 2 6.3V
LDO2 VH H2 50
X5R
01005
OMIT_TABLE
1 C5652 1 C5653 VN D4 PN6V7_RACER
ROOM=ACORN

220PF 10UF 50
5%
2 16V
C0G
20%
2 10V
X5R-CERM CP2 C3+ C2 ACORN_CP2_CAP_POS 42
Charge Pump 2 Caps
01005 0402-0.1MM C3- C4 ACORN_CP2_CAP_NEG
ROOM=ACORN ROOM=ACORN 42
1 C5621
1UF
PP_BOOST1_ACORN F4 VB VP E4 PP10V0_RACER 20%
OMIT_TABLE
50
42 ACORN_CP2_CAP_POS 2 16V
CER-X5R
1 C5654 1 C5655 C4+ D2 ACORN_CP3_CAP1_POS 42
1 C5640 1 C5641 1 C5645 42
ACORN_CP2_CAP_NEG 0201
ROOM=ACORN
220PF 10UF CP3 C4- D3 ACORN_CP3_CAP1_NEG 42
4.7UF 10UF 4UF
5% 20% 20% 20% 20%
2 16V
C0G
01005
2 10V
X5R-CERM
0402-0.1MM C5+ E2 ACORN_CP3_CAP2_POS 42
2 16V
X5R
0402
2 10V
X5R-CERM
0402-0.1MM
2 6.3V
CERM-X5R
0201
Charge Pump 3 Caps
ROOM=ACORN ROOM=ACORN ROOM=ACORN
C5- E3 ACORN_CP3_CAP2_NEG ROOM=ACORN ROOM=ACORN
42
1 C5631
0.22UF
PP_VDD_MAIN B4 IN HWEN H1 PP1V8_TOUCH_RACER_S2 20%
45 43 41 34 31 27 23 21 19 18
50 46
17 50
42
ACORN_CP3_CAP1_POS 2 6.3V
X5R
1 C5690 L5600 EN1 F2 RACER_TO_ACORN_ORB_SCAN IN 50 42
ACORN_CP3_CAP1_NEG 01005
ROOM=ACORN
4.7UF 1.5UH-20%-1.6A-0.18OHM EN2 F3 TOUCH_TO_ACORN_PP5V25_EN IN 50
20%
2 6.3V ACORN_LX G4 SW I2C3_AP_SCL 42 ACORN_CP3_CAP2_POS
CER 2 1 SCL G2
B 0402 IN 10 50
ACORN_CP3_CAP2_NEG B
E1 CP23_GND

H3 SIDO_GND

SDA G3 I2C3_AP_SDA 42
1 C5632
D1 CP1_GND

ROOM=ACORN PIWA2012FE-SM 10 50
ROOM=ACORN BI
0.22UF
F1 AGND

AMUX G1 ACORN_TO_PMU_ADC OUT 20


20%
2 6.3V
X5R
1 C5660 01005
ROOM=ACORN
1000PF
10%
2 6.3V
X5R-CERM
01005
ROOM=ACORN

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

CG: Power Supplies - Touch & Display


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
56 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 42 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
Display Flex Connector
Display Control Signals Rcpt: 516S00210
Plug: 516S00211
<-- This one on MLB

FL5700 J5700
150OHM-25%-200MA-0.7DCR BM28P0.6-34DS/2-0.35V
F-ST-SM
11 IN
AP_TO_DISPLAY_RESET_L 2 1 AP_TO_DISPLAY_RESET_CONN_L 43
ROOM=B2B_DISPLAY

01005
R5700 1 ROOM=B2B_DISPLAY
1 C5700 PP_VDD_MAIN_HILO_CONN 35
PWR
36 PP_VDD_MAIN_HILO_CONN
61.9K 220PF 43 43

1% 5%
1/32W 2 10V
C0G-CERM
MF 01005 SIG

D
01005 2
ROOM=B2B_DISPLAY
ROOM=B2B_DISPLAY
43
PP1V8_DISPLAY_CONN 1 2 D
43
DISPLAY_TO_PMU_AMUX_CONN 3 4
AP_TO_DISPLAY_RESET_CONN_L 5 6 MTEST
R5701 43
MTEST 7 8 PP3V0_DISPLAY_CONN
43

PMU_TO_DISPLAY_PANICB 1
10 2 PMU_TO_DISPLAY_PANICB_CONN 43 43
20 IN 43
43
PMU_TO_DISPLAY_PANICB_CONN 9 10 NO_TEST=1 NC_SPI_AP_TO_DISPLAY_FLASH_SCLK
5%
1/32W
MF
1 C5701 NC_SPI_DISPLAY_FLASH_CS_L NO_TEST=1 11 12 PP1V0_DISPLAY_DVDD_CONN 43

01005 220PF NC_PP_VPP NO_TEST=1 13 14 NO_TEST=1 NC_DISPLAY_PIFA


5%
ROOM=B2B_DISPLAY
2 10V
C0G-CERM
NC_SPI_DISPLAY_FLASH_TO_AP_MISO NO_TEST=1 15 16 ISP_TO_DISPLAY_FLASH_INT_CONN 43
01005 17 18 NO_TEST=1 NC_SPI_AP_TO_DISPLAY_FLASH_MOSI
ROOM=B2B_DISPLAY
43
90_MIPI_AP_TO_DISPLAY_DATA2_CONN_P 19 20 DISPLAY_TO_AP_ALIVE_CONN 43

FL5702 43
90_MIPI_AP_TO_DISPLAY_DATA2_CONN_N 21 22
150OHM-25%-200MA-0.7DCR 23 24
8
DISPLAY_TO_AP_ALIVE 2 1 DISPLAY_TO_AP_ALIVE_CONN 43 43
90_MIPI_AP_TO_DISPLAY_CLK_CONN_P 25 26 90_MIPI_AP_TO_DISPLAY_DATA1_CONN_P 43
OUT
01005 90_MIPI_AP_TO_DISPLAY_CLK_CONN_N 27 28 90_MIPI_AP_TO_DISPLAY_DATA1_CONN_N
ROOM=B2B_DISPLAY
1 C5702 43
29 30
43

56PF 90_MIPI_AP_TO_DISPLAY_DATA3_CONN_P 90_MIPI_AP_TO_DISPLAY_DATA0_CONN_P


5% 43 31 32 43
2 25V
NP0-C0G-CERM 90_MIPI_AP_TO_DISPLAY_DATA3_CONN_N 33 34 90_MIPI_AP_TO_DISPLAY_DATA0_CONN_N
01005 43 43
ROOM=B2B_DISPLAY

PWR
FL5703 37 38
150OHM-25%-200MA-0.7DCR
20 IN
DISPLAY_TO_PMU_AMUX 2 1 DISPLAY_TO_PMU_AMUX_CONN 43
01005
ROOM=B2B_DISPLAY
1 C5703
56PF
5%
2 25V
NP0-C0G-CERM
01005
ROOM=B2B_DISPLAY

C FL5704 Display MIPI L5700 CRITICAL C


150OHM-25%-200MA-0.7DCR 65OHM-0.7-2GHZ-3.4OHM
TAM0605
ISP_TO_DISPLAY_FLASH_INT 2 1 ISP_TO_DISPLAY_FLASH_INT_CONN 90_MIPI_AP_TO_DISPLAY_DATA0_P 4 1 90_MIPI_AP_TO_DISPLAY_DATA0_CONN_P
8 IN
01005
43 8 BI
SYM_VER-2
43
Display Power
ROOM=B2B_DISPLAY
1 C5704 FL5780
220PF 8 BI
90_MIPI_AP_TO_DISPLAY_DATA0_N 3 2 90_MIPI_AP_TO_DISPLAY_DATA0_CONN_N 43 33-OHM-25%-1500MA
5% ROOM=B2B_DISPLAY
2 10V
C0G-CERM
GND_VOID
PP1V8_IO 2 1 PP1V8_DISPLAY_CONN
29 28 27 17 16 14 10 8 7 6 5 43
01005
ROOM=B2B_DISPLAY L5710 CRITICAL 35 34 32 30
0201
65OHM-0.7-2GHZ-3.4OHM
TAM0605 ROOM=B2B_DISPLAY
1 C5781
8 IN
90_MIPI_AP_TO_DISPLAY_DATA1_P 4 SYM_VER-2 1 90_MIPI_AP_TO_DISPLAY_DATA1_CONN_P 43
220PF
5%
2 10V
C0G-CERM
01005
8 IN
90_MIPI_AP_TO_DISPLAY_DATA1_N 3 2 90_MIPI_AP_TO_DISPLAY_DATA1_CONN_N 43
ROOM=B2B_DISPLAY
ROOM=B2B_DISPLAY
GND_VOID

L5720 CRITICAL FL5782


65OHM-0.7-2GHZ-3.4OHM 33-OHM-25%-1500MA
90_MIPI_AP_TO_DISPLAY_DATA2_P 4
TAM0605
SYM_VER-2 1 90_MIPI_AP_TO_DISPLAY_DATA2_CONN_P PP1V0_DISPLAY_DVDD 2 1 PP1V0_DISPLAY_DVDD_CONN
8 IN 43 19 43
0201
ROOM=B2B_DISPLAY
1 C5782
8 IN
90_MIPI_AP_TO_DISPLAY_DATA2_N 3 2 90_MIPI_AP_TO_DISPLAY_DATA2_CONN_N 43
220PF
ROOM=B2B_DISPLAY
5%
GND_VOID
2 10V
C0G-CERM
L5730
65OHM-0.7-2GHZ-3.4OHM
CRITICAL 01005
ROOM=B2B_DISPLAY

TAM0605
90_MIPI_AP_TO_DISPLAY_DATA3_P 4 SYM_VER-2 1 90_MIPI_AP_TO_DISPLAY_DATA3_CONN_P
8 IN 43
FL5783
FERR-70OHM-25%-0.300A
8 IN
90_MIPI_AP_TO_DISPLAY_DATA3_N 3 2 90_MIPI_AP_TO_DISPLAY_DATA3_CONN_N 43 19
PP3V0_DISPLAY 1 2 PP3V0_DISPLAY_CONN 43
GND_VOID ROOM=B2B_DISPLAY
01005
B L5740 CRITICAL ROOM=B2B_DISPLAY
1 C5783 B
65OHM-0.7-2GHZ-3.4OHM
220PF
5%
90_MIPI_AP_TO_DISPLAY_CLK_P 4
TAM0605
SYM_VER-2 1 90_MIPI_AP_TO_DISPLAY_CLK_CONN_P 2 10V
C0G-CERM
8 IN 43 01005
ROOM=B2B_DISPLAY

8 IN
90_MIPI_AP_TO_DISPLAY_CLK_N 3 2 90_MIPI_AP_TO_DISPLAY_CLK_CONN_N 43
GND_VOID ROOM=B2B_DISPLAY
XW5784
SHORT-0201
45 42 41 34 31 27 23 21 19 18
PP_VDD_MAIN 1 2 PP_VDD_MAIN_HILO_CONN 43
50 46
ROOM=B2B_DISPLAY
1 C5784 1 C5785 1 C5786
220PF 220PF 220PF
XW5785
SHORT-0201
5%
2 10V
5%
2 10V
5%
2 10V
C0G-CERM C0G-CERM C0G-CERM
1 2 01005 01005 01005
ROOM=B2B_DISPLAY ROOM=B2B_DISPLAY ROOM=B2B_DISPLAY
ROOM=B2B_DISPLAY

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

CG: B2B Display


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
57 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 43 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C C

Orb + Touch Connector on MLB Bottom

B B

A SYNC_DATE=08/25/2015 A
PAGE TITLE

CG: B2B Orb & Touch


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
58 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 44 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D
VDD_MAIN OV CUT-OFF CIRCUIT D

43 42 41 34 31 27 23 21 19 18
PP_VDD_MAIN 48 47 23
PP_VBUS1_E75_RVP
DZ5900
50 46
0201
K A PP3V0_S2
C5900 1 19 36 47 48 50

0.47UF
1 20% RB521ES-30
R5901 25V 2
X5R
1.3M 0201
1% ROOM=OV_CUTOFF
1/20W

2
MF CRITICAL
2 0201
ROOM=OV_CUTOFF VDD
OMIT
SHORT-20L-0.05MM-SM U5900
XW5900 TPS3700RUG
X2QFN
2 1 OV_VMON_INA 5 INA
OUTA 7
ROOM=SOC NC To Hydra and E75
R5903
OUTB 1 PP_HYDRA_ACC1_R 1
0.00 2 PP_HYDRA_ACC1 48 49

C PP_VDD_MAIN_VMON 3 INB
NC0 4 0%
1/32W
C
NC MF
NOSTUFF ROOM=OV_CUTOFF NC1 8 01005
1 NC
R5902 1 C5902 GND ROOM=OV_CUTOFF

100K 15PF

6
1% 5%
1/32W
MF 2 16V
NP0-C0G-CERM
2 01005 01005
ROOM=OV_CUTOFF ROOM=OV_CUTOFF

B B

A SYNC_MASTER=sync SYNC_DATE=01/10/2017
A
PAGE TITLE

I/O: Overvoltage Cut-Off Circuit


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
59 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 45 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

ACCESSORY BUCK
I2C ADDRESS: 0x52
U6100
FPF1204UCX
43 42 41 34 31 27 23 21 19 18
PP_VDD_MAIN A2 VIN WLCSP-COMBO
VOUT A1
PP_VDD_MAIN_ACC_BUCK_VIN
50 45
ROOM=ACC_BUCK
CRITICAL C6100 1
49 48 47 38 22 20 17 14 12 10 PP1V8_S2 B2 ON 4UF
50 20%
6.3V
CER-X5R 2
GND 0201
ROOM=ACC_BUCK
B1

A2
VIN
U6110 CRITICAL
FAN53741 L6110
CSP
0.47UH-20%-2.52A-0.08OHM To Hydra
49 20 10
I2C0_AP_SDA A1 SDA ROOM=ACC_BUCK SW B2 ACC_BUCK_SW 1 2 PP_ACC_VAR 19 48
BI
PIGA1608-SM
C 49 20 10 IN
I2C0_AP_SCL B1 SCL CRITICAL FB
C1 ACC_BUCK_FB ROOM=ACC_BUCK
2OMIT
1 C6110
100PF
1 C6111
0.1UF
1 C6112
18UF
1 C6117
18UF
1
R6116 C
5% 20% 20% 20% 10K
GND XW6110
SHORT-20L-0.05MM-SM 2 16V
NP0-C0G 2 6.3V
X5R-CERM 2 6.3V
CER-X5R 2 6.3V
CER-X5R
5%
1/32W
ROOM=ACC_BUCK 01005 01005 0402-0.1MM 0402-0.1MM MF

C2
1 ROOM=ACC_BUCK ROOM=ACC_BUCK ROOM=ACC_BUCK ROOM=ACC_BUCK
2 01005
ROOM=ACC_BUCK

ACC_BUCK_TO_PMU_AMUX 20
OUT

B B

A SYNC_MASTER=test_mlb SYNC_DATE=10/17/2016
A
PAGE TITLE

I/O: Accessory Buck


DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
61 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 46 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

USB-PD

49 48 46 38 22 20 17 14 12 10
PP1V8_S2
50
50 48 45 36 19
PP3V0_S2
C 1 C6290 1 C6291
PP1V8_VCCD_CCG2 C
1.0UF 1.0UF
20% 20%
2 6.3V
X5R 2 6.3V
X5R
1 C6292
0201-1 0201-1 1.0UF
ROOM=USB_PD ROOM=USB_PD 20%
2 6.3V
X5R NCNC
0201-1
ROOM=USB_PD

VCONN2 C4
VDDD E3

VCCD A1

VDDIO E1

VCONN1 E4
48 45 23
PP_VBUS1_E75_RVP
1
R6210
499K
1%
1/20W CCG2_TO_SMC_INT_L C3 B4 CCG2_TO_HYDRA_CC
MF 10 4 OUT GPIO_C3 CRITICAL CC1 OUT 48
2 201 D3 A4
ROOM=USB_PD
PP5V0_USB_RVP_R
NC
C2
GPIO_D3 U6200 CC2 NC 1 C6200
GPIO_C2 CSP B3 220PF
D2 RD1 NC 5%
1 NC GPIO_D2ROOM=USB_PD 2 10V
R6211 1 C6210 NC
B2 GPIO_B2
C0G-CERM
01005
50K 22NF CG8740AAT ROOM=USB_PD
1%
1/32W 20% R6200 50 23 22 21 10 IN
I2C0_SMC_SCL A3 I2C_0_SCL XRES B1 PMU_TO_CCG2_RESET_L IN 20
MF 2 6.3V
X5R-CERM I2C0_SMC_SDA 43.2 I2C0_SMC_SDA_CCG2_R A2
1 2 I2C_0_SDA
2 01005 01005 50 23 22 21 10 BI
ROOM=USB_PD ROOM=USB_PD 1%
1/32W 10 4 BI
AP_BI_CCG2_SWDIO E2 SWD_IO
MF
01005 10 4 IN
AP_TO_CCG2_SWCLK D1 SWD_CLK

VSS VSS

D4

C1
B B

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

I/O: USB PD
DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
62 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 47 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

Hydra
I2C Address: 0011010X

50 47 45 36 19
PP3V0_S2 PP_ACC_VAR 19 46

1 C6390 1 C6391
1.0UF 0.1UF 49 47 46 38 22 20 17 14 12 10
PP1V8_S2
20% 20% 50
2 6.3V 2 6.3V
X5R X5R-CERM 1 C6395 C
C 0201-1
ROOM=HYDRA
01005
ROOM=HYDRA
0.01UF
R6300 2
10%
6.3V

H4

H5

C6
D6
A6
B6

E6
HYDRA_TO_PMU_USB_BRICK_ID 1
6.34K 2 X5R
20 OUT 01005
1%
ROOM=HYDRA VDD1V8 VDD3V0
1/32W ACC_PWR
1 C6300 MF
01005 U6300 From Tigris2
0.01UF ROOM=HYDRA
10% CBTL1612A1
2 6.3V 37 BI
90_MIKEYBUS_DATA_P C2 DIG_DP P_IN G6 PP_VBUS1_E75_RVP 23 45 47
X5R WLCSP
01005 37 BI
90_MIKEYBUS_DATA_N D2 DIG_DN ROOM=HYDRA ACC1 A5 PP_HYDRA_ACC1 45 49
ROOM=HYDRA

90_USB_BB_DATA_P D3 USB1_DP
CRITICAL ACC1 B5 1 C6311 1 C6312
50 BI
ACC1 C5 0.47UF 0.47UF
50
90_USB_BB_DATA_N D4 USB1_DN 20% 20%
BI
ACC1 D5 2 25V 25V
2 CER-X5R
L6300 HYDRA_TO_PMU_USB_BRICK_ID_R F3 BRICK_ID ACC1 E5
CER-X5R
0201 0201
15NH-250MA
90_USB_AP_DATA_L_P ACC2 A7 PP_HYDRA_ACC2 ROOM=HYDRA ROOM=HYDRA

6
90_USB_AP_DATA_P 1 2 B3 USB0_DP
49
BI
ACC2 B7
GND_VOID
0201 90_USB_AP_DATA_L_N B4 USB0_DN
ROOM=HYDRA ACC2 C7
L6301 11 IN
UART_AP_TO_ACCESSORY_TXD D1 UART0_TX ACC2 D7
15NH-250MA 11
UART_ACCESSORY_TO_AP_RXD C1 UART0_RX ACC2 E7
OUT
90_USB_AP_DATA_N 1 2
6 BI
GND_VOID 11 IN
UART_AP_DEBUG_TXD F2 UART1_TX DP1 C3 90_HYDRA_DP1_CONN_P BI 49
0201
ROOM=HYDRA 11 OUT
UART_AP_DEBUG_RXD E2 UART1_RX DN1 C4 90_HYDRA_DP1_CONN_N BI 49

GND B1 UART2_TX DP2 A3 90_HYDRA_DP2_CONN_P BI 49


MAKE_BASE=TRUE A1 UART2_RX DN2 A4 90_HYDRA_DP2_CONN_N 49
NC BI

6 OUT
SWD_DOCK_TO_AP_SWCLK E1 JTAG_CLK CON_DET_L G3 HYDRA_CON_DETECT_L IN 49

6
SWD_DOCK_BI_AP_SWDIO F1 JTAG_DIO HYDRA_TO_TIGRIS_VBUS1_VALID_L
POW_GATE_EN* H3
BI
OUT 4 23
PMU_HYDRA_TO_AP_FORCE_DFU H2 FORCE_DFU
50 20 11 OUT
SWITCH_EN E4 PMU_TO_AP_HYDRA_ACTIVE_READY
B G2 EXT_SW_EN HOST_RESET F6 HYDRA_TO_PMU_HOST_RESET
IN 4 6 20

20
B
NC OUT
HYDRA_TO_NUB_DOCK_CONNECT G1 DOCK_CONNECT
12 OUT
SDA G5 I2C1_SMC_SDA BI 10

47 IN
CCG2_TO_HYDRA_CC B2 CC0 SCL G4 I2C1_SMC_SCL IN 10
A2 CC1 INT F7 HYDRA_TO_NUB_INT OUT 12

BYPASS F5 HYDRA_BYPASS

DVSS
DVSS1
1 C6330
1.0UF
20%

E3
G7
H1
H6
H7

F4
2 6.3V
X5R
0201-1
ROOM=HYDRA

A SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
PAGE TITLE

I/O: Hydra
DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
63 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 48 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

ARC DOCK FLEX CONNECTOR


Rcpt: 516S00038 <-- This one on MLB
FL6400 Plug: 516S00037
150OHM-25%-200MA-0.7DCR
48 47 46 38 22 20 17 14 12 10
PP1V8_S2 2 1 PP1V8_SAKONNET_CONN 49
50
01005
ROOM=B2B_DOCK 1 C6400
220PF
5%
2 10V
C0G-CERM
01005
R6416 ROOM=B2B_DOCK
J6400
I2C0_AP_SCL 0.00 I2C0_AP_TO_SAKONNET_SCL_CONN BM28P0.6-44DS-0.35V
46 20 10 IN
2 1 49 F-ST-SM

D 0%
1/32W 1 C6416
CKPLUS_WAIVE=I2C_PULLUP
50 49
SPKRAMP_BOT_TO_COIL_OUT_NEG 45 46 D
MF
01005 56PF SPKRAMP_BOT_TO_COIL_OUT_POS
ROOM=B2B_DOCK 5% 50 49
1 2
2 25V
NP0-C0G-CERM COIL_TO_SPKRAMP_BOT_VSENSE_POS_CONN 3 4 90_HYDRA_DP1_CONN_P
01005 49 48
ROOM=B2B_DOCK 49
COIL_TO_SPKRAMP_BOT_VSENSE_NEG_CONN 5 6 90_HYDRA_DP1_CONN_N 48
R6418 7 8
I2C0_AP_SDA 2
0.00 1 I2C0_AP_BI_SAKONNET_SDA_CONN PP_CODEC_TO_LOWERMIC4_BIAS_CONN 9 10 90_HYDRA_DP2_CONN_N
46 20 10 BI 49 49 48

0%
CKPLUS_WAIVE=I2C_PULLUP LOWERMIC4_TO_CODEC_BIAS_FILT_RET 11 12 90_HYDRA_DP2_CONN_P
1/32W
MF
1 C6418 38
LOWERMIC4_TO_CODEC_AIN4_CONN_N 13 14
48

01005 56PF 49
LOWERMIC4_TO_CODEC_AIN4_CONN_P
ROOM=B2B_DOCK 5% 49
15 16 PP_HYDRA_ACC1_CONN 49
2 25V
NP0-C0G-CERM PP1V8_IMU_COMPASS_DOCK_CONN 17 18 MIKEYBUS_REFERENCE 37
01005 49
ROOM=B2B_DOCK 49
I2C1_AOP_BI_COMPASS_SDA_DOCK_CONN 19 20 HYDRA_CON_DETECT_CONN_L 49
I2C1_AOP_TO_COMPASS_SCL_DOCK_CONN 21 22 PP1V8_SAKONNET_CONN 49
R6419 49
COMPASS_TO_AOP_INT_DOCK_CONN 23 24 I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_CONN 49
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK 2
49.9 1 I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_CONN 49
50 41 38 12 IN 49
25 26 I2C0_AP_BI_SAKONNET_SDA_CONN 49
1%
1/32W
MF
1 C6419 49
LOWERMIC1_TO_CODEC_AIN1_CONN_P 27 28 I2C0_AP_TO_SAKONNET_SCL_CONN 49
01005 68PF 49
LOWERMIC1_TO_CODEC_AIN1_CONN_N 29 30 I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK_CONN 49
ROOM=B2B_DOCK 5%
2 25V
NP0-C0G-CERM 38
LOWERMIC1_TO_CODEC_BIAS_FILT_RET 31 32 I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_CONN 49
01005 49
PP_CODEC_TO_LOWERMIC1_BIAS_CONN 33 34
R6420 ROOM=B2B_DOCK
49
I2C1_AP_BI_MIC1_SDA_CONN 35 36 PP_HYDRA_ACC2_CONN 49
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK 2
49.9 1 I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK_CONN I2C1_AP_TO_MIC1_SCL_CONN 37 38
50 41 38 12 IN 49 49

1% 39 40 ARC1_TO_SOLENOID1_OUT_NEG
1/32W
MF
1 C6420 SOLENOID1_TO_ARC1_VSENSE_NEG 41 42
41 49

01005 68PF 41
ARC1_TO_SOLENOID1_OUT_POS
ROOM=B2B_DOCK 5% 41
SOLENOID1_TO_ARC1_VSENSE_POS 43 44 41 49
2 25V
NP0-C0G-CERM
01005
Compass (Dock Flex Location) R6421
ROOM=B2B_DOCK 23
PP_VBUS1_E75 47 48

C NOSTUFF
FL6430 41 38 12 BI
I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT 2
49.9 1 I2S_AOP_AMPS_TO_CODEC_ASP1_DOUT_CONN 49
C6490
0.1UF
1 C6491
0.1UF
1 C6492
0.1UF
1 C6493
220PF
1 C6494
220PF
1 ROOM=B2B_DOCK C6495
0.1UF
1 C6496
0.1UF
1 C6497
0.1UF
1
C
150OHM-25%-200MA-0.7DCR 1% 10% 10% 10% 5% 5% 10% 10% 10%
PP1V8_IMU_S2 2 1 PP1V8_IMU_COMPASS_DOCK_CONN 1/32W
MF
1 C6421 25V 2
X5R
25V 2
X5R
25V 2
X5R
25V 2
COG
25V 2
COG
25V 2
X5R
25V 2
X5R
25V 2
X5R
26 25 17
NOSTUFF
49
01005 68PF 0201 0201 0201 01005 01005 0201 0201 0201
01005 5% ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK
ROOM=B2B_DOCK 1 C6430 ROOM=B2B_DOCK
2 25V
NP0-C0G-CERM
220PF 01005
5% ROOM=B2B_DOCK
2 10V
C0G-CERM 49 41
ARC1_TO_SOLENOID1_OUT_POS
NOSTUFF
01005
ROOM=B2B_DOCK
ARC1_TO_SOLENOID1_OUT_NEG 41 49 SOUTH SPEAKER FL6480
R6431 150OHM-25%-200MA-0.7DCR
0.00
IN
I2C1_AOP_SCL 2 1
NOSTUFF
I2C1_AOP_TO_COMPASS_SCL_DOCK_CONN 49 C6472 1 C6471 1 C6470 1 C6473 1 50 OUT
COIL_TO_SPKRAMP_BOT_VSENSE_POS 2 1 COIL_TO_SPKRAMP_BOT_VSENSE_POS_CONN 49

0%
CKPLUS_WAIVE=I2C_PULLUP 820PF 220PF 220PF 820PF 01005 NOSTUFF
1/32W
MF
1 C6431 10%
10V 2
5%
10V 2
5%
10V 2
10%
10V 2 ROOM=B2B_DOCK 1 C6480
01005 56PF X5R
01005
C0G-CERM
01005
C0G-CERM
01005
X5R
01005
220PF
ROOM=B2B_DOCK 5% 5%
2 25V
NP0-C0G-CERM
ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK ROOM=B2B_DOCK 2 10V
C0G-CERM
NOSTUFF 01005
ROOM=B2B_DOCK Hydra FL6482
01005
ROOM=B2B_DOCK
R6432 R6410 150OHM-25%-200MA-0.7DCR
I2C1_AOP_SDA 2
0.00 1 I2C1_AOP_BI_COMPASS_SDA_DOCK_CONN HYDRA_CON_DETECT_L 2
100 1 HYDRA_CON_DETECT_CONN_L COIL_TO_SPKRAMP_BOT_VSENSE_NEG 2 1 COIL_TO_SPKRAMP_BOT_VSENSE_NEG_CONN
BI 49 48 OUT 49 50 OUT 49
CKPLUS_WAIVE=I2C_PULLUP NOSTUFF
0% NOSTUFF 5% 01005
1/32W
MF
1 C6432 1/32W
MF
1 C6410 ROOM=B2B_DOCK 1 C6482
01005 56PF 01005 27PF 220PF
ROOM=B2B_DOCK 5% ROOM=B2B_DOCK 5% 5%
NOSTUFF 2 25V
NP0-C0G-CERM 2 16V
NP0-C0G 2 10V
C0G-CERM
01005 01005 01005
FL6433 ROOM=B2B_DOCK FL6411 ROOM=B2B_DOCK ROOM=B2B_DOCK
150OHM-25%-200MA-0.7DCR 10-OHM-1.1A
COMPASS_TO_AOP_INT 2 1 COMPASS_TO_AOP_INT_DOCK_CONN PP_HYDRA_ACC1 1 2 PP_HYDRA_ACC1_CONN
OUT 49 48 45 49
50 49
SPKRAMP_BOT_TO_COIL_OUT_POS
01005 NOSTUFF 01005 IN
ROOM=B2B_DOCK 1 C6433 ROOM=B2B_DOCK 1 C6411 C6484 1 1 C6483
220PF 220PF
B 5%
2 10V
5%
10V
2 C0G-CERM
820PF
10% 5%
220PF B
C0G-CERM 10V 2 2 10V
01005
ROOM=B2B_DOCK
FL6413 01005
ROOM=B2B_DOCK
X5R
01005
C0G-CERM
01005
22-OHM-25%-1800MA ROOM=B2B_DOCK ROOM=B2B_DOCK

48
PP_HYDRA_ACC2 1 2 PP_HYDRA_ACC2_CONN 49
0201
ROOM=B2B_DOCK
1 C6413 SPKRAMP_BOT_TO_COIL_OUT_NEG
220PF 50 49 IN
5%
2 10V
C0G-CERM
01005 C6486 1 1 C6485
LOWER MIC1 + LOWER MIC4 ROOM=B2B_DOCK 820PF
10%
10V 2
5%
220PF
2 10V
FL6450 FL6462 X5R
01005
C0G-CERM
01005
150OHM-25%-200MA-0.7DCR 150OHM-25%-200MA-0.7DCR ROOM=B2B_DOCK ROOM=B2B_DOCK

37 OUT
LOWERMIC1_TO_CODEC_AIN1_P 2 1 LOWERMIC1_TO_CODEC_AIN1_CONN_P 49 37 OUT
LOWERMIC4_TO_CODEC_AIN4_N 2 1 LOWERMIC4_TO_CODEC_AIN4_CONN_N 49
01005
ROOM=B2B_DOCK 1 C6450
01005
ROOM=B2B_DOCK
1 C6462
56PF 56PF
5% 5%
25V
2 NP0-C0G-CERM
2 25V
NP0-C0G-CERM 01005
FL6452
01005
ROOM=B2B_DOCK
FL6464 ROOM=B2B_DOCK
150OHM-25%-200MA-0.7DCR
150OHM-25%-200MA-0.7DCR
PP_CODEC_TO_LOWERMIC4_BIAS 2 1 PP_CODEC_TO_LOWERMIC4_BIAS_CONN 49
37 OUT
LOWERMIC1_TO_CODEC_AIN1_N 2 1 LOWERMIC1_TO_CODEC_AIN1_CONN_N 49
38
01005
01005
ROOM=B2B_DOCK
1 C6452 ROOM=B2B_DOCK 1 C6464
56PF 220PF
5% 5%
2 25V 2 10V
C0G-CERM
NP0-C0G-CERM 01005
01005
FL6454 ROOM=B2B_DOCK ROOM=B2B_DOCK
150OHM-25%-200MA-0.7DCR R6465
0.00
A 38
PP_CODEC_TO_LOWERMIC1_BIAS 2 1 PP_CODEC_TO_LOWERMIC1_BIAS_CONN 49 33 10 IN
I2C1_AP_SCL 2 1 I2C1_AP_TO_MIC1_SCL_CONN
CKPLUS_WAIVE=I2C_PULLUP
49
A
C6454
SYNC_MASTER=test_mlb

01005 1 0%
SYNC_DATE=10/13/2016

ROOM=B2B_DOCK
220PF
1/32W
MF
1 C6465 PAGE TITLE

5%
2 10V
01005
ROOM=B2B_DOCK 5%
56PF I/O: B2B Dock
C0G-CERM 2 25V
NP0-C0G-CERM DRAWING NUMBER SIZE
01005
FL6460 ROOM=B2B_DOCK
01005 051-02221 D
150OHM-25%-200MA-0.7DCR R6466
ROOM=B2B_DOCK
Apple Inc. REVISION

37
LOWERMIC4_TO_CODEC_AIN4_P 2 1 LOWERMIC4_TO_CODEC_AIN4_CONN_P 49 33 10
I2C1_AP_SDA 2
0.00 1 I2C1_AP_BI_MIC1_SDA_CONN 49
9.0.0
OUT BI
CKPLUS_WAIVE=I2C_PULLUP NOTICE OF PROPRIETARY PROPERTY: BRANCH
01005
ROOM=B2B_DOCK
1 C6460 0%
1/32W 1 C6466 THE INFORMATION CONTAINED HEREIN IS THE evt-1
56PF MF
01005 56PF PROPRIETARY PROPERTY OF APPLE INC.
5% 5% THE POSESSOR AGREES TO THE FOLLOWING: PAGE
2 25V
NP0-C0G-CERM
ROOM=B2B_DOCK
2 25V I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
64 OF 80
01005 NP0-C0G-CERM II NOT TO REPRODUCE OR COPY IT
ROOM=B2B_DOCK
01005 SHEET
ROOM=B2B_DOCK III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 49 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

11 UART_AP_TO_GNSS_TXD S1 IOS1 J_INT_BOT IOS87 S87 PP1V8_S2 10 12 14 17 20 22 38 46 47 48


49 50
11 UART_AP_TO_GNSS_RTS_L
S2 IOS2 INTERPOSER-BOT-D22 IOS88 S88
11 UART_GNSS_TO_AP_CTS_L
S3 IOS3 SMT-PAD IOS89 S89 PP_VDD_MAIN 18 19 21 23 27 31 34 41 42 43
SYM 3 OF 3 45 46 50
11 UART_GNSS_TO_AP_RXD
S4 IOS4 IOS90 S90 BB_TO_PMU_PCIE_HOST_WAKE_L 20

11 AP_TO_GNSS_WAKE
S5 IOS5 IOS91 S91 PMU_TO_BBPMU_RESET_L 20

D 20 PMU_TO_GNSS_EN
S6 IOS6 IOS92 S92 PMU_AMUX_AY 20 D
11 AP_TO_BB_TIME_MARK
S7 IOS7 SIGNAL IOS93 S93 AOP_TO_WLAN_CONTEXT_B 12

7 90_PCIE_AP_TO_BB_REFCLK_N
S8 IOS8 IOS94 S94 UART_BB_TO_AOP_RXD 12
S9 IOS9 IOS95 S95 UART_AOP_TO_BB_TXD
7 90_PCIE_AP_TO_BB_REFCLK_P
S10 IOS10 IOS96 S96 AOP_TO_WLAN_CONTEXT_A
12 G1 IOG1 J_INT_BOT IOG63 G63 G125 IOG125
J_INT_BOT IOG187 G187
12 G2 IOG2 INTERPOSER-BOT-D22 IOG64 G64 G126 IOG126 IOG188 G188
7 90_PCIE_BB_TO_AP_RXD_P
S11 IOS11 IOS97 S97 BT_TO_PMU_HOST_WAKE INTERPOSER-BOT-D22
20 G3 IOG3 SMT-PAD IOG65 G65 G127 IOG127 IOG189 G189
7 90_PCIE_BB_TO_AP_RXD_N
S12 IOS12 IOS98 S98 PMU_TO_BT_REG_ON SYM 1 OF 3 SMT-PAD
20 G4 IOG4 IOG66 G66 G128 IOG128 IOG190 G190
7 90_PCIE_AP_TO_BB_TXD_P
S13 IOS13 IOS99 S99 PMU_TO_WLAN_CLK32K SYM 2 OF 3
20 G5 IOG5 IOG67 G67 G129 IOG129 IOG191 G191
S14 IOS14 IOS100 S100 WLAN_TO_PMU_HOST_WAKE 20 G6 IOG6 GND IOG68 G68 G130 IOG130 IOG192 G192
90_PCIE_AP_TO_BB_TXD_N S15 IOS15 IOS101 S101 PMU_TO_WLAN_REG_ON
7 20 G7 IOG7 IOG69 G69 G131 IOG131 GND IOG193 G193
7 90_PCIE_WLAN_TO_AP_RXD_P
S16 IOS16 IOS102 S102 PMU_AMUX_BY 20 G8 IOG8 IOG70 G70 G132 IOG132 IOG194 G194
S17 IOS17 IOS103 S103 CODEC_TO_SPKRAMP_BOT_ARC_MCLK 38 41 G9 IOG9 IOG71 G71 G133 IOG133 IOG195 G195
7 90_PCIE_WLAN_TO_AP_RXD_N
S18 IOS18 IOS104 S104 PMU_TO_BB_USB_VBUS_DETECT 20 G10 IOG10 IOG72 G72 G134 IOG134 IOG196 G196
7 90_PCIE_AP_TO_WLAN_REFCLK_N
S19 IOS19 IOS105 S105 PMU_HYDRA_TO_AP_FORCE_DFU 11 20 48 G11 IOG11 IOG73 G73 G135 IOG135 IOG197 G197
S20 IOS20 IOS106 S106 AP_TO_BT_WAKE 11 G12 IOG12 IOG74 G74 G136 IOG136 IOG198 G198
90_PCIE_AP_TO_WLAN_REFCLK_P S21 IOS21 IOS107 S107 WLAN_TO_AP_TIME_SYNC
7 11 G13 IOG13 IOG75 G75 G137 IOG137 IOG199 G199
7 90_PCIE_AP_TO_WLAN_TXD_N
S22 IOS22 IOS108 S108 RADIO_PA_NTC 20 G14 IOG14 IOG76 G76 G138 IOG138 IOG200 G200
S23 IOS23 IOS109 S109 AP_TO_MANY_BSYNC 8 12 20 21 28 G15 IOG15 IOG77 G77 G139 IOG139 IOG201 G201
7 90_PCIE_AP_TO_WLAN_TXD_P S24 IOS24 IOS110 S110 TOUCH_TO_AMUX_PP1V8 20 G16 IOG16 IOG78 G78 G140 IOG140 IOG202 G202
S25 IOS25 IOS111 S111 PP3V5_RACER 42 G17 IOG17 IOG79 G79 G141 IOG141 IOG203 G203
S26 IOS26 IOS112 S112 PP1V1_RACER 42
G18 IOG18 IOG80 G80 G142 IOG142 IOG204 G204
20 PMU_TO_IKTARA_EN_EXT_1P8V S27 IOS27 IOS113 S113
G19 IOG19 IOG81 G81 G143 IOG143 IOG205 G205
10 IKTARA_TO_SMC_INT
S28 IOS28 IOS114 S114 PP5V25_TOUCH_VDDH 42 G20 IOG20 IOG82 G82 G144 IOG144 IOG206 G206
47 23 22 21 10 I2C0_SMC_SCL
S29 IOS29 IOS115 S115 RACER_TO_ACORN_ORB_SCAN 42 G21 IOG21 IOG83 G83 G145 IOG145 IOG207 G207
47 23 22 21 10 I2C0_SMC_SDA
S30 IOS30 IOS116 S116 PP1V8_TOUCH_RACER_S2 17 42
G22 IOG22 IOG84 G84 G146 IOG146 IOG208 G208
36 31 BB_TO_STROBE_DRIVER_GSM_BURST_IND
S31 IOS31 IOS117 S117 I2C3_AP_SCL 10 42 G23 IOG23 IOG85 G85 G147 IOG147 IOG209 G209
S32 IOS32 IOS118 S118 I2C3_AP_SDA
C 37 PDM_CODEC_TO_SPKRAMP_TOP_CLK
NC
S33 IOS33 IOS119 S119 TOUCH_TO_ACORN_PP5V25_EN
10 42

42
G24
G25
IOG24 IOG86 G86
G87
G148
G149
IOG148 IOG210 G210
G211
C
S34 S120 IOG25 IOG87 IOG149 IOG211
37 PDM_CODEC_TO_SPKRAMP_TOP_DATA IOS34 IOS120 PN6V7_RACER 42 G26 G88 G150 G212
S35 S121 IOG26 IOG88 IOG150 IOG212
7 PCIE_AP_TO_BB_RESET_L IOS35 IOS121 PMU_TO_TOUCH_CLK32K_RESET_L 20 G27 IOG27 IOG89 G89 G151 IOG151 IOG213 G213
10 I2S_AP_TO_SPKRAMP_TOP_MCLK
S36 IOS36 IOS122 S122 PP10V0_RACER 42 G28 IOG28 IOG90 G90 G152 IOG152 IOG214 G214
11 AP_TO_SPKRAMP_TOP_RESET_L
S37 IOS37 IOS123 S123 AP_TO_RACER_RESET_L 11
G29 IOG29 IOG91 G91 G153 IOG153 IOG215 G215
11 SPKRAMP_TOP_TO_AP_INT_L
S38 IOS38 IOS124 S124 RACER_TO_AOP_INT_L 12
G30 IOG30 IOG92 G92 G154 IOG154 IOG216 G216
10 I2C2_AP_SDA
S39 IOS39 IOS125 S125 SWD_AOP_TO_MANY_SWCLK 4 12 16
G31 IOG31 IOG93 G93 G155 IOG155 IOG217 G217
10 I2C2_AP_SCL
S40 IOS40 IOS126 S126 SWD_AOP_BI_RACER_SWDIO 12
G32 IOG32 IOG94 G94 G156 IOG156 IOG218 G218
41 38 19 PP1V8_AUDIO_VA_S2
S41 IOS41 IOS127 S127 UART_AOP_TO_RACER_TXD 12
G33 IOG33 IOG95 G95 G157 IOG157 IOG219 G219
4
PP_GPU_LVCC S42 IOS42 IOS128 S128 UART_RACER_TO_AOP_RXD 12
G34 IOG34 IOG96 G96 G158 IOG158 IOG220 G220
4
PP_CPU_PCORE_LVCC S43 IOS43 IOS129 S129 HALL2_TO_AOP_IRQ_L 12
G35 IOG35 IOG97 G97 G159 IOG159 IOG221 G221
11 AP_TO_BB_IPC_GPIO1
S44 IOS44 IOS130 S130 AP_TO_RACER_REF_CLK 10
G36 IOG36 IOG98 G98 G160 IOG160 IOG222 G222
11 AP_TO_BB_RESET_L
S45 IOS45 IOS131 S131 SPI_AP_TO_RACER_CS_L 10
G37 IOG37 IOG99 G99 G161 IOG161 IOG223 G223
12
HALL3_TO_AOP_IRQ_L S46 IOS46 IOS132 S132 SPI_RACER_TO_AP_MISO 10
G38 IOG38 IOG100 G100 G162 IOG162 IOG224 G224
S47 IOS47 IOS133 S133 SPI_AP_TO_RACER_MOSI 10
NC G39 IOG39 IOG101 G101 G163 IOG163 IOG225 G225
10 5 BOARD_ID3
S48 IOS48 IOS134 S134 SPI_AP_TO_RACER_SCLK 10
G40 IOG40 IOG102 G102 G164 IOG164 IOG226 G226
7 PCIE_WLAN_BI_AP_CLKREQ_L
S49 IOS49 IOS135 S135 PP_BATT_VCC 22 23
G41 IOG41 IOG103 G103 G165 IOG165 IOG227 G227
7 PCIE_AP_TO_WLAN_RESET_L
S50 IOS50 IOS136 S136
G42 IOG42 IOG104 G104 G166 IOG166 IOG228 G228
49 41 38 12 I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK
S51 IOS51 IOS137 S137 PP3V0_S2 19 36 45 47 48
G43 IOG43 IOG105 G105 G167 IOG167 IOG229 G229
41 38 12 I2S_CODEC_ASP1_TO_AOP_AMPS_DIN
S52 IOS52 IOS138 S138
G44 IOG44 IOG106 G106 G168 IOG168 IOG230 G230
49 41 38 12 I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK
S53 IOS53 IOS139 S139 90_USB_BB_DATA_P 48
G45 IOG45 IOG107 G107 G169 IOG169 IOG231 G231
20 PMU_TO_IKTARA_RESET_L
S54 IOS54 IOS140 S140 90_USB_BB_DATA_N 48
G46 IOG46 IOG108 G108 G170 IOG170 IOG232 G232
10 I2S_BB_TO_AP_DIN
S55 IOS55 IOS141 S141
G47 IOG47 IOG109 G109 G171 IOG171 IOG233 G233
10 I2S_BB_TO_AP_LRCLK
S56 IOS56 IOS142 S142 PP_VBUS2_IKTARA 23
G48 IOG48 IOG110 G110 G172 IOG172 IOG234 G234
10 I2S_BB_TO_AP_BCLK
S57 IOS57 IOS143 S143
G49 IOG49 IOG111 G111 G173 IOG173 IOG235 G235
10 I2S_AP_TO_BB_DOUT
S58 IOS58 IOS144 S144
G50 G112 G174 G236
B 11 BB_TO_AP_RESET_DETECT_L
S59 IOS59 IOS145 S145
G51
IOG50
IOG51
IOG112
IOG113 G113 G175
IOG174
IOG175
IOG236
IOG237 G237 B
11 AP_TO_BBPMU_RADIO_ON_L
S60 IOS60 IOS146 S146 IKTARA_COIL2 25
G52 IOG52 IOG114 G114 G176 IOG176 IOG238 G238
11 AP_TO_WLAN_DEVICE_WAKE
S61 IOS61 IOS147 S147
G53 IOG53 IOG115 G115 G177 IOG177 IOG239 G239
41 12 SPKRAMP_BOT_ARC_TO_AOP_INT_L
S62 IOS62 IOS148 S148
G54 IOG54 IOG116 G116 G178 IOG178 IOG240 G240
41 12 AOP_TO_SPKRAMP_BOT_ARC_RESET_L
S63 IOS63 IOS149 S149
G55 IOG55 IOG117 G117 G179 IOG179 IOG241 G241
S64 IOS64 IOS150 S150 IKTARA_COIL1 25
NC G56 IOG56 IOG118 G118 G180 IOG180 IOG242 G242
12 SWD_AOP_BI_BB_SWDIO
S65 IOS65 IOS151 S151
G57 IOG57 IOG119 G119 G181 IOG181 IOG243 G243
49 41 25 12 4 I2C1_AOP_SDA
S66 IOS66 IOS152 S152
G58 IOG58 IOG120 G120 G182 IOG182 IOG244 G244
49 41 25 12 4 I2C1_AOP_SCL
S67 IOS67 IOS153 S153
G59 IOG59 IOG121 G121 G183 IOG183 IOG245 G245
43 42 41 34 31 27 23 21 19 18 PP_VDD_MAIN
S68 IOS68 IOS154 S154 AP_TO_BB_COREDUMP 11
50 46 45 G60 IOG60 IOG122 G122 G184 IOG184 IOG246 G246
S69 IOS69 IOS155 S155 PCIE_BB_BI_AP_CLKREQ_L 7
G61 IOG61 IOG123 G123 G185 IOG185 IOG247 G247
S70 IOS70 IOS156 S156 SPKRAMP_TOP_TO_COIL_OUT_POS 36
G62 IOG62 IOG124 G124 G186 IOG186 IOG248 G248
S71 IOS71 IOS157 S157 SPKRAMP_TOP_TO_COIL_OUT_NEG 36
S72 IOS72 IOS158 S158 COIL_TO_SPKRAMP_TOP_VSENSE_POS 36
S73 IOS73 IOS159 S159 COIL_TO_SPKRAMP_TOP_VSENSE_NEG 36
S74 IOS74 IOS160 S160 COIL_TO_SPKRAMP_BOT_VSENSE_POS 49
S75 IOS75 IOS161 S161 COIL_TO_SPKRAMP_BOT_VSENSE_NEG 49
S76 IOS76 IOS162 S162 SPKRAMP_BOT_TO_COIL_OUT_POS 49

11 UART_AP_TO_BT_RTS_L S77 IOS77 IOS163 S163 SPKRAMP_BOT_TO_COIL_OUT_NEG 49

11 UART_BT_TO_AP_CTS_L
S78 IOS78 IOS164 S164 AP_TO_NFC_DEV_WAKE 11

11 UART_AP_TO_BT_TXD
S79 IOS79 IOS165 S165 UART_NFC_TO_AP_CTS_L 11

11 UART_BT_TO_AP_RXD
S80 IOS80 IOS166 S166 UART_AP_TO_NFC_TXD 11

38 34 27 21 19 PP_VDD_BOOST
S81 IOS81 IOS167 S167 UART_NFC_TO_AP_RXD 11

11 UART_AP_TO_WLAN_TXD
S82 IOS82 IOS168 S168 UART_AP_TO_NFC_RTS_L 11

11 UART_AP_TO_WLAN_RTS_L
S83 IOS83 IOS169 S169 AP_TO_NFC_FW_DWLD_REQ 11

11 UART_WLAN_TO_AP_RXD
S84 IOS84 IOS170 S170 NFC_TO_PMU_HOST_WAKE
A 11 UART_WLAN_TO_AP_CTS_L
S85 IOS85 IOS171 S171 PMU_TO_NFC_EN
20

20 SYNC_MASTER=test_mlb SYNC_DATE=10/13/2016
A
48 47 46 38 22 20 17 14 12 10 PP1V8_S2
S86 IOS86 IOS172 S172 PAGE TITLE
NC
50 49
I/O: Interposer (Bottom)
DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
65 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 50 OF 51
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C C

Radios on MLB Bottom

B B

A SYNC_DATE=06/04/2015 A
PAGE TITLE

RADIOS
DRAWING NUMBER SIZE

051-02221 D
Apple Inc. REVISION

9.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
80 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 51 OF 51
8 7 6 5 4 3 2 1
CR-1 : @MLB_BOT_LIB.MLB_BOT(SCH_1):PAGE1

8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
7 0008448938 ENGINEERING RELEASED 2017-04-11

X893 MLB Bottom: EVT


D D

LAST_MODIFICATION=Tue Apr 11 16:10:11 2017


PAGE CSA CONTENTS SYNC DATE PAGE CSA CONTENTS SYNC DATE
1 1 TABLE OF CONTENTS 07/29/2016
2 2 SYSTEM:BOM Tables 03/08/2017
3 4 SYSTEM: Mechanical Components 12/01/2016
4 6 BOOTSTRAPPING 11/03/2016
5 7 SYSTEM: Testpoints (Bottom) test_mlb 01/17/2017
6 34 SYSTEM POWER: Iktara mlb_bot 04/04/2017
7 49 AUDIO: Speaker Amp Bottom mlb_bot 04/04/2017
8 50 AUDIO: Speaker Amp Top mlb_bot 04/04/2017
9 55 HALL EFFECT mlb_bot 04/04/2017
10 58 CG: B2B Luna & Touch mlb_bot 04/04/2017
11 66 I/O: Interposer (Top) mlb_bot 04/04/2017
12 80 RADIOS 07/29/2016
13 1 RADIO_MLB
C 14 2 BASEBAND C
15 3 BASEBAND MEMORY/DEBUG
16 4 BASEBAND POWER
17 5 BASEBAND PMIC
18 6 TRANSCEIVERS
19 7 ET MODULATOR
20 8 TDD TRANSMIT
21 9 FDD TRANSMIT
22 10 PRIMARY RECEIVE
23 11 LOWER ANTENNA & COUPLERS
24 12 DIVERSITY RECEIVE ASM'S
25 13 DIVERSITY RECEIVE LNA'S
26 14 UPPER ANTENNA FEEDS
27 15 GNSS
28 16 TEST POINTS & SIM
29 17 RF CONNECTORS AND MC
30 1 SymbolPorts
31 4 Guinness WIFI 01/30/2014
B 32 5 WiFiANTFeeds
B
33 1 page1
34 75 NFC

A
Sub Designs TABLE_HIERARCHY_CONFIG_HEAD
TABLE OF CONTENTS SYNC_DATE=07/29/2016 A
HARD/ DRAWING TITLE
SOURCE PROJECT SUB-DESIGN NAME VERSION SOFT
SYNC_DATE/TIME
SCH,MLB,BOT,X893
BOM:639-03229
TABLE_HIERARCHY_CONFIG_ITEM

D221 RADIO_MLB 0.115.0 S 2017_04_05_18:48:43


TABLE_HIERARCHY_CONFIG_ITEM DRAWING NUMBER SIZE

D22 NFC_MLB 0.22.0 S 2017_03_22_22:11:23 051-02247 D


MCO:056-04080 D22 WIFI_MLB 0.20.0 S 2017_04_04_09:54:33
TABLE_HIERARCHY_CONFIG_ITEM

Apple Inc. REVISION

7.0.0
TABLE_5_HEAD

NOTICE OF PROPRIETARY PROPERTY: BRANCH


PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
evt-1
051-02247 1 SCH,MLB_BOT,X893 SCH NO COMMON THE POSESSOR AGREES TO THE FOLLOWING: PAGE

820-00869 1 PCB,MLB_BOT,X893 PCB NO COMMON


TABLE_5_ITEM I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 1 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

EEEE Codes TABLE_5_HEAD

Iktara Soft-Term Cap Sub BOMs


PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM TABLE_5_HEAD TABLE_5_HEAD

825-7691 1 EEEE FOR (MLB_BOT, 639-03229) EEEE_HM07 NO COMMON PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION
TABLE_5_ITEM TABLE_5_ITEM

132S00021 8 CAP,CER,0.082UF,10%,50V,X7R,0402 C3452,C3453,C3454,C3456,C3461,C3462,C3463,C3464 NO COMMON 685-00159 1 SUBBOM,MLB,BOT,CAP,TYPICAL,X893 SUBBOM_CAP CRITICAL COMMON


TABLE_5_ITEM

132S0423 2 CAP,CER,0.022UF,50V,X7R,10%,0402 C3451,C3465 CRITICAL COMMON


TABLE_5_ITEM
Touch/Luna B2B

Global Capacitors 132S0423 2 C3455,C3466 CRITICAL NOSTUFF TABLE_5_HEAD

CAP,CER,0.022UF,50V,X7R,10%,0402
PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION

D 138S00159 1 CAP,SOFT-TERM,2.2UF,6.3V,0201,KYOCERA C5890 CRITICAL SOFT_CAP


TABLE_5_ITEM
D
TABLE_ALT_HEAD TABLE_CRITICAL_HEAD TABLE_ALT_HEAD TABLE_5_ITEM

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: 138S0831 1 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C5890 CRITICAL TYPICAL_CAP
PART NUMBER PART NUMBER
TABLE_CRITICAL_ITEM

TABLE_ALT_ITEM

138S00149 0402-3T,10.5uF@1V TABLE_ALT_ITEM

138S00148 138S00149 BOM_TABLE_ALTS ALL 0402-3T,10.5uF@1V, Kyocera 685-00185 685-00184 BOM_TABLE_ALTS SUBBOM_DS SUBBOM,MLB,BOT,DIODES,ONSEMI,X893

TABLE_ALT_ITEM TABLE_ALT_HEAD

138S00150 138S00149 BOM_TABLE_ALTS ALL 0402-3T,10.5uF@1V, SEMCO PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
PART NUMBER
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION


TABLE_ALT_ITEM

138S00151 138S00149 BOM_TABLE_ALTS ALL 0402-3T,10.5uF@1V, TY


TABLE_ALT_ITEM

TABLE_5_ITEM

685-00160 685-00159 BOM_TABLE_ALTS SUBBOM_CAP SUBBOM,MLB,BOT,CAP,SOFT,X893


685-00184 1 SUBBOM,MLB,BOT,DIODES,DIODES,X893 SUBBOM_DS CRITICAL COMMON
TABLE_ALT_HEAD TABLE_CRITICAL_HEAD TABLE_5_ITEM

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT 371S00133 4 DIODES,SHOTTKY DIODE,30V,2A,0603 D3400,D3401,D3402,D3403 CRITICAL DIODES_DS
PART NUMBER
TABLE_CRITICAL_ITEM TABLE_5_ITEM

TABLE_ALT_ITEM

138S00144 0402,16uF@1V 371S00132 4 ONSEMI,SHOTTKY DIODE,30V,2A,0603 D3400,D3401,D3402,D3403 CRITICAL ONSEMI_DS


138S00143 138S00144 BOM_TABLE_ALTS ALL 0402,16uF@1V, Kyocera
TABLE_ALT_ITEM

138S00163 138S00144 BOM_TABLE_ALTS ALL 0402,16uF@1V, Taiyo

TABLE_ALT_HEAD TABLE_CRITICAL_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
PART NUMBER
TABLE_CRITICAL_ITEM

TABLE_ALT_ITEM

138S00139 0201,3uF@1V
138S00138 138S00139 BOM_TABLE_ALTS ALL 0201,3uF@1V, Kyocera
TABLE_ALT_ITEM

138S00164 138S00139 BOM_TABLE_ALTS ALL 0201,3uF@1V, Taiyo

TABLE_ALT_HEAD TABLE_CRITICAL_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS: CRITICAL PART# COMMENT
PART NUMBER
TABLE_CRITICAL_ITEM

TABLE_ALT_ITEM

138S00146 0402,5.1uF@3V
138S00145 138S00146 BOM_TABLE_ALTS ALL 0402,5.1uF@3V, Kyocera
TABLE_ALT_ITEM

138S00165 138S00146 BOM_TABLE_ALTS ALL 0402,5.1uF@3V, Taiyo

C PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


TABLE_ALT_HEAD

CRITICAL PART# COMMENT


TABLE_CRITICAL_HEAD
C
PART NUMBER
TABLE_CRITICAL_ITEM

TABLE_ALT_ITEM

138S00141 0201,1.1uF@3V
138S00140 138S00141 BOM_TABLE_ALTS ALL 0201,1.1uF@3V, Kyocera
TABLE_ALT_ITEM

138S00142 138S00141 BOM_TABLE_ALTS ALL 0201,1.1uF@3V, SEMCO


TABLE_ALT_ITEM

138S00166 138S00141 BOM_TABLE_ALTS ALL 0201,1.1uF@3V, Taiyo

Global Ferrites TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


TABLE_CRITICAL_HEAD

PART NUMBER CRITICAL PART# COMMENT


TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

152S00558 152S00557 BOM_TABLE_ALTS ALL IND,MLD,0.47UH,20%,2.5A,80MO,1608 152S00557 IND,MLD,0.47UH,20%,2.5A,80MO,1608


TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

155S00194 155S0610 BOM_TABLE_ALTS ALL FERR BD,150 OHM,25%,200MA,0.7 DCR,01005 155S0610 FERR BD,150 OHM,25%,200MA,0.7 DCR,01005
TABLE_ALT_ITEM

155S00200 155S0610 BOM_TABLE_ALTS ALL FERR BD,150 OHM,25%,200MA,0.7 DCR,01005

Global R/C Alternates


PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:
TABLE_ALT_HEAD

TABLE_CRITICAL_HEAD

PART NUMBER CRITICAL PART# COMMENT


TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

B 138S0648 138S0652 BOM_TABLE_ALTS ALL CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO

TABLE_ALT_ITEM
138S0652 CAP,X5R,4.7UF,6.3V,0.65MM,0402,TAIYO
TABLE_CRITICAL_ITEM
B
138S00024 138S0986 BOM_TABLE_ALTS ALL CAP,CER,3-TERM,7.5UF,20%,4V,0402,TAIYO/TDK 138S0986 CAP,CER,3-TERM,7.5UF,20%,4V,0402,TAIYO/TDK
TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

138S0706 138S0739 BOM_TABLE_ALTS ALL CAP,CER,1UF,20%,10V,X5R,0201,MURATA 138S0739 CAP,CER,1UF,20%,10V,X5R,0201,MURATA


TABLE_ALT_ITEM

138S0945 138S0739 BOM_TABLE_ALTS ALL CAP,CER,1UF,20%,10V,X5R,0201,KYOCERA

TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

138S0739 138S0706 BOM_TABLE_ALTS ALL CAP,CER,X5R,0.22UF,20%,6.3V,20% 138S0706 CAP,CER,X5R,0.22UF,20%,6.3V,20%


TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

132S0436 132S0400 BOM_TABLE_ALTS ALL CAP,CER,X5R,0.22UF,20%,6.3V,01005 132S0400 CAP,CER,X5R,0.22UF,20%,6.3V,01005


TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

138S00049 138S0831 BOM_TABLE_ALTS ALL CAP,CER,X5R,2.2UF,20%,6.3V,0201 138S0831 CAP,CER,X5R,2.2UF,20%,6.3V,0201

Global Inductors TABLE_ALT_HEAD

PART NUMBER ALTERNATE FOR BOM OPTION REF DES COMMENTS:


TABLE_CRITICAL_HEAD

PART NUMBER CRITICAL PART# COMMENT


TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

152S00653 152S00651 BOM_TABLE_ALTS ALL IND,1.2UH,3A,2016,0.65Z 152S00651 IND,1.2UH,3A,2016,0.65Z


TABLE_ALT_ITEM TABLE_CRITICAL_ITEM

152S00654 152S00652 BOM_TABLE_ALTS ALL IND,1.2UH,3A,2016,0.8Z 152S00652 IND,1.2UH,3A,2016,0.8Z

Multi-Vendor Criticals TABLE_CRITICAL_HEAD TABLE_CRITICAL_HEAD

CRITICAL PART# COMMENT CRITICAL PART# COMMENT

A
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

138S0979 CAP,CER,X5R,10UF,20%,10V,0402,H=0.65MM
TABLE_CRITICAL_ITEM
132S00008 CAP,CER,0.1UF,10%,50V,X7R,0402
TABLE_CRITICAL_ITEM
SYNC_MASTER= SYNC_DATE=03/08/2017 A
PAGE TITLE
138S0683 CAP,CER,X5R,1UF,10%,25V,0402 131S0804 CAP,CER,27PF,5%,C0G,25V,0201

132S0663 CAP,CER,X5R,1UF,10%,25V,0402
TABLE_CRITICAL_ITEM

131S0307 CAP,CER,NP0/C0G,100PF,5%,16V,01005
TABLE_CRITICAL_ITEM

SYSTEM:BOM Tables
DRAWING NUMBER SIZE
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM

132S0288 CAP,CER,X5R,0.1UF,10%,16V,0201 131S00053 CAP,CER,C0G,220PF,5%,10V,01005 051-02247 D


TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM Apple Inc. REVISION
132S0275 CAP,CER,X5R,470PF,10%,10V,01005 117S0055 RES,MF,1/20W,2M OHM,5,0201,SMD
TABLE_CRITICAL_ITEM TABLE_CRITICAL_ITEM
7.0.0
132S0245 CAP,CER,X5R,0.01UF,10%,6.3V,01005 107S0257 THERMISTOR,NTC,10K OHM,1%,B=3435,01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
2 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 2 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

FIDUCIALS
D D
FD0401
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY

FD0402
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY

FD0403
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY

FD0404
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY

FD0405
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY

FD0406
FID
0P5SQ-CROSS-NSP
1
ROOM=ASSEMBLY

C FD0410 C
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY

FD0411
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY

FD0412
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY

FD0413
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY

FD0414
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY

FD0415
FID
0P5SQ-SMP3SQ-NSP
1
ROOM=ASSEMBLY

B B

CRITICAL
SB0400
STDOFF-SUBMERGED-X891
1

ROOM=ASSEMBLY

A SYNC_DATE=12/01/2016 A
PAGE TITLE

SYSTEM: Mechanical Components


DRAWING NUMBER SIZE

051-02247 D
Apple Inc. REVISION

7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
4 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 3 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

BOOTSTRAPPING:BOARD ID[3]

PP1V8_S2 6 9 11 12

C C

R0630
BOARD_ID3 1
1.00K 2
11 OUT
CKPLUS_WAIVE=SINGLE_NODENET
5%
1/32W
MF
01005
ROOM=SOC

B B

D221 Selected (BOARD_ID3) ->

A SYNC_DATE=11/03/2016 A
SYNC_MASTER
PAGE TITLE

BOOTSTRAPPING
DRAWING NUMBER SIZE

051-02247 D
Apple Inc. REVISION

7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
6 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 4 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Test Points Probe Points


TP0700 TP0750 TP0780
12 11 8 7 6 PP_VDD_MAIN 1
TP-P55
ROOM=TEST
A VDD_MAIN
GND
TP-P55
ROOM=TEST
A 11 10
PP1V8_TOUCH_RACER_S2
TP-P55
ROOM=TEST
A Iktara Debug
PP0700
P2MM-NSM
D TP0701
1 PP5V25_TOUCH_VDDH TP0751 GND TP0790
1 11 6 IN
PMU_TO_IKTARA_EN_EXT_1P8V 1
SM
PP ROOM=TEST
D
A 11 10 A A Stockholm GND TP
TP-P55 TP-P55 TP-P55
ROOM=TEST ROOM=TEST ROOM=TEST
PP0701
P2MM-NSM
TP0702
1 PP3V5_RACER TP0752 IKTARA_ANA1 1
SM
ROOM=TEST
A 11 10 A 6 IN PP
TP-P55 TP-P55
ROOM=TEST ROOM=TEST

TP0703 TP0753 PP0702


P2MM-NSM
1 PN6V7_RACER SM
A 11 10 A 6 IN
IKTARA_GPIO3 1
PP ROOM=TEST
TP-P55 TP-P55
ROOM=TEST ROOM=TEST

PP10V0_RACER TP0754 PP0703


PP_BATT_VCC TP0515
1 VBATT 11 10 A IKTARA_GPIO4
P2MM-NSM
1
SM
11 A TP-P55 6 IN PP ROOM=TEST
TP-P55 ROOM=TEST
ROOM=TEST

TP0522
1 TP0755 PP0704
A 11 10
PP1V1_RACER A P2MM-NSM
TP-P55 SM
ROOM=TEST TP-P55 11 6 IN
IKTARA_TO_SMC_INT 1
PP ROOM=TEST
ROOM=TEST

TP0705 TP0707 TP0709 TOUCH_TO_ACORN_PP5V25_EN TP0756


1 1 1 11 10 A
A A A TP-P55
TP-P55 TP-P55 TP-P55 ROOM=TEST
ROOM=TEST ROOM=TEST ROOM=TEST

TP0706 TP0708 TP0710 TOUCH_TO_AMUX_PP1V8 TP0757


1 1 1 11 10 A
A A A TP-P55
TP-P55 TP-P55 TP-P55
C ROOM=TEST ROOM=TEST ROOM=TEST
ROOM=TEST
C
PMU_TO_TOUCH_CLK32K_RESET_L TP0758
11 10 A
TP-P55
ROOM=TEST

AMUX 12 11 10
AP_TO_MANY_BSYNC TP0759
A
PMU_AMUX_AY TP0713
1
TP-P55
11 A ANALOG MUX A OUTPUT ROOM=TEST
TP-P55
ROOM=TEST
HALL2_TO_AOP_IRQ_L TP0760
11 10 A
TP-P55
ROOM=TEST

PMU_AMUX_BY TP0715
1 TP0761
11 A ANALOG MUX B OUTPUT 11 10
AP_TO_RACER_RESET_L A
TP-P55
ROOM=TEST TP-P55
ROOM=TEST

UART_RACER_TO_AOP_RXD TP0762
11 10 A
DFU TP-P55
ROOM=TEST

PMU_HYDRA_TO_AP_FORCE_DFU TP0714
1 TP0763
11 A 11 10
RACER_TO_AOP_INT_L A
TP-P55
ROOM=TEST FORCE DFU TP-P55
ROOM=TEST

UART_AOP_TO_RACER_TXD TP0764
B 11 10 A B
LVCC TP-P55
ROOM=TEST

PP_GPU_LVCC TP0720
1
11 A
TP-P55
ROOM=TEST

PP_CPU_PCORE_LVCC TP0721
1 RACER_TO_ACORN_ORB_SCAN TP0766
11 A 11 10 A
TP-P55 TP-P55
ROOM=TEST ROOM=TEST

SPI_AP_TO_RACER_CS_L TP0767
COIL 11 10
TP-P55
ROOM=TEST
A

IKTARA_COIL1 TP0730 SPI_AP_TO_RACER_MOSI TP0768


11 6 A 11 10 A
TP-P55 TP-P55
ROOM=TEST ROOM=TEST

IKTARA_COIL2 TP0731
11 6 A
TP-P55
ROOM=TEST

A SYNC_MASTER=test_mlb SYNC_DATE=01/17/2017 A
I2C3_AP_SDA TP0771 PAGE TITLE
11 10
TP-P55
A SYSTEM: Testpoints (Bottom)
ROOM=TEST DRAWING NUMBER SIZE

051-02247 D
I2C3_AP_SCL TP0772 Apple Inc. REVISION
11 10 A 7.0.0
TP-P55
ROOM=TEST NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
7 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 5 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Iktara

D D

PP_IKTARA_VRECT
C3445 1 C3411 1 C3412 1
220PF 2.2UF 2.2UF
5% 20% 20%
25V 25V 25V
COG 2 X5R 2 X5R 2
01005 0402-4 0402-4
ROOM=IKTARA ROOM=IKTARA ROOM=IKTARA

R3401
1
0.020 2 PP_IKTARA_VMID
C3440 1 C3441 1
1%
2.2UF
20%
2.2UF
20%
1/6W
MF
1 C3413 1 C3442 1 C3443
25V
X5R 2
25V
X5R 2 0402 2.2UF 2.2UF 220PF
2 ROOM=IKTARA 2 20% 20% 5%
0402-4 0402-4 2 25V 2 25V 2 25V
ROOM=IKTARA ROOM=IKTARA X5R X5R COG
XW3401 XW3400 0402-4 0402-4 01005
ROOM=IKTARA ROOM=IKTARA ROOM=IKTARA
SHORT-10L-0.05MM-SM
SHORT-10L-0.05MM-SM
1 ROOM=IKTARA
ROOM=IKTARA
1
PP_IKTARA_VMID_SENSE

PP_IKTARA_VRECT_SENSE

D1
D2
D3
D4
D5
D6
D7

H1
E1

E4

K1
F1

L1
J1
VRECT_VDD
VRECT_VDD
VRECT_VDD
VRECT_VDD
VRECT_VDD
VRECT_VDD
VRECT_VDD

VRECT_S

VMID_S

VMID_R_VDD

VMID_VDD
VMID_VDD
VMID_VDD
VMID_VDD
C K OMIT_TABLE K OMIT_TABLE K OMIT_TABLE K OMIT_TABLE
C
D3400
DSN2
D3401
DSN2
D3402
DSN2
D3403
DSN2
NSR20F30NX NSR20F30NX NSR20F30NX NSR20F30NX
ROOM=IKTARA ROOM=IKTARA
A A ROOM=IKTARA A A ROOM=IKTARA
CRITICAL
B5 CLAMP1 HV_GPO1 H4 PP_VBUS2_IKTARA
U3400 HV_GPO2 H5
NC 11

IKTARA_COMM1 C3415 C3444


C5 COMM1 BC59355A2
WLCSP BOOTB_VDD H2
NC 1
1UF
1
220PF
Pull-Ups
1 C3406 ROOM=IKTARA
NC 10%
25V
2 X5R
5%
2 25V
0.033UF SW J2
402
COG 12 11 8 7 6 5
PP_VDD_MAIN
10% 01005
K2
50V
2 X7R C3404 SW OMIT ROOM=IKTARA ROOM=IKTARA

R3406 1
To Coil 0402
ROOM=IKTARA
0.1UF
IKTARA_BOOT1
SW L2 XW3402
SHORT-20L-0.05MM-SM 2M
1 2 C7 BOOT1_VDD 5%
11 5
IKTARA_COIL1 VOUT G1 IKTARA_VOUT_SNS 1 2 1/20W
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE 10% ROOM=IKTARA
MF
201 2
1
R3450 1 C3451 1 C3452 1 C3453 1 C3454 1 C3455 1 C3456 16V
X5R-CERM
B6 AC1 VMID_AUX_SW_VDD E6 ROOM=IKTARA

100K 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0201 B7 AC1 VMID_AUX_VDD E5 PP5V0_VMID_AUX_IKTARA
10% 10% 10% 10% 10% 10% ROOM=IKTARA
1%
2 50V 50V
2 CER-X7R 2 50V 2 50V 2 50V 2 50V
IKTARA_AC1 C6 AC1
1/20W
MF CER-X7R CER-X7R CER-X7R CER-X7R CER-X7R VDD5V E3 PP5V0_VDD_IKTARA
0402 0402 0402 0402 0402 0402
2 201 ROOM=IKTARA ROOM=IKTARA ROOM=IKTARA ROOM=IKTARA ROOM=IKTARA ROOM=IKTARA
VDIG_CORE_VDD F7 PP1V5_VDIG_CORE_IKTARA 6
PP1V8_IKTARA
H7 PP1V8_IKTARA
NOSTUFF VDDO 6 R34071
C3402 1 1 C3403 VAUX_1P8_VDD G7 1 C3419 1 C3418 1 C3417 1 C3416 10K
5%
2200PF 2200PF 1/32W
10% 10% 1UF 1UF 4UF 2.2UF MF
To Coil 50V
X5R 2
50V
2 X5R 20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
20%
2 6.3V
01005 2
ROOM=IKTARA
0201 0201 X5R X5R CERM-X5R X5R-CERM
11 5
IKTARA_COIL2 ROOM=IKTARA ROOM=IKTARA 0201 0201 0201 0201-2
ROOM=IKTARA ROOM=IKTARA ROOM=IKTARA ROOM=IKTARA
OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE OMIT_TABLE
1
R3460 1 C3461 1 C3462 1 C3463 1 C3464 1 C3465 1 C3466 IKTARA_AC2 B1 AC2
0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF L4 I2C0_SMC_SDA
B 1%
100K 10% 10% 10% 10% 10% 10% B2 AC2
SDA
L5 I2C0_SMC_SCL
IN 11
B
1/20W
MF
2 50V
CER-X7R
0402
50V
2 CER-X7R
0402
2 50V
CER-X7R
0402
2 50V
CER-X7R
0402
2 50V
CER-X7R
0402
2 50V
CER-X7R
0402
C3405 C2 AC2
SCL
K4 IKTARA_TO_SMC_INT
BI 11
R3420
2 201 ROOM=IKTARA ROOM=IKTARA ROOM=IKTARA ROOM=IKTARA ROOM=IKTARA ROOM=IKTARA
0.1UF INT OUT 5 11
100
1 2 IKTARA_BOOT2 C1 BOOT2_VDD RESET* J4 PMU_TO_IKTARA_RESET_R_L 1 2 PMU_TO_IKTARA_RESET_L 11
IN
5%
1 C3407 10%
16V GPIO1 H6
1/32W
MF
0.033UF X5R-CERM NC 01005
10% 0201 GPIO2 L6 ROOM=IKTARA
50V
2 X7R NC
0402
ROOM=IKTARA
GPIO3/SWDIO J6 IKTARA_GPIO3 OUT 5
ROOM=IKTARA
IKTARA_COMM2 GPIO4/SWCLK K5 IKTARA_GPIO4 5
C3 COMM2
OUT
GPIO5 J5
NC
B3 CLAMP2 GPIO6 K7
NC
GPIO7 K6 IKTARA_GPIO7
IKTARA_ANA1 E2
R3422
5 OUT
F2
ANA1 R3421
NC ANA2 E7 PMU_TO_IKTARA_EN_EXT_1P8V_R 100 PMU_TO_IKTARA_EN_EXT_1P8V
PP_VDD_MAIN 1
0.00 2 PP_VDD_MAIN_IKTARA G3 EN_EXT_1P8 1 2 IN 5 11
12 11 8 7 6 5 ANA3
5%
0% G2 ANA4 VSYS_ANA_VDD F3 PP_VDD_MAIN 5 6 7 8 11 12 1/32W
1/32W NC MF
MF 01005
01005 VSYS_1P8_VDD F6 PP1V8_S2 4 9 11 12
ROOM=IKTARA
ROOM=IKTARA G6 REFBP
NC
OTP_WREN J7
G5 1
DIGTEST R3408
RGND PGND AVSS 1.00K
5%
1/32W
MF
A1
A2
A3
A4
A5
A6
A7
B4

J3
K3
L3

C4
G4
H3
L7
F5
F4
2 01005ROOM=IKTARA

A SYNC_MASTER=mlb_bot SYNC_DATE=04/04/2017
A
PAGE TITLE

SYSTEM POWER: Iktara


DRAWING NUMBER SIZE

051-02247 D
Apple Inc. REVISION

7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
34 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 6 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

South Speaker Amplifier


APN: 338S00295
I2C ADDRESS: 1000 000x
0x80

12 11 8 6 5
PP_VDD_MAIN PP1V8_AUDIO_VA_S2 8 11

C4907 1 C4905 1 C4909 1 C4914 1 1 C4925 1 C4926


18UF 18UF 18UF 4UF 0.1UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 2 6.3V 6.3V
CER-X5R 2 CER-X5R 2 CER-X5R 2 CERM-X5R 2 X5R-CERM 2 X5R-CERM
0402-0.1MM 0402-0.1MM 0402-0.1MM 0201
ROOM=SPKAMP1
01005
ROOM=SPKAMP1
0201
ROOM=SPKAMP1
ROOM=SPKAMP1 ROOM=SPKAMP1 ROOM=SPKAMP1

A5

F5
CRITICAL
C L4900 VP VA C
1.2UH-20%-3A-0.077OHM
SPKRAMP_BOT_LX A2 A1 PP_SPKRAMP_BOT_VBOOST
1 2
B2
SW U4900 VBST_B
B1
MEHK2016T-SM SW CS35L26B-A1 VBST_B
ROOM=SPKAMP1
D6 WLCSP C1
1 C4927 1 C4928 1 C4903 1 C4904 1 C4931 1 C4932
11 BI
I2C1_AOP_SDA SDA VBST_A 220PF 0.1UF 10UF 10UF 10UF 10UF
ROOM=SPKAMP1 D1 5% 10% 20% 20% 20% 20%
I2C1_AOP_SCL E6 VBST_A 2 10V
C0G-CERM 2 16V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM
11 IN SCL CRITICAL 01005 0201 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM
ROOM=SPKAMP1 ROOM=SPKAMP1 ROOM=SPKAMP1 ROOM=SPKAMP1 ROOM=SPKAMP1 ROOM=SPKAMP1
SPKRAMP_BOT_ARC_TO_AOP_INT_L A7
11 BI INT*
AOP_TO_SPKRAMP_BOT_ARC_RESET_L A6
11 IN RESET*
SPKRAMP_BOT_TO_SPKRAMP_TOP_SYNC F6
ALIVE/SYNC ISNS+
F1 SPKRAMP_BOT_ISENSE_POS
1 C4930
8 BI
E1 0.01UF
E5 ISNS- SPKRAMP_BOT_ISENSE_NEG 10%
AD0/PDM_CLK1 2 6.3V
X5R
B7 01005
11 IN
CODEC_TO_SPKRAMP_BOT_ARC_MCLK MCLK ROOM=SPKAMP1
E2 COIL_TO_SPKRAMP_BOT_VSENSE_POS
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK C7 VSNS+ IN 11
11 8 IN SCLK E3 COIL_TO_SPKRAMP_BOT_VSENSE_NEG
VSNS- IN 11
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK C6
11 8 IN LRCK/FSYNC
D7
SDIN D2 SPKRAMP_BOT_TO_COIL_OUT_POS
OUT+ 11
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN B6 C2 SPKRAMP_BOT_TO_COIL_OUT_NEG
11 8 BI SDOUT OUT- 11

F7
PDM_CLK0
NC
E7 F4
C4922 1 1 C4934
PDM_DATA0 FILT+ SPKRAMP_BOT_FILT 470PF 470PF
NC 10% 10%
D5 F3 10V 2 2 10V
PDM_DATA1 AD1 X5R X5R
GNDP GNDA 1 C4929 01005
ROOM=SPKAMP1
01005
ROOM=SPKAMP1
2.2UF
B 20% B

A3
A4
B3
B4
C3
C4
C5
D3
D4

B5
E4
F2
2 6.3V
X5R-CERM
0201
ROOM=SPKAMP1

A SYNC_MASTER=mlb_bot SYNC_DATE=04/04/2017
A
PAGE TITLE

AUDIO: Speaker Amp Bottom


DRAWING NUMBER SIZE

051-02247 D
Apple Inc. REVISION

7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
49 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 7 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Pull Downs
AP_TO_SPKRAMP_TOP_RESET_L 8 11

1
R5001
100K
5%
1/32W
MF
2 01005
ROOM=SPKAMP2

D North Speaker Amplifier


APN: 338S00295
D

I2C ADDRESS: 1000 000x


0x80

12 11 7 6 5
PP_VDD_MAIN PP1V8_AUDIO_VA_S2 7 11

C5027 1 C5026 1 C5028 1 C5029 1 1 C5015 1 C5016


18UF 18UF 18UF 4UF 0.1UF 2.2UF
20% 20% 20% 20% 20% 20%
6.3V 6.3V 6.3V 6.3V 6.3V 2 6.3V
CER-X5R 2 CER-X5R 2 CER-X5R 2 CERM-X5R 2 2 X5R-CERM X5R-CERM
0402-0.1MM 0402-0.1MM 0402-0.1MM 0201 01005 0201
ROOM=SPKAMP2 ROOM=SPKAMP2 ROOM=SPKAMP2 ROOM=SPKAMP2 ROOM=SPKAMP2 ROOM=SPKAMP2

A5

F5
CRITICAL
L5000 VP VA
C 1.2UH-20%-3A-0.11OHM C
1 2 SPKRAMP_TOP_LX A2 SW U5000 VBST_B A1 PP_SPKRAMP_TOP_VBOOST
MEFE2016T-SM B2 SW CS35L26B-A1 VBST_B B1
ROOM=SPKAMP2
WLCSP
1 C5012 1 C5011 1 C5024 1 C5025 1 C5006 1 C5008
11 BI
I2C2_AP_SDA D6 SDA VBST_A C1 220PF 0.1UF 10UF 10UF 10UF 10UF
ROOM=SPKAMP2 5% 10% 20% 20% 20% 20%
I2C2_AP_SCL VBST_A D1 2 10V
C0G-CERM 2 16V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM 2 10V
X5R-CERM
11 IN E6 SCL CRITICAL 01005 0201 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM
SPKRAMP_TOP_TO_AP_INT_L ROOM=SPKAMP2 ROOM=SPKAMP2 ROOM=SPKAMP2 ROOM=SPKAMP2 ROOM=SPKAMP2 ROOM=SPKAMP2
11 BI A7 INT*

11 8 IN
AP_TO_SPKRAMP_TOP_RESET_L A6 RESET*
SPKRAMP_BOT_TO_SPKRAMP_TOP_SYNC F6 ALIVE/SYNC ISNS+ F1 SPKRAMP_TOP_ISENSE_POS
1 C5019
7 BI 0.01UF
ISNS- E1 SPKRAMP_TOP_ISENSE_NEG 10%
E5 AD0/PDM_CLK1 2 6.3V
X5R
01005
11 IN
I2S_AP_TO_SPKRAMP_TOP_MCLK B7 MCLK ROOM=SPKAMP2
VSNS+ E2 COIL_TO_SPKRAMP_TOP_VSENSE_POS
I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK C7 SCLK
IN 11
11 7 IN
VSNS- E3 COIL_TO_SPKRAMP_TOP_VSENSE_NEG IN 11

11 7 IN
I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK C6 LRCK/FSYNC

D7 SDIN SPKRAMP_TOP_TO_COIL_OUT_POS
OUT+ D2 11

11 7 BI
I2S_CODEC_ASP1_TO_AOP_AMPS_DIN B6 SDOUT OUT- C2 SPKRAMP_TOP_TO_COIL_OUT_NEG 11

11 IN
PDM_CODEC_TO_SPKRAMP_TOP_CLK F7 PDM_CLK0 C5000 1 1 C5001
470PF 470PF
11 IN
PDM_CODEC_TO_SPKRAMP_TOP_DATA E7 PDM_DATA0 FILT+ F4 SPKRAMP_TOP_FILT 10%
10V
10%
10V
X5R 2 2 X5R
D5 PDM_DATA1 AD1 F3 01005
ROOM=SPKAMP2
01005
ROOM=SPKAMP2
GNDP GNDA
1 C5018
2.2UF

A3
A4
B3
B4
C3
C4
C5
D3
D4

B5
E4
F2
B 20%
2 6.3V
X5R-CERM B
0201
ROOM=SPKAMP2

A SYNC_MASTER=mlb_bot SYNC_DATE=04/04/2017
A
PAGE TITLE

AUDIO: Speaker Amp Top


DRAWING NUMBER SIZE

051-02247 D
Apple Inc. REVISION

7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
50 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 8 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

D D

C Hall Effect C
APN:353S3697

12 11 6 4
PP1V8_S2
1 C5530

1
0.1UF
20%
2 6.3V VDD
X5R-CERM
01005
ROOM=HALL
U5530
AK8789
DFN HALL3_TO_AOP_IRQ_L
ROOM=HALL OUT1 4 OUT 11
CRITICAL
OUT2 3 NC

THRM
VSS PAD

5
B B

A SYNC_MASTER=mlb_bot SYNC_DATE=04/04/2017
A
PAGE TITLE

HALL EFFECT
DRAWING NUMBER SIZE

051-02247 D
Apple Inc. REVISION

7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
55 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 9 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

Racer I/O Luna + Touch Connector


Rcpt: 516S00325 <-- This one on MLB
FL5800 Plug: 516S00326
150OHM-25%-200MA-0.7DCR J5800
11 5 IN
AP_TO_RACER_RESET_L 2 1 AP_TO_RACER_RESET_CONN_L 10 AA26DK-S028VA1
01005 F-ST-SM
ROOM=B2B_TOUCH_ORB
1 C5800 33
220PF 29 30
5%
2 10V
C0G-CERM
01005 10
SPI_AP_TO_RACER_SCLK_CONN 1 2 SPI_AP_TO_RACER_MOSI_CONN 10
ROOM=B2B_TOUCH_ORB
10
SPI_AP_TO_RACER_CS_CONN_L 3 4 SPI_RACER_TO_AP_MISO_CONN 10

D C5860 10
AP_TO_RACER_RESET_CONN_L 5 6 RACER_TO_AOP_INT_CONN_L 10 D
R5801 27PF 10
RACER_TO_ACORN_ORB_SCAN_CONN 7 8 PP10V0_RACER_CONN 10
AP_TO_RACER_REF_CLK 1
0.00 2 AP_TO_RACER_REF_CLK_C 1 2 AP_TO_RACER_REF_CLK_CONN SWD_AOP_TO_RACER_CONN 9 10 UART_RACER_TO_AOP_RXD_CONN
11 IN 10 10 10

0% 10
SWD_AOP_BI_RACER_SWDIO_CONN 11 12 UART_AOP_TO_RACER_TXD_CONN 10
1/32W 5%
MF 25V 10
HALL2_TO_AOP_IRQ_CONN_L 13 14 PP1V8_TOUCH_RACER_CONN 10
01005 C0G
ROOM=B2B_TOUCH_ORB
0201 15 16
ROOM=B2B_TOUCH_ORB
10
AP_TO_RACER_REF_CLK_CONN 17 18 PP1V1_RACER_CONN 10
19 20 PN6V7_RACER_CONN 10
PMU_TO_TOUCH_CLK32K_RESET_CONN_L 21 22 PP3V5_RACER_CONN
FL5802 10
I2C3_AP_BI_TOUCH_EEPROM_SDA_CONN 23 24 AP_TO_TOUCH_BSYNC_CONN
10

150OHM-25%-200MA-0.7DCR 10 10
I2C3_AP_TO_TOUCH_EEPROM_SCL_CONN 25 26 TOUCH_TO_ACORN_PP5V25_EN_CONN
RACER_TO_AOP_INT_L 2 1 RACER_TO_AOP_INT_CONN_L 10 10
11 5 OUT 10
10
TOUCH_TO_AMUX_PP1V8_CONN 27 28 PP5V25_TOUCH_VDDH_CONN 10
01005
ROOM=B2B_TOUCH_ORB
1 C5802
220PF 31 32
5%
2 10V 34
C0G-CERM
01005
ROOM=B2B_TOUCH_ORB
Touch and Misc I/O ROOM=B2B_TOUCH_ORB

FL5803 FL5840
150OHM-25%-200MA-0.7DCR 150OHM-25%-200MA-0.7DCR
UART_AOP_TO_RACER_TXD 2 1 UART_AOP_TO_RACER_TXD_CONN TOUCH_TO_ACORN_PP5V25_EN 2 1 TOUCH_TO_ACORN_PP5V25_EN_CONN 10
11 5 IN
01005
10 11 5 OUT
01005 1 C5840
Touch And Racer Power
ROOM=B2B_TOUCH_ORB
1 C5803 ROOM=B2B_TOUCH_ORB
220PF
56PF 5%
5%
2 25V 2 10V
C0G-CERM
NP0-C0G-CERM 01005
01005 ROOM=B2B_TOUCH_ORB
ROOM=B2B_TOUCH_ORB FL5890
33-OHM-25%-1500MA
FL5804 FL5841 PP1V8_TOUCH_RACER_S2 1 2 PP1V8_TOUCH_RACER_CONN
C 150OHM-25%-200MA-0.7DCR 150OHM-25%-200MA-0.7DCR 11 5
OMIT_TABLE 0201
10
C
11 5 OUT
UART_RACER_TO_AOP_RXD 2 1 UART_RACER_TO_AOP_RXD_CONN 10 11 5 OUT
TOUCH_TO_AMUX_PP1V8 2 1 TOUCH_TO_AMUX_PP1V8_CONN 10 C5890 1 ROOM=B2B_TOUCH_ORB
1 C5891
01005 01005 2.2UF 220PF
ROOM=B2B_TOUCH_ORB
1 C5804 ROOM=B2B_TOUCH_ORB
1 C5841 20%
6.3V
5%
56PF 220PF X5R-CERM 2 2 10V
C0G-CERM
5% 5% 0201 01005
2 25V 2 10V
C0G-CERM ROOM=B2B_TOUCH_ORB
ROOM=B2B_TOUCH_ORB
NP0-C0G-CERM 01005
01005 ROOM=B2B_TOUCH_ORB FL5891
ROOM=B2B_TOUCH_ORB 150OHM-25%-0.28A-0.69OHM
FL5805 11 5
PP5V25_TOUCH_VDDH 2 1 PP5V25_TOUCH_VDDH_CONN 10
150OHM-25%-200MA-0.7DCR R5842 01005
RACER_TO_ACORN_ORB_SCAN 2 1 RACER_TO_ACORN_ORB_SCAN_CONN PMU_TO_TOUCH_CLK32K_RESET_L 2
33.2 1 PMU_TO_TOUCH_CLK32K_RESET_CONN_L 10 ROOM=B2B_TOUCH_ORB
1 C5892
11 5 OUT 10 11 5 IN 220PF
01005 1% 5%
ROOM=B2B_TOUCH_ORB
1 C5805 1/32W
MF
1 C5842 2 10V
C0G-CERM
56PF 01005 100PF 01005
5% 5% ROOM=B2B_TOUCH_ORB
2 25V
NP0-C0G-CERM
ROOM=B2B_TOUCH_ORB
2 16V
NP0-C0G FL5893
01005 01005 33-OHM-25%-1500MA
ROOM=B2B_TOUCH_ORB ROOM=B2B_TOUCH_ORB
11 5
PP3V5_RACER 2 1 PP3V5_RACER_CONN 10

FL5806 0201
1 C5893
150OHM-25%-200MA-0.7DCR ROOM=B2B_TOUCH_ORB
220PF
11 5
SPI_AP_TO_RACER_CS_L 2 1 SPI_AP_TO_RACER_CS_CONN_L 10
5%
2 10V
IN
01005 C0G-CERM
ROOM=B2B_TOUCH_ORB
1 C5806 01005
ROOM=B2B_TOUCH_ORB

5%
56PF FL5894
2 25V
33-OHM-25%-1500MA
NP0-C0G-CERM
01005 11 5
PN6V7_RACER 2 1 PN6V7_RACER_CONN 10
ROOM=B2B_TOUCH_ORB
0201
ROOM=B2B_TOUCH_ORB
1 C5894
220PF
R5807 R5844 5%
2 10V
B 11 IN
SPI_AP_TO_RACER_SCLK 1
0.00 2
NOSTUFF
SPI_AP_TO_RACER_SCLK_CONN 10 12 11 IN
SWD_AOP_TO_MANY_SWCLK 2
49.9 1 SWD_AOP_TO_RACER_CONN 10 C0G-CERM
01005 B
0% 1% ROOM=B2B_TOUCH_ORB
1/32W
MF
1 C5807 1/32W
MF
1 C5844 FL5895
01005 56PF 01005 100PF 150OHM-25%-200MA-0.7DCR
5% 5%
ROOM=B2B_TOUCH_ORB
2 25V
NP0-C0G-CERM
ROOM=B2B_TOUCH_ORB
2 16V
NP0-C0G 11 5
PP10V0_RACER 2 1 PP10V0_RACER_CONN 10
01005 01005 01005
ROOM=B2B_TOUCH_ORB
ROOM=B2B_TOUCH_ORB
ROOM=B2B_TOUCH_ORB
1 C5895
220PF
FL5845 5%
2 10V
FL5809 150OHM-25%-200MA-0.7DCR C0G-CERM
01005
SPI_AP_TO_RACER_MOSI 1
0.00 2 SPI_AP_TO_RACER_MOSI_CONN SWD_AOP_BI_RACER_SWDIO 2 1 SWD_AOP_BI_RACER_SWDIO_CONN 10 ROOM=B2B_TOUCH_ORB
11 5 IN
0%
NOSTUFF
10 11 BI
NOSTUFF 01005
FL5896
1 C5809 C5845 33-OHM-25%-1500MA
1/32W
MF
56PF
R5845 1 ROOM=B2B_TOUCH_ORB
1
56PF PP1V1_RACER 2 1 PP1V1_RACER_CONN
01005
5% 10K 5% 11 5 10
ROOM=B2B_TOUCH_ORB 1%
2 25V 1/32W 2 25V 0201
NP0-C0G-CERM
01005 MF
01005 2
NP0-C0G-CERM
01005 ROOM=B2B_TOUCH_ORB
1 C5896
ROOM=B2B_TOUCH_ORB
ROOM=B2B_TOUCH_ORB
ROOM=B2B_TOUCH_ORB
220PF
5%
2 10V
FL5810 FL5847
C0G-CERM
01005
150OHM-25%-200MA-0.7DCR ROOM=B2B_TOUCH_ORB
150OHM-25%-200MA-0.7DCR
SPI_RACER_TO_AP_MISO 2 1 SPI_RACER_TO_AP_MISO_CONN
11 OUT 10
12 11 5 IN
AP_TO_MANY_BSYNC 2 1 AP_TO_TOUCH_BSYNC_CONN 10
01005
ROOM=B2B_TOUCH_ORB
1 C5810 01005
1 C5847
56PF ROOM=B2B_TOUCH_ORB
5% 100PF
2 25V
NP0-C0G-CERM
5%
01005 2 16V
NP0-C0G
AP I2C Filters ROOM=B2B_TOUCH_ORB
01005
ROOM=B2B_TOUCH_ORB

R5820
0.00
A 11 5 OUT
I2C3_AP_SDA 2 1 I2C3_AP_BI_TOUCH_EEPROM_SDA_CONN 10
SYNC_MASTER=mlb_bot SYNC_DATE=04/04/2017
A
0%
1/32W
1 C5820 PAGE TITLE
MF 56PF
01005 5%
2 25V
Hall Effect CG: B2B Luna & Touch
ROOM=B2B_TOUCH_ORB
NP0-C0G-CERM FL5850 DRAWING NUMBER SIZE
01005 150OHM-25%-200MA-0.7DCR 051-02247 D
ROOM=B2B_TOUCH_ORB
11 5 IN
HALL2_TO_AOP_IRQ_L 2 1 HALL2_TO_AOP_IRQ_CONN_L 10
Apple Inc. REVISION
01005
1 C5850 7.0.0
R5821 ROOM=B2B_TOUCH_ORB
220PF NOTICE OF PROPRIETARY PROPERTY: BRANCH
I2C3_AP_SCL 0.00 I2C3_AP_TO_TOUCH_EEPROM_SCL_CONN
11 5 IN
2 1 10
5%
2 10V
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
evt-1
0% C0G-CERM
1/32W
MF
1 C5821 01005
ROOM=B2B_TOUCH_ORB
THE POSESSOR AGREES TO THE FOLLOWING:
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
PAGE

58 OF 80
01005 56PF II NOT TO REPRODUCE OR COPY IT
ROOM=B2B_TOUCH_ORB
5% SHEET
2 25V III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
NP0-C0G-CERM
01005 IV ALL RIGHTS RESERVED 10 OF 34
ROOM=B2B_TOUCH_ORB

8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

12 UART_AP_TO_GNSS_TXD S1 IOS1 J_INT_TOP IOS87 S87 PP1V8_S2 4 6 9 11 12

12 UART_AP_TO_GNSS_RTS_L
S2 IOS2 INTERPOSER-TOP-D22 IOS88 S88
12 UART_GNSS_TO_AP_CTS_L
S3 IOS3 SMT-PAD IOS89 S89 PP_VDD_MAIN 5 6 7 8 11 12
S4 SYM 3 OF 3 S90
12 UART_GNSS_TO_AP_RXD IOS4 IOS90 BB_TO_PMU_PCIE_HOST_WAKE_L 12

D 12 AP_TO_GNSS_WAKE
S5
S6
IOS5 IOS91 S91
S92
PMU_TO_BBPMU_RESET_L
PMU_AMUX_AY
12 D
12 PMU_TO_GNSS_EN IOS6 IOS92 5

12 AP_TO_BB_TIME_MARK
S7 IOS7 SIGNAL IOS93 S93 AOP_TO_WLAN_CONTEXT_B 12

12 90_PCIE_AP_TO_BB_REFCLK_N
S8 IOS8 IOS94 S94 UART_BB_TO_AOP_RXD 12
S9 IOS9 IOS95 S95 UART_AOP_TO_BB_TXD
90_PCIE_AP_TO_BB_REFCLK_P S10 IOS10 IOS96 S96 AOP_TO_WLAN_CONTEXT_A
12 G1 IOG1 J_INT_TOP IOG63 G63 G125 IOG125
J_INT_TOP IOG187 G187
12 12 G2 IOG2 INTERPOSER-TOP-D22 IOG64 G64 G126 IOG126 IOG188 G188
12 90_PCIE_BB_TO_AP_RXD_P
S11 IOS11 IOS97 S97 BT_TO_PMU_HOST_WAKE INTERPOSER-TOP-D22
12 G3 IOG3 SMT-PAD IOG65 G65 G127 IOG127 IOG189 G189
12 90_PCIE_BB_TO_AP_RXD_N
S12 IOS12 IOS98 S98 PMU_TO_BT_REG_ON SYM 1 OF 3 SMT-PAD
12 G4 IOG4 IOG66 G66 G128 IOG128 IOG190 G190
12 90_PCIE_AP_TO_BB_TXD_P
S13 IOS13 IOS99 S99 PMU_TO_WLAN_CLK32K SYM 2 OF 3
12 G5 IOG5 IOG67 G67 G129 IOG129 IOG191 G191
S14 IOS14 IOS100 S100 WLAN_TO_PMU_HOST_WAKE 12 G6 IOG6 GND IOG68 G68 G130 IOG130 IOG192 G192
90_PCIE_AP_TO_BB_TXD_N S15 IOS15 IOS101 S101 PMU_TO_WLAN_REG_ON
12 12 G7 IOG7 IOG69 G69 G131 IOG131 GND IOG193 G193
12 90_PCIE_WLAN_TO_AP_RXD_P
S16 IOS16 IOS102 S102 PMU_AMUX_BY 5 G8 IOG8 IOG70 G70 G132 IOG132 IOG194 G194
S17 IOS17 IOS103 S103 CODEC_TO_SPKRAMP_BOT_ARC_MCLK 7 G9 IOG9 IOG71 G71 G133 IOG133 IOG195 G195
90_PCIE_WLAN_TO_AP_RXD_N S18 IOS18 IOS104 S104 PMU_TO_BB_USB_VBUS_DETECT
12 12 G10 IOG10 IOG72 G72 G134 IOG134 IOG196 G196
12 90_PCIE_AP_TO_WLAN_REFCLK_N
S19 IOS19 IOS105 S105 PMU_HYDRA_TO_AP_FORCE_DFU 5 G11 IOG11 IOG73 G73 G135 IOG135 IOG197 G197
S20 IOS20 IOS106 S106 AP_TO_BT_WAKE 12 G12 IOG12 IOG74 G74 G136 IOG136 IOG198 G198
90_PCIE_AP_TO_WLAN_REFCLK_P S21 IOS21 IOS107 S107 WLAN_TO_AP_TIME_SYNC 12
12 G13 IOG13 IOG75 G75 G137 IOG137 IOG199 G199
12 90_PCIE_AP_TO_WLAN_TXD_N
S22 IOS22 IOS108 S108 RADIO_PA_NTC 12 G14 IOG14 IOG76 G76 G138 IOG138 IOG200 G200
S23 IOS23 IOS109 S109 AP_TO_MANY_BSYNC 5 10 12 G15 IOG15 IOG77 G77 G139 IOG139 IOG201 G201
12 90_PCIE_AP_TO_WLAN_TXD_P
S24 IOS24 IOS110 S110 TOUCH_TO_AMUX_PP1V8 5 10 G16 IOG16 IOG78 G78 G140 IOG140 IOG202 G202
S25 IOS25 IOS111 S111 PP3V5_RACER 5 10
G17 IOG17 IOG79 G79 G141 IOG141 IOG203 G203
S26 IOS26 IOS112 S112 PP1V1_RACER 5 10
G18 IOG18 IOG80 G80 G142 IOG142 IOG204 G204
6 5 PMU_TO_IKTARA_EN_EXT_1P8V
S27 IOS27 IOS113 S113
G19 IOG19 IOG81 G81 G143 IOG143 IOG205 G205
6 5 IKTARA_TO_SMC_INT
S28 IOS28 IOS114 S114 PP5V25_TOUCH_VDDH 5 10
G20 IOG20 IOG82 G82 G144 IOG144 IOG206 G206
6 I2C0_SMC_SCL
S29 IOS29 IOS115 S115 RACER_TO_ACORN_ORB_SCAN 5 10
G21 IOG21 IOG83 G83 G145 IOG145 IOG207 G207
6 I2C0_SMC_SDA
S30 IOS30 IOS116 S116 PP1V8_TOUCH_RACER_S2 5 10
G22 IOG22 IOG84 G84 G146 IOG146 IOG208 G208
12 BB_TO_STROBE_DRIVER_GSM_BURST_IND
S31 IOS31 IOS117 S117 I2C3_AP_SCL 5 10
G23 G85 G147 G209
C NC
S32 IOS32 IOS118 S118 I2C3_AP_SDA 5 10
G24
IOG23
IOG24
IOG85
IOG86 G86 G148
IOG147
IOG148
IOG209
IOG210 G210
C
8PDM_CODEC_TO_SPKRAMP_TOP_CLK S33 IOS33 IOS119 S119 TOUCH_TO_ACORN_PP5V25_EN 5 10
G25 IOG25 IOG87 G87 G149 IOG149 IOG211 G211
8 PDM_CODEC_TO_SPKRAMP_TOP_DATA
S34 IOS34 IOS120 S120 PN6V7_RACER 5 10
G26 IOG26 IOG88 G88 G150 IOG150 IOG212 G212
12 PCIE_AP_TO_BB_RESET_L
S35 IOS35 IOS121 S121 PMU_TO_TOUCH_CLK32K_RESET_L 5 10
G27 IOG27 IOG89 G89 G151 IOG151 IOG213 G213
8 I2S_AP_TO_SPKRAMP_TOP_MCLK
S36 IOS36 IOS122 S122 PP10V0_RACER 5 10
G28 IOG28 IOG90 G90 G152 IOG152 IOG214 G214
8 AP_TO_SPKRAMP_TOP_RESET_L
S37 IOS37 IOS123 S123 AP_TO_RACER_RESET_L 5 10
G29 IOG29 IOG91 G91 G153 IOG153 IOG215 G215
8 SPKRAMP_TOP_TO_AP_INT_L
S38 IOS38 IOS124 S124 RACER_TO_AOP_INT_L 5 10
G30 IOG30 IOG92 G92 G154 IOG154 IOG216 G216
8 I2C2_AP_SDA
S39 IOS39 IOS125 S125 SWD_AOP_TO_MANY_SWCLK 10 12
G31 IOG31 IOG93 G93 G155 IOG155 IOG217 G217
8 I2C2_AP_SCL
S40 IOS40 IOS126 S126 SWD_AOP_BI_RACER_SWDIO 10
G32 IOG32 IOG94 G94 G156 IOG156 IOG218 G218
8 7 PP1V8_AUDIO_VA_S2
S41 IOS41 IOS127 S127 UART_AOP_TO_RACER_TXD 5 10
G33 IOG33 IOG95 G95 G157 IOG157 IOG219 G219
5
PP_GPU_LVCC S42 IOS42 IOS128 S128 UART_RACER_TO_AOP_RXD 5 10
G34 IOG34 IOG96 G96 G158 IOG158 IOG220 G220
5
PP_CPU_PCORE_LVCC S43 IOS43 IOS129 S129 HALL2_TO_AOP_IRQ_L 5 10
G35 IOG35 IOG97 G97 G159 IOG159 IOG221 G221
12 AP_TO_BB_IPC_GPIO1
S44 IOS44 IOS130 S130 AP_TO_RACER_REF_CLK 10
G36 IOG36 IOG98 G98 G160 IOG160 IOG222 G222
12 AP_TO_BB_RESET_L
S45 IOS45 IOS131 S131 SPI_AP_TO_RACER_CS_L 5 10
G37 IOG37 IOG99 G99 G161 IOG161 IOG223 G223
9 HALL3_TO_AOP_IRQ_L S46 IOS46 IOS132 S132 SPI_RACER_TO_AP_MISO 10
G38 IOG38 IOG100 G100 G162 IOG162 IOG224 G224
S47 IOS47 IOS133 S133 SPI_AP_TO_RACER_MOSI 5 10
NC G39 IOG39 IOG101 G101 G163 IOG163 IOG225 G225
4BOARD_ID3 S48 IOS48 IOS134 S134 SPI_AP_TO_RACER_SCLK 10
G40 IOG40 IOG102 G102 G164 IOG164 IOG226 G226
12 PCIE_WLAN_BI_AP_CLKREQ_L
S49 IOS49 IOS135 S135 PP_BATT_VCC 5
G41 IOG41 IOG103 G103 G165 IOG165 IOG227 G227
12 PCIE_AP_TO_WLAN_RESET_L
S50 IOS50 IOS136 S136
G42 IOG42 IOG104 G104 G166 IOG166 IOG228 G228
8 7 I2S_CODEC_ASP1_TO_AOP_AMPS_BCLK
S51 IOS51 IOS137 S137 PP3V0_S2 12
G43 IOG43 IOG105 G105 G167 IOG167 IOG229 G229
8 7 I2S_CODEC_ASP1_TO_AOP_AMPS_DIN
S52 IOS52 IOS138 S138
G44 IOG44 IOG106 G106 G168 IOG168 IOG230 G230
8 7 I2S_CODEC_ASP1_TO_AOP_AMPS_LRCLK
S53 IOS53 IOS139 S139 90_USB_BB_DATA_P 12
G45 IOG45 IOG107 G107 G169 IOG169 IOG231 G231
6 PMU_TO_IKTARA_RESET_L
S54 IOS54 IOS140 S140 90_USB_BB_DATA_N 12
G46 IOG46 IOG108 G108 G170 IOG170 IOG232 G232
12 I2S_BB_TO_AP_DIN
S55 IOS55 IOS141 S141
G47 IOG47 IOG109 G109 G171 IOG171 IOG233 G233
12 I2S_BB_TO_AP_LRCLK
S56 IOS56 IOS142 S142 PP_VBUS2_IKTARA 6
G48 IOG48 IOG110 G110 G172 IOG172 IOG234 G234
12 I2S_BB_TO_AP_BCLK
S57 IOS57 IOS143 S143
G49 IOG49 IOG111 G111 G173 IOG173 IOG235 G235
B 12 I2S_AP_TO_BB_DOUT
S58
S59
IOS58 IOS144 S144
S145
G50 IOG50 IOG112 G112 G174 IOG174 IOG236 G236 B
12 BB_TO_AP_RESET_DETECT_L IOS59 IOS145 G51 IOG51 IOG113 G113 G175 IOG175 IOG237 G237
12 AP_TO_BBPMU_RADIO_ON_L
S60 IOS60 IOS146 S146 IKTARA_COIL2 5 6
G52 IOG52 IOG114 G114 G176 IOG176 IOG238 G238
12 AP_TO_WLAN_DEVICE_WAKE
S61 IOS61 IOS147 S147
G53 IOG53 IOG115 G115 G177 IOG177 IOG239 G239
7 SPKRAMP_BOT_ARC_TO_AOP_INT_L
S62 IOS62 IOS148 S148
G54 IOG54 IOG116 G116 G178 IOG178 IOG240 G240
7 AOP_TO_SPKRAMP_BOT_ARC_RESET_L
S63 IOS63 IOS149 S149
G55 IOG55 IOG117 G117 G179 IOG179 IOG241 G241
S64 IOS64 IOS150 S150 IKTARA_COIL1 5 6
NC G56 IOG56 IOG118 G118 G180 IOG180 IOG242 G242
12 SWD_AOP_BI_BB_SWDIO S65 IOS65 IOS151 S151
G57 IOG57 IOG119 G119 G181 IOG181 IOG243 G243
7 I2C1_AOP_SDA
S66 IOS66 IOS152 S152
G58 IOG58 IOG120 G120 G182 IOG182 IOG244 G244
7 I2C1_AOP_SCL
S67 IOS67 IOS153 S153
G59 IOG59 IOG121 G121 G183 IOG183 IOG245 G245
12 11 8 7 6 5 PP_VDD_MAIN
S68 IOS68 IOS154 S154 AP_TO_BB_COREDUMP 12
G60 IOG60 IOG122 G122 G184 IOG184 IOG246 G246
S69 IOS69 IOS155 S155 PCIE_BB_BI_AP_CLKREQ_L 12
G61 IOG61 IOG123 G123 G185 IOG185 IOG247 G247
S70 IOS70 IOS156 S156 SPKRAMP_TOP_TO_COIL_OUT_POS 8
G62 IOG62 IOG124 G124 G186 IOG186 IOG248 G248
S71 IOS71 IOS157 S157 SPKRAMP_TOP_TO_COIL_OUT_NEG 8
S72 IOS72 IOS158 S158 COIL_TO_SPKRAMP_TOP_VSENSE_POS 8
S73 IOS73 IOS159 S159 COIL_TO_SPKRAMP_TOP_VSENSE_NEG 8
S74 IOS74 IOS160 S160 COIL_TO_SPKRAMP_BOT_VSENSE_POS 7
S75 IOS75 IOS161 S161 COIL_TO_SPKRAMP_BOT_VSENSE_NEG 7
S76 IOS76 IOS162 S162 SPKRAMP_BOT_TO_COIL_OUT_POS 7

12 UART_AP_TO_BT_RTS_L
S77 IOS77 IOS163 S163 SPKRAMP_BOT_TO_COIL_OUT_NEG 7

12 UART_BT_TO_AP_CTS_L
S78 IOS78 IOS164 S164 AP_TO_NFC_DEV_WAKE 12

12 UART_AP_TO_BT_TXD
S79 IOS79 IOS165 S165 UART_NFC_TO_AP_CTS_L 12

12 UART_BT_TO_AP_RXD
S80 IOS80 IOS166 S166 UART_AP_TO_NFC_TXD 12

12 NC_PP_VDD_BOOST
S81 IOS81 IOS167 S167 UART_NFC_TO_AP_RXD 12

12 UART_AP_TO_WLAN_TXD
S82 IOS82 IOS168 S168 UART_AP_TO_NFC_RTS_L 12

12 UART_AP_TO_WLAN_RTS_L
S83 IOS83 IOS169 S169 AP_TO_NFC_FW_DWLD_REQ 12

A 12 UART_WLAN_TO_AP_RXD
S84 IOS84 IOS170 S170 NFC_TO_PMU_HOST_WAKE 12
SYNC_MASTER=mlb_bot SYNC_DATE=04/04/2017 A
12 UART_WLAN_TO_AP_CTS_L
S85 IOS85 IOS171 S171 PMU_TO_NFC_EN 12 PAGE TITLE

12 11 9 6 4 PP1V8_S2
S86 IOS86 IOS172 S172
NC I/O: Interposer (Top)
DRAWING NUMBER SIZE

051-02247 D
Apple Inc. REVISION

7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
66 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 11 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
SUBDESIGN_SUFFIX=W

SUBDESIGN_SUFFIX=S
31 11 90_PCIE_AP_TO_WLAN_REFCLK_P 90_PCIE_AP_TO_WLAN_REFCLK_P PP_VDD_MAIN PP_VDD_MAIN 5 6 7 8 11 12 17 31 34

31 11 90_PCIE_AP_TO_WLAN_REFCLK_N 90_PCIE_AP_TO_WLAN_REFCLK_N PP1V8_SDRAM PP1V8_S2 4 6 9 11 12 14 31 34


PP_VDD_MAIN
34 31 17 12 11 8 7 6 5 PP_VDD_MAIN
31 11 90_PCIE_AP_TO_WLAN_TXD_P 90_PCIE_AP_TO_WLAN_TX_P PP1V8_S2
34 31 14 12 11 9 6 4 PP1V8_SDRAM
31 11 90_PCIE_AP_TO_WLAN_TXD_N 90_PCIE_AP_TO_WLAN_TX_N
31 11 90_PCIE_WLAN_TO_AP_RXD_P 90_PCIE_WLAN_TO_AP_RX_P
31 11 90_PCIE_WLAN_TO_AP_RXD_N 90_PCIE_WLAN_TO_AP_RX_N PMU_TO_NFC_EN
34 11 PMU_TO_NFC_EN
31 11 PCIE_WLAN_BI_AP_CLKREQ_L PCIE_AP_BI_WLAN_CLKREQ_L BB_TO_NFC_CLK
34 18 12 BB_TO_NFC_CLK
31 11 PCIE_AP_TO_WLAN_RESET_L PCIE_AP_TO_WLAN_PERST_L UART_BB_TO_WLAN_COEX 12 14 31 NFC_TO_BB_CLK_REQ
UART_BB_TO_WLAN_COEX 34 18 12 NFC_TO_BB_CLK_REQ
31 11 WLAN_TO_PMU_HOST_WAKE PCIE_WLAN_TO_PMU_WAKE UART_WLAN_TO_BB_COEX 12 14 31 AP_TO_NFC_FW_DWLD_REQ
UART_WLAN_TO_BB_COEX 34 11 AP_TO_NFC_FW_DWLD

D AOP_TO_WLAN_CONTEXT_A AOP_TO_WLAN_CONTEXT_A
34 11
AP_TO_NFC_DEV_WAKE AP_TO_NFC_DEV_WAKE
nfc_mlb
D
31 11
34 11
NFC_TO_PMU_HOST_WAKE NFC_TO_PMU_HOST_WAKE
31 11 AOP_TO_WLAN_CONTEXT_B AOP_TO_WLAN_CONTEXT_B
NC NFC_DWP_TX_TP
31 11 AP_TO_BT_WAKE AP_TO_BT_WAKE WIFI_MLB
UART_AP_TO_NFC_TXD
34 11 UART_AP_TO_NFC_TXD
31 11 AP_TO_WLAN_DEVICE_WAKE AP_TO_WLAN_DEV_WAKE UART_NFC_TO_AP_RXD
BT_TO_PMU_HOST_WAKE BT_TO_PMU_HOST_WAKE 11 31 34 11 UART_NFC_TO_AP_RXD
UART_BT_TO_AP_CTS_L UART_BT_TO_AP_CTS_L 11 31 34 11
UART_AP_TO_NFC_RTS_L UART_AP_TO_NFC_RTS_L
31 11 PMU_TO_BT_REG_ON PMU_TO_BT_REG_ON UART_NFC_TO_AP_CTS_L
UART_BT_TO_AP_RXD UART_BT_TO_AP_RXD 11 31 34 11 UART_NFC_TO_AP_CTS_L
31 11 PMU_TO_WLAN_CLK32K PMU_TO_WLAN_32K
UART_AP_TO_BT_RTS_L UART_AP_TO_BT_RTS_L 11 31
31 11 PMU_TO_WLAN_REG_ON PMU_TO_WLAN_REG_ON NFC_SWP1
UART_AP_TO_BT_TXD UART_AP_TO_BT_TXD 11 31 34 28 12 NFC_SWP1

50_UAT_WLAN_5G_SOUTH
50_UAT_WLAN_2G_SOUTH
31 11 UART_WLAN_TO_AP_CTS_L UART_WLAN_TO_AP_CTS_L
UART_WLAN_TO_AP_RXD UART_WLAN_TO_AP_RXD

50_LAT_WLAN_MLC
31 11

31 11 UART_AP_TO_WLAN_RTS_L UART_AP_TO_WLAN_RTS_L
31 11 UART_AP_TO_WLAN_TXD UART_AP_TO_WLAN_TXD

31 11 WLAN_TO_AP_TIME_SYNC WLAN_TIME_SYNC

MAKE_BASE=TRUE
50_UAT_WLAN_2G_SOUTH 12 29 32 11 NC_PP_VDD_BOOST NC_PP_VDD_BOOST
50_UAT_WLAN_5G_SOUTH 12 29 32

50_LAT_WLAN 12 29 32 SUBDESIGN_SUFFIX=K I63


34 31 17 12 11 8 7 6 5
PP_VDD_MAIN PP_VDD_MAIN AP_TO_BBPMU_SDWN_L AP_TO_BBPMU_RADIO_ON_L 11 14

34 31 14 12 11 9 6 4
PP1V8_S2 PP1V8_SDRAM PMU_TO_BBPMU_ON PMU_TO_BBPMU_RESET_L 11 17

29 11
PP3V0_S2 PP3V0_TRISTAR AP_TO_BB_RESET_L AP_TO_BB_RESET_L 11 15

AP_TO_BB_MESA_ON NC

AP_TO_BB_COREDUMP_TRIG AP_TO_BB_COREDUMP 11 14

C AP_TO_BB_IPC_GPIO AP_TO_BB_IPC_GPIO1
AP_TO_MANY_BSYNC
11 14 C
UART_BB_TO_WLAN_COEX TOUCH_TO_BBPMU_FORCE_PWM 5 10 11 17
31 14 12 UART_BB_TO_WLAN_COEX
31 14 12 UART_WLAN_TO_BB_COEX
UART_WLAN_TO_BB_COEX

BB_TO_AP_RESET_DETECT_L BB_TO_AP_RESET_DETECT_L 11 14

RADIO PA NTC BB_TO_AP_GSM_TXBURST BB_TO_STROBE_DRIVER_GSM_BURST_IND 11 14

1
90_PCIE_AP_TO_BB_REFCLK_P 90_PCIE_AP_TO_BB_REFCLK_P 11 14
I71 OMIT 90_PCIE_AP_TO_BB_REFCLK_N
C3043 1 R3043 RADIO_PA_NTC XW3043 90_PCIE_AP_TO_BB_REFCLK_N
90_PCIE_AP_TO_BB_TXD_P
11 14

100PF 11 SHORT-20L-0.05MM-SM 90_PCIE_AP_TO_BB_TX_P 11 14


10KOHM-1% PA_NTC_RETURN 90_PCIE_AP_TO_BB_TXD_N
5% 1 2 RADIO_MLB_KAROO 90_PCIE_AP_TO_BB_TX_N 11 14
16V 2 01005
NP0-C0G ROOM=PMU
90_PCIE_BB_TO_AP_RX_P 90_PCIE_BB_TO_AP_RXD_P
01005 2 ROOM=PMU
32 29 12 50_LAT_WLAN 50_LAT_WLAN
11 14
ROOM=PMU
90_PCIE_BB_TO_AP_RX_N 90_PCIE_BB_TO_AP_RXD_N
12 50_UAT_WLAN_2G_SOUTH
11 14
32 29
50_UAT_WLAN_2G_SOUTH PCIE_AP_TO_BB_RESET_L
32 29 12 50_UAT_WLAN_5G_SOUTH
PCIE_AP_TO_BB_PERST_L 11 14
50_UAT_WLAN_5G_SOUTH PCIE_BB_BI_AP_CLKREQ_L
PCIE_AP_BI_BB_CLKREQ_L 11 14

PCIE_BB_TO_PMU_WAKE_L BB_TO_PMU_PCIE_HOST_WAKE_L 11 14

AP_TO_BB_DEVICE_WAKE

UART_AOP_TO_BB_TXD UART_AOP_TO_BB_TXD 11 14

UART_BB_TO_AOP_RXD UART_BB_TO_AOP_RXD 11 14

SWD_AP_TO_BB_CLK SWD_AOP_TO_MANY_SWCLK 10 11 15
SWD_AOP_BI_BB_SWDIO
B SWD_AP_BI_BB_IO
USB_BB_VBUS PMU_TO_BB_USB_VBUS_DETECT
11 15

11 14
B
90_USB_BB_P 90_USB_BB_DATA_P 11 14

90_USB_BB_N 90_USB_BB_DATA_N 11 14

UART_AP_TO_BB_TXD NC
UART_BB_TO_AP_RXD NC

I2S_BB_TO_AP_BCLK I2S_BB_TO_AP_BCLK 11 14

I2S_BB_TO_AP_LRCLK I2S_BB_TO_AP_LRCLK 11 14

I2S_AP_TO_BB_DOUT I2S_AP_TO_BB_DOUT 11 14

I2S_BB_TO_AP_DIN I2S_BB_TO_AP_DIN 11 14

NFC_SWP1 PMU_TO_GNSS_EN
34 28 12 SIM1_SWP PMU_TO_GNSS_EN 11 27

UART_AP_TO_GNSS_TXD UART_AP_TO_GNSS_TXD 11 27
34 18 12
NFC_TO_BB_CLK_REQ NFC_TO_BB_CLKREQ UART_GNSS_TO_AP_RXD UART_GNSS_TO_AP_RXD 11 27
34 18 12
BB_TO_NFC_CLK BB_TO_NFC_CLK UART_AP_TO_GNSS_RTS_L UART_AP_TO_GNSS_RTS_L 11 27
UART_GNSS_TO_AP_CTS_L UART_GNSS_TO_AP_CTS_L 11 27

AP_TO_GNSS_TIME_MARK AP_TO_BB_TIME_MARK 11 27

AP_TO_GNSS_DEVICE_WAKE AP_TO_GNSS_WAKE 11 27

A SYNC_DATE=07/29/2016 A
PAGE TITLE

RADIOS
DRAWING NUMBER SIZE

051-02247 D
Apple Inc. REVISION

7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
80 OF 80
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
IV ALL RIGHTS RESERVED 12 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
CK
1. ALL RESISTANCE VALUES ARE IN OHMS, 0.1 WATT +/- 5%. APPD
REV ECN DESCRIPTION OF REVISION
2. ALL CAPACITANCE VALUES ARE IN MICROFARADS. DATE
3. ALL CRYSTALS & OSCILLATOR VALUES ARE IN HERTZ.
7 0008448938 ENGINEERING RELEASED 2017-04-11

RADIO_MLB PORTS
D
ICE17.2 RADIO_MLB 28
28

27 26 23
27

18
20 19 18 17 12

17 16 15 14 12

29
29
12
IN

IN
POWER
PP_VDD_MAIN
PP1V8_S2
PP3V0_S2
D

Tue Apr 11 16:10:08 2017


IN

PDF PAGE CSA PAGE CONTENTS


ANTENNA FEEDS
TABLE_TABLEOFCONTENTS_HEAD
CLOCKS 17 IO
50_LAT_WLAN
50_UAT_WLAN_2G_SOUTH
2 2 BASEBAND PMU_TO_BB_GNSS_32K 17 IO
50_UAT_WLAN_5G_SOUTH

3
TABLE_TABLEOFCONTENTS_ITEM

3 BASEBAND MEMORY/DEBUG 28 17 14 12
BB CONTROL
AP_TO_BBPMU_RADIO_ON_L
17 IO

TABLE_TABLEOFCONTENTS_ITEM
IN
PMU_TO_BBPMU_RESET_L
4TABLE_TABLEOFCONTENTS_ITEM
4 BASEBAND POWER 28

28
17

15
12

12
IN

IN
AP_TO_BB_RESET_L

5TABLE_TABLEOFCONTENTS_ITEM
5 BASEBAND PMIC 14 12 OUT
BB_TO_AP_RESET_DETECT_L
BB_TO_STROBE_DRIVER_GSM_BURST_IND
6TABLE_TABLEOFCONTENTS_ITEM
6 TRANSCEIVERS 28 14

28
12

14
OUT

IN
AP_TO_BB_MESA_ON_K

7TABLE_TABLEOFCONTENTS_ITEM
7 ET MODULATOR 14 12 IN
AP_TO_BB_COREDUMP
AP_TO_MANY_BSYNC
8TABLE_TABLEOFCONTENTS_ITEM
8 TDD TRANSMIT 28

14
17 12

12
IN

IN
AP_TO_BB_IPC_GPIO1

9 9 FDD TRANSMIT
TABLE_TABLEOFCONTENTS_ITEM

10 10 PRIMARY RECEIVE PCIE


90_PCIE_AP_TO_BB_REFCLK_P
C TABLE_TABLEOFCONTENTS_ITEM
28 14 12 IN
90_PCIE_AP_TO_BB_REFCLK_N C
11
TABLE_TABLEOFCONTENTS_ITEM
11 LOWER ANTENNA & COUPLERS 28

28
14

14
12

12
IN

IN
90_PCIE_AP_TO_BB_TXD_P
90_PCIE_AP_TO_BB_TXD_N
12
TABLE_TABLEOFCONTENTS_ITEM
12 DIVERSITY RECEIVE ASM'S 28

28
14

14
12

12
IN

OUT
90_PCIE_BB_TO_AP_RXD_P
90_PCIE_BB_TO_AP_RXD_N
13
TABLE_TABLEOFCONTENTS_ITEM
13 DIVERSITY RECEIVE LNA'S 28

28
14

14
12

12
OUT

IN
PCIE_AP_TO_BB_RESET_L
PCIE_BB_BI_AP_CLKREQ_L
14
TABLE_TABLEOFCONTENTS_ITEM
14 UPPER ANTENNA FEEDS 28
16

14
2

12
IO

OUT
BB_TO_PMU_PCIE_HOST_WAKE_L

15 15 GNSS AP_TO_BB_DEVICE_WAKE
TABLE_TABLEOFCONTENTS_ITEM

16 16 TEST POINTS & SIM 28 14


UART
UART_AP_TO_BB_TXD_K
TABLE_TABLEOFCONTENTS_ITEM
IN

28 14 OUT
UART_BB_TO_AP_RXD_K

ALTERNATES 14 12
AOP
UART_AOP_TO_BB_TXD
IN

14 12 OUT
UART_BB_TO_AOP_RXD
PART NUMBER ALTERNATE FOR REFERENCE DESIGNATOR(S) DESCRIPTION BOM OPTION
PART NUMBER
197S00040 197S00044 VTCXO_K AVX VC-TCXO ?
197S00042
335S00013
197S00044
335S0894
VTCXO_K
EPROM_K
NDK VC-TCXO
ON SEMI EEPROM
?
? 14 12
AUDIO
I2S_BB_TO_AP_BCLK
OUT
14 12 OUT
I2S_BB_TO_AP_LRCLK
138S0719 138S1103 C522_K MURATA ? I2S_AP_TO_BB_DOUT
14 12 IN

138S00133 138S00128 C509_K, C523_K, C605_K, C624_K, C626_K, C1114_K, C1116_K MURATA ? 14 12 OUT
I2S_BB_TO_AP_DIN

B 138S00049
138S0831
138S00032
138S00032
C402_K, C433_K, C437_K, C510_K, C720_K

C402_K, C433_K, C437_K, C510_K, C720_K


MURATA
MURATA
?
? 28 14 12
WLAN
UART_BB_TO_WLAN_COEX
B
IN

28 14 12 OUT
UART_WLAN_TO_BB_COEX
138S00086 138S0884 C500_K, C501_K, C502_K, C514_K, C515_K MURATA ?
339S00363 339S00353 GNSS_K PILSNER STATS ?
16
NFC
NFC_SWP1
IO

18 12 IN
NFC_TO_BB_CLK_REQ
28 18 12 OUT
BB_TO_NFC_CLK

GNSS
BOM OPTIONS 28

28

28

28
27

27

27

27
12

12

12

12
IN

IN

OUT

IN
PMU_TO_GNSS_EN
UART_AP_TO_GNSS_TXD
UART_GNSS_TO_AP_RXD
UART_AP_TO_GNSS_RTS_L
TABLE_5_HEAD

PART# QTY DESCRIPTION REFERENCE DESIGNATOR(S) CRITICAL BOM OPTION 28 27 12 OUT


UART_GNSS_TO_AP_CTS_L
TABLE_5_ITEM

998-05780 1 BASEBAND, UNFUSED U_BB_K CRITICAL BB_UNFUSED


28 27 12 IN
AP_TO_BB_TIME_MARK
TABLE_5_ITEM

998-05781 1 BASEBAND, LOCAL FUSED U_BB_K CRITICAL BB_LOCAL_FUSED 27 12 IN


AP_TO_GNSS_WAKE

DEBUG
TABLE_5_ITEM

998-05782 1 BASEBAND, DEV FUSED U_BB_K CRITICAL BB_DEV_FUSED


TABLE_5_ITEM

337S00244 1 BASEBAND, PRODUCTION FUSED U_BB_K CRITICAL BB_PROD_FUSED 28 15 12 IN


SWD_AOP_TO_MANY_SWCLK
TABLE_5_ITEM

16 3 IO
SWD_AOP_BI_BB_SWDIO
138S00159 7 CAP,SOFT-TERM,2.2uF,6.3V,0201,KYOCERA C402_K,C437_K,C438_K,C433_K,C510_K,C720_K,C1601_K SOFT_CAP
28 14 12 IN
PMU_TO_BB_USB_VBUS_DETECT
TABLE_5_ITEM

138S0831 7 CAP,TYPICAL,2.2UF,6.3V,0201,MURATA C402_K,C437_K,C438_K,C433_K,C510_K,C720_K,C1601_K TYPICAL_CAP 16 2 IO


90_USB_BB_DATA_P
90_USB_BB_DATA_N
A 16 2 IO RADIO_MLB A
DRAWING TITLE

SCH,MLB,BOT,X893
DRAWING NUMBER SIZE

051-02247 D
Apple Inc. REVISION

7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
1 OF 17
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
IV ALL RIGHTS RESERVED 13 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BASEBAND
17 16 15 14 11 6 5 4 3 2 1 PP1V8_S2
1 1
R200_K R208_K
100K 100K
1% 1%
1/32W 1/32W
MF MF
2 01005
BASEBAND 2 01005
BASEBAND
16 2 1 PCIE_BB_BI_AP_CLKREQ_L
16 5 2 1 AP_TO_BBPMU_RADIO_ON_L

17 16 15 14 11 6 5 4 3 2 1 PP1V8_S2
1
R201_K
D 1%
100K
1/32W
D
MF
2 01005
BASEBAND
16 2 SIM1_DETECT_K

U_BB_K
U_BB_K VDD_SIM1_K
PMB9948
16 5 4
PMB9948 BGA
BGA 1 SYM 7 OF 9
SYM 1 OF 9
R202_K OMIT_TABLE
OMIT_TABLE 4.7K
5% U5 SYS_CLK D1
1/32W 28 18 IN
SYSCLK_26MHZ_K RXDAT_MAIN_0_1- 90_DIGRF_M0_RX1_N_K IN 18

SIM CARD 1
G18 CC1_CLK FS MF D2
SIM1_CLK_K RXDAT_MAIN_0_1+ 90_DIGRF_M0_RX1_P_K
28 OUT 2 01005 SYSCLK_26MHZ_EN_K V6 SYS_CLK_EN IN 18

SIM1_IO_K F19 CC1_IO FS 18 OUT


28 14 BI
RXDAT_MAIN_0_2- C2 90_DIGRF_M0_RX2_N_K
SIM1_RST_K F18 CC1_RST FS SIM1_IO_K IN 18
28 OUT 16 2
RXDAT_MAIN_0_2+ C3 90_DIGRF_M0_RX2_P_K 18
IN

CLOCKS AND CONTROL


RXDAT_MAIN_1_1- M1 90_DIGRF_M1_RX1_N_K 18
IN
PP1V8_S2

SIM CARD 2
H18 17 16 15 14 11 6 5 4 3 2 1
M2

DIGRF V4.0 MAIN


CC2_IN FS RXDAT_MAIN_1_1+ 90_DIGRF_M1_RX1_P_K
NC IN 18

H19 CC2_CLK FS 1 1
NC R207_K R209_K RXDAT_MAIN_1_2- L1 90_DIGRF_M1_RX2_N_K
G19 CC2_IO FS 1.00K 1.00K IN 18

NC 1% 1% RXDAT_MAIN_1_2+ L2 90_DIGRF_M1_RX2_P_K
H20 CC2_RST FS 1/32W 1/32W
IN 18

NC I2S2_CLK0 W2 I2S_BB_TO_AP_BCLK 13 MF MF
OUT 12
TXDAT_MAIN_0_1- E1 90_DIGRF_M0_TX_N_K
UART_BB_TO_AP_RXD_K J20 USIF1_TXD_MTSR FS I2S2_CLK1 AA4 AP_TO_BB_MESA_ON_K 2 01005
BASEBAND 2 01005
BASEBAND
OUT 18 28

I2S2
28 13 OUT IN 13 28
EINT3 TXDAT_MAIN_0_1+ E2 90_DIGRF_M0_TX_P_K
28 13 UART_AP_TO_BB_TXD_K J18 USIF1_RXD_MRST FS I2S2_RX Y3 I2S_AP_TO_BB_DOUT 12 13 5 2 I2C_BBPMU_SCL_K OUT 18 28
IN IN
W3 N1
USIF1

I2S2_TX I2S_BB_TO_AP_DIN OUT 12 13 5 2 I2C_BBPMU_SDA_K TXDAT_MAIN_1_1- 90_DIGRF_M1_TX_N_K OUT 18 28

K20 USIF1_RTS* I2S2_WA0 Y4 I2S_BB_TO_AP_LRCLK 13 TXDAT_MAIN_1_1+ N2 90_DIGRF_M1_TX_P_K


NC OUT 12 OUT 18 28

EINT4 K19 USIF1_CTS* FS FS I2S2_WA1 W4 AP_TO_BB_COREDUMP 13


IN 12
EINT2 MPHY_MAIN_0_EN A3 DIGRF_M0_EN_K 18
OUT
UART_BB_TO_AOP_RXD E19 USIF3_TXD_MTSR MPHY_MAIN_1_EN K4 DIGRF_M1_EN_K
C 13

13
12 OUT
UART_AOP_TO_BB_TXD E18 USIF3_RXD_MRST FS
THERM_SNS_A T18 NC
H2
OUT 18
C
THERM_SNS_C T19
12 IN
RXDAT_AUX_0_1- 90_DIGRF_A0_RX1_N_K
NC IN 18
USIF3

RXDAT_AUX_0_1+ H1 90_DIGRF_A0_RX1_P_K
28 DEV_HW_CONFIG_K D18 USIF3_RTS* IN 18
IN
EINT6 D19 USIF3_CTS* FS RXDAT_AUX_0_2- J1 90_DIGRF_A0_RX2_N_K
NC IN 18

RXDAT_AUX_0_2+ J2 90_DIGRF_A0_RX2_P_K
EINT5 13 12 AP_TO_BB_IPC_GPIO1 Y7 USIF2_TXD_MTSR IN 18
BI

DIGRF V4.0 AUX


Y6 USIF2_RXD_MRST I2C1_SCL L19 T1
I2C1

I2C_BB_EEPROM_SCL_K RXDAT_AUX_1_1- 90_DIGRF_A1_RX1_N_K


NC 2 IN 18 28

I2C1_SDA L20 I2C_BB_EEPROM_SDA_K RXDAT_AUX_1_1+ T2 90_DIGRF_A1_RX1_P_K


USIF2

2 IN 18 28

Y5 USIF2_RTS*
NC
AA7 USIF2_CTS* I2C2_SCL B16 I2C_BBPMU_SCL_K OUT 14 17 RXDAT_AUX_1_2- U1 90_DIGRF_A1_RX2_N_K IN 18
I2C2

NC I2C2_SDA A15 I2C_BBPMU_SDA_K BI 14 17 RXDAT_AUX_1_2+ U2 90_DIGRF_A1_RX2_P_K IN 18

EXTRA I/OS TXDAT_AUX_0_1- G2 90_DIGRF_A0_TX_N_K 18


OUT
J17 CLKOUT1 TXDAT_AUX_0_1+ G1 90_DIGRF_A0_TX_P_K
NC OUT 18

USB_DPLUS Y1 90_USB_BB_DATA_P 12 13 28 TXDAT_AUX_1_1- R1 90_DIGRF_A1_TX_N_K 18


BI OUT
EINT7 U7 MMCI1_CD* USB_DMINUS AA1 90_USB_BB_DATA_N 28 TXDAT_AUX_1_1+ R2 90_DIGRF_A1_TX_P_K
NC BI 12 13 OUT 18

13 BB_TO_AP_RESET_DETECT_L V9 MMCI1_CLK VBUS W1 PMU_TO_BB_USB_VBUS_DETECT


12 OUT 1 16
MPHY_AUX_0_EN J4 DIGRF_A0_EN_K
BB_DEBUG_ERROR_K W7 AA3 USB_BB_TUNE_K OUT 18
MMC/SDIO1

28 OUT MMCI1_CMD USB_TUNE T4


MPHY_AUX_1_EN DIGRF_A1_EN_K
U9 Y2 OUT 18
USB 3.0

BB_HW_ID<0>_K MMCI1_DAT_0 USB_TEST


28 IN NC 1
BB_HW_ID<1>_K V7 MMCI1_DAT_1 R205_K BASEBAND
28 IN
USB30_TXP AB2 200
BB_HW_ID<2>_K V8 MMCI1_DAT_2 NC 1%
28 IN
USB30_TXN AB1 1/32W
BB_HW_ID<3>_K U8 MMCI1_DAT_3 NC MF
28 IN
USB30_RXP AC1
NC 2 01005
BASEBAND
USB30_RXN AC2
NC

B B
PCI_PET_P1 AE16 90_PCIE_BB_TO_AP_RXD_P
EXT INTERRUPT

28
EINT0 BBPMU_ALERT_L_K C15 EINT0 OUT 12 13
U_BB_K
17 IN
PCI_PET_N1 AE15 90_PCIE_BB_TO_AP_RXD_N 28
CC1_IN SIM1_DETECT_K K18 EINT1 FS OUT 12 13
PMB9948
AE13
PCIE

28 14 IN
PCI_PER_P1 90_PCIE_AP_TO_BB_TXD_P 28
28 BB_TO_PMU_PCIE_HOST_WAKE_L M20 EINT2 BOOTROM DRIVEN IN 12 13
BGA
13 12 OUT
PCI_PER_N1 AE14 90_PCIE_AP_TO_BB_TXD_N 28 SYM 9 OF 9
L18 EINT3 FS IN 12 13

NC PCI_REFCLK_P AC15 90_PCIE_AP_TO_BB_REFCLK_P 12 13 28 17 BBPMU_STBY_K C16 MODEM_STDBYOMIT_TABLE


IN OUT
PCI_REFCLK_N AC14 90_PCIE_AP_TO_BB_REFCLK_N 28 FS PCIE_CLKREQ* N18 PCIE_BB_BI_AP_CLKREQ_L 28
IN 12 13
28
E17 FTA_TRIG
BB_TO_STROBE_DRIVER_GSM_BURST_IND BI 12 13 14

PCI_REF_RES AA15 PCIE_REF_RES_K


13 12 OUT
PCIE_PERST* P18 PCIE_AP_TO_BB_RESET_L 12 13 28 PERST PULLED DOWN AT AP
IN
GNSS_BLANK_K F17
1 27 OUT IDC_PA_BLANKING
BASEBAND R206_K E16 1
28 13 12 IN
UART_WLAN_TO_BB_COEX IDC_UART_RXD FS C201_K
200 F16 100PF
1% 28 13 12 OUT
UART_BB_TO_WLAN_COEX IDC_UART_TXD FS
1/32W 5%
MF 16V
2 NP0-C0G
AP_TO_BBPMU_RADIO_ON_L D15 SDWN_REQ* FS
2 01005
BASEBAND
28 17 14 13 12 OUT 01005
BASEBAND
BBPMU_VCLK_K B13
28 17 OUT VCLK

BBPMU_VDIO_K C14
28 17 BI VDIO

BB EEPROM BASEBAND

17 16 15 14 11 6 5 4 3 2 1 PP1V8_S2

1 C200_K 1 1
1UF R203_K R204_K
20% 10K 10K
16V
2 CER-X5R 1% 1%
0201 1/32W 1/32W
BASEBAND MF MF
2 01005 2 01005
A1

BASEBAND BASEBAND
VCC
A EPROM_K
A
PAGE TITLE
CAT24C08C4A
2 I2C_BB_EEPROM_SCL_K B1 SCL
WLCSP
SDA B2 I2C_BB_EEPROM_SDA_K 2
BASEBAND
DRAWING NUMBER SIZE

051-02247 D
Apple Inc. REVISION
VSS
BASEBAND
7.0.0
NOTICE OF PROPRIETARY PROPERTY:
A2

BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
2 OF 17
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
IV ALL RIGHTS RESERVED 14 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BASEBAND MEMORY/DEBUG

17 16 15 14 11 6 5 4 3 2 1 PP1V8_S2

D 1
D
R300_K
100K
1%
1/32W
MF
2 01005
BASEBAND
U_BB_K 28 15 13 12 IN
AP_TO_BB_RESET_L
PMB9948
BGA
SYM 2 OF 9
OMIT_TABLE
V11 NAND_ADQ_0 DDR_DQ_0 AE6
NC NC
AB12 NAND_ADQ_1 DDR_DQ_1 AD7
NC NC
AA12 NAND_ADQ_2 U_BB_K
NC
Y13 NAND_ADQ_3 PMB9948
NC
W11 NAND_ADQ_4 BGA
NC SYM 6 OF 9
V12 NAND_ADQ_5 OMIT_TABLE
NC
U13 NAND_ADQ_6
NC
V13 NAND_ADQ_7
NC

DBB EMIC
NAND IF

U_BB_K
BBPMU_PWRGOOD_K B14 PWRGOOD PMB9948
28 18 17 IN BGA
DDR_DQ_15 AD15 NC B15 XG_RESET* 28 13 12 IN
SWD_AOP_TO_MANY_SWCLK F15 SWDCLK FS SYM 5 OF 9
BBPMU_XG_RESET_L_K OMIT_TABLE

PMU CONTROL
DDR_DQ_16 AE2 E15 SWDIO
28 17 IN
28 SWD_AOP_BI_BB_SWDIO FS
Y10 NAND_ALE NC 13 12 BI

C NC
NC
Y9 NAND_CE*
28 17 IN
BBPMU_XG_RESET_SD_L_K B17 XG_SDWN*
28 OUT
BB_JTAG_TDO_K C19 TDO TRIG_IN C20 NC
C
Y11 NAND_CLE BB_TO_AP_RESET_ACT_L_K M19 RESET2* BB_JTAG_TDI_K B20 TDI
NC HW_MON1 D20
28 OUT 28 IN
HW_MON1_K
U11 N20 CP_RESET_BB* FS C18 OUT 28

JTAG
NAND_RB* 28 AP_TO_BB_RESET_L BB_JTAG_TMS_K TMS
NC HW_MON2 E20
15 13 12 IN 28 IN
HW_MON2_K
AC9 NAND_RE* BB_JTAG_TCK_K D17 TCK
OUT 28

NC XCVR0_RESET_L_K L4 RESET_TRX1* 28 IN
W10 NAND_WE*
18 OUT
BB_JTAG_TRST_L_K A19 TRST*
NC XCVR1_RESET_L_K U4 RESET_TRX2* 28 IN
W12 NAND_WP*
18 OUT B19 RTCK

MONITORING
NC NC
F4 TPIU_TRACEPKT0
NC
E4 TPIU_TRACEPKT1
NC
B8 DDR_CA_0 E5 TPIU_TRACEPKT2
NC NC
A8 DDR_CA_1 F5 TPIU_TRACEPKT3
NC L10 RCT_MON2 NC
A9 NC E7

ADN SENSE
DDR_CA_2

CONTACT
NC L11 RCT_MON1 NC TPIU_TRACEPKT4
B9 DDR_CA_3 NC F6 TPIU_TRACEPKT5
NC NC
C10 DDR_CA_4 H16 VSS_SENSE D6 TPIU_TRACEPKT6
NC VSS P19 NC
A13 DDR_CA_5 DDR_DQ_31 AE19 G7 TPIU_TRACEPKT7
NC NC V1 NC

TPIU
C12 VSS G6
NC DDR_CA_6 AD9 N19 NC TPIU_TRACEPKT8
C13 DDR_DQS_T_0 NC VSS D5
NC DDR_CA_7 AE9 T20 NC TPIU_TRACEPKT9
D13 DDR_DQS_C_0 NC VSS F8
NC DDR_CA_8 AD13 AA6 NC TPIU_TRACEPKT10
E14 DDR_DQS_T_1 NC VSS C6
NC DDR_CA_9 AE12 B18 NC TPIU_TRACEPKT11
DDR_DQS_C_1 NC VSS C5
AD6 V2 NC TPIU_TRACEPKT12
DDR_DQS_T_2 NC VSS C7
AE5 AA5 NC TPIU_TRACEPKT13
DDR_DQS_C_2 NC VSS D7
AE17 W13 NC TPIU_TRACEPKT14
DDR_DQS_T_3 NC VSS E8
AC16 W15 NC TPIU_TRACEPKT15
DDR_DQS_C_3 NC VSS
VSS W17 C4 TPIU_TRACECLK
DDR_CK_T B11 NC
NC VSS W19 D4 TPIU_TRACECTL
DDR_CK_C A11 NC
NC VSS W20
AD10
B DDR_DQM_0
DDR_DQM_1 AD12
NC VSS W5 BASEBAND
B
NC VSS Y17
VSS Y19
DDR_DQM_3 AD16 NC
BASEBAND
CLOCKS & CONTROL

DDR_CS_1 B10 NC

G16 FSYS_32K DDR_CKE_1 AB10 BB_DDR_CKE_K 4


17 OUT
BBPMU_32K_K
28 27 15 TCXO_BB_GNSS_32K_K R20 F32K FS DDR_VREF_DQ AE10 BB_DDR_VREF_DQ_K
IN

NC
P20 OSC32K DDR_VREF_CA A12 BB_DDR_VREF_CA_K

BASEBAND 1 C300_K 1 C301_K


47PF 47PF
5% 5%
2 16V
CERM 2 16V
CERM
01005 01005
BASEBAND BASEBAND

R302_K
1
0.00 2
17 16 15 14 11 6 5 4 3 2 1 PP1V8_S2 PP1V8_TCXO_K
0%
1/32W
MF 1 C303_K
3

01005
0.1UF VDD
20%
6.3V
2 X5R-CERM
01005
TCXO_K
32.768KHZ-5PPM
A BASEBAND
CSP A
1 CAL/NC CLKOUT 2 TCXO_BB_GNSS_32K_K PAGE TITLE
NC OUT 15 27 28

BASEBAND MEMORY/DEBUG
GND DRAWING NUMBER SIZE

051-02247 D
4

Apple Inc. REVISION

7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
3 OF 17
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
IV ALL RIGHTS RESERVED 15 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1
6
4 VDD_CORE_1V0_K AA16 VDD_CORE_MAIN

BASEBAND POWER U_BB_K


5
AA18 VDD_CORE_MAIN
1 C413_K 1 C418_K PMB9948
AA20 VDD_CORE_MAIN
1UF 0.1UF BGA
20% 20% AB5 VDD_CORE_MAIN SYM 4 OF 9
16V
2 CER-X5R 6.3V
2 X5R-CERM R14 VDD_CORE_MAIN DBB POWER PINS
0201 01005 OMIT_TABLE
BASEBAND BASEBAND R16 VDD_CORE_MAIN
Y20 AA20 VDD_EMIC_IO_0 AC7 VDD_IO_1V2_K
T16 VDD_CORE_MAIN
4 5

VDD_EMIC_IO_0 AC8
U15 VDD_CORE_MAIN 1 C424_K 1 C427_K 1 C429_K 1 C431_K 1 C434_K 1 C436_K
VDD_EMIC_IO_1 AB15
U16 VDD_CORE_MAIN 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 1UF
VDD_EMIC_IO_1 AB14 20% 20% 20% 20% 20% 20%
U18 VDD_CORE_MAIN 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 16V
2 CER-X5R
VDD_EMIC_IO_2 AC5
V14 VDD_CORE_MAIN 01005 01005 01005 01005 01005 0201
VDD_EMIC_IO_2 AC6 BASEBAND BASEBAND BASEBAND BASEBAND BASEBAND BASEBAND
V16 VDD_CORE_MAIN AC17
D V18 VDD_CORE_MAIN
VDD_EMIC_IO_3
VDD_EMIC_IO_3 AC18
AE11
D
W16 VDD_CORE_MAIN
VDD_EMIC_IO_CA AC11
W18 VDD_CORE_MAIN
VDD_EMIC_IO_CA AC12
Y16 VDD_CORE_MAIN
VDD_EMIC_1V8_IO AB16 VDD_DDR_1V8_K
Y14 VDD_CORE_MAIN
4 5

VDD_LDO_DLL_EMIC AE11
Y18 VDD_CORE_MAIN 1 C440_K
Y20 VDD_CORE_MAIN 0.1UF
20%
6.3V
2 X5R-CERM
01005
BASEBAND
6 5 4 VDD_CORE_1V0_K L6 VDD_CORE_3G VDD_LDO_USB_SS AC3 VDD_IO_1V2_K 4 5

M4 VDD_CORE_3G LDO_MON_USB_SS AD1


1 C414_K 1 C419_K NC 1 C407_K
M5 VDD_CORE_3G VDD_USB_SS_IO AA2 VDD_USB_3V15_K
1UF 0.1UF 5
0.22UF
20% 20% N6 VDD_CORE_3G 20%
16V
2 CER-X5R 6.3V
2 X5R-CERM 1 C435_K 6.3V
2 X5R
P4 VDD_CORE_3G
0201 01005 0.1UF 01005
BASEBAND BASEBAND R6 VDD_CORE_3G 20%
M5 6.3V
2 X5R-CERM
U6 VDD_CORE_3G VDD_LDO_DIGRF_PHY1 F1 VDD_IO_1V2_K 4 5
01005
V4 VDD_CORE_3G LDO_MON_DIGRF1 G4 BASEBAND
NC 1 C425_K 1 C428_K 1 C430_K 1 C432_K
V5 VDD_CORE_3G VDD_LDO_DIGRF_PHY2 K2
1UF 0.1UF 0.1UF 0.1UF
LDO_MON_DIGRF2 D3 20% 20% 20% 20% U_BB_K
VDD_CORE_1V0_K B6 VDD_CORE_LTE NC 16V
2 CER-X5R 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM
6 5 4
VDD_LDO_DIGRF_PHY3 K1 PMB9948
B7 VDD_CORE_LTE 0201 01005 01005 01005
1 C415_K 1 C420_K LDO_MON_DIGRF3 N4 BASEBAND BASEBAND BASEBAND BASEBAND BGA
C11 VDD_CORE_LTE NC
1UF 0.1UF VDD_LDO_DIGRF_PHY4 P1 A10 VSS SYM 3 OF 9 VSS_USB AB3
20% 20% C8 VDD_CORE_LTE
16V
2 CER-X5R 6.3V
2 X5R-CERM LDO_MON_DIGRF4 R4 A14 VSS GROUND VSS_PLL W9
D11 VDD_CORE_LTE NC OMIT_TABLE
0201 01005 A2 VSS VSS_PLL W14
BASEBAND BASEBAND D9 VDD_CORE_LTE
B6 B7 A4 VSS VSS_MPHY_1 E3
E11 VDD_CORE_LTE
VDD_LDO_PCIE U20 AA14 VSS VSS_MPHY_1 F3
E9 VDD_CORE_LTE
LDO_MON_PCIE U19 AA17 VSS VSS_MPHY_2 H3
C F10
F11
VDD_CORE_LTE
VDD_PCIE_1V8 V20
NC
PP1V8_S2 1 2 3 4 5 6 11 14 15 16 17
AA19 VSS VSS_MPHY_2 J3 C
VDD_CORE_LTE AA8 M3
F12 VSS VSS_MPHY_3
VDD_CORE_LTE VPP Y8 NC
1 C426_K M17 N3
F13 0.1UF VSS VSS_MPHY_3
VDD_CORE_LTE A1 20% AC10 R3
F9 DUMMY_BALL NC 6.3V VSS VSS_MPHY_4
VDD_CORE_LTE A20 2 X5R-CERM B1 T3
G10 DUMMY_BALL NC 01005 VSS VSS_MPHY_4
VDD_CORE_LTE AE1 BASEBAND B12
G11 DUMMY_BALL NC VSS
VDD_CORE_LTE AE20 B2
H10 DUMMY_BALL NC VSS
VDD_CORE_LTE U_BB_K B3
H11 VSS VSS_PCIE_TX V19
VDD_CORE_LTE PMB9948 B4
H15 BGA VSS
VDD_CORE_LTE B5 N10
J10 AA11 CKE_MEM SYM 8 OF 9 AA13 VSS VSS
VDD_CORE_LTE 3 BB_DDR_CKE_K VSS_EMIC C1 N11
J11 D14 ZQ_MEM LPDDR2 RAM AB17 VSS VSS
VDD_CORE_LTE ZQ_MEM_K VSS_EMIC D8 N12
J12 OMIT_TABLE AB18 VSS VSS
VDD_CORE_LTE VSS_EMIC E10 N13
J13 AB19 VSS VSS
VDD_CORE_LTE VSS_EMIC E12 N14
J5 1 AB9 VSS VSS
VDD_CORE_LTE R400_K VSS_EMIC E13 N16
J6 AC19 VSS VSS
VDD_CORE_LTE 240 VSS_EMIC E6 N17
J7 1% A16 AC4 VSS VSS
VDD_CORE_LTE 1/32W 5 4 VDD_DDR_1V8_K VDD1_MEM VSS_EMIC F14 N7
J8 MF A6 AD11 VSS VSS
VDD_CORE_LTE 2 01005 VDD1_MEM VSS_EMIC F2 N8
J9 BASEBAND AB20 AD17 VSS VSS
VDD_CORE_LTE VDD1_MEM VSS_EMIC F7 N9
K11 AD3 AD18 VSS VSS
VDD_CORE_LTE VDD1_MEM VSS_EMIC G13 P10
K13 AD20 VSS VSS
VDD_CORE_LTE A17 VSS_EMIC G14 P11
VDD_IO_1V2_K VDD2_MEM VSS VSS
K15 VDD_CORE_LTE
5 4
VSS_EMIC AD4
A5 VDD2_MEM G3 VSS VSS P12
K5 VDD_CORE_LTE VSS_EMIC AD5
AC20 VDD2_MEM G9 VSS VSS P15
K8 VDD_CORE_LTE VSS_EMIC AD8
A7 VDD2_MEM H5 VSS VSS P17
M10 VDD_CORE_LTE VSS_EMIC C9
AD2 VDD2_MEM H6 VSS VSS P2
M11 VDD_CORE_LTE VSS_EMIC D10
H7 VSS VSS P3
M13 AC13 D12
B M15
VDD_CORE_LTE
VDD_CORE_LTE AE18
VDDQ_MEM
VDDQ_MEM
VSS_EMIC
VSS_EMIC G12
H8 VSS VSS P6 B
H9 VSS VSS P7
M8 VDD_CORE_LTE AE4 VDDQ_MEM VSS_EMIC H12
J16 VSS VSS P8
M9 VDD_CORE_LTE AE7 VDDQ_MEM VSS_EMIC H13
K10 VSS VSS P9
R12 VDD_CORE_LTE VSS_EMIC J15
K16 VSS VSS R13
R9 VDD_CORE_LTE VSS_EMIC K12
K3 VSS VSS R15
L17 VDD_CORE_LTE VSS_EMIC L13
K6 VSS VSS R17
C17 VDD_CORE_LTE VSS_EMIC M12
K7 VSS VSS R7
H17 VDD_CORE_LTE VSS_EMIC N15
K9 VSS VSS T11
P14 VDD_CORE_LTE VSS_EMIC P13
VDD_CORE_1V0_K L16 VSS VSS T12
6 5 4
P16 VDD_CORE_LTE VSS_EMIC V15
K17 VSS VSS T13
1 C416_K 1 C421_K M18 VDD_CORE_LTE L3 VSS VSS T14
1UF 1UF AB7 VDD_CORE_DSP
20% 20% L5 VSS VSS T15
16V
2 CER-X5R 16V
2 CER-X5R AB8 VDD_CORE_DSP
VSSQ_MEM AD19 L7 VSS VSS T17
0201 0201 U10 VDD_CORE_TD
BASEBAND BASEBAND VSSQ_MEM AD14 L8 VSS VSS T7
V10 VDD_CORE_TD
AB7 U10 VSSQ_MEM AE3 L9 VSS VSS U14
5 4 VDD_IO_1V2_K Y12 VDD_LDO_PLL VSSQ_MEM AE8 M16 VSS VSS U17
U12 LDO_MON_PLL D16 VSS VSS R18
NC BASEBAND AB4 VSS VSS U3
PP1V8_S2 R19 VDD_RTC
11 6
17
5 4 3 2
16 15
1
14 M6 VSS VSS V17
VDD_SIM1_K G20 VDD_SIM1
16 5 2
VDD_IO_1V2_K M7 VSS VSS G17
5 VDD_SIM2_K F20 VDD_SIM2 5 4

1 C402_K 1 C403_K 1 C404_K 1 C405_K 1 C437_K 1 C438_K 1 C409_K 1 C410_K BASEBAND


2.2UF 0.1UF 0.1UF 0.1UF 2.2UF 2.2UF 0.1UF 0.1UF
PP1V8_S2 AB6 VDD_IO18 20% 20% 20% 20% 20% 20% 20% 20%
17 16 15 14 11 6 5 4 3 2 1
6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM 6.3V
2 X5R-CERM
AA9 VDD_IO18
1 C411_K 1 C412_K 1 C400_K 1 C441_K 1 C417_K 1 C422_K 0201 01005 01005 01005 0201 0201 01005 01005
G8 VDD_IO18 BASEBAND BASEBAND BASEBAND BASEBAND BASEBAND BASEBAND BASEBAND BASEBAND
A 16V
1UF
20%
0.1UF
20%
6.3V
0.47UF
10%
6.3V
0.47UF
10%
6.3V
0.1UF
20%
6.3V
0.1UF
20%
6.3V
J19 VDD_IO18
OMIT_TABLE OMIT_TABLE OMIT_TABLE
A
2 CER-X5R 2 X5R-CERM 2 CERM-X5R 2 CERM-X5R 2 X5R-CERM 2 X5R-CERM R10 PAGE TITLE
0201 01005 0201 0201 01005 01005 VDD_IO18
BASEBAND BASEBAND BASEBAND BASEBAND BASEBAND BASEBAND R11
R8
VDD_IO18 5 4 VDD_DDR_1V8_K BASEBAND POWER
VDD_IO18 1 1 1 1 DRAWING NUMBER SIZE
C433_K C406_K C408_K C439_K
R401_K
T8 VDD_IO18 2.2UF 0.1UF 0.1UF 0.1UF 051-02247 D
10K 2 A18 VREF_0V6
20%
6.3V
20%
6.3V
20%
6.3V
20%
6.3V
Apple Inc. REVISION
VDD_VREFCP_K 1 VREF_0V6_K 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM 2 X5R-CERM
5

1% 5 4 VDD_IO_1V2_K AB13 VDD_LDO_CORE_EMIC 0201 01005 01005 01005 7.0.0


1/32W 1 C401_K BASEBAND BASEBAND BASEBAND BASEBAND NOTICE OF PROPRIETARY PROPERTY: BRANCH
MF AB11 LDO_MON_EMIC OMIT_TABLE
01005 0.01UF 1 C423_K NC THE INFORMATION CONTAINED HEREIN IS THE evt-1
BASEBAND 10% PROPRIETARY PROPERTY OF APPLE INC.
6.3V
2 X5R 1UF THE POSESSOR AGREES TO THE FOLLOWING: PAGE
20% BASEBAND
01005
BASEBAND
16V
2 CER-X5R I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
4 OF 17
0201 SHEET
BASEBAND III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 16 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

BASEBAND PMIC

D D

L500_K
BBPMU_K 0.47UH-20%-3.8A-0.037OHM
16 15 8 7 6 5 1 PP_VDD_MAIN B4 VSYS PMB6848 VMOD1LX D1 VMOD1LX_K 1 2 VDD_CORE_1V0_K 4 5 6

G4 VSYS UFWLB VMOD1LX D2 0805


17 16 15 14 11 6 5 4 3 2 1 PP1V8_S2 H8 VSWITCHVIN VMOD1SENSE D3 VMOD1_FB_K 5 L501_K
1.0UH-20%-2.6A-0.073OHM
28 18 15 OUT
BBPMU_PWRGOOD_K E4 XG_PWRGOOD VMOD2LX A2 VMOD2LX_K 1 2 VRF_CORE_1V0_K 5 6

28 13 12 PMU_TO_BBPMU_RESET_L B6 PMIC_ON VMOD2LX B2 0805


IN
28 14 13 12 AP_TO_BBPMU_RADIO_ON_L C4 SDWN* VMOD2SENSE B1 VMOD2_FB_K 5 L502_K
IN
2.2UH-20%-1.4A-0.21OHM
28 15 BI
BBPMU_XG_RESET_L_K F2 XG_RESET* VMOD3LX A7 VMOD3LX_K 1 2 VRF_ANA_1V3_K 5 6

28 15 OUT
BBPMU_XG_RESET_SD_L_K F6 XG_RESET_SD* VMOD3SENSE B7 VMOD3_FB_K 5
0805 L503_K
H4 VUSB_IO 0.7MM MAX Z 1.0UH-20%-1.9A-0.120OHM
4 VDD_USB_3V15_K
1 VMOD4LX H2 VMOD4LX_K 1 2 VDD_IO_1V2_K 4 5
C510_K A4
2.2UF 15 IN
BBPMU_32K_K CLK_32K VMOD4SENSE G1 VMOD4_FB_K 5
0603
20%
6.3V
2 X5R-CERM 14 BI
I2C_BBPMU_SDA_K F3 I2CSDA VSWITCH G8 VDD_DDR_1V8_K 4
R501_K
F4 2.2K 2
0201
BBPMU 14 IN
I2C_BBPMU_SCL_K I2CSCL GPIO1 G7 TOUCH_TO_BBPMU_FORCE_PWM_R_K 1 AP_TO_MANY_BSYNC IN 12 13 28

OMIT_TABLE 5%
1/32W
28 14 BBPMU_VDIO_K B3 VDIO VDD_VMOD1 E1 PP_VDD_MAIN 1 5 6 7 8 15 16 MF
BI
01005
VDD_VMOD1 E2
C 28 14 IN
BBPMU_VCLK_K D4 VCLK
VDD_VMOD2 A1 C
14 BBPMU_STBY_K G3 STBY VDD_VMOD4 H1
IN
VDD_VMOD3 A8
14 BBPMU_ALERT_L_K E3 ALERT* 1 C517_K
OUT
1UF
20%
C6 TESTENTRY VCHP_C+ C8 VCHP_CP_K 10V
2 X5R
E7 ANAMON VCHP_C- D8 VCHP_CN_K 0201
NC BBPMU
BBPMU.C8/D8
5 BBPMU_AGND_K G2 VSSA VCHP C7 VDD_BBPMU_3V3_K 5

C3 VSSA VDD_CHP D7 PP1V8_S2 1 2 3 4 5 6 11 14 15 16 17


2 D5 VSSA
XW500_K H5 VSSA VSIM1 G6 VDD_SIM1_K 2 4 16
OMIT
SHORT-10L-0.25MM-SM F7 VSSA VSIM2 H6 VDD_SIM2_K 4
1 H7 VSSA
E8 VRF A5 VFE_LNA_2V7_K 12 13
VSSA
B8 VFE_AUX B5 VFE_AUX_3V1_K 8 9 11
VSSA
F8 VREFCP F1 VDD_VREFCP_K 4
VSSA
C1 VSS_VMOD1 V1V8 F5 PP1V8_S2 1 2 3 4 5 6 11 14 15 16 17

C2 VSS_VMOD1
A3 V3V3 C5 VDD_BBPMU_3V3_K 5
VSS_VMOD2
A6 VSS_VMOD3 VPMIC E5 VPMIC_K
H3 VSS_VMOD4
VOTP E6 VOTP_K
D6 VSS_CHP VPMICREF G5 VPMICREF_K

B 1 C508_K 1 C516_K 1 C518_K 1 C519_K 1 C520_K 1 C521_K 1 C523_K 1 C509_K 1 C522_K B


0.22UF 1UF 2.2UF 1UF 10UF 10UF 0.47UF 0.47UF 4.7UF
20% 20% 20% 20% 20% 20% 20% 20% 20%
6.3V
2 X5R 10V
2 X5R 6.3V
2 X5R-CERM 10V
2 X5R 10V
2 X5R-CERM 10V
2 X5R-CERM 6.3V
2 X5R 6.3V
2 X5R 10V
2 X5R
5 BBPMU_AGND_K 01005 0201 0402 0201 0402-0.1MM 0402-0.1MM 01005 01005 0402-1
BBPMU BBPMU BBPMU BBPMU BBPMU BBPMU
BBPMU.G5 BBPMU.F1
16 15 8 7 6 5 1 PP_VDD_MAIN PP1V8_S2 1 2 3 4 5 6 11 14 15 16 17

1 C511_K 1 C512_K 1 C513_K 1 C503_K 1 C504_K 1 C505_K 1 C506_K 1 C507_K


100PF 27PF 15UF 15UF 15UF 15UF 15UF 15UF
5% 5% 20% 20% 20% 20% 20% 20%
16V
2 NP0-C0G 16V
2 NP0-C0G 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM 6.3V
2 CERM
01005 01005 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM 0402-0.1MM
BBPMU BBPMU
BBPMU.H1 BBPMU.A8 BBPMU.A1 BBPMU.B4 BBPMU.E2

XW501_K
SHORT-20L-0.05MM-SM
6 5 4 VDD_CORE_1V0_K 1 2 VMOD1_FB_K 5

OMIT
XW502_K
SHORT-20L-0.05MM-SM
6 5 VRF_CORE_1V0_K 1 2 VMOD2_FB_K 5

OMIT
XW503_K
SHORT-20L-0.05MM-SM
6 5 VRF_ANA_1V3_K 1 2 VMOD3_FB_K 5

OMIT
XW504_K
SHORT-20L-0.05MM-SM
5 4 VDD_IO_1V2_K 1 2 VMOD4_FB_K 5

A OMIT
A
1 C500_K 1 C501_K 1 C502_K 1 C514_K 1 C515_K PAGE TITLE

20UF
20%
6.3V
20UF
20%
6.3V
20UF
20%
6.3V
20UF
20%
6.3V
20UF
20%
6.3V
BASEBAND PMIC
2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R 2 CERM-X5R DRAWING NUMBER SIZE
0402
BBPMU
0402
BBPMU
0402
BBPMU
0402
BBPMU
0402
BBPMU 051-02247 D
Apple Inc. REVISION

7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
5 OF 17
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
IV ALL RIGHTS RESERVED 17 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

TRANSCEIVERS XCVR0_K
PMB5757
UFWLB
SYM 5 OF 5
LAYOUT: TRACE SHOULD B1 ~1NH/1MM B3 VSS VSS U16
XW600_K LAYOUT: TRACE SHOULD B1 ~1NH/1MM B9 VSS VSS U6
SHORT-10L-0.25MM-SM
R615_K
0.00 2 C12 VSS VSS U8
VRF_ANA_1V3_K 1 2 6 VDD_XCVR0_1V3_K VRF_ANA_1V3_K 1 6 VDD_XCVR1_1V3_K
6 5 6 5
C16 VSS VSS V3
OMIT 0% C2
1 C645_K 1 C604_K 1 C609_K 1 C613_K 1 C614_K 1 C615_K 1 C616_K 1 C617_K 1 C619_K 1 C620_K 1 C5945_K 1/32W 1 C623_K 1 C628_K 1 C632_K 1 C633_K 1 C634_K 1 C635_K 1 C636_K 1 C637_K 1 C638_K VSS
MF
0.1UF 15UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.22UF 27PF 15UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.1UF 0.22UF C4
D 10%
6.3V
2 CER-X5R
20%
6.3V
2 CERM 6.3V
20%
2 X5R-CERM 6.3V
20%
2 X5R-CERM
20%
6.3V
2 X5R-CERM
20%
6.3V
2 X5R-CERM
20%
6.3V
2 X5R-CERM
20%
6.3V
2 X5R-CERM 6.3V
20%
2 X5R-CERM 6.3V
2 X5R
20% 5%
16V
2 NP0-C0G
01005
XCVR 20%
6.3V
2 CERM 6.3V
20%
2 X5R-CERM
20%
6.3V
2 X5R-CERM
20%
6.3V
2 X5R-CERM 6.3V
20%
2 X5R-CERM
20%
6.3V
2 X5R-CERM
20%
6.3V
2 X5R-CERM
20%
6.3V
2 X5R-CERM 6.3V
2 X5R
20%
C8
VSS
VSS
D
01005 0402-0.1MM 01005 01005 01005 01005 01005 01005 01005 01005 01005 0402-0.1MM 01005 01005 01005 01005 01005 01005 01005 01005 D3 VSS
XCVR XCVR XCVR XCVR XCVR XCVR XCVR XCVR XCVR XCVR XCVR XCVR XCVR XCVR XCVR XCVR
NOSTUFF F15 VSS
F3 VSS
F5 VSS
XCVR0_K XCVR1_K F9 VSS
VDD_CORE_1V0_K L10 PMB5757 VDD_CORE_1V0_K L10 PMB5757 H11
6 VDD0V68_RET UFWLB 6 VDD0V68_RET UFWLB VSS
R614_K LAYOUT: MAX DCR 85MOHM R616_K H15
LAYOUT: MAX DCR 85MOHM L14 SYM 1 OF 5 L14 SYM 1 OF 5 VSS
1
0.00 2 6 VDD_XCVR0_1V3_K VDD1V3_MPHY
1
0.00 2 6 VDD_XCVR1_1V3_K VDD1V3_MPHY H3
6 5 VRF_CORE_1V0_K

0%
1
VRF_XCVR0_1V0_K
1
6
E14
H9
VDD1V3_CI SMARTI6T 6 5 VRF_CORE_1V0_K
0%
1
VRF_XCVR1_1V0_K
1
6
E14
H9
VDD1V3_CI SMARTI6T H5
VSS
VSS
1/32W
MF
C605_K C610_K VDD1V3_TXPLL 1/32W
MF
C624_K C629_K VDD1V3_TXPLL H7
0.47UF 0.1UF N6 0.47UF 0.1UF N6 VSS
01005 VDD1V3_RX1PLL 01005 VDD1V3_RX1PLL
XCVR 20% 20% XCVR 20% 20% J4 VSS
6.3V
2 X5R 6.3V
2 X5R-CERM N14 VDD1V3_RX2PLL 6.3V
2 X5R 6.3V
2 X5R-CERM N14 VDD1V3_RX2PLL K3 VSS
01005 01005 K7 VDD1V3_RXMS 01005 01005 K7 VDD1V3_RXMS
XCVR XCVR XCVR XCVR L12 VSS
NOSTUFF NOSTUFF
C6 VDD1V3_TXDIG FL600_K C6 VDD1V3_TXDIG L4 VSS
FL601_K B1 600-OHM-25%-0.1A B1 L8
600-OHM-25%-0.1A VDD1V3_TXRF VDD1V3_TXRF VSS
PP1V8_S2 1 2 VDD_XCVR1_1V8_K M13 VSS
PP1V8_S2 1 2 VDD_XCVR0_1V8_K R14 VDD1V3_RX2DCO
17 16 15 14 11 6 5 4 3 2 1 6
R14 VDD1V3_RX2DCO
14 11 6 5 4 3 2
17 16
1
15
6
0201-1 M15 VSS
0201-1 XCVR
XCVR 1 C606_K 1 C612_K N4 VDD1V3_RX1DCO 1 C625_K 1 C630_K N4 VDD1V3_RX1DCO M3 VSS
15UF 0.1UF 15UF 0.1UF P13 VSS
20% 20% D7 VDD1V3_TXDCO 20% 20% D7 VDD1V3_TXDCO
6.3V
2 CERM 6.3V
2 X5R-CERM 6.3V
2 CERM 6.3V
2 X5R-CERM P3 VSS
0402-0.1MM 01005 U4 VDD1V3_RXRF 0402-0.1MM 01005 U4 VDD1V3_RXRF R10 VSS
XCVR XCVR
R12 VSS
C14 VDD1V3_TXMS C14 VDD1V3_TXMS
R604_K R607_K R6 VSS
1
0.00 2 K15 1
0.00 2 K15 R8
6 5 1 PP_VDD_MAIN VDD_XCVR0_BAT_K 6 6 VRF_XCVR0_1V0_K VDD1V0_DIG 16 15 8 7 6 5 1 PP_VDD_MAIN VDD_XCVR1_BAT_K 6 6 VRF_XCVR1_1V0_K VDD1V0_DIG VSS
16 15 8 7
0% 0% T13 VSS
1 C602_K 1 C603_K 1/32W 1 C607_K 1 C611_K VDD_XCVR0_1V8_K G14 VDD1V8_CI 1 C621_K 1 C622_K 1/32W 1 C626_K 1 C631_K VDD_XCVR1_1V8_K G14 VDD1V8_CI
C 5%
100PF
5%
27PF MF
01005 0.47UF
20%
0.1UF
20%
6

T9 VDD1V8_RX 5%
100PF
5%
MF
27PF 01005 0.47UF
20%
0.1UF
20%
6

T9 VDD1V8_RX
T3
T5
VSS C
16V 16V XCVR 6.3V 6.3V D5 16V 16V XCVR 6.3V 6.3V D5 VSS
2 NP0-C0G 2 NP0-C0G 2 X5R 2 X5R-CERM VDD1V8_TX 2 NP0-C0G 2 NP0-C0G 2 X5R 2 X5R-CERM VDD1V8_TX U10
01005 01005 01005 01005 01005 01005 01005 01005 VSS
XCVR XCVR XCVR XCVR 6 VDD_XCVR0_BAT_K D13 VDD_BAT XCVR XCVR XCVR XCVR 6 VDD_XCVR1_BAT_K D13 VDD_BAT U12 VSS
NOSTUFF NOSTUFF
U14 VSS
CEXT0_RX2PLL_K N12 CEXT_RX2PLL CELL_CLK_EN J12 SYSCLK_26MHZ_EN_K 14 CEXT1_RX2PLL_K N12 CEXT_RX2PLL CELL_CLK_EN J12
IN
J8 XCVR
CEXT0_TXPLL_K CEXT_TXPLL CELL_CLK J14 SYSCLK_26MHZ_K OUT 14 28 CEXT1_TXPLL_K J8 CEXT_TXPLL CELL_CLK J14 NC
CEXT0_RX1PLL_K P7 CEXT_RX1PLL CEXT1_RX1PLL_K P7 CEXT_RX1PLL
CEXT0_TXMAG_K B5 CEXT_TXMAG CEXT1_TXMAG_K B5 CEXT_TXMAG XCVR1_K
PMB5757
28 BB_TO_NFC_CLK F13 FSYS_RF GPO0 J6 F13 FSYS_RF GPO0 J6 XCVR1_RFE_GPO0_K UFWLB
1 C639_K 1 C640_K 1 C641_K 1 C608_K
13 12 OUT NC C642_K C643_K C644_K 1 C627_K NC OUT 20
SYM 5 OF 5
NFC_TO_BB_CLK_REQ M11 FSYS_RF_EN_CLK_ON GPO1 K5 XCVR1_26MHZ_EN_K M11 FSYS_RF_EN_CLK_ON GPO1 K5
0.022UF 0.022UF 0.022UF 1UF 18 13 12 IN NC 0.022UF 0.022UF 0.022UF 1UF 6
NC B3 VSS VSS U16
10% 10% 10% 20% XCVR1_26MHZ_K G12 FSYS_C GPO2 L6 10% 10% 10% 20% GNSS_26MHZ_CLKOUT_K G12 FSYS_C GPO2 L6
10V
2 X5R 10V
2 X5R 10V
2 X5R 10V
2 X5R
6
NC 10V 10V 10V 10V
2 X5R
28 27 OUT NC B9 VSS VSS U6
XCVR1_26MHZ_EN_K E12 FSYS_C_EN GPO3 P11 XCVR0_TSYNC_OUT_K X5R X5R X5R E12 FSYS_C_EN GPO3 P11 XCVR0_TSYNC_IN_K
0201 0201 0201 0201 6 6
0201 0201 0201 0201 6
C12 VSS VSS U8
XCVR GPO4 N10 XCVR0_TSYNC_IN_K XCVR GPO4 N10 XCVR0_TSYNC_OUT_K
6 6
C16 VSS VSS V3
DIGRF_M0_EN_K F11 MPHY_EN GPO5 T7 XCVR0_MSYNC_OUT_K DIGRF_M1_EN_K F11 MPHY_EN GPO5 T7 XCVR0_MSYNC_IN_K
14 IN 6 14 IN 6
C2 VSS
DIGRF_A0_EN_K K11 MPHY2_EN GPO6 T11 XCVR0_MSYNC_IN_K DIGRF_A1_EN_K K11 MPHY2_EN GPO6 T11 XCVR0_MSYNC_OUT_K
14 IN 6 14 IN 6
C4 VSS
BBPMU_PWRGOOD_K K13 RESET_MAIN* BBPMU_PWRGOOD_K K13 RESET_MAIN*
28 18 17 15 IN 28 18 17 15 IN C8 VSS
XCVR0_RESET_L_K H13 RESET_TRX* XCVR1_RESET_L_K H13 RESET_TRX*
15 IN 15 IN D3 VSS
F15 VSS
6 XCVR0_JTAG_TMS_K K9 TMSC MI3 C10 NC 6 XCVR1_JTAG_TMS_K K9 TMSC MI3 C10 NC
F3 VSS
6 XCVR0_JTAG_TCK_K J10 TCKC MI4 D11 NC 6 XCVR1_JTAG_TCK_K J10 TCKC MI4 D11 NC
F5 VSS
F9 VSS
14 90_DIGRF_M0_RX1_P_K G16 MPHY_RX1_DAT 14 90_DIGRF_M1_RX1_P_K G16 MPHY_RX1_DAT H11 VSS
OUT OUT
14 90_DIGRF_M0_RX1_N_K H17 MPHY_RX1_DATX 14 90_DIGRF_M1_RX1_N_K H17 MPHY_RX1_DATX H15 VSS
OUT OUT
14 90_DIGRF_M0_RX2_P_K E16 MPHY_RX2_DAT 14 90_DIGRF_M1_RX2_P_K E16 MPHY_RX2_DAT H3 VSS
OUT OUT
B 14 OUT
90_DIGRF_M0_RX2_N_K F17 MPHY_RX2_DATX 14 OUT
90_DIGRF_M1_RX2_N_K F17 MPHY_RX2_DATX H5 VSS B
28 14 90_DIGRF_M0_TX_P_K J16 MPHY_TX_DAT RFFE_SDATA P9 RFFE1_DATA_K 18 19 20 21 23 24 28 28 14 90_DIGRF_M1_TX_P_K J16 MPHY_TX_DAT RFFE_SDATA P9 RFFE1_DATA_K 18 19 20 21 23
H7 VSS
IN BI IN BI 24 28
28 14 90_DIGRF_M0_TX_N_K K17 MPHY_TX_DATX RFFE_SCLK N8 RFFE1_CLK_K 18 19 20 21 23 24 28 28 14 90_DIGRF_M1_TX_N_K K17 MPHY_TX_DATX RFFE_SCLK N8 RFFE1_CLK_K 18 19 20 21 23
J4 VSS
IN OUT IN OUT 24 28

P17 RFFE_VIO M9 VDD_RFFE_VIO_1V8_K OUT 18 19 20 21 23 24 25 28


P17 RFFE_VIO M9 VDD_RFFE_VIO_1V8_K OUT 18 19 20 21 23
K3 VSS
90_DIGRF_A0_RX1_P_K MPHY2_RX1_DAT 90_DIGRF_A1_RX1_P_K MPHY2_RX1_DAT 24 25 28
14 OUT 28 14 OUT L12 VSS
90_DIGRF_A0_RX1_N_K N16 MPHY2_RX1_DATX RFFE2_SCLK M7 RFFE2_CLK_R_K 90_DIGRF_A1_RX1_N_K N16 MPHY2_RX1_DATX RFFE2_SCLK M7 RFFE2_CLK_R_K
14 OUT 6 16 28 14 OUT 6 16
L4 VSS
90_DIGRF_A0_RX2_P_K T17 MPHY2_RX2_DAT RFFE2_SDATA M5 RFFE2_DATA_R_K 90_DIGRF_A1_RX2_P_K T17 MPHY2_RX2_DAT RFFE2_SDATA M5 RFFE2_DATA_R_K
14 OUT 6 16 14 OUT 6 16
L8 VSS
90_DIGRF_A0_RX2_N_K R16 MPHY2_RX2_DATX 90_DIGRF_A1_RX2_N_K R16 MPHY2_RX2_DATX
14 OUT 14 OUT M13 VSS
90_DIGRF_A0_TX_P_K M17 MPHY2_TX_DAT XO_SUP D17 XO_SUP_K 90_DIGRF_A1_TX_P_K M17 MPHY2_TX_DAT XO_SUP D17
14 IN 6 14 IN NC M15 VSS
14 IN
90_DIGRF_A0_TX_N_K L16 MPHY2_TX_DATX AFCDAC D15 AFC_DAC_K 6 14 IN
90_DIGRF_A1_TX_N_K L16 MPHY2_TX_DATX AFCDAC D15 NC M3 VSS
XO B17 VCXO_26MHZ_K 6 XO B17 XCVR1_26MHZ_K 6
P13 VSS
P3 VSS
XCVR XCVR R10 VSS
R12

VDD_XCVR1_1V8_K 6
VCTCXO
R605_K
0.00 2
16 6 RFFE2_CLK_R_K 1
R609_K
0.00 2
RFFE2_CLK_K OUT 25
R6
R8
T13
T3
VSS
VSS
VSS
VSS
VSS
VDD_XCVR0_1V8_K XO_SUP_K 1 XO_SUP_R_K 0%
6 6
1/32W T5 VSS
0% MF
1 1 1/32W 1 C601_K 01005 VDD_CORE_1V0_K VDD_CORE_1V0_K U10 VSS
R600_K R602_K MF
6 5 4 6

27K 27K 01005 4700PF U12 VSS


5% 5% XCVR 10%
1/32W 1/32W 6.3V
2 X5R 1 C649_K U14 VSS
MF MF R610_K
01005 0.00 2 0.1UF
2 01005
XCVR 2 01005
XCVR XCVR RFFE2_DATA_R_K 1 RFFE2_DATA_K 20% XCVR
16 6 BI 25
6.3V
4

2 X5R-CERM
VCC 0% 01005
XCVR0_JTAG_TMS_K 6 1/32W
MF
XCVR1_JTAG_TMS_K VTCXO_K 01005
A XCVR0_JTAG_TCK_K
6

6
26MHZ-6PPM-1.8V
1P6X1P2-SM A
XCVR1_JTAG_TCK_K PAGE TITLE
6
1 3
1 1
R601_K R603_K
6 AFC_DAC_K VCONT OUT
VCXO_26MHZ_K 6

NFC_TO_BB_CLK_REQ 1 6 6 5 4 VDD_CORE_1V0_K VDD_CORE_1V0_K 6


TRANSCEIVERS
DRAWING NUMBER SIZE
562K 562K 1 C600_K GND
1% 1% XCVR 1
R606_K 051-02247 D
2

0.022UF 1
1/32W
MF
1/32W
MF 10%
6.3V 100K
C650_K
0.1UF
Apple Inc. REVISION
2 01005 2 01005 2 X6S 1%
XCVR XCVR 0201-1 1/32W
MF
20%
6.3V
2 X5R-CERM
7.0.0
2 01005 01005 NOTICE OF PROPRIETARY PROPERTY: BRANCH
XCVR
THE INFORMATION CONTAINED HEREIN IS THE
PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE

NOTE: GNSS_CLK REQUESTED WITH AT@CMD I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE


II NOT TO REPRODUCE OR COPY IT
6 OF 17
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST IV ALL RIGHTS RESERVED 18 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

ET MODULATOR

D D

ALPES II MODULE
XW701_K
SHORT-10L-0.25MM-SM
16 15 8 6 5 1 PP_VDD_MAIN 1 2 PP_VDD_MAIN_ET_K VPA_ET_K 8 9

OMIT
ET 1 1 1 1
C720_K C721_K C722_K C723_K
2.2UF 1000PF 100PF 27PF
20% 10% 5% 5%
6.3V
2 X5R-CERM 10V
2 X5R 16V
2 NP0-C0G 16V
2 NP0-C0G
0201 01005 01005 01005
C ET
OMIT_TABLE
ET ET ET C

VCC2 26
PVDD 3
ET_K
QM81004M
16 8 50_ET_DAC_N_K 8 VRAMP- LGA
16 8 50_ET_DAC_P_K 7 VRAMP+

16 13 12 11 9 8 6 VDD_RFFE_VIO_1V8_K 15 VIO
16 12 11 9 8 6 RFFE1_DATA_K 17 DATA
16 12 11 9 8 6 RFFE1_CLK_K 16 CLK

THERM
PAD
GND

1
2
4
5
6
9
10
11
12
13
14
18
19

22
23

27
28
29
30
31
32
20
21

24
25
USID=0XC
B B

A A
PAGE TITLE

ET MODULATOR
DRAWING NUMBER SIZE

051-02247 D
Apple Inc. REVISION

7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
7 OF 17
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
IV ALL RIGHTS RESERVED 19 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

TDD TRANSMIT XW800_K


SHORT-10L-0.25MM-SM
2G PA
28 27 19 18 17 13 12 PP_VDD_MAIN 1 2 PP_VDD_MAIN_2G_K
IN
OMIT
1 C803_K 1 C805_K 1 C807_K 1 C808_K 1 C800_K
15UF 100PF 3300PF 18PF 0.1UF
20% 5% 10% 2% 20%
6.3V
2 CERM 16V
2 NP0-C0G 6.3V
2 X5R 16V
2 CERM 6.3V
2 X5R-CERM
0402-0.1MM 01005 01005 01005 01005
RFFE RFFE RFFE RFFE

D D
L800_K
3.0NH+/-0.1NH-0.6A

11
1 2

4
50_2GMB_PA_OUT_K OUT 21 1710-1910
VBATT VCC 0201
RFFE
GSMPA_K 1 C811_K
SKY77367 0.5PF
LGA +/-0.05PF

XCVR0 TX 8 50_XCVR0_2GLB_TX_K 9 RFIN_LB_0 25V


2 COG-CERM
0201
10 RFIN_LB_1 RFFE
NC NOSTUFF
15 RFIN_MB_1 RFOUT_MB 8 50_2GMB_PA_OUT_M_K
NC
50_XCVR0_2GMB_TX_K 16 RFIN_MB_0 RFOUT_LB 1 50_2GLB_PA_OUT_M_K
XCVR0_K 8

PMB5757 R801_K
UFWLB 1
0.00 2 14 VIO
28 25 24 23 21 20 19 18 IN
VDD_RFFE_VIO_1V8_K VDD_RFFE_VIO_1V8_2G_K
SYM 3 OF 5 12 SDATA
0% RFFE1_DATA_K
PADACFN A12
28 24 23 21 20 19 18 BI
50_ET_DAC_N_K 1/32W
OUT 19 20 28
MF RFFE1_CLK_K 13 SCLK
PADACFP B13
28 24 23 21 20 19 18 IN
50_ET_DAC_P_K OUT 19 20 28 01005
GND
EPAD L803_K
1C801_K 1 C815_K 0.00 2
1

2
3
5
6
7

17
50_2GLB_PA_OUT_K 824- 915
B11 0.033UF 18PF OUT
TX2GHB
TX2GLB B7
50_XCVR0_2GMB_TX_K
50_XCVR0_2GLB_TX_K
8

8
1710-1910
824- 915
20%
6.3V
2 CER-X5R
2%
16V
2 CERM
USID=0X5 NOSTUFF
0%
1/32W
MF
TX25 A4 01005 01005 1 C812_K 01005
NC
TX35 A2 3900PF
NC 10%
TXH A10 50_XCVR0_B3_B4_B1_B25_TX_K 21 1710-1980 6.3V
2 CERM-X5R
OUT
TXL A8 50_XCVR0_LB_TX_K 21 699- 915 01005
OUT

C XCVR
C

MB HB TDD S-PAD
9 7 VPA_ET_K VDD_RFFE_VIO_1V8_K IN 18 19 20 21 23 24 25 28

XCVR1 TX 11 9 8 5 VFE_AUX_3V1_K
1 C804_K
0.1UF
20%
1 C806_K
18PF
2%
1 C809_K
5.6PF
+/-0.1PF
16V
2 NP0-C0G
01005
1C810_K
18PF
2%
16V
2 CERM
01005
RFFE
RFFE1_DATA_K
RFFE1_CLK_K IN
BI 18 19 20 21 23

18 19 20 21 23
24

24
28

28

XCVR1_K 6.3V
2 X5R-CERM 16V
2 CERM

VBATT 11

VIO 14

SDATA 12

SCLK 13
PMB5757

VCC1 8

VCC2 9
01005 01005
UFWLB RFFE RFFE
SYM 3 OF 5 11 9 8 5 VFE_AUX_3V1_K
PADACFN A12 50_ET_DAC_N_K OUT 19 20 28

PADACFP B13 50_ET_DAC_P_K OUT 19 20 28

B TDDPA_K B
3

50_XCVR1_B34_B39_TX_K 3 RFIN_MB MB-HB-TDD-PAD


VDD 8

TX2GHB B11 LGA-3 R800_K


NC SWTX1_K 50_XCVR1_B38_B40_B41_TX_K 5 RFIN_HB 0.00 2
TX2GLB B7 CXA4430GC-E
8
ANT 16 50_TDD_PAD_ANT_M_K 1 50_TDD_PAD_ANT_K
NC OUT 21

TX25 A4 50_XCVR1_2P5G_TX_K 2 RFIN LGA RF1 4 50_XCVR1_B7_B30_TX_K 21 2305-2570 1%


OUT 1
A2 C813_K 1/20W
TX35 NC RF2 6 50_XCVR1_B38_B40_B41_TX_K 8 2300-2690 0.5PF MF
0201
TXH A10 50_XCVR1_B34_B39_TX_K 1880-2025 XCVR1_RFE_GPO0_K 1 CTRL +/-0.05PF
8 18 IN 25V
2 COG-CERM
TXL A8 50_XCVR1_LB_TX_K 699- 915
OUT 21
0 RFIN<->RF1 GND 0201
XCVR NOSTUFF
XCVR 1 RFIN<->RF2
5

22 50_XCVR1_B38_B40_B41_RX_K 27 RX_B38_B40_B41
OUT

22 50_XCVR1_B34_B39_RX_K 25 RX_B34_B39
OUT

GND THRM_PAD

1
2
4
6
7
10
15
17
19
21
22
24
26
28
23
20
18

29
30
31
32
33
34
35
36
37
38
39
40
41
42
43
USID=0XF

A A
PAGE TITLE

TDD TRANSMIT
DRAWING NUMBER SIZE

051-02247 D
Apple Inc. REVISION

7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
8 OF 17
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
IV ALL RIGHTS RESERVED 20 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

FDD TRANSMIT
9 8 7 VPA_ET_K
VDD_RFFE_VIO_1V8_K IN 18 19 20 21 23 24 25 28
11 9 8 5 VFE_AUX_3V1_K 1 C900_K 1 C906_K RFFE1_DATA_K
18PF 22PF BI 18 19 20 21 23 24 28

1 C903_K 1 C904_K 2% 5% RFFE1_CLK_K


16V
2 CERM 16V
2 CERM
IN 18 19 20 21 23 24 28

0.1UF 18PF
20% 2% 01005 01005-1
6.3V
2 X5R-CERM 16V
2 CERM
01005 01005
D D

VCC1 41

VCC2 40

VIO 10
RFFE RFFE

VBATT 7

SDATA 8

SCLK 9
LBPA_K
2 L901_K
20 IN
50_XCVR0_LB_TX_K RFIN0 QM76041 0.6NH-+/-0.1NH-0.73A-0.1OHM
3 LGA 1 2
20 IN
50_XCVR1_LB_TX_K RFIN1 50_LAT_LB_M_K 50_LAT_LB_K BI 23 824-915
01005
20 50_2GLB_PA_OUT_K 18 2G_TX
IN 1

24

22
OUT

OUT
50_LB_DRX_K

50_XCVR0_LB_RX_K
12

26
LB_DIV

LB_RX0
LB S-PAD ANT1 16

ANT2 14
C902_K
0.8PF
+/-0.05PF
16V
2 C0G-CERM
01005

22 50_XCVR1_LB_RX_K 25 LB_RX1
OUT

22 50_XCVR0_VLB_RX_K 24 VLB_RX0 L903_K


OUT
1.1NH-+/-0.1NH-0.85A
22 50_XCVR1_VLB_RX_K 23 VLB_RX1
OUT 1 2
50_UAT_LB_M_K 50_UAT_LB_K BI 23 824-915
01005
RFFE
GND THRM_PAD
1 C909_K
1.6PF

1
4
5
6
11
13
15
17
19
20
21
22
27
28
29
30
31
32
33
34
35
36
37
38
39
42

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
+/-0.1PF
16V
2 NP0-C0G
01005
USID=0XD RFFE
NOSTUFF

C C

9 8 7 VPA_ET_K

11 9 8 5 VFE_AUX_3V1_K 1 C907_K 1 C905_K


22PF 22PF
2% 5%
16V
2 CERM 16V
2 CERM VDD_RFFE_VIO_1V8_K 18 19 20 21 23 24 25 28
IN
01005 01005-1 RFFE1_DATA_K 18 19 20 21 23 24 28
BI
RFFE1_CLK_K IN 18 19 20 21 23 24 28

B B
29

37

38

26

28

27
VBATT

VCC1

VCC2

VIO

SDATA

SCLK
20 50_2GMB_PA_OUT_K 34 RFIN_GSM
IN
20 IN
50_XCVR0_B3_B4_B1_B25_TX_K 31 RFIN_MB C901_K
50_XCVR1_B7_B30_TX_K 32 MHBPA_K 5.0PF
20 IN RFIN_HB 1 2
50_LAT_MB_HB_M_K 50_LAT_MB_HB_K
AFEM-8056-AP1 BI 23

LGA 1 +/-0.1PF 1710-2690


20 50_TDD_PAD_ANT_K 7 TRX2 25V
IN C0G
22 50_XCVR1_B40B_NO_FILT_RX_K 8 TRX3 0201
OUT RFFE
L900_K
ANT1 14 10NH-3%-0.3A
24 50_LAT_MB_HB_DRX_K 10 MB_HB_DRX 0201
OUT
11 RFFE
22 OUT
50_XCVR0_2G_RX_K DCS_PCS_RX
ANT2 13 2
22 50_XCVR0_B1_B4_RX_K 1 RX_B1
OUT
22

22

22

22
OUT

OUT

OUT

OUT
50_XCVR0_B3_RX_K
50_XCVR1_B7_RX_K
50_XCVR0_B4_B66_RX_K
50_XCVR0_B25_RX_K
3 RX_B3
5 RX_B7
17 RX_B66
19 RX_B25
MB/HB S-PAD 50_UAT_MB_HB_M_K
L902_K
1.0NH-+/-0.1NH-0.9A-0.05OHM
1
01005
2 50_UAT_MB_HB_K BI 23 1710-2690

22 50_XCVR1_B30_RX_K 21 RX_B30 1 C908_K


OUT
1.0PF
GND EPAD +/-0.1PF
16V
2 NP0-C0G
01005
2
4
12
15
16
18
20
22
23
24
25
30
33
35
36
39
40
41
42
6
9

43
44
45
46
47
48
49
50
51
52
53
54
55
56
57
RFFE
NOSTUFF

A
USID=0XE
A
PAGE TITLE

FDD TRANSMIT
DRAWING NUMBER SIZE

051-02247 D
Apple Inc. REVISION

7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
9 OF 17
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
IV ALL RIGHTS RESERVED 21 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

PRIMARY RECIEVE
L1001_K
22NH-3%-0.14A-2.26OHM
10 50_XCVR0_VLB_RX_M_K 1 2 50_XCVR0_VLB_RX_K 21
IN
01005
XCVR L1016_K
15NH-3%-0.17A-1.53OHM

D 10 50_XCVR1_VLB_RX_M_K 1 2 50_XCVR1_VLB_RX_K IN 21 D
01005
L1030_K XCVR
10NH-+/-3%-0.25A
10 50_XCVR0_LB_RX_M_K 1 2 50_XCVR0_LB_RX_K 21
IN
01005
XCVR 1

L1008_K
9.1NH-3%-0.17A-1.7OHM L1000_K
01005 8.2NH-3%-0.3A-0.5OHM
XCVR
NOSTUFF 1 2
10 50_XCVR1_LB_RX_M_K 50_XCVR1_LB_RX_K IN 21
2 01005
XCVR 1

R1000_K
50_XCVR0_B1_B4_RX_M_K 1
0.00 2
50_XCVR0_B1_B4_RX_K
L1023_K
10 IN 21
18NH-3%-0.16A-1.63OHM

XCVR0 PRX
0%
1/32W
MF
01005
XCVR
1

L1027_K
XCVR1 PRX 2
01005
XCVR

3.3NH+/-0.1NH-180MA XCVR1_K L1017_K


XCVR0_K 01005 PMB5757 0.00
XCVR UFWLB 10 50_XCVR1_B30_RX_M_K 50_XCVR1_B30_RX_K IN 21
PMB5757 0%
UFWLB SYM 2 OF 5 1
2 1/32W
SYM 2 OF 5 FBRRF1 A16 50_XCVR1_LAT_CPLR_K IN 23 MF
01005
FBRRF1 A16 50_XCVR0_LAT_CPLR_K IN 23 FBRRF2 A14 50_XCVR1_UAT_CPLR_K IN 23
L1024_K
FBRRF2 A14 50_XCVR0_UAT_CPLR_K IN 23 L1003_K VSS B15 3.3NH-+/-0.1NH-0.4A-0.25OHM
VSS B15
3.9NH+/-0.1NH-180MA 01005
1 2 XCVR
50_XCVR0_B4_B66_RX_M_K 50_XCVR0_B4_B66_RX_K
C W2
10

01005
IN 21
RX1 W2
V1
50_XCVR1_B7_RX_M_K 10 2620-2690
2
C
RX1 50_XCVR0_B3_RX_M_K 10 1805-1880 XCVR RX2 50_XCVR1_B30_RX_M_K 10 2350-2360
V1 U2 L1018_K
RX2 50_XCVR0_GSM1900_RX_M_K 10 1930-1990 RX3 1.0NH+/-0.1NH-0.22A-0.9OHM
RX3 U2 1 L1009_K RX4 T1 50_XCVR1_B38_B40_B41_RX_M_K 10 2300-2690
50_XCVR1_B7_RX_M_K 1 2 50_XCVR1_B7_RX_K
RX4 T1 50_XCVR0_B4_B66_RX_M_K 10 2110-2155 1.6PF RX5 R2 50_XCVR1_LB_RX_M_K 10 852- 960
10 IN 21

+/-0.1PF 01005
RX5 R2 50_XCVR0_GSM1800_RX_M_K 1805-1880 2 16V RX6 P1 50_XCVR1_B40B_NO_FILT_RX_M_K 2300-2400 1
10
NP0-C0G 10

RX6 P1 50_XCVR0_B1_B4_RX_M_K 10 2110-2170 01005 RX7 N2


N2 XCVR M1
RX7 RX8 50_XCVR1_VLB_RX_M_K 10 717- 821 L1015_K
RX8 M1 50_XCVR0_B25_RX_M_K 10 1930-1995 RX9 L2 1.5NH+/-0.1NH-220MA
01005
RX9 L2 L1004_K RX10 K1 50_XCVR1_B34_B39_RX_M_K 10 1880-2025 XCVR
RX10 K1 50_XCVR0_VLB_RX_M_K 10 717- 821
1.2NH-+/-0.1NH-0.80A RX11 J2
J2 1 2 H1 2
RX11 10 50_XCVR0_B25_RX_M_K 50_XCVR0_B25_RX_K IN 21 RX12
RX12 H1 50_XCVR0_LB_RX_M_K 10 852- 960 01005 RX13 G2 L1019_K
XCVR 1 7PF
RX13 G2 RX14 F1
50_XCVR1_B38_B40_B41_RX_M_K 1 2 50_XCVR1_B38_B40_B41_RX_K
RX14 F1 RX15 E2 10 IN 20

E2 L1010_K D1 +/-0.1PF 1
RX15 2.4NH-+/-0.1NH-0.45A RX16 16V
RX16 D1 01005 NP0-C0G
XCVR XCVR 01005
XCVR L1025_K
XCVR 1.3NH-+/-0.1NH-0.7A-0.08OHM
2
01005-1
L1005_K XCVR
3.6NH+/-0.1NH-180MA
1 2 2
10 50_XCVR0_B3_RX_M_K 50_XCVR0_B3_RX_K IN 21

01005
XCVR 1 L1020_K
1
0.00 2
10 50_XCVR1_B34_B39_RX_M_K 50_XCVR1_B34_B39_RX_K IN 20

L1011_K 0%
1/32W 1
2.6NH-+/-0.1NH-0.45A-0.2OHM MF
B 01005
XCVR
NOSTUFF
01005
XCVR
L1026_K
B
2 3.6NH-+/-0.1NH-0.35A-0.3OHM
01005

L1021_K
2.4NH-+/-0.1NH-0.45A
10 50_XCVR1_B40B_NO_FILT_RX_M_K 1 2 50_XCVR1_B40B_NO_FILT_RX_K 21
IN
01005
1 C1001_K
2.0PF
+/-0.1PF
16V
2 NP0-C0G
GSMDI_K 01005
GSM1800-1900 XCVR
B8867
L1006_K LGA
0.6NH+/-0.1NH-320MA
10 50_XCVR0_GSM1800_RX_M_K 1 2 50_XCVR0_GSM1800_RX_K 4 GSM1800
01005
1 COMMON 1 50_XCVR0_2G_RX_K IN 21
XCVR 3 GSM1900
50_XCVR0_GSM1900_RX_K
1

L1012_K
3.0NH+/-0.1NH-200MA L1014_K
01005 GND
XCVR 3.6NH-+/-0.1NH-0.35A-0.3OHM
01005
2
5
6
2
L1007_K 2
1.3NH+/-0.1NH-220MA
A 10 50_XCVR0_GSM1900_RX_M_K 1
01005
2
A
1 PAGE TITLE

PRIMARY RECEIVE
L1013_K DRAWING NUMBER SIZE
3.0NH+/-0.1NH-200MA 051-02247 D
01005
XCVR Apple Inc. REVISION

2
7.0.0
NOTICE OF PROPRIETARY PROPERTY: BRANCH

THE INFORMATION CONTAINED HEREIN IS THE


PROPRIETARY PROPERTY OF APPLE INC.
evt-1
THE POSESSOR AGREES TO THE FOLLOWING: PAGE
I TO MAINTAIN THIS DOCUMENT IN CONFIDENCE
II NOT TO REPRODUCE OR COPY IT
10 OF 17
SHEET
III NOT TO REVEAL OR PUBLISH IT IN WHOLE OR PART
CONFIDENTIAL AND PROPRIETARY APPLE SYSTEM DESIGN. FOR REFERENCE PURPOSE ONLY - NOT A CHANGE REQUEST
IV ALL RIGHTS RESERVED 22 OF 34
8 7 6 5 4 3 2 1
8 7 6 5 4 3 2 1

LOWER ANTENNA AND COUPLER

D LOWER ANTENNA COUPLER D

LATDI_K
DPX202690DT-4090A2SJ 11 9 8 5 VFE_AUX_3V1_K
0805 R1100_K
1.8NH-+/-0.1NH-0.70A 1 C1105_K 1 C1107_K
21 BI
50_LAT_MB_HB_K 4 HI COM 2 50_LAT_LB_MB_HB_M_K 1 2 18PF 0.1UF
2% 20%
01005 16V
2 CERM 6.3V
2 X5R-CERM
50_LAT_LB_K 6 LO
21 BI 1 C1100_K 01005 01005
RFFE RFFE

9
GND 0.7PF
+/-0.05PF
16V VDD

1
3
5
2 NP0-C0G
01005 LATCP_K C1103_K
SKY16708-11 56PF
50_LAT_LB_MB_HB_K 1 RFIN1 LGA RFOUT1 2 50_LAT1_CPL_K 1 2 50_LAT1_ANT_K 29
OUT
13 RFIN2 RFOUT2 14
NC NC 5% 1
FL1100_K 25V
6 USID NP0-C0G-CERM
10-OHM-1.1A 01005
VDD_RFFE_VIO_1V8_K 1 2 VDD_RFFE_VIO_LATCP_1V8_K 5 4 50_XCVR0_LAT_CPLR_K
L1100_K
28 25 24 23 21 20 19 18 IN VIO RF_CPL1 OUT 22
56NH-100MA-3.9OHM
01005 28 24 23 21 20 19 18 RFFE1_DATA_K 12 SDATA RF_CPL2 16 50_XCVR1_LAT_CPLR_K 22 0201
BI OUT
8 UP_RFFE
28 24 23 21 20 19 18 IN
RFFE1_CLK_K SCLK
1 1 FOR ESD AND LOW FREQUENCY IMD
C1111_K C1109_K 2
0.033UF 5PF GND
20% +/-0.1PF
6.3V
2 CER-X5R 16V
2 NP0-C0G

3
7
10
11
15
01005 01005

C USID=0X6 C

UPPER ANTENNA COUPLER LAT TUNER GPO


FL1102_K
10-OHM-1.1A
17 16 15 14 6 5 4 3 2 1 PP1V8_S2 1 2 PP1V8_GPOLAT_K
11 9 8 5 VFE_AUX_3V1_K 01005
1 1 1
B 1 C1104_K 1 C1106_K
C1114_K
0.47UF
C1116_K
0.47UF
C1115_K
33PF B
20% 20% 5%
18PF 0.1UF 6.3V
2 X5R 6.3V
2 X5R 16V
2 NP0-C0G-CERM
2% 20%

9
16V
2 CERM 6.3V
2 X5R-CERM 01005 01005 01005
VDD 01005 01005
RFFE RFFE GPOLAT_K
UATCP_K R1101_K
SKY16708-11 0.00 2 QM18099
RFFE1_CLK_FILT_K 1 17 RFFE_GPOLAT_CLK_K WLCSP
50_UAT_MB_HB_K 1 RFIN1 LGA RFOUT1 2 50_UAT_MB_HB_TX_SOUTH_K
24 IN
21 BI IN 29
0% A3 VIO GPO1 A4 LAT_TUNER_GPO1_K
50_UAT_LB_K 13 RFIN2 RFOUT2 14 50_UAT_LB_SOUTH_K 1/32W OUT 29
21 BI BI 29
MF 1 C1102_K GPO2 B1 LAT_TUNER_GPO2_K
FL1101_K 01005 A1 SCLK
OUT 29

6 USID RFFE 33PF GPO3 B4 LAT_TUNER_GPO3_K


10-OHM-1.1A 5% OUT 29

16V
2 NP0-C0G-CERM A2 SDATA GPO4 C1 LAT_TUNER_GPO4_K
VDD_RFFE_VIO_1V8_K 1 2 VDD_RFFE_VIO_UATCP_1V8_K 5 VIO RF_CPL1 4 50_XCVR0_UAT_CPLR_K OUT 29
28 25 24 23 21 20 19 18 IN OUT 22
01005 GPO5 C2
01005 RFFE1_DATA_K 12 SDATA RF_CPL2 16 50_XCVR1_UAT_CPLR_K B2 USID1 NC
24 23 21 20 19 18 BI OUT 22
GPO6 C4
28
RFFE1_CLK_K 8 SCLK R1102_K NC
24 23 21 20 19 18
28
IN
0.00 2 GPO7 C3
24 RFFE1_DATA_FILT_K 1 17 RFFE_GPOLAT_DATA_K NC
BI
GND 0% GND
1 C1112_K 1 C1108_K 1/32W
MF
USID=0X8

B3
0.033UF 5PF 01005 1 C1101_K
3
7
10
11
15

20% +/-0.1PF RFFE


6.3V
2 CER-X5R 16V
2 NP0-C0G 33PF
5%
01005 01005 16V
2 NP0-C0G-CERM
USID=0X7 01005

A A
PAGE TITLE

LOWER ANTENNA & COUPLERS


DRAWING NUMBER SIZE

You might also like