Oscillator Frequency Upconverter

Data Sheet AD9552

FEATURES GENERAL DESCRIPTION
Converts a low frequency input reference signal to a high The AD9552 is a fractional-N phase locked loop (PLL) based
frequency output signal clock generator designed specifically to replace high frequency
Input frequencies from 6.6 MHz to 112.5 MHz crystal oscillators and resonators. The device employs a sigma-
Output frequencies up to 900 MHz delta (Σ-Δ) modulator (SDM) to accommodate fractional
Preset pin programmable frequency translation ratios frequency synthesis. The user supplies an input reference signal
Arbitrary frequency translation ratios via SPI port by connecting a single-ended clock signal directly to the REF
On-chip VCO pin or by connecting a crystal resonator across the XTAL pins.
Accepts a crystal resonator and/or an external oscillator
The AD9552 is pin programmable, providing one of 64 standard
as a reference frequency source
output frequencies based on one of eight common input
Secondary output (either integer-related to the primary
frequencies. The device also has a 3-wire SPI interface, enabling
output or a copy of the reference input)
the user to program custom input-to-output frequency ratios.
RMS jitter: <0.5 ps
SPI-compatible, 3-wire programming interface The AD9552 relies on an external capacitor to complete the loop
Single supply (3.3 V) filter of the PLL. The output is compatible with LVPECL, LVDS,
Very low power: <400 mW (under most conditions) or single-ended CMOS logic levels, although the AD9552 is
Small package size (5 mm × 5 mm) implemented in a strictly CMOS process.

APPLICATIONS The AD9552 is specified to operate over the extended industrial

temperature range of −40°C to +85°C.
Cost effective replacement of high frequency VCXO, OCXO,
and SAW resonators
Extremely flexible frequency translation with low jitter for
SONET/SDH (including FEC), 10 Gb Ethernet, Fibre
Channel, and DRFI/DOCSIS
High-definition video frequency translation
Wireless infrastructure
Test and measurement (including handheld devices)

BASIC BLOCK DIAGRAM

AD9552

INPUT OUT2
REF
FREQUENCY OUTPUT
PLL
SOURCE CIRCUITRY OUT1
XTAL SELECTOR

PIN-DEFINED AND SERIAL PROGRAMMING

07806-001

Figure 1.

Rev. E Document Feedback

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AD9552
TABLE OF CONTENTS
Features .............................................................................................. 1
Applications ....................................................................................... 1
General Description ......................................................................... 1
Basic Block Diagram ........................................................................ 1
Revision History ............................................................................... 2
Specifications..................................................................................... 3
Crystal Input Characteristics ...................................................... 4
Output Characteristics ................................................................. 4
Jitter Characteristics ..................................................................... 5
Serial Control Port ....................................................................... 6
Serial Control Port Timing ......................................................... 6
Absolute Maximum Ratings ............................................................ 7
ESD Caution .................................................................................. 7
Pin Configuration and Function Descriptions ............................. 8
Typical Performance Characteristics ............................................. 9
Input/Output Termination Recommendations .......................... 12
Theory of Operation ...................................................................... 13
REVISION HISTORY
11/12—Rev. D to Rev. E
Changes to Figure 2 ........................................................................... 8
Changes to Serial Control Port Section ........................................20
Changes to Table 17 .........................................................................24
Changes to Table 18 .........................................................................25
Updated Outline Dimensions (Changed CP-32-2 to CP-32-7) ...... 31
Changes to Ordering Guide ...........................................................31
7/11—Rev. C to Rev. D
Changes to Table 1, Reference Clock Input Characteristics,
Input High Voltage and Input Low Voltage Parameter Values ... 4
Changes to Table 8, Added Endnote for Pin 9 and Pin 10 .......... 8
Changes to Part Initialization Automatic Power-On Reset
Section, Second Paragraph ............................................................ 17
Changes to Thermal Performance Section , First Paragraph ... 19
Changes to Serial Port Control Section, First Paragraph .......... 20
Changes to Table 20, Added Endnote to Bit 2 Description ...... 27
Updated Outline Dimensions ....................................................... 31
7/10—Rev. B to Rev. C
Changed Crystal Load Capacitance to 15 pF............. Throughout
Added Conditions Statement to Specifications Section, Supply
Voltage Specifications, and Input Voltage Specifications ............ 3
Reformatted Specifications Section (Renumbered Sequentially)..... 3
Added Input/Output Termination Recommendations Section,
Figure 17, and Figure 18 (Renumbered Sequentially) ............... 13
Rev. E | Page 2 of 32
Data Sheet
Preset Frequency Ratios ............................................................ 13
Component Blocks ..................................................................... 15
Part Initialization and Automatic Power-On Reset ............... 17
Output/Input Frequency Relationship .................................... 17
Calculating Divider Values ....................................................... 17
Low Dropout (LDO) Regulators .............................................. 18
Applications Information .............................................................. 19
Thermal Performance ................................................................ 19
Serial Control Port ......................................................................... 20
Serial Control Port Pin Descriptions ....................................... 20
Operation of the Serial Control Port ....................................... 20
Instruction Word (16 Bits) ........................................................ 21
MSB/LSB First Transfers ........................................................... 21
Register Map ................................................................................... 23
Register Map Descriptions ........................................................ 24
Outline Dimensions ....................................................................... 30
Ordering Guide .......................................................................... 30
Moved Preset Frequency Ratios Section ..................................... 13
Changes to Component Blocks Section ...................................... 15
Added Part Initialization and Automatic Power-On
Reset Section ................................................................................... 17
4/10—Rev. A to Rev. B
Changes to Preset Frequency Ratios Section .............................. 12
Moved Table 15 and Changes to Table 15 ................................... 13
Changes to Figure 17...................................................................... 14
Changes to PLL Section, Output Dividers Section, and
Input-to-OUT2 Option Section ............................................... 15
Changes to Output/Input Frequency Relationship Section ...... 16
Changes to Table 22 ....................................................................... 23
Changes to Table 26 ....................................................................... 26
9/09—Rev. 0 to Rev. A
Changes to Table 4.............................................................................3
Changes to Table 5.............................................................................4
Added Table 6; Renumbered Sequentially .....................................4
Changes to Figure 5 ...........................................................................9
Changes to PLL Section ................................................................. 14
Changes to Table 22 ....................................................................... 21
Changes to Table 25 ....................................................................... 24
7/09—Revision 0: Initial Version
Data Sheet AD9552

SPECIFICATIONS
Minimum (min) and maximum (max) values apply for the full range of supply voltage and operating temperature variations. Typical (typ)
values apply for VDD = 3.3 V; TA = 25°C, unless otherwise noted.

Table 1.
Parameter Min Typ Max Unit Test Conditions/Comments
SUPPLY VOLTAGE 3.135 3.30 3.465 V Pin 7, Pin 18, Pin 21, Pin 28
POWER CONSUMPTION
Total Current 149 169 mA At maximum output frequency with both output channels active
VDD Current By Pin
Pin 7 2 3 mA
Pin 18 77 86 mA
Pin 21 35 41 mA
Pin 28 35 41 mA
LVPECL Output Driver 36 41 mA 900 MHz with 100 Ω termination between both pins of the output
driver
LOGIC INPUT PINS
INPUT CHARACTERISTICS 1
Logic 1 Voltage, VIH 1.0 V For the CMOS inputs, a static Logic 1 results from either a pull-up
resistor or no connection
Logic 0 Voltage, VIL 0.8 V
Logic 1 Current, IIH 3 µA
Logic 0 Current, IIL 17 µA
LOGIC OUTPUT PINS
Output Characteristics
Output Voltage High, VOH 2.7 V
Output Voltage Low, VOL 0.4 V
RESET PIN
Input Characteristics 2
Input Voltage High, VIH 1.8 V
Input Voltage Low, VIL 1.3 V
Input Current High, IINH 0.3 12.5 µA
Input Current Low, IINL 31 43 µA
Minimum Pulse Width High 2 ns
REFERENCE CLOCK
INPUT CHARACTERISTICS
Frequency Range 7.94 MHz N3 = 255; 2× frequency multiplier enabled; valid for all VCO bands
6.57 MHz N 3 = 255; 2× frequency multiplier enabled; fVCO = 3.35 GHz, which con-
strains the frequency at OUT1 to be an integer sub-multiple of 3.35 GHz
(that is, fOUT1 = 3.35 ÷ M GHz, where M is the product of the P0 and P1
output divider values)
93.06 MHz SDM4 disabled; N3 = 365; valid for all VCO bands
71.28 MHz SDM4 enabled; N3 = 476; valid for all VCO bands
112.5 MHz SDM 4 disabled; N3 = 36 5; fVCO = 4.05 GHz, which constrains the
frequency at OUT1 to be an integer sub-multiple of 4.05 GHz (that is,
fOUT1 = 4.05÷M GHz, where M is the product of the P0 and P1 output
divider values)
86.17 MHz SDM4 enabled; N3 = 47 6; fVCO = 4.05 GHz, which constrains the frequency
at OUT1 to be an integer sub-multiple of 4.05 GHz (that is, fOUT1 =
4.05÷M GHz, where M is the product of the P0 and P1 output divider
values)

Rev. E | Page 3 of 32
AD9552 Data Sheet
Parameter Min Typ Max Unit Test Conditions/Comments
Input Capacitance 3 pF
Input Resistance 130 kΩ
Duty Cycle 40 60 %
Input Voltage
Input High Voltage, VIH 1.62 V
Input Low Voltage, VIL 0.52 V
Input Threshold Voltage 1.0 V When ac coupling to the input receiver, the user must dc bias the input
to 1 V
VCO CHARACTERISTICS
Frequency Range
Upper Bound 4050 MHz
Lower Bound 3350 MHz
VCO Gain 45 MHz/V
VCO Tracking Range ±300 ppm
VCO Calibration Time 140 μs fPFD 7 = 77.76 MHz; time between completion of the VCO calibration
command (the rising edge of CS (Pin 12)) to the rising edge of LOCKED
(Pin 20).
1
The A[2:0], Y[5:0], and OUTSEL pins have 100 kΩ internal pull-up resistors.
2
The RESET pin has a 100 kΩ internal pull-up resistor, so the default state of the device is reset.
3
N is the integer part of the feedback divider.
4
Sigma-delta modulator.
5
The minimum allowable feedback divider value with the SDM disabled.
6
The minimum allowable feedback divider value with the SDM enabled.
7
The frequency at the input to the phase-frequency detector.

CRYSTAL INPUT CHARACTERISTICS

Table 2.
Parameter Min Typ Max Unit Test Conditions/Comments
CRYSTAL FREQUENCY
Range 10 26 52 MHz
Tolerance 20 ppm
CRYSTAL MOTIONAL RESISTANCE 100 Ω
CRYSTAL LOAD CAPACITANCE 15 pF Using a crystal with a specified load capacitance other than
15 pF (8 pF to 24 pF) is possible, but necessitates using the
SPI port to configure the AD9552 crystal input capacitance.

OUTPUT CHARACTERISTICS
Table 3.
Parameter Min Typ Max Unit Test Conditions/Comments
LVPECL MODE
Differential Output Voltage Swing 690 765 889 mV Output driver static
Common-Mode Output Voltage VDD − 1.77 VDD − 1.66 VDD − 1.20 V Output driver static
Frequency Range 0 900 MHz
Duty Cycle 40 60 % Up to 805 MHz output frequency
Rise/Fall Time 1 (20% to 80%) 255 305 ps 100 Ω termination between both pins of
the output driver

Rev. E | Page 4 of 32
Data Sheet AD9552
Parameter Min Typ Max Unit Test Conditions/Comments
LVDS MODE
Differential Output Voltage Swing
Balanced, VOD 247 454 mV Voltage swing between output pins;
output driver static
Unbalanced, ΔVOD 25 mV Absolute difference between voltage
swing of normal pin and inverted pin;
output driver static
Offset Voltage
Common Mode, VOS 1.125 1.375 V Output driver static
Common-Mode Difference, ΔVOS 25 mV Voltage difference between output pins;
output driver static
Short-Circuit Output Current 17 24 mA
Frequency Range 0 900 MHz
Duty Cycle 40 60 % Up to 805 MHz output frequency
Rise/Fall Time1 (20% to 80%) 285 355 ps 100 Ω termination between both pins of
the output driver
CMOS MODE
Output Voltage High, VOH Output driver static; standard drive
strength setting
IOH = 10 mA 2.8 V
IOH = 1 mA 2.8 V
Output Voltage Low, VOL Output driver static; standard drive
strength setting
IOL = 10 mA 0.5 V
IOL = 1 mA 0.3 V
Frequency Range 0 200 MHz 3.3 V CMOS; standard drive strength
setting
Duty Cycle 45 55 % At maximum output frequency
Rise/Fall Time1 (20% to 80%) 500 745 ps 3.3 V CMOS; standard drive strength
setting; 15 pF load
1
The listed values are for the slower edge (rise or fall).

JITTER CHARACTERISTICS
Table 4.
Parameter Min Typ Max Unit Test Conditions/Comments
JITTER GENERATION Input = 19.44 MHz crystal resonator
12 kHz to 20 MHz 0.64 ps rms fOUT = 622.08 MHz (integer mode)
0.70 ps rms fOUT = 625 MHz (fractional mode)
50 kHz to 80 MHz 0.47 ps rms fOUT = 622.08 MHz (integer mode)
0.50 ps rms fOUT = 625 MHz (fractional mode)
4 MHz to 80 MHz 0.11 ps rms fOUT = 622.08 MHz (integer mode)
0.12 ps rms fOUT = 625 MHz (fractional mode)
JITTER TRANSFER BANDWIDTH 100 kHz See the Typical Performance Characteristics section
JITTER TRANSFER PEAKING 0.3 dB See the Typical Performance Characteristics section

Rev. E | Page 5 of 32
AD9552 Data Sheet
SERIAL CONTROL PORT
Table 5.
Parameter Min Typ Max Unit Test Conditions/Comments
CS
Input Logic 1 Voltage 1.6 V
Input Logic 0 Voltage 0.5 V
Input Logic 1 Current 0.03 µA
Input Logic 0 Current 2 µA
Input Capacitance 2 pF
SCLK
Input Logic 1 Voltage 1.6 V
Input Logic 0 Voltage 0.5 V
Input Logic 1 Current 2 µA
Input Logic 0 Current 0.03 µA
Input Capacitance 2 pF
SDIO
Input
Input Logic 1 Voltage 1.6 V
Input Logic 0 Voltage 0.5 V
Input Logic 1 Current 1 µA
Input Logic 0 Current 1 µA
Input Capacitance 2 pF
Output
Output Logic 1 Voltage 2.8 V 1 mA load current
Output Logic 0 Voltage 0.3 V 1 mA load current

SERIAL CONTROL PORT TIMING

Table 6.
Parameter Limit Unit
SCLK
Clock Rate, 1/tCLK 50 MHz max
Pulse Width High, tHIGH 3 ns min
Pulse Width Low, tLOW 3 ns min
SDIO to SCLK Setup, tDS 4 ns min
SCLK to SDIO Hold, tDH 0 ns min
SCLK to Valid SDIO, tDV 13 ns max
CS to SCLK Setup (tS) and Hold (tH) 0 ns min
CS Minimum Pulse Width High 6.4 ns min

Rev. E | Page 6 of 32
Data Sheet AD9552

ABSOLUTE MAXIMUM RATINGS

Table 7. ESD CAUTION
Parameter Rating
Supply Voltage (VDD) 3.6 V
Maximum Digital Input Voltage −0.5 V to VDD + 0.5 V
Storage Temperature −65°C to +150°C
Operating Temperature Range −40°C to +85°C
Lead Temperature (Soldering, 10 sec) 300°C
Junction Temperature 150°C
Stresses above those listed under Absolute Maximum Ratings
may cause permanent damage to the device. This is a stress
rating only; functional operation of the device at these or any
other conditions above those indicated in the operational
section of this specification is not implied. Exposure to absolute
maximum rating conditions for extended periods may affect
device reliability.

Rev. E | Page 7 of 32
AD9552 Data Sheet

PIN CONFIGURATION AND FUNCTION DESCRIPTIONS

OUT1
OUT1
GND
VDD
Y3

Y1
Y0
Y2
32
31
30
29
28
27
26
25
Y4 1 24 GND
Y5 2 23 OUT2
A0 3 AD9552 22 OUT2
A1 4 21 VDD
A2 5 TOP VIEW 20 LOCKED
(Not to Scale)
RESET 6 19 LDO
VDD 7 18 VDD
LDO 8 17 LDO

11
10

12
13
14
15
16
OUTSEL
XTAL
XTAL

FILTER
SCLK
SDIO
REF
CS

07806-002
NOTES
1. EXPOSED DIE PAD MUST BE CONNECTED TO GND.

Figure 2. Pin Configuration

Table 8. Pin Function Descriptions

Pin No. Mnemonic Type 1 Description
29, 30, 31, Y0, Y1, Y2, Y3, Y4, I Control Pins. These pins select preset values for the PLL feedback divider and the OUT1
32, 1, 2 Y5 dividers based on the input reference frequency selected via the A[0:2] pins and have
internal 100 kΩ pull-up resistors.
3, 4, 5 A0, A1, A2 I Control Pins. These pins select the input reference frequency and have internal 100 kΩ pull-
up resistors.
6 RESET I Digital Input, Active High. Resets internal logic to default states. This pin has an internal
100 kΩ pull-up resistor, so the default state of the device is reset.
7, 18, 21, 28 VDD P Power Supply Connection: 3.3 V Analog Supply.
8, 17, 19 LDO P/O LDO Decoupling Pins. Connect a 0.47 μF decoupling capacitor from each of these pins to
ground.
9, 10 XTAL I Crystal Resonator Input. Connect a crystal resonator across these pins. 2
11 REF I Reference Clock Input. Connect this pin to an active clock input signal, or connect it to VDD
when using a crystal resonator across the XTAL pins.
12 CS I Digital Input, Active Low, Chip Select.
13 SCLK I Serial Data Clock.
14 SDIO I/O Digital Serial Data Input/Output.
15 OUTSEL I Logic 0 selects LVDS and Logic 1 selects LVPECL-compatible levels for both OUT1 and OUT2
when the outputs are not under SPI port control. Can be overridden via the programming
registers. This pin has an internal 100 kΩ pull-up resistor.
16 FILTER I/O Loop Filter Node for the PLL. Connect an external 12 nF capacitor from this pin to Pin 17 (LDO).
20 LOCKED O Active High Locked Status Indicator for the PLL.
26, 22 OUT1, OUT2 O Complementary Square Wave Clocking Outputs.
27, 23 OUT1, OUT2 O Square Wave Clocking Outputs.
24, 25 GND P Analog Ground.
EP Exposed Die Pad The exposed die pad must be connected to GND.
1
I = input, I/O = input/output, O = output, P = power, P/O = power/output.
2
When no crystal is in use, leave these pins floating. The terminations are handled by internal circuitry.

Rev. E | Page 8 of 32
Data Sheet AD9552

TYPICAL PERFORMANCE CHARACTERISTICS

CARRIER 624.988784MHz 0.4009dBm CARRIER 622.068199MHz 0.5831dBm
–20 –20
–30 –30
–40 –40
–50 –50
–60 –60
–70 –70
PHASE NOISE (dB)

PHASE NOISE (dB)

–80 –80
–90 –90
–100 –100
–110 –110
–120 –120
–130 –130
–140 –140
–150 –150
–160 –160
–170 –170
–180 –180

07806-014

07806-016
100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 3. Phase Noise, Fractional-N, Pin Programmed Figure 6. Phase Noise, Integer, SDM Off
(fXTAL = 19.44 MHz, fOUT1 = 625 MHz) (fXTAL = 19.44 MHz, fOUT1 = 622.08 MHz)

CARRIER 624.999995MHz 0.4057dBm CARRIER 622.079986MHz 0.3798dBm

–20 –20
–30 –30
–40 –40
–50 –50
–60 –60
–70 –70
PHASE NOISE (dB)
PHASE NOISE (dB)

–80 –80
–90 –90
–100 –100
–110 –110
–120 –120
–130 –130
–140 –140
–150 –150
–160 –160
–170 –170
–180 –180
07806-015

07806-017
100 1k 10k 100k 1M 10M 100M 100 1k 10k 100k 1M 10M 100M
FREQUENCY (Hz) FREQUENCY (Hz)

Figure 4. Phase Noise, Fractional-N, Pin Programmed Figure 7. Phase Noise, Integer, SDM Off
(fREF = 19.44 MHz, fOUT1 = 625 MHz) (fREF = 19.44 MHz, fOUT1 = 622.08 MHz)

10 35

0
30
LVPECL
JITTER TRANSFER
JITTER TRANSFER (dB)

SUPPLY CURRENT (mA)

–10
25

–20 1
JITTER PEAKING
20
0
–30
–1
LVDS (STRONG)
15
–40
–2

–50 10 LVDS (WEAK)

–3
1k 10k 100k

–60 5
07806-018

07806-019

1k 10k 100k 1M 10M 100 1k

FREQUENCY OFFSET (Hz) FREQUENCY (MHz)

Figure 5. Jitter Transfer and Jitter Peaking Figure 8. Supply Current vs. Output Frequency,
LVPECL and LVDS (15 pF Load)

Rev. E | Page 9 of 32
AD9552 Data Sheet
25 1.6

LVPECL
1.4
20
SUPPLY CURRENT (mA)

AMPLITUDE (V p-p)
1.2
LVDS (STRONG)
15

1.0

10
0.8

5 LVDS (WEAK)
0.6

0 0.4

07806-023
07806-020
0 50 100 150 200 250 0 200 400 600 800 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 9. Supply Current vs. Output Frequency, Figure 12. Peak-to-Peak Output Voltage vs. Frequency,
CMOS (15 pF Load) LVPECL and LVDS (15 pF Load)

4.0 60

3.5
5pF

3.0
AMPLITUDE (V p-p)

10pF
DUTY CYCLE (%)
2.5

20pF
2.0 55

1.5

1.0
LVDS (WEAK)
0.5 LVDS (STRONG)
LVPECL
0 50
07806-021

07806-024
0 100 200 300 400 500 100 200 300 400 500 600 700 800 900 1000
FREQUENCY (MHz) FREQUENCY (MHz)

Figure 10. Peak-to-Peak Output Voltage vs. Frequency, Figure 13. Duty Cycle vs. Output Frequency,
CMOS LVPECL and LVDS (15 pF Load)

55

54
5pF
10pF
20pF
DUTY CYCLE (%)

200mV/DIV

53

52

51
07806-025

50
07806-022

0 100 200 300 500ps/DIV

FREQUENCY (MHz)

Figure 11. Duty Cycle vs. Output Frequency, CMOS Figure 14. Typical Output Waveform, LVPECL (805 MHz)

Rev. E | Page 10 of 32
Data Sheet AD9552
100mV/DIV

500mV/DIV
07806-026

07806-027
500ps/DIV 1.25ns/DIV

Figure 15. Typical Output Waveform, LVDS Figure 16. Typical Output Waveform, CMOS
(805 MHz, 3.5 mA Drive Current) (250 MHz, 15 pF Load)

Rev. E | Page 11 of 32
AD9552 Data Sheet

INPUT/OUTPUT TERMINATION RECOMMENDATIONS

0.1µF

AD9552 AD9552
3.3V HIGH DOWNSTREAM 3.3V DOWNSTREAM

100Ω
100Ω

DIFFERENTIAL IMPEDANCE DEVICE DIFFERENTIAL DEVICE

OUTPUT INPUT OUTPUT
(LVDS OR (LVDS OR
LVPECL MODE) 0.1µF
LVPECL MODE)

07806-028

07806-029
Figure 17. AC-Coupled LVDS or LVPECL Output Driver Figure 18. DC-Coupled LVDS or LVPECL Output Driver

Rev. E | Page 12 of 32
Data Sheet AD9552

THEORY OF OPERATION
LOCKED FILTER

DETECTOR LOCK AD9552

DETECT
2
OUT2
REFA 3350MHz TO
4050MHz 4 TO 11 1 TO 63
XTAL CHARGE 2
2× PFD PUMP VCO P0 P1 OUT1
TUNING
CONTROL
N = 4N1 + N0
XTAL
N1 4 OR 5

Σ-Δ N
SERIAL 3 MODULATOR
REGISTER BANK
PORT
MOD,
FRAC
3
A2:0
PRECONFIGURED N, MOD, FRAC, P0, P1 P0, P1
6 DIVIDER VALUES

07806-006
Y5:0

Figure 19. Detailed Block Diagram

PRESET FREQUENCY RATIOS The Y[5:0] pins select the appropriate feedback and output dividers
The frequency selection pins (A[2:0] and Y[5:0]) allow the user to synthesize the output frequencies (see Table 10). The output
to hardwire the device for preset input and output divider values frequencies provided in Table 10 are exact; that is, the number of
based on the pin logic states (see Figure 19). The pins decode decimal places displayed is sufficient to maintain full precision.
ground or open connections as Logic 0 or Logic 1, respectively. Where a decimal representation is not practical, a fractional
Use the serial I/O port to change the divider values from the multiplier is used.
preset values provided by the A[2:0] and Y[5:0] pins. The VCO and output frequency shift in frequency by a ratio of the
The A[2:0] pins select one of eight input reference frequencies reference frequency used vs. the frequency specified in Table 9.
(see Table 9). The user supplies the input reference frequency by Note that the VCO frequency must stay within the minimum and
connecting a single-ended clock signal to the REF pin or a crystal maximum range specified in Table 1. Typically, the selection of
resonator across the XTAL pins. If the A[2:0] pins select 10 MHz, the VCO frequency band, as well as the gain adjustment, by the
12 MHz, 12.8 MHz, or 16 MHz, the input frequency to the AD9552 external pin strap occurs as part of the device’s automatic VCO
doubles internally. Alternatively, if Register 0x1D[2] is set to 1, calibration process, which initiates at power up (or reset). If the
the input frequency doubles. user changes the VCO frequency band via the SPI interface,
however, a forced VCO calibration should be initiated by first
Table 9. Input Reference Frequency Selection Pins enabling SPI control of the VCO calibration (Register 0x0E[2] = 1)
A2 A1 A0 Reference Frequency (MHz) and then writing a 1 to the calibrate VCO bit (Register 0x0E[7]).
0 0 0 10.00
0 0 1 12.00
0 1 0 12.80
0 1 1 16.00
1 0 0 19.20
1 0 1 19.44
1 1 0 20.00
1 1 1 26.00

Rev. E | Page 13 of 32
AD9552 Data Sheet

Table 10. Output Frequency Selection Pins

Y5 Y4 Y3 Y2 Y1 Y0 VCO Frequency (MHz) Output (MHz)
0 0 0 0 0 0 3732.48 51.84
0 0 0 0 0 1 3888 54
0 0 0 0 1 0 3840 60
0 0 0 0 1 1 3932.16 61.44
0 0 0 1 0 0 3750 62.5
0 0 0 1 0 1 3733.296 66.666
0 0 0 1 1 0 3560.439 74.17582
0 0 0 1 1 1 3564 74.25
0 0 1 0 0 0 3732.48 77.76
0 0 1 0 0 1 3932.16 98.304
0 0 1 0 1 0 4000 100
0 0 1 0 1 1 3825 106.25
0 0 1 1 0 0 3840 120
0 0 1 1 0 1 4000 125
0 0 1 1 1 0 3724 133
0 0 1 1 1 1 3732.48 155.52
0 1 0 0 0 0 3750 156.25
0 1 0 0 0 1 3825 159.375
0 1 0 0 1 0 3867.188 161.1328125
0 1 0 0 1 1 3944.531 10518.75/64
0 1 0 1 0 0 3999.086 155.52 × (15/14)
0 1 0 1 0 1 4015.959 155.52 × (255/237)
0 1 0 1 1 0 4023.878 167.6616
0 1 0 1 1 1 3554.742 177.7371
0 1 1 0 0 0 3932.16 245.76
0 1 1 0 0 1 4000 250
0 1 1 0 1 0 3732.48 311.04
0 1 1 0 1 1 3840 320
0 1 1 1 0 0 4000 400
0 1 1 1 0 1 3471.4 433.925
0 1 1 1 1 0 3718.75 531.25
0 1 1 1 1 1 3763.2 537.6
1 0 0 0 0 0 3984.375 569.1964
1 0 0 0 0 1 3732.48 622.08
1 0 0 0 1 0 3748.229 624.7048
1 0 0 0 1 1 3750 625
1 0 0 1 0 0 3763.978 622.08 × (239/237)
1 0 0 1 0 1 3779.927 629.9878
1 0 0 1 1 0 3840 640
1 0 0 1 1 1 3849.12 641.52
1 0 1 0 0 0 3867.188 625 × (66/64)
1 0 1 0 0 1 3944.531 657.421875
1 0 1 0 1 0 3961.105 657.421875 × (239/238)
1 0 1 0 1 1 3999.086 622.08 × (15/14)
1 0 1 1 0 0 4014.769 669.1281
1 0 1 1 0 1 4015.959 622.08 × (255/237)
1 0 1 1 1 0 4017.857 625 × (15/14)
1 0 1 1 1 1 4025.032 670.8386
1 1 0 0 0 0 4032.976 622.08 × (255/236)
1 1 0 0 0 1 3452.846 625 × (66/64) × (15/14)
1 1 0 0 1 0 3467.415 625 × (255/237) × (66/64)
1 1 0 0 1 1 3468.75 693.75
1 1 0 1 0 0 3481.996 622.08 × (253/226)
1 1 0 1 0 1 3521.903 657.421875 × (255/238)

Rev. E | Page 14 of 32
Data Sheet AD9552
Y5 Y4 Y3 Y2 Y1 Y0 VCO Frequency (MHz) Output (MHz)
1 1 0 1 1 0 3536.763 657.421875 × (255/237)
1 1 0 1 1 1 3582.686 716.5372
1 1 1 0 0 0 3593.75 718.75
1 1 1 0 0 1 3598.672 719.7344
1 1 1 0 1 0 3740.355 748.0709
1 1 1 0 1 1 3750 750
1 1 1 1 0 0 3888 777.6
1 1 1 1 0 1 3897.843 779.5686
1 1 1 1 1 0 3906.25 781.25
1 1 1 1 1 1 4028.32 625 × (10/8) × (66/64)

COMPONENT BLOCKS Reference Monitor

Input Reference
The AD9552 offers the following input reference options:
• Crystal resonator connected directly across the XTAL pins
• CMOS-compatible, single-ended clock source connected
directly to the REF pin
In the case of a crystal resonator, the AD9552 expects a crystal
with a specified load capacitance of 15 pF (default). The
AD9552 provides the load capacitance internally. The internal
load capacitance consists of a fixed component of 13 pF and a
variable (programmable) component of 0 pF to 15.75 pF.
After applying power to the AD9552 (or after a device reset),
the programmable component assumes a value of 2 pF. This
establishes the default load capacitance of 15 pF.
To accommodate crystals with a specified load capacitance other
than 15 pF (8 pF to 23.75 pF), the user can adjust the program-
mable capacitance in 0.25 pF increments via Register 0x1B[5:0].
Note that when the user sets Register 0x1B[7] to 0 (enabling SPI
control of the XTAL tuning capacitors), the variable capacitance
changes from 2 pF (its power-up value) to 15.75 pF due to the
default value of Register 0x1B[5:0]. This causes the crystal load
capacitance to be 23.75 pF until the user overwrites the default
contents of Register 0x1B[5:0].
A noncomprehensive, alphabetical list of crystal manufacturers
includes the following:
• AVX/Kyocera
• ECS
• Epson Toyocom
• Fox Electronics
• NDK
• Siward
The AD9552 evaluation board functions with the NDK
NX3225SA crystal or with the Siward 571200-A258-001 crystal.
Although these crystals meet the load capacitance and motional
The REF input includes a monitor circuit that detects signal
presence at the REF input. If the device detects a clock signal on
the REF pin, it automatically selects the REF input as the input
reference source and shuts down the crystal oscillator. This auto-
matic preference for a REF input signal is the default mode of
operation. However, the user can override the default setting via
Register 0x1D[0]. Setting this bit forces the device to override the
signal detector associated with the REF input and activates the
crystal oscillator (whether or not a REF input signal is present).
2× Frequency Multiplier
The 2× frequency multiplier provides the option to double
the frequency delivered by either the REF or XTAL input. This
allows the user to take advantage of a higher frequency deli-
vered to the PLL, which allows for greater separation between
the frequency generated by the PLL and the associated reference
spur. However, increased reference spur separation comes at the
expense of the harmonic spurs introduced by the frequency
multiplier. As such, beneficial use of the frequency multiplier
is application specific.
PLL
The PLL consists of a phase/frequency detector (PFD), a
partially integrated analog loop filter (see Figure 20), an
integrated voltage-controlled oscillator (VCO), and a
feedback divider with an optional third-order SDM that
allows for fractional divide ratios. The PLL produces a
nominal 3.7 GHz signal that is phase-locked to the input
reference signal.
The loop bandwidth of the PLL is nominally 50 kHz. The PFD of
the PLL drives a charge pump that automatically changes current
proportionately to the feedback divider value. This increase or
decrease in current maintains a constant loop bandwidth with
changes in the input reference or the output frequency.
FROM 1.25kΩ 1.25kΩ 2.5kΩ
TO
CHARGE
PUMP VCO
105pF 15pF 15pF 20pF
2.5kΩ

resistance requirements of the AD9552 according to their data

16
sheets, Analog Devices, Inc., does not guarantee their operation
07806-004

EXTERNAL
with the AD9552, nor does Analog Devices endorse one supplier LOOP FILTER
CAPACITOR
of crystals over another.
Figure 20. Internal Loop Filter

Rev. E | Page 15 of 32
AD9552
The gain of the PLL is proportional to the current delivered
by the charge pump. The user can override the default charge
pump current setting, and, thereby, the PLL gain, by using
Register 0x0A[7:0].
The PLL has a VCO with 128 frequency bands spanning a range
of 3350 MHz to 4050 MHz (3700 MHz nominal). However, the
actual operating frequency within a particular band depends on
the control voltage that appears on the loop filter capacitor. The
control voltage causes the VCO output frequency to vary linearly
within the selected band. This frequency variability allows the
control loop of the PLL to synchronize the VCO output signal
with the reference signal applied to the PFD. Typically, selection
of the VCO frequency band (as well as gain adjustment) occurs
automatically as part of the device’s automatic VCO calibration
process, which initiates at power up (or reset). Alternatively, the
user can force VCO calibration by first enabling SPI control of
VCO calibration (Register 0x0E[2] = 1) and then writing a 1 to
the calibrate VCO bit (Register 0x0E[7]). To facilitate system
debugging, the user can override the VCO band setting by first
enabling SPI control of VCO band (Register 0x0E[0] = 1) and
then writing the desired value to Register 0x10[7:1].
The PLL has a feedback divider coupled with a third-order
SDM that enables the PLL to provide integer-plus-fractional
frequency upconversion. The integer factor, N, is variable via
an 8-bit programming register. The range of N is from NMIN to
255, where NMIN is 36 or 47 depending on whether the SDM is
disabled or enabled, respectively. The SDM in the feedback path
allows for a fractional divide value that takes the form of N +
F/M, where N is the integer part (eight bits), M is the modulus
(20 bits), and F is the fractional part (20 bits), with all three
parameters being positive integers.
The feedback SDM gives the AD9552 the ability to support a
wide range of output frequencies with exact frequency ratios
relative to the input reference.
PLL Locked Indicator
The PLL provides a status indicator that appears at an external
pin (LOCKED). The indicator shows when the PLL has acquired
a locked condition.
Output Dividers
Two integer dividers exist in the output chain. The first divider (P0)
yields an integer submultiple of the VCO frequency. The second
divider (P1) establishes the frequency at OUT1 as an integer
submultiple of the output frequency of the P0 divider.
Input-to-OUT2 Option
By default, OUT2 delivers an output frequency that is the same
frequency as OUT1. However, the user has the option of making
OUT2 a replica of the input frequency (REF or XTAL) by
programming Register 33[3] = 1.
Rev. E | Page 16 of 32
Data Sheet
Output Drivers
The user has control over the following output driver parameters
via the programming registers:
• Logic family and pin functionality
• Polarity (for CMOS family only)
• Drive current
• Power-down
The logic families are LVDS, LVPECL, and CMOS. Selection of
the logic family is via the mode control bits in the OUT1 driver
control register (Register 0x32[5:3]) and the OUT2 driver control
register (Register 0x34[5:3]), as detailed in Table 11. Regardless
of the selected logic family, each output driver uses two pins:
OUT1 and OUT1 are used by one driver, and OUT2 and OUT2
are used by the other. This enables support of the differential
signals associated with the LVDS and LVPECL logic families.
CMOS, on the other hand, is a single-ended signal requiring
only one output pin, but both output pins are available for
optional provision of a dual, single-ended CMOS output clock.
Refer to the first entry (CMOS (both pins)) in Table 11.
Table 11. Output Channel Logic Family and Pin Functionality
Mode
Control Bits[2:0] Logic Family and Pin Functionality
000 CMOS (both pins)
001 CMOS (positive pin), tristate (negative pin)
010 Tristate (positive pin), CMOS (negative pin)
011 Tristate (both pins)
100 LVDS
101 LVPECL
110 Undefined
111 Undefined
If the mode bits indicate the CMOS logic family, the user has
control of the logic polarity associated with each CMOS output
pin via the OUT1 and OUT2 driver control registers.
If the mode bits indicate the CMOS or LVDS logic family, the
user can select whether the output driver uses weak or strong
drive capability via the OUT1 and OUT2 driver control registers.
In the case of the CMOS family, the strong setting allows for
driving increased capacitive loads. In the case of the LVDS
family, the nominal weak and strong drive currents are 3.5 mA
and 7 mA, respectively.
The OUT1 and OUT2 driver control registers also have a power-
down bit to enable/disable the output drivers. The power-down
function is independent of the logic family selection.
Note that, unless the user programs the device to allow SPI port
control of the output drivers, the drivers default to LVPECL or
LVDS, depending on the logic level on the OUTSEL pin (Pin 15).
For OUTSEL = 0, both outputs are LVDS. For OUTSEL = 1, both
outputs are LVPECL. In the pin-selected LVDS mode, the user
can still control the drive strength, using the SPI port.
Data Sheet AD9552
PART INITIALIZATION AND AUTOMATIC POWER- Note that NMIN and K can each be one of two values. The value
ON RESET of NMIN depends on the state of the SDM. NMIN = 36 when the
The AD9552 has an internal power-on reset circuit. At power-up, SDM is disabled or NMIN = 47 when it is enabled. The value of K
internal logic relies on the internal reference monitor to select depends on the 2× frequency multiplier. K = 1 when the 2×
either the crystal oscillator or the reference input and then frequency multiplier is bypassed, or K = 2 when it is enabled.
initiates VCO calibration using whichever is found. If both are The frequency at the input to the PFD (fPFD) is calculated as
present, the external reference path is chosen. follows:
VCO calibration is required in order for the device to lock. If fPFD = K × fREF
the input reference signal is not present, VCO calibration waits
The operating range of the VCO (3.35 GHz ≤ fVCO ≤ 4.05 GHz)
until a valid input reference is present. As soon as an input
places the following constraint on fPFD:
reference signal is present, VCO calibration starts. The user
should wait at least 3 ms for the VCO calibration routine to  3350   
  MHz ≤ f PFD ≤  4050  MHz
finish before programming the VCO control register (Register  N + FRAC   N + FRAC 
 MOD   MOD 
0x0E) via serial communication.
If the user wishes to use the crystal oscillator input even if the
CALCULATING DIVIDER VALUES
reference input is present, the user needs to set Bit 0 (use crystal This section provides a three-step procedure for calculating the
resonator) in Register 0x1D. divider values when given a specific fOUT1/fREF ratio (fREF is the
frequency of either the REF input signal source or the external
Any change to the preset frequency selection pins or the PLL
crystal resonator). The computation process is described in
divide ratios requires the user to recalibrate the VCO.
general terms, but a specific example is provided for clarity.
OUTPUT/INPUT FREQUENCY RELATIONSHIP The example is based on a frequency control pin setting of
The frequency at OUT1 and OUT2 is a function of the PLL A[2:0] = 111 (see Table 9) and Y[5:0] = 101000 (see Table 10),
feedback divider values (N, FRAC, and MOD) and the output yielding the following:
divider values (P0 and P1). The equations that define the
fREF = 26 MHz
frequency at OUT1 and OUT2 (fOUT1 and fOUT2, respectively)
are as follows. fOUT1 = 625 × (66/64) MHz
 N+ FRAC
 1. Determine the output divide factor (ODF).
f OUT1 = f REF  K × MOD 

 P0 P1  Note that the VCO frequency (fVCO) spans 3350 MHz to
4050 MHz. The ratio, fVCO/fOUT1, indicates the required ODF.
fOUT2 = fOUT1
Given the specified value of fOUT1 (~644.53 MHz) and the
where: range of fVCO, the ODF spans a range of 5.2 to 6.3. The ODF
fREF is the input reference or crystal resonator frequency. must be an integer, which means that ODF = 6 (because 6
K is the input mode scale factor. is the only integer between 5.2 and 6.3).
N is the integer feedback divider value.
2. Determine suitable values for P0 and P1.
FRAC and MOD are the fractional feedback divider values.
P0 and P1 are the OUT1 divider values. The ODF is the product of the two output dividers, so
ODF = P0P1. It has already been determined that ODF = 6
The numerator of the fOUT1 equation contains the feedback division
for the given example. Therefore, P0P1 = 6 with the constraints
factor, which has an integer part (N) due to an integer divider
that P0 and P1 are both integers and that 4 ≤ P0 ≤ 11 (see
along with an optional fractional part (FRAC/MOD) associated
the Output/Input Frequency Relationship section). These
with the feedback SDM.
constraints lead to the single solution: P0 = 6 and P1 = 1.
The following constraints apply:
Although this particular example yields a single solution
N MIN ∈ {36 , 47} for the output divider values with fOUT1 ≈ 644.53 MHz, some
N ∈ {N MIN , N MIN + 1,, 255}
fOUT1 frequencies result in multiple ODFs rather than just
one. For example, if fOUT1 = 100 MHz the ODF ranges from
FRAC ∈ {0, 1 ,  , 1,048,575} 34 to 40. This leads to an assortment of possible values for
MOD ∈ {1, 2 ,  , 1,048,575} P0 and P1, as shown in Table 12.
K ∈ {1, 2}
P0 ∈ {4 , 5, , 11}
P1 ∈ {1 , 2, , 63}

Rev. E | Page 17 of 32
AD9552 Data Sheet
Table 12. Combinations for P0 and P1 It is imperative that long division be used to obtain the correct
P0 P1 ODF (P0 × P1)
results. Avoid the use of a calculator or math program, because
these do not always yield correct results due to internal rounding
4 9 36
and/or truncation. Some calculators or math programs may be up
4 10 40
to the task if they can handle very large integer operations, but such
5 7 35
are not common.
5 8 40
6 6 36 In the example, N = 148 and R/Y = 1228/1664, which reduces
7 5 35 to R/Y = 307/416. These values of N, R, and Y constitute the
8 5 40 following respective feedback divider values:
9 4 36 N = 148, FRAC = 307, and MOD = 416.
10 4 40 The only caveat is that N and MOD must meet the constraints
The P0 and P1 combinations listed in Table 12 are all equally given in the Output/Input Frequency Relationship section.
valid. However, note that they yield only three valid ODF In the example, FRAC is nonzero, so the division value is an
values (35, 36, and 40) from the original range of 34 to 40. integer plus the fractional component, FRAC/MOD. This
3. Determine the feedback divider values for the PLL. implies that the feedback SDM is necessary as part of the
feedback divider. If FRAC = 0, the feedback division factor
Repeat this step for each ODF when multiple ODFs exist is an integer and the SDM is not required (it can be bypassed).
(for example, 35, 36, and 40 in the case of Table 12).
Although the feedback divider values obtained in this way
To calculate the feedback divider values for a given ODF, provide the proper feedback divide ratio to synthesize the exact
use the following equation: output frequency, they may not yield optimal jitter performance
 f OUT 1  X at the final output. One reason for this is that the value of MOD
  × ODF = defines the period of the SDM, which has a direct impact on the
 f  Y
 REF 
spurious output of the SDM. Specifically, in the spectral band
Note that the left side of the equation contains variables with from dc to fPFD, the SDM exhibits spurs at intervals of fPFD/
known quantities. Furthermore, the values are necessarily MOD. Thus, the spectral separation (Δf) of the spurs associated
rational, so the left side is expressible as a ratio of two inte- with the feedback SDM is
gers, X and Y. Following is an example equation.
f PFD
∆f =
  66   MOD
 625  
  64   × 6 = 625(66)(6) = 247,500 = X Because the SDM is in the feedback path of the PLL, these spurs
 26  26(64) 1664 Y appear in the output signal as spurious components offset by Δf
 
  from fOUT1. Therefore, a small MOD value pro-duces relatively
In the context of the AD9552, X/Y is always an improper large spurs with relatively large frequency offsets from fOUT1,
fraction. Therefore, it is expressible as the sum of an integer, whereas a large MOD value produces smaller spurs but more
N, and the proper fraction, R/Y (R and Y are integers). closely spaced to fOUT1. Clearly, the value of MOD has a direct
impact on the spurious content (that is, jitter) at OUT1.
X R
=N+ Generally, the largest possible MOD value yields the smallest spurs.
Y Y
Thus, it is desirable to scale MOD and FRAC by the integer part
247,500 R
=N+ of 220 divided by the value of MOD obtained previously. In the
1664 Y example, the value of MOD is 416, yield-ing a scale factor of 2520
This particular example yields N = 148, Y = 1664, and (the integer part of 220/416). A scale factor of 2520 leads to FRAC
R = 1228. To arrive at this result, use long division to convert = 307 × 2520 = 773,640 and MOD = 416 × 2520 = 1,048,320.
the improper fraction, X/Y, to an integer (N) and a proper
LOW DROPOUT (LDO) REGULATORS
fraction (R/Y). Note that dividing Y into X by means of
long division yields an integer, N, and a remainder, R. The The AD9552 is powered from a single 3.3 V supply and contains
proper fraction has a numerator (R, the remainder) and a on-chip LDO regulators for each function to eliminate the need
denominator (Y, the divisor), as shown in Figure 21. for external LDOs. To ensure optimal performance, each LDO
output should have a 0.47 μF capacitor connected between its
N
Y X access pin and ground, and this capacitor should be kept as
X R
close to the device as possible.
07806-005

–NY =N+
Y Y
R
Figure 21. Example Long Division

Rev. E | Page 18 of 32
Data Sheet AD9552

APPLICATIONS INFORMATION
THERMAL PERFORMANCE
Table 13. Thermal Parameters for the 32-Lead LFCSP Package
Symbol Thermal Characteristic Using a JEDEC51-7 Plus JEDEC51-5 2S2P Test Board 1 Value 2 Unit
θJA Junction-to-ambient thermal resistance, 0.0 m/sec airflow per JEDEC JESD51-2 (still air) 40.5 °C/W
θJMA Junction-to-ambient thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-6 (moving air) 35.4 °C/W
θJMA Junction-to-ambient thermal resistance, 2.5 m/sec airflow per JEDEC JESD51-6 (moving air) 31.8 °C/W
θJB Junction-to-board thermal resistance, 1.0 m/sec airflow per JEDEC JESD51-8 (moving air) 23.3 °C/W
θJC Junction-to-case thermal resistance (die-to-heat sink) per MIL-Std 883, Method 1012.1 4.2 °C/W
ΨJT Junction-to-top-of-package characterization parameter, 0 m/sec airflow per JEDEC JESD51-2 (still air) 0.4 °C/W
1
The exposed pad on the bottom of the package must be soldered to ground to achieve the specified thermal performance.
2
Results are from simulations. The PCB is a JEDEC multilayer type. Thermal performance for actual applications requires careful inspection of the conditions in the
application to determine whether they are similar to those assumed in these calculations.

The AD9552 is specified for an ambient temperature (TA). To Values of θJA are provided for package comparison and PCB design
ensure that TA is not exceeded, an airflow source can be used. considerations. θJA can be used for a first-order approximation
Use the following equation to determine the junction tempera- of TJ using the following equation:
ture on the application PCB: TJ = TA + (θJA × PD)
TJ = TCASE + (ΨJT × PD) where TA is the ambient temperature (°C).
where: Values of θJC are provided for package comparison and PCB
TJ is the junction temperature (°C). design considerations when an external heat sink is required.
TCASE is the case temperature (°C) measured by the customer
at the top center of the package. Values of θJB are provided for package comparison and PCB
ΨJT is the value indicated in Table 13. design considerations.
PD is the power dissipation (see the Specifications section).

Rev. E | Page 19 of 32
AD9552
SERIAL CONTROL PORT
The AD9552 serial control port is a flexible, synchronous, serial
communications port that allows an easy interface to many
industry-standard microcontrollers and microprocessors. Single
or multiple byte transfers are supported, as well as MSB first or
LSB first transfer formats. The AD9552 serial control port is
configured for a single bidirectional I/O pin (SDIO only).
The serial control port has two types of registers: read-only and
buffered. Read-only registers are nonbuffered and ignore write
commands. All writable registers are buffered (also referred to
as mirrored) and require an I/O update to transfer the new values
from a temporary buffer on the chip to the actual register. To
invoke an I/O update, write a 1 to the I/O update bit found in
Register 0x05[0]. Because any number of bytes of data can
be changed before issuing an update command, the update
simultaneously enables all register changes occurring since
any previous update.
SERIAL CONTROL PORT PIN DESCRIPTIONS
SCLK (serial data clock) is the serial shift clock. This pin is an
input. SCLK is used to synchronize serial control port reads and
writes. Write data bits are registered on the rising edge of this
clock, and read data bits are registered on the falling edge. This
pin is internally pulled down by a 30 kΩ resistor to ground.
SDIO (digital serial data input/output) is a dual-purpose pin
that acts as input only or as an input/output. The AD9552
defaults to bidirectional pins for I/O.
CS (chip select bar) is an active low control that gates the read and
write cycles. When CS is high, SDIO is in a high impedance state.
This pin is internally pulled up by a 100 kΩ resistor to 3.3 V. It
should not be left floating. See the Operation of the Serial Control
Port section on the use of the CS pin in a communication cycle.
SCLK 13 AD9552
SDIO 14
SERIAL
CONTROL
PORT
07806-006
CS 12
Figure 22. Serial Control Port
OPERATION OF THE SERIAL CONTROL PORT
Framing a Communication Cycle with CS
The CS line gates the communication cycle (a write or a read oper-
ation). CS must be brought low to initiate a communication cycle.
The CS stall high function is supported in modes where three
or fewer bytes of data (plus instruction data) are transferred.
Bits[W1:W0] must be set to 00, 01, or 10 (see Table 14). In these
modes, CS may temporarily return high on any byte boundary,
allowing time for the system controller to process the next byte.
CS can go high on byte boundaries only and can go high during
either part (instruction or data) of the transfer. During this period,
Rev. E | Page 20 of 32
Data Sheet
the serial control port state machine enters a wait state until all
data has been sent. If the system controller decides to abort before
the complete transfer of all the data, the state machine must be reset
either by completing the remaining transfer or by returning the
CS line low for at least one complete SCLK cycle (but fewer than
eight SCLK cycles). A rising edge on the CS pin on a nonbyte
boundary terminates the serial transfer and flushes the buffer.
Table 14. Byte Transfer Count
Bytes to Transfer
W1 W0 (Excluding the 2-Byte Instruction)
0 0 1
0 1 2
1 0 3
1 1 Streaming mode
In the streaming mode (Bits[W1:W0] = 11), any number of data
bytes can be transferred in a continuous stream. The register
address is automatically incremented or decremented (see the
MSB/LSB First Transfers section). CS must be raised at the end
of the last byte to be transferred, thereby ending the stream mode.
Communication Cycle—Instruction Plus Data
There are two parts to a communication cycle with the AD9552.
The first part writes a 16-bit instruction word into the AD9552,
coincident with the first 16 SCLK rising edges. The instruction
word provides the AD9552 serial control port with information
regarding the data transfer, which is the second part of the
communication cycle. The instruction word defines whether
the upcoming data transfer is a read or a write, the number of
bytes in the data transfer, and the starting register address for
the first byte of the data transfer.
Write
If the instruction word is for a write operation (Bit I15 = 0), the
second part is the transfer of data into the serial control port
buffer of the AD9552. The length of the transfer (1, 2, or 3 bytes;
or streaming mode) is indicated by two bits (Bits[W1:W0]) in
the instruction byte. The length of the transfer indicated by
(Bits[W1:W0]) does not include the 2-byte instruction. CS can
be raised after each sequence of eight bits to stall the bus (except
after the last byte, where it ends the cycle). When the bus is stalled,
the serial transfer resumes when CS is lowered. Stalling on nonbyte
boundaries resets the serial control port.
Read
If the instruction word is for a read operation (Bit I15 = 1), the
next N × 8 SCLK cycles clock out the data from the address
specified in the instruction word, where N is 1, 2, 3, or 4, as
determined by Bits[W1:W0]. In this case, 4 is used for streaming
mode, where four or more words are transferred per read. The
data read back is valid on the falling edge of SCLK.
The default mode of the AD9552 serial control port is bidirec-
tional mode, and the data read back appears on the SDIO pin.
Data Sheet
By default, a read request reads the register value that is currently
in use by the AD9552. However, setting Register 0x04[0] = 1
causes the buffered registers to be read instead. The buffered
registers are the ones that take effect during the next I/O update.
AD9552
MSB/LSB FIRST TRANSFERS
The AD9552 instruction word and byte data can be MSB first or
LSB first. The default for the AD9552 is MSB first. The LSB first
mode can be set by writing a 1 to Register 0x00[6] and requires
that an I/O update be executed. Immediately after the LSB first

CONTROL REGISTERS
SCLK 13
REGISTER BUFFERS
bit is set, all serial control port operations are changed to LSB
SERIAL
AD9552 first order.
SDIO 14 CONTROL REGISTER
CORE
PORT UPDATE When MSB first mode is active, the instruction and data bytes
EXECUTE AN
must be written from MSB to LSB. Multibyte data transfers in
CS 12
MSB first format start with an instruction byte that includes the

07806-007
INPUT/OUTPUT
UPDATE
register address of the most significant data byte. Subsequent
Figure 23. Relationship Between the Serial Control Port Register Buffers and data bytes must follow in order from high address to low address.
the Control Registers
In MSB first mode, the serial control port internal address gen-
The AD9552 uses Register 0x00 to Register 0x34. Although the erator decrements for each data byte of the multibyte transfer cycle.
AD9552 serial control port allows both 8-bit and 16-bit instruc- When LSB first = 1 (LSB first), the instruction and data bytes
tions, the 8-bit instruction mode provides access to five address must be written from LSB to MSB. Multibyte data transfers
bits (Address Bits[A4:A0]) only, which restricts its use to Address in LSB first format start with an instruction byte that includes
Space 0x00 to Address Space 0x01. The AD9552 defaults to 16-bit the register address of the least significant data byte followed
instruction mode on power-up, and the 8-bit instruction mode by multiple data bytes. The serial control port internal byte
is not supported. address generator increments for each data byte of the multibyte
INSTRUCTION WORD (16 BITS) transfer cycle.
The MSB of the instruction word (see Table 15) is R/W, which The AD9552 serial control port register address decrements from
indicates whether the instruction is a read or a write. The next the register address just written toward 0x00 for multibyte I/O
two bits, W1 and W0, are the transfer length in bytes. The final operations if the MSB first mode is active (default). If the LSB
13 bits are the address bits (Address Bits[A12:A0]) at which the first mode is active, the serial control port register address
read or write operation is to begin. increments from the address just written toward 0x34 for
multibyte I/O operations.
For a write, the instruction word is followed by the number of
bytes of data indicated by Bits[W1:W0], which is interpreted Unused addresses are not skipped during multibyte I/O operations.
according to Table 14. The user should write the default value to a reserved register and
should write only zeros to unmapped registers. Note that it is more
Address Bits[A12:A0] select the address within the register map
efficient to issue a new write command than to write the default
that is written to or read from during the data transfer portion
value to more than two consecutive reserved (or unmapped)
of the communication cycle. The AD9552 uses all of the 13-bit
registers.
address space. For multibyte transfers, this address is the starting
byte address.

Table 15. Serial Control Port, 16-Bit Instruction Word, MSB First
MSB LSB
I15 I14 I13 I12 I11 I10 I9 I8 I7 I6 I5 I4 I3 I2 I1 I0
R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0

Table 16. Definition of Terms Used in Serial Control Port Timing Diagrams
Parameter Description
tCLK Period of SCLK
tDV Read data valid time (time from falling edge of SCLK to valid data on SDIO)
tDS Setup time between data and rising edge of SCLK
tDH Hold time between data and rising edge of SCLK
tS Setup time between CS and SCLK
tH Hold time between CS and SCLK
tHIGH Minimum period that SCLK should be in a logic high state
tLOW Minimum period that SCLK should be in a logic low state

Rev. E | Page 21 of 32
AD9552 Data Sheet
CS

SCLK DON'T CARE DON'T CARE

SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 DON'T CARE

07806-008
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA

Figure 24. Serial Control Port Write—MSB First, 16-Bit Instruction, Two Bytes Data

CS
SCLK
DON'T CARE DON'T CARE

SDIO R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 A4 A3 A2 A1 A0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0 D7 D6 D5 D4 D3 D2 D1 D0

07806-009
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N – 1) DATA REGISTER (N – 2) DATA REGISTER (N – 3) DATA

Figure 25. Serial Control Port Read—MSB First, 16-Bit Instruction, Four Bytes Data

tHIGH
tDS
tS tDH tCLK tH
tLOW
CS

SCLK DON'T CARE DON'T CARE

SDIO DON'T CARE R/W W1 W0 A12 A11 A10 A9 A8 A7 A6 A5 D4 D3 D2 D1 D0 DON'T CARE

07806-010
Figure 26. Serial Control Port Write—MSB First, 16-Bit Instruction, Timing Measurements

CS

SCLK

tDV
07806-011

SDIO DATA BIT N DATA BIT N – 1

Figure 27. Timing Diagram for Serial Control Port Register Read

CS

SCLK DON'T CARE DON'T CARE

SDIO DON'T CARE A0 A1 A2 A3 A4 A5 A6 A7 A8 A9 A10 A11 A12 W0 W1 R/W D0 D1 D2 D3 D4 D5 D6 D7 D0 D1 D2 D3 D4 D5 D6 D7 DON'T CARE

07806-012
16-BIT INSTRUCTION HEADER REGISTER (N) DATA REGISTER (N + 1) DATA

Figure 28. Serial Control Port Write—LSB First, 16-Bit Instruction, Two Bytes Data

tS tH

CS

tCLK
tHIGH tLOW

tDS
SCLK

tDH
07806-013

SDIO BIT N BIT N + 1

Figure 29. Serial Control Port Timing—Write

Rev. E | Page 22 of 32
Data Sheet AD9552

REGISTER MAP
A bit that is labeled “aclr” is an active high, autoclearing bit. When set to a Logic 1 state, the control logic automatically returns it to a
Logic 0 state upon completion of the indicated task.

Table 17. Register Map

Addr. Register (LSB)
(Hex) Name (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default
0x00 Serial port 0 LSB first Register 1 1 Register LSB first 0 0x18
control map reset map reset
(aclr)
0x04 Readback Unused Unused Unused Unused Unused Unused Unused Readback 0x00
control control
0x05 I/O update Unused Unused Unused Unused Unused Unused Unused I/O update 0x00
(aclr)
0x0A PLL charge Charge pump current control[7:0] 0x80
pump and (3.5 µA granularity, ~900 µA full scale)
PFD
control
0x0B PLL charge Enable SPI Enable SPI CP mode[1:0] Enable CP PFD PFD Force VCO 0x30
pump and control of control of mode feedback reference to
PFD charge antiback- control input edge input edge midpoint
control pump lash control control frequency
current period
0x0C PLL charge Unused CP offset CP offset current[1:0] Enable CP Reserved Reserved Reserved 0x00
pump and current offset
PFD polarity current
control control
0x0D PLL charge Antibacklash control[1:0] Unused Unused Unused Unused Unused PLL lock 0x00
pump and detector
PFD power-
control down
0x0E VCO Calibrate Enable ALC threshold[2:0] Enable SPI Boost VCO Enable SPI 0x70
control VCO (aclr) ALC control of supply control of
VCO VCO band
calibration setting
0x0F VCO VCO level control[5:0] Unused Unused 0x80
control
0x10 VCO VCO band control[6:0] Unused 0x80
control
0x11 PLL control N[7:0] (SDM integer part) 0x00
0x12 PLL control MOD[19:12] (SDM modulus) 0x80
0x13 PLL control MOD[11:4] (SDM modulus) 0x00
0x14 PLL control MOD[3:0] (SDM modulus) Enable SPI Bypass Disable SDM Reset PLL 0x00
control of SDM
output
frequency
0x15 PLL control FRAC[19:12] (SDM fractional part) 0x20
0x16 PLL control FRAC[11:4] (SDM fractional part) 0x00
0x17 PLL control FRAC[3:0] (SDM fractional part) Unused Unused Unused P1 divider[5] 0x01
0x18 PLL control P1 divider[4:0] P0 divider[2:0] 0x00
0x19 PLL control Enable SPI Unused Unused 0x20
control
of OUT1
dividers
0x1A Input Receiver Band gap voltage adjust[4:0] Unused Enable SPI 0x00
receiver and reset (aclr) (00000 = maximum, 11111 = minimum) control of
band gap band gap
voltage
0x1B XTAL Disable SPI Unused XTAL tuning capacitor control[5:0] 0x80
tuning control of (0.25 pF per bit, inverted binary coding)
control XTAL tuning
Rev. E | Page 23 of 32
AD9552 Data Sheet
Addr. Register (LSB)
(Hex) Name (MSB) Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0 Default
capacitance
0x1C XTAL Unused Unused Unused Unused Unused Unused Unused Unused 0x00
control
0x1D XTAL Unused Unused Unused Unused Unused Select 2× Unused Use crystal 0x00
control frequency resonator
multiplier
0x32 OUT1 OUT1 drive OUT1 OUT1 mode control[2:0] OUT1 CMOS polarity[1:0] Enable SPI 0xA8
driver strength power- control of
control down OUT1
driver
control
0x33 Select OUT2 Unused Unused Unused Unused OUT2 Unused Unused Unused 0x00
source source
0x34 OUT2 OUT2 drive OUT2 OUT2 mode control[2:0] OUT2 CMOS polarity[1:0] Enable SPI 0xA8
driver strength power- control of
control down OUT2
driver
control

REGISTER MAP DESCRIPTIONS

Control bit functions are active high unless stated otherwise. Register address values are always hexadecimal unless otherwise indicated.

Serial Port Control (Register 0x00 to Register 0x05)

Table 18.
Address Bit Bit Name Description
0x00 7 Unused Forced to Logic 0 internally, which enables 3-wire mode only.
6 LSB first Bit order for SPI port.
0 = most significant bit and byte first (default).
1 = least significant bit and byte first.
5 Register map reset Resets the register map to the default values. This is an autoclearing bit.
4 Unused Forced to Logic 1 internally, which enables 16-bit mode (the only mode supported by
the device).
[3:0] Unused Mirrored version of the contents of Register 0x00[7:4] (that is, Bits[3:0] = Bits[7:4]).
0x04 [7:1] Unused Unused.
0 Readback control For buffered registers, serial port readback reads from actual (active) registers instead of
from the buffer.
0 = reads values currently applied to the internal logic of the device (default).
1 = reads buffered values that take effect on next assertion of I/O update.
0x05 [7:1] Unused Unused.
0 I/O update Writing a 1 to this bit transfers the data in the serial I/O buffer registers to the internal
control registers of the device. This is an autoclearing bit.

Rev. E | Page 24 of 32
Data Sheet AD9552
PLL Charge Pump and PFD Control (Register 0x0A to Register 0x0D)
Table 19.
Address Bit Bit Name Description
0x0A [7:0] Charge pump current control These bits set the magnitude of the PLL charge pump current. The granularity is
~3.5 μA with a full-scale magnitude of ~900 μA. Register 0x0A is ineffective unless
Register 0x0B[7] = 1. Default is 0x80, or ~448 μA.
0x0B 7 Enable SPI control of charge Controls functionality of Register 0x0A.
pump current 0 = the device automatically controls the charge pump current (default).
1 = charge pump current defined by Register 0x0A.
6 Enable SPI control of Controls functionality of Register 0x0D[7:6].
antibacklash period 0 = the device automatically controls the antibacklash period (default).
1 = antibacklash period defined by Register 0x0D[7:6].
[5:4] CP mode Controls the mode of the PLL charge pump.
00 = tristate.
01 = pump up.
10 = pump down.
11 = normal (default).
3 Enable CP mode control Controls functionality of Bits[5:4] (CP mode).
0 = the device automatically controls the charge pump mode (default).
1 = charge pump mode is defined by Bits[5:4].
2 PFD feedback input edge control Selects the polarity of the active edge of the PLL’s feedback input.
0 = positive edge (default).
1 = negative edge.
1 PFD reference input edge control Selects the polarity of the active edge of the PLL’s reference input.
0 = positive edge (default).
1 = negative edge.
0 Force VCO to midpoint frequency Selects VCO control voltage functionality.
0 = normal VCO operation (default).
1 = force VCO control voltage to midscale.
0x0C 7 Unused Unused.
6 CP offset current polarity Selects the polarity of the charge pump offset current of the PLL. This bit is ineffective
unless Bit 3 = 1.
0 = pump up (default).
1 = pump down.
[5:4] CP offset current Controls the magnitude of the charge pump offset current of the PLL as a fraction of
the value in Register 0x0A. This bit is ineffective unless Bit 3 = 1.
00 = 1/2 (default).
01 = 1/4.
10 = 1/8.
11 = 1/16.
3 Enable CP offset current control Controls functionality of Bits[6:4].
0 = the device automatically controls charge pump offset current (default).
1 = charge pump offset current defined by Bits[6:4].
2:0 Reserved
0x0D [7:6] Antibacklash control Controls the PFD antibacklash period of the PLL. These bits are ineffective unless
Register 0x0B[6] = 1.
00 = minimum (default).
01 = low.
10 = high.
11 = maximum.
[5:1] Unused Unused.
0 PLL lock detector power-down Controls power-down of the PLL lock detector.
0 = lock detector active (default).
1 = lock detector powered down.

Rev. E | Page 25 of 32
AD9552 Data Sheet
VCO Control (Register 0x0E to Register 0x10)
Table 20.
Address Bit Bit Name Description
0x0E 7 Calibrate VCO Initiates VCO calibration (this is an autoclearing bit). This bit is ineffective unless Bit 2 = 1.
6 Enable ALC Enables automatic level control (ALC) of the VCO.
0 = Register 0x0F[7:2] defines the VCO level.
1 = the device automatically controls the VCO level (default).
[5:3] ALC threshold Controls the VCO ALC threshold detector level from minimum (000) to maximum
(111).
The default is 110.
2 Enable SPI control of VCO Enables functionality of Bit 7 1.
calibration 0 = the device automatically performs VCO calibration (default).
1 = Bit 7 controls VCO calibration.
1 Boost VCO supply Selects VCO supply voltage.
0 = normal supply voltage (default).
1 = increase supply voltage by 100 mV.
0 Enable SPI control of VCO band Controls VCO band setting functionality.
setting 0 = the device automatically selects the VCO band (default).
1 = VCO band defined by Register 0x10[7:1].
0x0F [7:2] VCO level control Controls the VCO amplitude from minimum (00 0000) to maximum (11 1111). The
default is 10 0000.
These bits are ineffective unless 0x0E[6] = 0.
[1:0] Unused Unused.
0x10 [7:1] VCO band control Controls the VCO frequency band from minimum (000 0000) to maximum (111 1111).
The default is 100 0000.
0 Unused Unused.
1
An I/O update must be asserted after setting this bit and before issuing a SPI-controlled VCO calibration (writing 1 to Register 0x0E, Bit 7).

PLL Control (Register 0x11 to Register 0x19)

Table 21.
Address Bit Bit Name Description
0x11 [7:0] N The 8-bit integer divide value for the SDM. Default is 0x00.
Note that operational limitations impose a lower boundary of 64 (0x40) on N.
0x12 [7:0] MOD Bits[19:12] of the 20-bit modulus of the SDM.
0x13 [7:0] MOD Bits[11:4] of the 20-bit modulus of the SDM.
0x14 [7:4] MOD Bits[3:0] of the 20-bit modulus of the SDM.
Default is MOD = 1000 0000 0000 0000 0000 (524,288).
3 Enable SPI control of Controls output frequency functionality.
output frequency 0 = output frequency defined by the Y[3:0] pins (default).
1 = contents of Register 0x11 to Register 0x17 define output frequency via N, MOD, and FRAC.
2 Bypass SDM Controls bypassing of the SDM.
0 = allow integer-plus-fractional division (default).
1 = allow only integer division.
1 Disable SDM Controls the SDM internal clocks.
0 = normal operation (SDM clocks active) (default).
1 = SDM disabled (SDM clocks stopped).
0 Reset PLL Controls initialization of the PLL.
0 = normal operation (default).
1 = resets the counters and logic associated with the PLL but does not affect the output dividers.
0x15 [7:0] FRAC Bits[19:12] of the 20-bit fractional part of the SDM.
0x16 [7:0] FRAC Bits[11:4] of the 20-bit fractional part of the SDM.
0x17 [7:4] FRAC Bits[3:0] of the 20-bit fractional part of the SDM.
Default is FRAC = 0010 0000 0000 0000 0000 (131,072).
[3:1] Unused Write zeros to these bits when programming this register.
0 P1 divider Bit 5 of the 6-bit P1 divider for OUT1.

Rev. E | Page 26 of 32
Data Sheet AD9552
Address Bit Bit Name Description
0x18 [7:3] P1 divider Bits[4:0] of the 6-bit P1 divider for OUT1 (1 ≤ P1 ≤ 63). Do not set these bits to 000000. Default is
P1 = 10 0000 (32). The P1 bits are ineffective unless Register 0x19[7] = 1.
[2:0] P0 divider The 3-bit P0 divider for OUT1. The P0 divide value is as follows:
000 = 4 (default).
001 = 5.
010 = 6.
011 = 7.
100 = 8.
101 = 9.
110 = 10.
111 = 11.
The P0 bits are ineffective unless Register 0x19[7] = 1.
0x19 7 Enable SPI control of Controls functionality of OUT1 dividers.
OUT1 dividers 0 = OUT1 dividers defined by the Y[5:0] pins (default).
1 = contents of Register 0x17 and Register 0x18 define OUT1 dividers (P0 and P1).
[6:0] Unused Unused.

Input Receiver and Band Gap Control (Register 0x1A)

Table 22.
Address Bit Bit Name Description
0x1A 7 Receiver reset Input receiver reset control. This is an autoclearing bit.
0 = normal operation (default).
1 = reset input receiver logic.
[6:2] Band gap voltage adjust Controls the band gap voltage setting from minimum (0 0000) to maximum (1 1111).
Default is 0 0000.
1 Unused Unused.
0 Enable SPI control of band gap Enables functionality of Bits[6:2].
voltage 0 = the device automatically selects receiver band gap voltage (default).
1 = Bits[6:2] define the receiver band gap voltage.

XTAL Control (Register 0x1B to Register 0x1D)

Table 23.
Address Bit Bit Name Description
0x1B 7 Disable SPI control of XTAL Disables functionality of Bits[5:0].
tuning capacitance 0 = tuning capacitance defined by Bits[5:0].
1 = the device automatically selects XTAL tuning capacitance (default).
6 Unused Unused.
[5:0] XTAL tuning capacitor control Capacitance value coded as inverted binary (0.25 pF per bit); that is, 111111 is 0 pF,
111110 is 0.25 pF, and so on. The default value, 000000, is 15.75 pF.
0x1C [7:0] Unused Unused.
0x1D [7:3] Unused Unused.
2 Select 2× frequency multiplier Select/bypass the 2× frequency multiplier.
0 = bypassed (default).
1 = selected.
1 Unused Unused.
0 Use crystal resonator Automatic external reference select override.
0 = the device automatically selects the external reference path if an external
reference signal is present (default).
1 = the device uses the crystal resonator input whether or not an external reference
signal is present.

Rev. E | Page 27 of 32
AD9552 Data Sheet
OUT1 Driver Control (Register 0x32)
Table 24.
Address Bit Bit Name Description
0x32 7 OUT1 drive strength Controls the output drive capability of the OUT1 driver.
0 = weak.
1 = strong (default).
6 OUT1 power-down Controls power-down functionality of the OUT1 driver.
0 = OUT1 active (default).
1 = OUT1 powered down.
[5:3] OUT1 mode control OUT1 driver mode selection.
000 = CMOS, both pins active.
001 = CMOS, positive pin active, negative pin tristate.
010 = CMOS, positive pin tristate, negative pin active.
011 = CMOS, both pins tristate.
100 = LVDS.
101 = LVPECL (default).
110 = not used.
111 = not used.
[2:1] OUT1 CMOS polarity Selects the polarity of the OUT1 pins in CMOS mode.
00 = positive pin logic is true = 1, false = 0/negative pin logic is true = 0, false = 1 (default).
01 = positive pin logic is true = 1, false = 0/negative pin logic is true = 1, false = 0.
10 = positive pin logic is true = 0, false = 1/negative pin logic is true = 0, false = 1.
11 = positive pin logic is true = 0, false = 1/negative pin logic is true = 1, false = 0.
These bits are ineffective unless Bits[5:3] select CMOS mode.
0 Enable SPI control of OUT1 Controls OUT1 driver functionality.
driver control 0 = OUT1 is LVDS or LVPECL, per the OUTSEL pin (Pin 15) (default).
1 = OUT1 functionality defined by Bits[7:1].

Select OUT2 Source Control (Register 0x33)

Table 25.
Address Bit Bit Name Description
0x33 [7:4] Unused Unused.
3 OUT2 source Selects the signal source for OUT2.
0 = source for OUT2 is the output of the P1 divider (default).
1 = source for OUT2 is the input reference (REF or XTAL).
[2:0] Unused Unused.

Rev. E | Page 28 of 32
Data Sheet AD9552
OUT2 Driver Control (Register 0x34)
Table 26.
Address Bit Bit Name Description
0x34 7 OUT2 drive strength Controls the output drive capability of the OUT2 driver.
0 = weak.
1 = strong (default).
6 OUT2 power-down Controls power-down functionality of the OUT2 driver.
0 = OUT2 active (default).
1 = OUT2 powered down.
[5:3] OUT2 mode control OUT2 driver mode selection.
000 = CMOS, both pins active.
001 = CMOS, positive pin active, negative pin tristate.
010 = CMOS, positive pin tristate, negative pin active.
011 = CMOS, both pins tristate.
100 = LVDS.
101 = LVPECL (default).
110 = not used.
111 = not used.
[2:1] OUT2 CMOS polarity Selects the polarity of the OUT2 pins in CMOS mode.
00 = positive pin logic is true = 1, false = 0/negative pin logic is true = 0, false = 1 (default).
01 = positive pin logic is true = 1, false = 0/negative pin logic is true = 1, false = 0.
10 = positive pin logic is true = 0, false = 1/negative pin logic is true = 0, false = 1.
11 = positive pin logic is true = 0, false = 1/negative pin logic is true = 1, false = 0.
These bits are ineffective unless Bits[5:3] select CMOS mode.
0 Enable SPI control of OUT2 Controls OUT2 driver functionality.
driver control 0 = OUT2 is LVDS or LVPECL, per the OUTSEL pin (Pin 15) (default).
1 = OUT2 functionality defined by Bits[7:1].

Rev. E | Page 29 of 32
AD9552 Data Sheet

OUTLINE DIMENSIONS
5.10 0.30
5.00 SQ 0.25
PIN 1 4.90 0.18
INDICATOR PIN 1
25 32 INDICATOR
24 1
0.50
BSC
EXPOSED 3.25
PAD
3.10 SQ
2.95

17 8
16 9
0.50 0.25 MIN
TOP VIEW 0.40 BOTTOM VIEW
0.30 FOR PROPER CONNECTION OF
0.80 THE EXPOSED PAD, REFER TO
0.75 THE PIN CONFIGURATION AND
0.05 MAX FUNCTION DESCRIPTIONS
0.70 SECTION OF THIS DATA SHEET.
0.02 NOM
COPLANARITY
0.08
SEATING 0.20 REF
PLANE

112408-A
COMPLIANT TO JEDEC STANDARDS MO-220-WHHD.

Figure 30. 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ]

5 mm × 5 mm Body, Very Very Thin Quad
(CP-32-7)
Dimensions shown in millimeters

ORDERING GUIDE
Model 1 Temperature Range Package Description Package Option
AD9552BCPZ −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-7
AD9552BCPZ-REEL7 −40°C to +85°C 32-Lead Lead Frame Chip Scale Package [LFCSP_WQ] CP-32-7
AD9552/PCBZ Evaluation Board
1
Z = RoHS Compliant Part.

Rev. E | Page 30 of 32
Data Sheet AD9552

NOTES

Rev. E | Page 31 of 32
AD9552 Data Sheet

NOTES

©2009–2012 Analog Devices, Inc. All rights reserved. Trademarks and

registered trademarks are the property of their respective owners.
D07806-0-11/12(E)

Rev. E | Page 32 of 32