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Jameco Part Number 1550768

HCPL-7601/7611
CMOS/TTL Compatible, Low Input Current, High Speed,
High CMR Optocoupler

Data Sheet

Description
The HCPL-7601/11 is a low input current version of the
HCPL-2601/11 and 6N137 (without enable). The
optically coupled gates combine an AlGaAs high-
efficiency light emitting diode and an integrated high
gain photon detector to create a low input current
device for low power applications. The output of the
detector IC is an open collector Schottky-clamped
transistor. The internal shield provides a guaranteed
common mode transient immunity specification of
10,000 V/µs (HCPL-7611).
This unique design provides maximum ac and dc
circuit isolation while achieving CMOS and TTL
compatibility. The optocoupler ac and dc operational
parameters are guaranteed from -40°C to 85°C with
no derating required allowing trouble free system
performance. This product is suitable for high speed
logic interfacing, input/output buffering, and
applications that require low input-current switching
levels.
Schematic
IF ICC
VCC
2+ 8
IO
VO
6 • Digital isolation for A/D, D/A conversion
VF
GND
3- 5 • Pulse transformer replacement
HCPL-7601/11 SHIELD
Features
• Low input current version of HCPL-2601/11 and 6N137
• Wide input current range: IF = 2 mA to 10 mA
• CMOS/TTL compatible
• Guaranteed switching threshold: IF = 2 mA (max.)
• Internal shield for high Common Mode Rejection (CMR)
HCPL-7601: 5,000 V/µs (typical) at VCM = 50 V, IF = 4 mA
HCPL-7611: 15,000 V/µs (typical) at VCM = 1000 V, IF = 4 mA
• High speed: 10 Mbd typical
• Guaranteed ac and dc performance over temperature:
-40°C to 85°C
• IEC/EN/DIN EN 60747-5-2 approval: VIORM = 600 VRMS
• UL recognized: 3750 VRMS, 1 minute
• CSA accepted
• Low supply current requirement
• Low TPSK: 40 ns guaranteed
• Lead-free option “-000E”
Applications
• Isolated line receiver
• Simplex/multiplex data transmission
• Programmable logic controllers
• Computer-peripheral interface
• Microprocessor system interface
• Switching power supply
• Instrument input/output isolation
• Ground loop elimination

USE OF A 0.1 µF BYPASS CAPACITOR TRUTH TABLE

CONNECTED BETWEEN PINS 5 AND 8 (POSITIVE LOGIC)
IS REQUIRED (SEE NOTE 1). LED OUTPUT
ON L
OFF H

CAUTION: The small device geometries inherent to the design of this bipolar component increase the
component’s susceptibility to damage from electrostatic discharge (ESD). It is advised that normal static
precautions be taken in handling and assembly of this component to prevent damage and/or degradation
which may be induced by ESD.
The HCPL-7601/11 family offers
many features that are especially
beneficial to system designers. The
low input current requirements
and guaranteed switching
threshold (2 mA max.) allows the
LED to be driven directly by any
standard high-speed CMOS gate
(e.g. 74HC/HCT). This will simplify
designs by eliminating the need for
special driver circuits and result in
lower part counts and greater
system reliability while freeing up
valuable printed circuit board
space.
The wide current input range of
2 mA to 10 mA and guaranteed ac
and dc performance over a wide
temperature range will also
simplify designs. Low supply
current requirements mean lower
power dissipation allowing for the
use of a smaller, less expensive
power supply. The high speed
(10 Mbd typ.) and low propagation
delay skew (Tpsk ≤ 40 ns
guaranteed) allow for easier
design of high speed parallel
applications. The world-wide
regulatory approval (UL/CSA/IEC/
EN/DIN EN 60747-5-2) will
facilitate the acceptance of the end
product in international markets.
2
Regulatory Information
The HCPL-7601 and HCPL-7611
have been approved by the
following organizations:
UL
Approved under UL 1577,
component recognition FILE
E55361).
IEC/EN/DIN EN 60747-5-2
Approved under:
IEC 60747-5-2:1997 + A1:2002
EN 60747-5-2:2001 + A1:2002
DIN EN 60747-5-2 (VDE 0884
Teil 2):2003-01
This optocoupler is suitable for
“safe electrical isolation” only
within the safety limit data.
Maintenance of the safety data
shall be ensured by means of
protective circuits.
Can be used for safe electrical
separation between ac mains and
SELV (safety extra-low voltage) in
equipment according to the
following specifications:
DIN VDE 0804/05.89
DIN VDE 0160/05.88
Reference voltage (VDE 011b Tab
4): 630 Vac.
CSA
Approved under CSA22.2 No. 0 -
General Requirements, Canadian
Electrical Code, Part II; and CSA
Component Acceptance Notice #5,
File CA 88324.
Absolute Maximum Ratings
(No Derating Required up to 85° C)
Storage Temperature ....................................................... -55° C to +125° C
Operating Temperature ..................................................... -40° C to +85° C
Lead Solder Temperature ................................................... 260° C for 10 s
(1.6 mm below seating plane)
Average Input Current - IF (See Note 2.) ........................................ 20 mA
Reverse Input Voltage - VR ...................................................................... 3 V
Supply Voltage - VCC ........................................... 7 V (1 Minute Maximum)
Output Collector Current - IO ........................................................... 50 mA
Output Collector Power Dissipation .............................................. 85 mW
Output Collector Voltage - VO* ............................................................... 7 V
Total Package Power Dissipation .................................................. 250 mW
*Selection for higher output voltage up to 20 V is available.

Recommended Operating Conditions

Parameter Symbol Min. Max. Units
Input Voltage, Low Level VFL 0 0.8 V
Input Current, High Level IFH 2 10 mA
Supply Voltage, Output VCC 4.5 5.5 V
Fan Out @ RL= 1 kΩ N 5 TTL
Loads
Operating Temperature TA -40 85 °C
Output Pull-up Resistor RL 330 4k Ω

3
Package Outline Drawing
Standard DIP Package

9.40 (0.370)
9.90 (0.390)

8 7 6 5
TYPE NUMBER* 0.18 (0.007)
6.10 (0.240) 0.33 (0.013)
A 7601 DATE CODE
6.60 (0.260)
YYWW 7.36 (0.290)
7.88 (0.310) 5° TYP.
PIN ONE 1 2 3 4

1.78 (0.070) MAX.

1.19 (0.047) MAX. DIMENSIONS IN MILLIMETERS AND (INCHES).

3.56 ± 0.13 4.70 (0.185) MAX. PINOUT DIAGRAM

(0.140 ± 0.005)

PIN ONE N/C 1 8 VCC

0.51 (0.020) MIN.
2.92 (0.115) MIN. ANODE 2 7 N/C

CATHODE 3 6 VOUT
0.76 (0.030) 0.65 (0.025) MAX.
1.24 (0.049) N/C 4 5 GND
2.28 (0.090)
2.80 (0.110)

*TYPE NUMBER FOR: HCPL-7601 = 7601 NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.
HCPL-7611 = 7611

Gull Wing Surface Mount Option 300*

8 7 6 5

DIMENSIONS IDENTICAL TO
STANDARD DIP EXCEPT AS NOTED.

1 2 3 4

9.65 ± 0.25
(0.380 ± 0.010)
7.62 ± 0.25
(0.300 ± 0.010)
0.255 ± 0.075
(0.010 ± 0.003)

0.635 ± 0.25
(0.025 ± 0.010)
0.51 ± 0.130
(0.020 ± 0.005) 12° NOM.

* REFER TO OPTION 300 DATA SHEET FOR MORE INFORMATION.

NOTE: FLOATING LEAD PROTRUSION IS 0.5 mm (20 mils) MAX.

4
Solder Reflow Temperature Profile

300
PREHEATING RATE 3°C + 1°C/–0.5°C/SEC.
REFLOW HEATING RATE 2.5°C ± 0.5°C/SEC. PEAK
PEAK
TEMP.
TEMP.
245°C
240°C
PEAK
TEMP.
230°C
TEMPERATURE (°C)

200
2.5°C ± 0.5°C/SEC.
SOLDERING
30 TIME
160°C 200°C
150°C SEC.
140°C
30
3°C + 1°C/–0.5°C SEC.

100
PREHEATING TIME
150°C, 90 + 30 SEC. 50 SEC.

TIGHT
TYPICAL
ROOM
TEMPERATURE LOOSE

0
0 50 100 150 200 250

TIME (SECONDS)

Recommended Pb-free IR Profile

TIME WITHIN 5 °C of ACTUAL

PEAK TEMPERATURE
tp
20-40 SEC.
260 +0/-5 °C
Tp
217 °C
TL
RAMP-UP
TEMPERATURE

3 °C/SEC. MAX. RAMP-DOWN

150 - 200 °C 6 °C/SEC. MAX.
Tsmax
Tsmin
ts tL
PREHEAT 60 to 150 SEC.
60 to 180 SEC.

25
t 25 °C to PEAK
TIME
NOTES:
THE TIME FROM 25 °C to PEAK TEMPERATURE = 8 MINUTES MAX.
Tsmax = 200 °C, Tsmin = 150 °C

5
IEC/EN/DIN EN 60747-5-2 Insulation Characteristics
Description Symbol Characteristics Unit
Installation classification per DIN VDE 0109*/12.83, Table 1
for rated mains voltage ≤300 VRMS I-IV
for rated mains voltage ≤600 VRMS I-III
Climatic Classification 40/85/21
Pollution Degree (DIN VDE 0109/12.83)* 2
Maximum Working Insulation Voltage VIORM 600 VRMS
848 Vpeak
Input to Output Test Voltage, Method b** VPR = 1.6 X VIORM VPR 960 VRMS
Production test with tP = 1 sec,
Partial discharge < 5 pC 1357 Vpeak
Input to Output Test Voltage, Method a** VPR = 1.2 X VIORM VPR 720 VRMS
Production test with tP = 60 sec,
Partial discharge < 5 pC 1018 Vpeak
Highest Allowable Overvoltage**
(Transient Overvoltage, tTR = 10 sec) VTR 6000 Vpeak
Safety-limiting values (Maximum values allowed in the event
of a failure, also see Figure 16)
Case Temperature TSI 175 °C
Input Power PSI,Input 80 mW
Output Power PSI,Output 250 mW
Insulation Resistance at TSI, VIO = 500 V RIS ≥1011 Ω
* This part may also be used in Pollution Degree 3 environments where the rated mains voltage is ≤ 300 VRMS (per DIN VDE 0190/12.83).
** Refer to the front of the optocoupler section of the current Optoelectronics Designers Catalog for a more detailed description of IEC/EN/DIN EN
60747-5-2 and other product safety regulations.

Insulation Related Specifications

Parameter Symbol Value Units Conditions
Minimum External Clearance L (IO1) 7.0 mm Measured from input terminals
(External Air Gap) to output terminals
Minimum External Creepage L (IO2) 8.0 mm Measured from input terminals
(External Tracking) to output terminals
Minimum Internal Clearance 0.5 mm Through insulation distance
(Internal Plastic Gap) from conductor to conductor
Comparative Tracking Index CTI 175 V DIN IEC 112/VDE 303 P1
Isolation Group (per DIN VDE 0109) IIIa Material Group

6
Electrical Specifications
Over recommended temperature (TA = -40°C to 85°C) unless otherwise specified. (See note 1.)
Parameter Symbol Min. Typ.* Max. Units Test Conditions Fig. Note
Input Threshold ITH 1 2 mA VCC = 5.5 V, IO ≥ 13 mA, 5
Current VO = 0.6 V
High Level Output IOH 3 100 µA VCC = 5.5 V, VO = 5.5 V 1
Current VFL = 0.8 V
Low Level Output VOL 0.35 0.6 V VCC = 5.5 V, IF = 2 mA, 2, 4,
Voltage IOL (Sinking) = 13 mA 6
High Level Supply ICCH 4.75 7 mA VCC = 5.5 V, IF = 0 mA
Current
Low Level Supply ICCL 6 10 mA VCC = 5.5 V, IF = 4 mA
Current
Input Forward VF 1.2 1.5 1.85 V IF = 4 mA 3
Voltage
Input Reverse BVR 3 V IR = 100 µA
Breakdown Voltage
Input Capacitance CIN 72 pF VF = 0, f = 1 MHz
Input Diode ∆VF/∆TA -1.6 mV/°C IF = 4 mA 3
Temperature
Coefficient
Input-Output VISO 3750 VRMS RH ≤ 50%, t = 1 min. 3, 9
Insulation TA = 25°C
Resistance RI-O 1012 1013 Ω TA = 25°C VI-O = 500 V 3
(Input-Output)
1011 TA = 100°C
Capacitance CI-O 0.6 pF f = 1 MHz, VI-O = 0 Vdc 3
(Input-Output)
*All typicals at TA = 25°C, VCC = 5 V.

7
Switching Specifications
Over recommended temperature (TA = -40°C to 85°C), VCC = 5 V, CL = 15 pF

Parameter Symbol Device Min. Typ.* Max. Unit Test Conditions Fig. Note
Propagation tPLH 25 58 75 TA = 25°C IF = 2 mA, 7, 8, 4, 10
Delay Time 100 RL = 1 kΩ 10
to High 25 55 75 TA = 25°C IF = 4 mA
Output 100 RL = 350 Ω
Level
Propagation 35 73 100 ns TA = 25°C IF = 2 mA 7, 9, 5, 10
Delay Time tPHL 120 RL = 1 kΩ 10
to Low 25 57 75 TA = 25°C IF = 4 mA
Output 100 RL = 350 Ω
Level
Pulse Width |tPHL-tPLH| 16 55 IF = 2 mA RL = 1 kΩ 11, 4, 5
Distortion 4 40 IF = 4 mA RL = 350 Ω 12
Propagation tPSK 75 IF = 2 mA RL = 1 kΩ 6, 10
Delay Skew 40 IF = 4 mA RL = 350 Ω
Output Rise trise 58 IF = 2 mA RL = 1 kΩ 13
Time 24 IF = 4 mA RL = 350 Ω
(10% - 90%)
Output Fall tfall 10 IF = 2 - 4 mA RL = 350 - 1 kΩ 13
Time
(10% - 90%)
Common CMH HCPL- 1,000 5,000 VCM = 50 V IF = 0 mA 14 7
Mode 7601 Vo(min) = 2 V
Transient RL = 350 - 1 kΩ
Immunity at HCPL- 10,000 15,000 VCM = 1000 V TA = 25°C
High Output 7611
Level
Common CML HCPL- 1,000 5,000 V/µs IF = 2 - 4 mA Vo(max) = 0.8 V 14 8
Mode 7601 RL = 350 - 1 kΩ TA = 25°C
Transient VCM = 50 V
Immunity at HCPL- 2,000 5,000 IF = 2 mA
Low Output 7611 RL = 1 kΩ
Level VCM = 1000 V
10,000 15,000 IF = 4 mA
RL = 350 Ω
VCM = 1000 V

*All typicals at TA = 25°C, VCC = 5 V.

8
Notes: 5. The tPHL propagation delay is measured assumes that good board layout proce-
1. Bypassing of the power supply line is from the 50% point on the leading edge of dures were followed to reduce the
required with a 0.1 µF ceramic disc the input pulse to the 1.5 V point on the effective input/output capacitance as
capacitor adjacent to each optocoupler, as leading edge of the output pulse. shown in Figure 15.
illustrated in Figure 15. Total lead length 6. tPSK is equal to the worst case difference in 9. In accordance with UL and CSA
between both ends of the capacitor and tPHL and/or tPLH that will be seen between requirements, each optocoupler is proof
the isolator pins should not exceed 10 mm. units at any given temperature within the tested by applying an insulation test
2. Peaking circuits may produce transient operating condition range. voltage ≥ 5000 Vrms for one second
input currents up to 50 mA, 50 ns maximum 7. CMH is the maximum tolerable rate of rise (leakage detection current limit,
pulse width, provided average current does of the common mode voltage to assure II-O ≤ 5 µA).
not exceed 20 mA. that the output will remain in a high logic 10. AC performance at IF = 4 mA is
3. Device considered a two terminal device: state (i.e., VOUT > 2.0 V). approximately equivalent to the HCPL-
pins 1 , 2, 3, and 4 shorted together, and 8. CML is the maximum tolerable rate of fall 2601/11 at IF = 7.5 mA for comparison
pins 5, 6, 7, and 8 shorted together. of the common mode voltage to assure purposes.
4. The tPLH propagation delay is measured that the output will remain in a low logic
from the 50% point on the trailing edge of state (i.e., VOUT < 0.8 V). This specification
the input pulse to the 1.5 V point on the
trailing edge of the output pulse.
IOH – HIGH LEVEL OUTPUT CURRENT – µA

VOL – LOW LEVEL OUTPUT VOLTAGE – V

15 0.6 10-1

IF – INPUT FORWARD CURRENT – A

VCC = 5.5 V VCC = 5.5 V TA = 25° C
VO = 5.5 V IF = 2 - 4 mA
VIN = 0.8 V 10-2
0.5
10 TA = 85° C TA = -40° C
-3
10
IO = 16.0 mA
0.4
-4
10
5
IO = 13.0 mA
0.3 -5
10

-6
0 0.2 10
-60 -40 -20 0 20 40 60 80 100 -60 -40 -20 0 20 40 60 80 100 0.8 1.0 1.2 1.4 1.6 1.8 2.0

TA – TEMPERATURE – °C TA – TEMPERATURE – °C VF – INPUT FORWARD VOLTAGE – V

Figure 1. High level output current vs. Figure 2. Low level output voltage vs. Figure 3. Typical input forward current vs.
temperature. temperature. input forward voltage.
IOL – LOW LEVEL OUTPUT CURRENT – mA
ITH – INPUT THRESHOLD CURRENT – mA

5.0 2.5 55
VCC = 5.0 V
VO = 0.6 V
VO – OUTPUT VOLTAGE – V

IO = 13.0 mA
4.0 2.0 50
RL = 350 Ω
IF = 4 mA
RL = 1 kΩ
3.0 1.5 45
RL = 4 kΩ
IF = 2 mA
2.0 1.0 40

1.0 0.5 35
VCC = 5 V
VOL = 0.6 V
0 0 30
0 0.5 1.0 1.5 2.0 -60 -40 -20 0 20 40 60 80 100 -50 -30 -10 0 10 30 50 70 90

IF – FORWARD INPUT CURRENT – mA TA – TEMPERATURE – °C TA – TEMPERATURE – °C

Figure 4. Output voltage vs. forward input Figure 5. Input threshold current vs. Figure 6. Low level output current vs.
current. temperature. temperature.

9
 +5 V
PULSE GEN. IF
ZO = 50 Ω 1 VCC 8
tf = tr = 5 ns
0.1µF
2 7 RL
BYPASS
INPUT OUTPUT VO
MONITORING 3 6 MONITORING
NODE NODE 120
*CL VCC = 5 V

tPLH – PROPAGATION DELAY – ns

4 5 110 TA = 25° C
RM GND
100 IF = 2-4 mA, RL = 4 kΩ

90
80
*CL IS APPROXIMATELY 15 pF WHICH INCLUDES
PROBE AND STRAY WIRING CAPACITANCE. 70
IF = 2-4 mA, RL = 1 kΩ
60
IF
INPUT 50
50% IF
IF IF = 2-4 mA, RL = 350 Ω
40
tPHL tPLH
30
OUTPUT -50 -30 -10 0 10 30 50 70 90
VO 1.5 V TA – TEMPERATURE – °C

Figure 7. Test circuit for tPHL and tPLH. Figure 8. tPLH – Propagation delay vs.
temperature.

PULSE WIDTH DISTORTION (tPHL- tPLH) – ns

100 120 30
VCC = 5 V VCC = 5 V IF = 2 mA, RL = 350 Ω
tPHL – PROPAGATION DELAY – ns

TA = 25° C
tP – PROPAGATION DELAY – ns

RL = 350 – 4 kΩ 110
90 TA = 25° C 15
TPLH @ RL = 4 kΩ IF = 2 mA, RL = 1 kΩ
100
IF = 4 mA, RL = 350 Ω
80
90 0
IF = 2 mA
70 80 IF = 4 mA, RL = 1 kΩ
TPHL @ RL = 350 – 4 kΩ -15
60 70
TPLH @ RL = 1 kΩ
IF = 2 mA, RL = 4 kΩ
IF = 4 mA 60 -30
50
50
40 TPLH @ RL = 350 Ω -45
40
IF = 4 mA, RL = 4 kΩ
30 30 -60
-50 -30 -10 0 10 30 50 70 90 1 2 3 4 5 6 7 8 9 10 11 -50 -30 -10 0 10 30 50 70 90

TA – TEMPERATURE – °C IF – INPUT CURRENT – mA TA – TEMPERATURE – °C

Figure 9. tPHL – Propagation delay vs. Figure 10. Propagation delay vs. input Figure 11. Pulse width distortion vs.
temperature. current. temperature.
PULSE WIDTH DISTORTION (tPHL - tPLH) – ns

30 330
tFALL
tRISE, tFALL – RISE, FALL TIME – ns

VCC = 5 V VCC = 5.0 V

20 TA = 25° C 320 IF = 2 – 4 mA tRISE
10 310

0 300 RL = 4 kΩ
RL = 350 Ω 290
-10
RL = 1 kΩ
60
-20
RL = 1 kΩ
-30
40
-40
RL = 4 kΩ RL = 350 Ω
-50 20
-60 RL = 350 Ω, 1 kΩ, 4 kΩ

-70 0
0 2 4 6 8 10 12 -60 -40 -20 0 20 40 60 80 100

IF – INPUT CURRENT – mA TA – TEMPERATURE – °C

Figure 12. Pulse width distortion vs. input Figure 13. Rise and fall time vs. temperature.
current.

10
IF VCC 8 +5 V
1

B 0.1 µF
2 7 BYPASS RL
A OUTPUT VO
VFF 3 6 MONITORING
NODE

4 5
GND

VCM
+ _
PULSE
GENERATOR
ZO = 50 Ω

VCM (PEAK)
VCM
0V
SWITCH AT A: IF = 0 mA
5V CMH
VO VO (MIN.)
SWITCH AT B: IF = 2 or 4 mA
VO VO (MAX.)
0.35 V CML

Figure 14. Test circuit for common mode transient immunity and typical waveforms.

250
220
200

PSI, OUTPUT – mW
VCC BUS 150
PSI, INPUT – mW

50 100
0.1µF
40
30
50
OUTPUT 20
10
GND BUS 0 0
0 25 50 75 100 125 140 150 175
10 mm MAX.
(SEE NOTE 1) TA – TEMPERATURE – °C

Figure 15. Recommended printed circuit board layout. Figure 16. Dependence of safety-limiting data on
ambient temperature.

11
 (INPUT DRIVE CIRCUIT) DEVICE

VCC = 5 V 8 VCC2
I kΩ
390
(MAX.)

2 6

2N3906** 0.1 µF
BYPASS
*74LS04 3 5 GND 2
SHIELD

*ANY TTL GATE **ANY PNP TRANSITOR

CMOS OR TTL INTERFACE CIRCUIT

1N4148
VCC = 5 V VCC = 5 V
620 Ω
(MAX.)
2
I kΩ
(MAX.)
*74HC04 *74LS05

*ANY CMOS HC OR HCT GATE *ANY OPEN COLLECTOR TTL

OR OPEN DRAIN CMOS GATE
CMOS DRIVE CIRCUIT FOR INPUT DRIVE CIRCUIT
LOW POWER APPLICATIONS FOR HIGH CMR APPLICATIONS

Figure 17. Recommended interface circuits.

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Avago, Avago Technologies, and the A logo are trademarks of Avago Technologies, Pte. in the United States and other countries.
Data subject to change. Copyright © 2006 Avago Technologies Pte. All rights reserved. Obsoletes 5989-0309EN
5989-2128EN March 13, 2006