NMIS-L-3000

32-BIT INPUTS & 32-BIT OUPUTS CARD

Getting Started
The NMIS-3000 32-In 32-Out Card provides a JEDSTACK™ computer system with 32-bits of latched
outputs and 32-bits of latchable inputs. The inputs and outputs are arranged to easily connect to control
points. Two 34 conductor ribbon cable, or 68 individual wires can be used to connect to the 64 I/O points
with 2 power and 2 ground connections. The NMIS-3000 is 2" x 4". The NMIL-3000 is identical to the
NMIS-3000, except for being slightly longer. Mounting tabs are added at each end of the board. The
NMIL-3000 is, therefore, 2" x 4.75". References to the NMIS-3000 also apply to the NMIL-3000, with
exception of references relative to these extra mounting tabs.

To make use of the NMIS-3000 requires board configuration, physical installation and the addition of the
necessary software. The remainder of this section deals with these steps in greater detail. The user will
probably want to read this section once, then scan the Circuit Description and Programming chapters
before taking any action, then again return to this section and follow the suggested installation procedure.
Finally, the other sections will tell more on the board's design and mechanical board mounting.

A few moments spent examining the NMIS-3000 will be useful. The 2x4 inch format of the NMIS board
series determines the physical outline of this board. (The NMIL-3000 has an active component area of 2x4
inches, but also has two mounting tabs, giving an overall size of 2x4.75 inches.) Close observation of the
board reveals the following features. Connector J1 and J2 runs along the left side of the board. The
individual I/O points are labeled on the board, grouped into ports of 8 lines each, Ports A through H. Next
to these connectors runs a vertical row of 8 bit latches. Four are 74HC573's which are used as input gates
with the optional externally controlled latching and four are 74HC574's which are used as output latches.
Further to the right of the latches are bus interface chip. A bi-directional transceiver, 74HC245, buffers the
data bus from the loads of the 74HC573 and 74HC574's. A 74HC32 is used in conjunction with a
74HC138 to generate the chip select and timing information to operate the latches and drivers. A Vertical
Stacking Connector in the lower, right-hand corner (top view) provides connections to the processor's
address and data bus, control signals, 5 Volt power and ground. Address decoding of the I/O chip's space
in memory is accomplished by two octal comparators, 74HC688's, and 16, two position jumpers. Each
jumper setting corresponds to the state of a particular address line. The NMIS-3000 occupies 4 addresses.
Any 4 byte boundary in the 64K address space of the JEDSTACK™ processor's bus can be selected by
correct jumper placement.

To install the NMIS-3000, the following procedure is suggested:

1) select the base address (or accept the factory default)

2) set the jumpers for the selected address (or check the factory default)
3) set the Jumper "A" for normal (+5V) or latched (external signal) operation
4) set the Jumper "B" for normal (ground) or controlled drive (external signal) operation
5) set the Jumper "C" for processor type
6) verify the selected address is free of memory conflict before installing the board
7) turn off the power to the system
8) install the board connecting the VSC
9) verify correct alignment visually
10) turn on system power
11) verify the presence of the board in memory
12) select the program or program segments to be used
13) install the program or program segments to be used

Selection of the base address for the board will depend greatly on the processor card being used, system
design, and how many other boards are being used in the system. For instance, the most popular CPU to
date that can use the NMIS-3000 is the F68HC11 based NMIS-0021. Although there could probably be
valid reasons for mapping the 32 Bit I/O almost anywhere in the 64K byte address space, a likely place
would be in the B000 hex area above the registers. If no additional 2x4"s™ cards were in the system, B040

2
hex is a likely choice. On the other hand, an address above the EEPROM at BC00 hex would have more
merit for both the NMIS-0021 CPU and the NMIX-0022 alike. The NMIX-0022 CPU's have a 68HC24
PRU that is loosely decoded in the B000 through B7FF hex range. Putting the 32 Bit I/O at BC00 would
clear any possible memory conflicts there, while having minimal impact on the greater goal of leaving
large areas of contiguous memory unbroken. The older NMIX-0011 and NMIX-0012 CPU's can use the
NMIS-3000, but these boards use the 0100 hex page for I/O. In this case an address such as 0110 hex
would be appropriate. Ultimately, this is a choice of the system designer and the practical restraints of the
processor used.

Once an address is selected, it is easy to set the jumpers. Convert the address to a binary number and,
starting left to right, set the jumper corresponding to each bit in the binary number to a "1" or "0". Refer to
Appendix A for graphic examples.

The center pin on Jumper "A" is the latch control pin. If the input readings are to continuously follow the
pins, Jumper "A" should be in the +5V position (toward the top edge, wtih VSC in lower right-hand corner,
top view). To latch the inputs, Jumper "A" must be removed and an external signal provided to control the
latching. If this were an output compare on the F68HC11 for instance, the state of all 32 input lines could
be attained by the processor each time the counter compare caused the associated output pin to toggle low.
The readings would be held until the line returned high again. When the line is high the 74HC573's are
transparent, passing the pins current state directly to the processors bus.

Jumper "B" controls the output port drivers. When it is set to ground (toward the bottom edge, wtih VSC in
lower right-hand corner, top view) the latches of the 74HC574's are enabled and it functions as a simple
output board. When it is set to +5V (toward the top edge of the board) the drivers of the 74HC574's are
disabled. Jumper "B" can be removed and an external signal provided to the center pin on Jumper "B" to
control the latching.

Selecting and setting the jumper marked "C" for correct processor type is straight forward. Jumper "C" has
two settings marked on the silkscreen, "65" and "80". If the processor type is a 6500 or 6800 type (such as
the F68HC11) the jumper should be in the "65" position. If the processor type is a 8031 or Z80 type (such
as the 8052AH) the jumper should be in the "80" position. The "C" jumper either applies the "E" clock or
+5V to the chip select gating. The "E" clock is necessary for correct timing information when using a 6500
or 6800 type processor on the JEDSTACK™ bus. To determine which type processor is which, check the
memory interface signals. If the processor itself has a RD and a WR line, it is an "80" type. If the processor
has a R/W line and a clock signal such as E or 02 (pronounced phase two), it is a "65" type.

The factory default address setting for the NMIS-3000 is 8000 hex and will be used in these examples.
Substitute the corrected value in place of 8000 hex if the base address has been modified. It is advisable to
verify the selected address is free of memory conflicts before installing the board. First look at the memory
addresses the 32 Bit I/O will occupy to see if other devices are already mapped there. These could cause
interference, called, bus contention. Dumping the area around 8000 will normally show an ascending
number pattern if no memory interferes, as is shown below in a dump by an F68HC11.

COLD
Max-FORTH V3.3
HEX OK
8000 40 DUMP
8000 0 1 2 3 4 5 6 7 8 9 A B C D E F
8010 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
8020 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
8030 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
OK

Turn off power to the system and carefully align the 34 pin Vertical Stacking Connector (VSC) with the
board to be mated. The VSC is a "straight through" connector so the NMIS-3000 can be added to the top or

3
the bottom of a board stack. It's easy to get a misalignment, so double check the fit by looking at the
connector from all four directions for pins that are not correctly mated. Use the provided 4-40 male/female
screw 3/4" brass hex standoffs in the hole adjacent to the VSC to increase mechanical rigidity. Turn the
system power on and examine the memory area around 8000 hex again.

COLD
Max-FORTH V3.3
HEX OK
8000 40 DUMP
8 0 0 0 FF FF FF FF 4 5 6 7 8 9 A B C D E F
8010 10 11 12 13 14 15 16 17 18 19 1A 1B 1C 1D 1E 1F
8020 20 21 22 23 24 25 26 27 28 29 2A 2B 2C 2D 2E 2F
8030 30 31 32 33 34 35 36 37 38 39 3A 3B 3C 3D 3E 3F
OK

Notice the first 4 locations now have different values. These are the registers of the 74HC573's chips. Their
contents will, of course, vary depending on the power up settings that happen to occur in the chip and what
external connections are doing to the inpur pins. If the ascending pattern has not changed, the processor
can not "see" the NMIS-3000 in its memory map. Recheck the address jumpers for proper settings and the
VSC for proper connection.

The NMIS-3000 is now running and communicating as it should.

Circuit Description

The NMIS-3000 32-In 32-Out Card is designed to stack on the 2x4"s™ NMIS Series, the "100 Squared"™
NMIX and the "Generic Target Computer"™ NMIT Series (with the Vertical Stacking Connector added to
the latter) of single board computers. The "JEDSTACK"™ provides the interface signals to the board
including address lines, data lines, control lines and 5 Volt power and ground. The fast HC devices allows
access times approaching 90nS.

The addressing of the octal latches on the NMIS-3000 is sensed by two 74HC688 (U1 and U2) octal
comparators that decode the 14 address lines (A15 - A4) and one control line (AS for F68HC11 systems,
CSEX for R65F11 systems) to select only four active locations out of a 64K address space.

The address locations where the card is active is user set by the arrangement of addressing jumpers. Each
significant address line can be sensed for high or low condition. (Jumpers were used rather than switches
for power savings reasons. Generally, schemes that employ switches use pull up resistors that are switched
to ground for a "0" and left open for a "1". When the switches are closed this means the resistors are
hooked from the +5V rail to ground. While this gives the comparator inputs a suitable logic level "1" or
"0", the selection of "0" wastes power. The design using jumpers hook the CMOS comparator inputs
directly to +5V or Ground without wasting power.)

When one of the four set addresses is selected by the processor, the 74HC688's generate a chip select to the
74HC138. This signal is also coupled back on the VSC via diode D1 to the MEMDIS pin. Additionally this
signal is OR'ed with Output Enable to create the signal that reverses the 74HC245 bus transceiver and
causes it to drive data back to the processor during a read.

The 74HC138 uses this chip select signal for its negative enables and the output of Jumper "C" for its one
positive enable. Jumper "C" will either provide a constant high if set for "80" type processors, or the "E"
clock if set for 6500 and 6800 type processors. The "E" clock is necessary for correct timing information
when using a 6500 or 6800 type processor on the JEDSTACK™ bus. If the processor type is a 6500 or
6800 type (such as the F68HC11) the jumper should be in the "65" position. If the processor type is a 8031
or Z80 type (such as the 8052AH) the jumper should be in the "80" position.

4
The address inputs to the 74HC138 include two real address lines, A0 and A1, and the R/W' line. The use
of the R/W' line allows selection between reading of the input latches or writing the output latches. The
eight decoded chip selects go to the latches, four to the 74HC574 output latches and four to the 74HC573
input latches.

The 74HC573's and 74HC574's are connected to the Data Bus by way of the 74HC245. The 74HC245 acts
as bus buffers, limiting the load placed on the Data Bus to only one HC load (rather than eight). This
increases the number of boards that can be put on the system than otherwise due to fan out limitations. By
way of this bus driver the 74HC573's send data to the processor and the 74HC574's accept data from the
processor.

The drivers on the 74HC574's are controlled by the signal from Jumper "B". When it is set to ground the
drivers on the 74HC574's are enabled. The drivers of the 74HC574's will control the level on their I/O pins
(providing there is no contention from attached equipment). When Jumper "B" is set to +5V the drivers on
the 74HC574's are disabled and the I/O pins are controlled by whatever external devices may be driving
them.

The center pin on Jumper "A" is the 74HC573's latch enable. When the line is high the 74HC573's are
transparent, passing the I/O pins' current state directly to the processor. Jumper "A" can be removed and an
external signal provided to control the latch enable. When the line is high, the 74HC573's are transparent.
When the line goes low the readings are latched at their state at the time. They will continue to be read in
that state despite any changes on the external I/O pins until the line returns high again.

Output drive capability of the 74HC574 list a sink and a source current of 25 mA. at normal 5 volt
operation. Worse case minimums at 25 degrees C with a 4.5 Volt supply show a sink current capability of
17 mA. at an output voltage of 1.5 Volts and a source capability of 15 mA. at an output voltage of 3.0
Volts. (Caution: The total current rating for the package is considerably less than the sum of all the rated
drivers. This means trying to sink all the drivers at once at full current is beyond the total system rating for
the part.)

When driving other logic, the HC outputs have voltages of 0.1V and VCC-0.1V for an output current of 20
uA. or the equivalent of 20 HC loads. The output drives for standard drive devices are such that they can
drive ten LSTTL loads and maintain the output voltage under or equal to 0.4 V across the full temperature
range. The maximum rated output current given on the individual pins, as mentioned, is 25 mA.. The
output short circuit currents of these devices will typically exceed these limits. The manufacturer reports
outputs can, however, be shorted for short periods of time for logic testing, if the maximum package power
dispassion of 500 mW is not violated.
Programming

The NMIS-3000 is a fairly straight forward I/O device with four parallel ports of eight bits each. It uses
four consecutive addresses. Each address can be fetched or stored by a byte access. In high level FORTH,
two addresses can be fetched or stored "at once" by using @ and ! instead of the byte oriented C@ and
C! . In C, the corresponding functions are peek() and poke(), and bytewise peekb() and PEEK
command and set with the POKE command.

When programming the NMIS-3000 it is necessary to know how the physical address and bit position
within the address affects the addressing of each bit. Further, each bit has an assigned pin on connectors J1
o r J2 .

The NMIS-3000's lowest addressed port has the least significant 8 bits. The least significant bit in this
location, PA0, controls pin-33 of J1. The second bit in that location, PA1, controls pin-33 of J1 and so on.
After the most significant bit in that byte, PA7 controlling pin-27, the least significant bit in the next
address in memory, PB0, controls output pin-28 and so on.

5
There is no read back provided on the output ports. The input ports and output ports share the same
addresses. The address to read Port A is the same address as the one to write Port E. Instructions which
perform read-modify-write instructions will not work for this configuration. A copy of the last written
output value should be kept in a separate variable, if single bit modifications are desired. The copy can be
read modified and then written to the output port.

Some useful program segments are shown in Appendix B.

Board Mounting

6
The NMIS-3000 has three mounting holes, one in the corner nearest the 34 pin Vertical Stacking
Connector which is the main mechanical mounting hole, and two in the opposite corners used for
alignment. Each hole is drilled at .110 inches. This will allow passage of a 4-40 screw shaft.

If additional 2x4"s™ are to be used they may be stacked above or below, as desired, on the female or male
side of the Vertical Stacking Connector respectively. A simple hex 3/4 inch standoff with a male screw on
one end and a female threaded hole on the other is the ideal interboard connection device. The Vertical
Stacking Connector was designed to work with this size spacer, giving reliable board to board connection.

The length of the standard spacer, .750 inches, plus the board thickness, .061 inches, gives a nominal
spacing board to board of .811 inches. If an exact spacing of .800 inches is desired (some standard
mounting hardware have .800 inch mounting board guides) .011 inches of the mounting surface at the
female end of the soft brass standoff can be removed by mill or metal file.

Only the mounting hole near the Vertical Stacking Connector has sufficient clearance around the hole to
allow for the head of a screw or the flats of the standoff to rest on. The trace closest to the hole is GND on
the top side of the board. All 2x4"s™ are designed with this same convention.

The two mounting holes at the other end board can be used for alignment pins, but do not have sufficient
clearance to allow the use of screw. All 2x4"s™ attempt to follow the convention, maintaining these two
mounting holes. If, however, there is sufficient reason to use that board space they may not always be
preserved.

The extremely small size of the boards means there are no guaranteed limits on how close components will
be placed to the edge of the 2x4"s™. Board guides will be difficult to use and designs should take this into
account. They may be acceptable if non conductive and very shallow. The main mounting hole remains the
best point of support.

This board is also available in the "long" version, the NMIL-3000. The NMIL boards have an additional
mounting tab on each end, so the total board outline is 2x4.750". Each end tab is 2"x3/8". Two .156"
mounting holes are centered on the tabs, .250" from the edges. Hex .250" male-female standoffs can be
used to make a rigid cage-like structure with NMIL boards. Special metal mounting tabs can also be used
to mount the boards perpendicular to a surface. The NMIL versions of NMIS boards add a little size, but
offer extremely roughed mounting.

Troubleshooting

7
The NMIS-3000 is a fairly simple and straight forward board. The most likely problem encountered
remains "operator error". There are a minimal number of things that could be wrong otherwise that are
customer serviceable.

Check the address selectors and verify they are set for the base address used in the program. Use the
memory dumps outlined in the "Getting Started" chapter. If the input registers don't appear in memory,
check the VSC connections and the 74HC688's. Finally replace the 74HC688's if necessary.

If the inputs still do not appear, check the outputs with a logic probe. First be sure to configure Jumper "B"
to enable the outputs. Check for all low after writing zeros to the locations. Then check for all high after
writing ones (FFFF hex) to the locations. If the outputs follow what is written, the 74HC574's are working
and the 74HC573's are the problem. If the outputs do work and the inputs don't, recheck Jumper "A" to see
it is either strapped high or the input signal occasionally goes high to let the latched data change.

If the inputs work and the outputs don't, check Jumper "B". If it is strapped low the outputs should be
enabled. If it is high they will be inhibited and can not control the pins.

The majority of the board uses surface mount technology, and there is little further service that can be
performed by the customer. Contact the factory for repair if these suggestions do not help.

Jumpers

8
 ADDRESSES 8000-8003 HEX

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X o o o o o o o o o o o o o * *
X X X X X X X X X X X X X X * *
o X X X X X X X X X X X X X * *
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRESSES 0110-0113 HEX

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
o o o o o o o X o o o X o o * *
X X X X X X X X X X X X X X * *
X X X X X X X o X X X o X X * *
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

ADDRESSES BC00-BC03 HEX

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
X o X X X X o o o o o o o o * *
X X X X X X X X X X X X X X * *
o X o o o o X X X X X X X X * *
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

* NOTE: These are "DON'T CARE" as long as 0 or 1, will not effect base address.

Program Segments

9
COLD

FORGET TASK
HEX
( 100 1C ! ( V3.3 only
( 50 1E ! ( V3.3 only
404 DP !

: IS CONSTANT ;
8000 IS BASE-ADDRESS

BASE-ADDRESS 0 + IS PORTA
BASE-ADDRESS 1 + IS PORTB
BASE-ADDRESS 2 + IS PORTC
BASE-ADDRESS 3 + IS PORTD

BASE-ADDRESS 0 + IS PORTE
BASE-ADDRESS 1 + IS PORTF
BASE-ADDRESS 2 + IS PORTG
BASE-ADDRESS 3 + IS PORTH

: PA@ PORTA C@ ;
: PB@ PORTB C@ ;
: PC@ PORTC C@ ;
: PD@ PORTD C@ ;

: PE! PORTA C! ;
: PF! PORTB C! ;
: PG! PORTC C! ;
: PH! PORTD C! ;

: PAB@ PORTA @ ;
: PCD@ PORTC @ ;

: PEF! PORTE ! ;
: PGH! PORTG ! ;

I/O Connectors

10
LEFT BOARD EDGE > |
TOP VIEW |
|
|
|+-----+
GND | | o o | +5V
|| |
PA 0 | | o o | PA 1
|| |
PA 2 | | o o | PA 3
|| |
PA 4 | | o o | PA 5
|| |
PA 6 | | o o | PA 7
|| |
PB0 | | o o | PB1
|| |
PB2 | | o o | PB3
|| |
PB4 | | o o | PB5
|| |
PB6 | | o o | PB7
|| |
PC0 | | o o | PC1
|| |
PC2 | | o o | PC3
|| |
PC4 | | o o | PC5
|| |
PC6 | | o o | PC7
|| |
PD 0 | | o o | PD 1
|| |
PD 2 | | o o | PD 3
|| |
PD 4 | | o o | PD 5
|| |
PD 6 | | o o | PD 7
|+-----+
|
| J1
|
|
|
|
|
|
|
|
|
|
|+-----+
GND | | o o | +5V

11
 || |
PE0 | | o o | PE1
|| |
PE2 | | o o | PE3
|| |
PE4 | | o o | PE5
|| |
PE6 | | o o | PE7
|| |
PF0 | | o o | PF1
|| |
PF2 | | o o | PF3
|| |
PF4 | | o o | PF5
|| |
PF6 | | o o | PF7
|| |
PG 0 | | o o | PG 1
|| |
PG 2 | | o o | PG 3
|| |
PG 4 | | o o | PG 5
|| |
PG 6 | | o o | PG 7
|| |
PH 0 | | o o | PH 1
|| |
PH 2 | | o o | PH 3
|| |
PH 4 | | o o | PH 5
|| |
PH 6 | | o o | PH 7
|+-----+
|
| J2
|

J1, J2 I/O Connector Pin Out

Parts List
NMIS-3000 32-IN 32-OUT PARTS LIST REV 1.0

PART# GENERIC DESCRIPTION

U 1 ,2 20 PIN SOCKET

12
 74HC688 OCTAL COMPARATOR
U 3 ,4 ,5 ,6 74HC573 OCTAL LATCH - SMD
U 7 ,8 ,9 ,1 0 74HC574 OCTAL LATCH - SMD
U11 74HC245 OCTAL BUS TRANSCEIVER -
SMD
U12 74HC138 3 TO 8 DECODER - SMD
U13 74HC32 QUAD OR - SMD

J1 34 PIN HEADER .1" DUAL INLINE

J2 34 PIN HEADER .1" DUAL INLINE
J3 34 PIN VSC HEADER .1" DUAL INLINE

C1-10 .1 u f MONOLYTHIC BYPASS

D1 1N4148 OR 1N914 SI G N A L D I O D E

PCB NMIS-3000 PCB REV 1.0

3x16 JUMPER PINS BERG STYLE .1" CENTER

JUMPERS
16 JUMPER SHUNTS BERG STYLE .1" CENTER
SHUNTS
3x3 JUMPER PINS BERG STYLE .1" CENTER
JUMPERS
3 JUMPER SHUNTS BERG STYLE .1" CENTER
SHUNTS

NMIS-3000 Parts List Rev 1.0

13
 (0,4.375) (2.000,4.375)

(0.250,4.200) (1.750,4.200)

(0,4.000) (2.000,4.000)
U1 C1

(0.0075,3.925) +5GND

GND 0

+5V 1

74HC688
1 0
(1.925,3.925)
C2

0
74HC573
2 4

1
PA

2
U3
6

3
C3
0

4
74HC573
2 4

5
PB

6
U4
6

7
A U2
0

8
2 4

15 14 13 12 11 10 9

14 13 12 11 10 9
PC

74HC573
5

C4

74HC688
6

U5
0

1
2 4

3
PD

5 7

ADDRESS15LINE
(0.150,2.200) 74HC573 C5
(1.850,2.200)
6

J1
1

U6
MEMDIS NC (1.750,1.950)
C6
(0.150,1.800) D1 E RESET
GND 0

+5V 1

74HC574 A15 INT

A14 +5
2 4

NMIS-3000 32-IN 32-OUT TTL V1.0 08/14/92

NMIS-3000 32-IN 32-OUT TTL V1.0
A12
PE

U7 R/W
5

B 65 A7 A13
6

C A6 A8
74HC574
0

C7 80 A5 A9
2 4

3
PF

U8 A4 A11
5

74HC138 A3 OE
6

U12 A2 A10
0

74HC574 C8 C10 A1 AS
2 4

A0
PG

74HC32 D7
5

U9 D0 D6
6

U13 D1 D5
0

D2 D4
2 4

GND
PH

74HC574 74HC245 D3
C9
5

1
6

U10 U11 (1.800,0.150)

1

J2
(0,0) AGY03
(2.000,0)

(0.250,-0.200) (1.750,-0.200)

(0,-0.375) (2.000,-0.375)
 8 7 6 5 4 3 1
DWG. NO. SH REV

REVISIONS
ZONE REV DESCRIPTION DATE APPROVED

+5V
LATCH
+5V

J1 U3 U4 A
D 34
PA0 32
30
33
31 PA1 CSR0 1
11 OC
CSR1 1
11 OC D
PA2 29 PA3 C C
PA4 28 27 PA5
26 PA0 2 1Q 19 D0A PB0 2 1Q 19 D0A
PA6 25 PA7 1D 1D
24 PA1 3 2Q 18 D1A PB1 3 2Q 18 D1A
PB0 23 PB1 2D 2D
22 PA2 4 3Q 17 D2A PB2 4 3Q 17 D2A
PB2 21 PB3 3D 3D
PA3 D3A PB3 D3A
PB4 20
18
19 PB5
PA4
5
6
4D 4Q
5Q
16
15 D4A PB4
5
6
4D 4Q
5Q
16
15 D4A U1
PB6 17 PB7 5D 5D 1 AS
16 PA5 7 6Q 14 D5A PB5 7 6Q 14 D5A G
PC0 15 PC1 6D 6D 2 JA0
14 PA6 8 7Q 13 D6A PB6 8 7Q 13 D6A P0
PC2 13 PC3 7D 7D 4 A2 +5V
12 PA7 9 8Q 12 D7A PB7 9 8Q 12 D7A P1
PC4 11 PC5 8D 8D 6 A4
P2
PC6 10 9 PC7 HC573 HC573 P3 8 A6 MEMDIS34 J3
PD0 8 7 PD1 33
P4 11 A7 32
PD2 6 5 PD3 E 31 RESET
P5 13 A5
PD4 4 3 PD5 A15 30 29 INT
P6 15 A3
PD6 2 1 PD7 A14 28 27
19 P7 17 JA1
A12 26 25 R/W
P=Q
Q0 3 JA0 A7 24 23 A13
U5 U6 Q1 5 JA2 A6 22 21 A8
Q2 7 JA4 A5 20 19 A9
CSR2 1
11 OC
CSR3 1
11 OC Q3 9 JA6 A4 18 17 A11
C C Q4 12 JA7 A3 16 15 OE
Q5 14 JA5 A2 14 13 A10
PC0 2 1Q 19 D0A PD0 2 1Q 19 D0A 16 JA3 A1 12 11 AS
1D 1D Q6
PC1 3 2Q 18 D1A PD1 3 2Q 18 D1A 18 JA1 A0 10 9 D7
2D 2D Q7
PC2 4 3Q 17 D2A PD2 4 3Q 17 D2A D0 8 7 D6
PC3 3D D3A PD3 3D D3A HC688 6 D5
C PC4
5
4D 4Q 16
D4A PD4
5
4D 4Q 16
D4A
U2
D1
4
5
D4
PC5
6
7
5D
6D
5Q
6Q
15
14 D5A PD5
6
7
5D
6D
5Q
6Q
15
14 D5A
D2
2
3
1 D3 C
PC6 8 7Q 13 D6A PD6 8 7Q 13 D6A 1
7D 7D G
PC7 9 8Q 12 D7A PD7 9 8Q 12 D7A P0 2 A8
8D 8D P1 4 A10
HC573 HC573 P2 6 A12
P3 8 A14
P4 11 A15
P5 13 A13
OC +5V U11 P6 15 A11
19 P7 17 A9
G 19
P=Q
DIR 1 OE Q0 3 JA8
Q1 5 JA10
B 18 P=Q Q2 7 JA12
D0A A1 2 D0
B1 Q3 9 JA14
+5V 17 Q4 12 JA15
D1A 3 D1 +5V
34 J2 U7 U8 D2A 16 B2 A2
A3 4 D2 Q5 14 JA13
33 15 B3 Q6 16 JA11
32 1 OC 1 OC D3A A4 5 D3 JA0
PE0 31 PE1 14 B4 Q7 18 JA9
30 CSW0 11 CP CSW1 11 CP D4A A5 6 D4 JA1
PE2 29 PE3 13 B5
28 D5A A6 7 D5 HC688 JA2
PE4 27 PE5 19 19 12 B6
26 PE0 1D 2 D0A PF0 1D 2 D0A D6A A7 8 D6 JA3
PE6 25 PE7 18 1Q 18 1Q 11 B7
24 PE1 2D 3 D1A PF1 2D 3 D1A D7A A8 9 D7 JA4
PF0 23 PF1 17 2Q 17 2Q B8
22 PE2 3D 4 D2A PF2 3D 4 D2A JA5
PF2 21 PF3 16 3Q 16 3Q HC245
20 PE3 4D 5 D3A PF3 4D 5 D3A JA6
PF4 19 PF5 15 4Q 15 4Q
18 PE4 5D 6 D4A PF4 5D 6 D4A JA7
PF6
PG0 16
17
15
PF7
PG1
PE5 14
13
6D
5Q
6Q
7 D5A PF5 14
13
6D
5Q
6Q
7 D5A U12 JA8
B PG2 14 13 PG3
PE6
12
7D 7Q
8 D6A PF6
12
7D 7Q
8 D6A JA9
PG4 12
10
11 PG5
PE7 8D 8Q
9 D7A PF7 8D 8Q
9 D7A
CSW0 15
14 Y0
1
A 2
A0
JA10
JA11
B
PG6 9 PG7 HC574 HC574 CSW1 A1
13 Y1 B 3 JA12
PH0 8 7 PH1 CSW2 R/W
12 Y2 C JA13
PH2 6 5 PH3 CSW3
11 Y3 JA14
PH4 4 3 PH5 CSR0 6
10 Y4 G1 JA15
PH6 2 1 PH7 CSR1 2A G 4
CSR2 9 Y5
2B G 5
CSR3 7 Y6
U9 U10 Y7
1 OC 1 OC HC138
CSW2 11 CP CSW3 11 CP +5V
19 19 E
PG0 1D 2 D0A PH0 1D 2 D0A
PG1 18
2D
1Q
3 D1A PH1 18
2D
1Q
3 D1A U13 80 65/68
PG2 17
3D
2Q
4 D2A PH2 17
3D
2Q
4 D2A 3 1 P=Q C
16 3Q 16 3Q 2 AS
PG3 4D 5 D3A PH3 4D 5 D3A
15 4Q 15 4Q
PG4 5D 6 D4A PH4 5D 6 D4A HC32
14 5Q 14 5Q
PG5 6D 7 D5A PH5 6D 7 D5A
13 6Q 13 6Q
PG6 7D 8 D6A PH6 7D 8 D6A
12 7Q 12 7Q
PG7 8D 9 D7A PH7 8D 9 D7A
8Q 8Q POWER SUPPLY PIN CONFIGURATION
SPARE GATES HC574 HC574

4
REFDES +5V GROUND
U13 6
5
U1,U2 20 10
HC32
A +5V +5V +5V +5V +5V +5V +5V +5V +5V
U3,U4,U5,U6 20 10
U13
8 9
10
BYPASS A
HC32 U7,U8,U9,U10 20 10 NMIS-3000
12
CAPACITORS U11 20 10
11
U13 13
C1 C2 C3 C4 C5 C6 C7 C8 C9
TITLE
HC32 U12 20 10 APPROVALS DATE
32-IN 32-OUT TTL BOARD
DRAWN
CIBI-ARDY 120391
U13 14 7 SIZE DWG NO. REV

D
CHECKED
1
FINISH
SHEET 1 OF 1
8 7 6 5 4 3 2 1
SCALE