SIEMENS 8-Bit Single-Chip Microcontroller SAB 8051A Microcontroller with factory ma: SAB 8051A/8031A Family -programmable ROM SAB 8031A Microcontroller for external ROM © Version for 12MHz/16MHz/ 20 MHz operating frequency 4k x8 ROM @ 128 x8 RAM @ Four 8-bit ports, 32 V/O lines Two 16-bit timer/event counters @ High-performance full-duplex serial channel with flexible transmitreceive © Boolean processor © 218 user bit-addressable locations @ Most instructions execute in: 1 us instruction cycle time at 12 MHz 750 ns instruction cycle time at 16 MHz 600 ns instruction cycle time at 20’MHz © 4s (3 us, 2.4 us) multiply and divide @ Packages P-DIP-40 and PL-CC-44 bound rate capability © Two temperature ranges available @ External memory expandable up to 128 010 70°C Kbyte 40 to 85 °C: T40/85 ‘© Compatible with SAB 8080/8085 peripherals Figure 1 Pin Configuration P-DIP-40 PL-CC-44 no ap ve 8583 nfl sof] roe 00 enum ms tle aif 02 an ede aes i327 1@ena@ ns Qs ssf] vo aoe 15 POA ADS re? Saf vos aos Piece 70.5 ADS nile ssf] me a Pras PO.6 ADE wi, 2 s2f] ror a0? RST/ Yoo PO.7 AD? aopsalfio gag a ropesily soata xf SAB 8031A/8051A NG. Broesz rz 80818 ohh ace ALE amiss ffs zal] v2.7 01s PSEN ro/raa fe aflras ave P27 AIS wiess}is rofl ras aos P26 Ald Wyrss[fi6 sf} #24 une P25 AIS esa (fir afd eas a 22 23 24 25 26 27 28 ei ai a0 geggsfceaes vall~ tile ae lee a2oos © Siemens Components, Inc. at‘SAB 8051A/8031A Family The SAB 8051A/8031A Family are standalone, high-performance single-chip microcontrollers fabricated in + 5 V advanced N-channel, silicon-gate Siemens MYMOS technology and supplied in a 40-pin Plastic P-DIP or 44-pin plastic leaded chip carrier (PL-CC-44) package. It provides the hardware features, architectural enhance- ‘ments and instructions that are necessary to make it a powerful and cost-effective controller for applications requiring up to 64 Kbytes of program memory and/or up to 64 Kbytes of data storage. The SAB 8051A contains a non-volatile 4K x 8 read-only program memory; a volatile 128 x 8 read/write data memory; 32 I/O lines; two 16-bit timer/counters; a five-source, two- Priority-level, nested interrupt structure; a serial VO port. for either multi-processor communications, /O expansion, or full duplex UART; and on-chip oscillator and clock circuits. The SAB 8031A is identical with the SAB 8051A, except that it lacks the program memory. For systems that require extra capability, the ‘SAB 8051A can be expanded using standard TTL-compatible memories and the byte- oriented SAB 8080 and SAB 8085 peripherals. The parts are available for standard temperature range (0 to 70 “C) and extended temperature range (T40/85: — 40 to 85 °C). |" Figure 2 ‘SAB 8051A/8031A Family j SAB 8051A/8031A ROM MCBO1580 42 © Siemens Components, Inc.‘SAB 8051A/8031A Family Ordering Information ayers Package Description (@-bit single-chip microcontroller) ‘SAB 8031A-P-40/85, P.DIP-40 Zz forexternalmemory, SAB BOSIANAOES | PL-CO-44 12M, ext. Temp SAB 6031A-P_ P-DIP-40 for extemal memory, SAB 8031A.N PLCC44 12MHz saBeCaAGP | P-DIPO || foraxtamalmemoy, SAB 8031A-16-N 16 Miz ‘SAB 8031A-20-P 40 for external memory, _ SAB 8031A-20-N 20 Mie ‘SAB 6051A-P-40/85 P-DIP-40, with 4-KByte mask-programmable ROM 12 MHz, ext. Temp. SAB 8051A-P | P-DiP-40 with 4-KByte mask programmable ROM ‘SAB 8051A.N PL-CC-44 | Mee ‘SAB 8051A-16-P PDIP4O Swit KByte mask-programmable ROM SABBOSIATEN | PL-CO-aa Cae 4 SAB B05iA20P P-DIP-A0 ) wih 4-KB te mask-programmable ROM SABBOSIAZON | PL.CG-Ad | PoMHe © Siomens Components, Inc. 43‘SAB 8051A/8031A Family Figure 3 Logic Symbot XTALI 7) 5s Sea | XTAL2 «>| 2 3 em (ss cers RST/V, >] 8 +] 5 = PSEN | ALE. | S 2 RxD —> 5 TxD <— — iNT —> —+> 1/8 iNTi—> go G To—> eo fs Ti — |s WR<— — R<— —! weLo00Ts 4 © Siemens Components, Inc.Pin Definitions and Functions SAB 8051 A/8031A Family Symbol | Pin Input (1) P-DIP-40 | PL-CC-44 | Output (0) Function PLOPL7 [18 29 vo PORT 1 is an 8bit quasi-biirectional /O port. Its used for the low-order address byte during program verfication. Port 4 can sink/source four LS TTL loads. RST | 9 10 RESET A high level on this pin resets the SAB 8051A. A ‘small intemal pulldown resistor permits power-on reset us- ing only a capacitor connected to Vcc. If veo is held within its spec while Vcc drops below spec, vPo will provide standby ower to the RAM. When vo is low, the RAMs current is, drawn from vec. P30-P37 [10-47 | 11, v0 1349 PORT 3 is an 8-bit quasi-bidirectional V/O por. It also con- tains the interrupt, timer, serial port and RD and WR pins that are used by various options. The output latch corre- ‘sponding to a secondary function must be programmed to a ‘one (1) fr that function to operate. Port 3 can sink/source | tour LS TTL loads. The secondary functions are assigned 10 the pins of pon 3, as follows: ~FsDidata (P3.0). Serial port's receiver data input (asynchronous) or data input/output (synchronous). ~T.Dictock (P3.1). Serial port's transmitter data output (asynchronous) or clock output (synchronous) ~INTO (3.2). Interrupt 0 input or gate control input for counter 0 -INT? (P3.3). Interrupt 1 input or gate control input for counter 1 TO (P3.4). Input to counter 0. -T1 (P3.5). Input to counter 1 WR (P3.6). The write control signal latches the data bye trom por 0 into the external data memory. AD (P3.7). The read control signal enables external data memory to por 0. xmat [19 at XTAL2 | 18 20 P20P27 [2128 [2431 |v0 XTAL 1 inputto the osclator's high gain amplifier. Required when a crystal is used. Connect fo Vss when external source is used on XTAL 2 XTAL 2 output from the oscilator's amplifier. Input to the in- ternal timing circuty. A crystal or external source can be used. PORT 2.is an 8-bit quasi-bidirectional V/O port. It also emits the high-order address byte when accessing extemal mem- ‘ory. Itis used for the high-order address and the control sig- nals during program verification, Port 2 can sink/source four LS TTL loads. ‘The Program Store Enable output is @ contro signal that ‘enables the external program memory to the bus during ex- temal fetch operations. Iti activated every six ‘oscillator periods, except during external data memory ac- cesses, Remains high during internal program execution. © Siemens Components, inc. 45‘SAB 8051A/8031A Family Pin Definitions and Functions (cont'd) ‘Symbol Pin P-DIP-40 | PL-CC-44 Input (1) Output (0) Function ALE 30 33 ° Provides Address Latch Enable output used for latching the address into external memory during normal operation. Itis activated every six oscillator periods except during an extemal data memory access. 31 [35 External Latch Enable when held at a TTL high level, the ‘SAB 8051A executes instructions from the internal ROM when the PC is less than 4096. When held at a TTL low lev: «1, the SAB 8051A fetches all instructions from external pro- ‘gram memory. For the SAB 80314 this pin must be tied low. P0.0-PO7 39-32 43-36 Port is an 8-bit open drain bidirectional V/O port. I is also the multiplexed low-order address and data bus when using ‘extemal memory. Its used for data output during program Verification. Port 0 can sink/source eight LS TTL loads. +5V Power Supply during operation and program venifica- tion. Ground (0 V) No Connection ele 46 © Siemens Components, Inc.SAB 8051A/8031A Family Figure 4 Block Diagram Frequency | Reference Counters | a ee {Hh por i 4096 byte Oscillotor , Two 16-8 | Program : ‘ Memor Data emer Timer Event 1 Timing i ally Counters (SAB 80514 only) 84 Kbyte Bus Exponter Contrat VV Parallel Por's Address Data Bus and 1/0 Pins Interrupts Contral Programmable Serial port Full duplex UART ‘Syrchronous Shifter Serial ser nN | ouT © Siemens Components, inc. 47SAB 8051A/8031A Family Absolute Maximum Ratings Ambient temperature Under BIAS non : SAB B051A/B031A. non 00 70°C ‘SAB 8051A/8031A-T40/85 .. 40 to 85°C Storage temperature, ~ 6510 150°C Voltage on Vcc pins with respect to ground (Vs). -08t07V Power dissipation... soo BW OC Characteristics Veo = 5 V+ 10 %; Ves = 0V Ta= Oto 70°C for the SAB 8051A/8031A Note: Stresses above those listed under “Absolute Maximum Ratings” may cause permanent dam- ‘age to the device. This isa stress rating only and functional operation of the device at these ‘or any other conditions above those indicated in the operational sections of this specification is rot implied. Exposure to absolute maximum rat- ing conditions for extended periods may affect device reliability. Tx= = 40 to 85 °C for the SAB 80514/8031A-T40/85 Parameter Limit Values Symbai Unit | Test Condition in max, va Inputiowvoltage =—stt*«~CSC OS 08 v [- vin Input high voltage | 20 | voc + 0.5 v - (except RST/VPD and XTAL 2) | Ys | Input ign votage fo Fas | weeos |v | xT Ons | RSTIVEDforroet XTAL2 | see wre | Power down votage $5 v | vecsov toASTAPD vou Output low voltage Fee “joas Pore .2.3 | ele ves | Ouputiow votage [- a -,—hELLreM Port 0, ALE, PSEN | vou Output high voltage | 24 = v Pons 1.2.8 | Vout Output high voltage | 2a - v Port 0, ALE, PSEN | 48 © Siemens Components, inc.‘SAB 8051 A/8031A Family DC Characteristics (cont'd) ‘Symbol | Parameter Limit Values Unit | Test Condition ‘min. max. | nT Logical 0 input current - - 500 h = 0.45 Ports 1, 2,3 ne | Logicat 0 input current XTAL 2 | SAB 8051A/8031A-12/16/20 - -32 mA | XTALI = vss SAB 8051 A/8031A-T40/85 - -25 mA | mW 2045V Te Input high current to = 500 vA [vn=Vvec-15V AISTVeo for reset uw Input leakage current - 210 wa [OV ume vec to port 0, EA | ie Power supply current Al outputs ‘SAB 8051A/8031A a 128 mA | disconnected ‘SAB 8051A/8031A-16 - 140 | ma ‘SAB 8051A/80314-20 - 140 mA 7 ry Power down current SAB 8051A/8031A-12/16/20 - 10 ma | voc=0V SAB 8051A/8031A-T40/85, - 18 mA | vo=45...55V 00 Capacitance of /O buffer = 40 pF | e=1MHz © Siemens Components, Inc. 49SAB 8051A/8031A Family AC Characteristics for SAB 8051A/8031A Vor = 5 V + 10%; Ves=0V (C.for port 0, ALE and PSEN outputs = 100 pF; C: for all other outputs = 80 pF) Ta= Oto 70 'C for the SAB 8051A/8031A, Ta=~ 40 to 85°C for the SAB 8051A-T3/8031A-T40/85 Program Memory Characteristics Unit Symbol | Parameter Limit Van | Clock T Variable clock JaMHz clock | theuct = 1.2 MHz to 12 MHz min. [mex min | | ani | ALE pulse width ae arcc-4o0 | = 8 ae ‘Address setup to ALE 1 - reuc.-30 = baal nuaxt | Address hold after ALE [4 = raa35 a a iv [AE wvaldnetuctonim [= 3 = [Rae Tr mar [ALE to PSEN (aoa wai 25 = 7s mma _| PSEN pulse width 2 ‘| 3eic35 | ine mw PSEN to valid instruction in - 150 - Secci- 100 | ns max Tapat instruction hold after PSEN [Oo] = ° = i Inputinstuction fost ater BSEN |= fe mc20 [as MaxesanioePEN [|= mace [= i Address to valid instruction in [=| 302 — | Bei 118 [ns ‘mae.___| ‘Address float to PSEN 0 i= ° a "5 *) Interfacing the SAB8051A to devices with float times up to 75 ns is permissible. The limited bus contention will not cause any damage to port 0 drivers. 4-10 © Siemens Components, Inc.‘SAB 8051A/8031A Family External Data Memory Characteristics mnt | RD pulse width 400 |- Geici-100|- ns ‘wewm | WR pulse width 400 [= 6ec-100 | ns ue _ [Address hold after ALE 132 *[- Bea |- 78 tL RD to valid data in ~ 252 - Sraci-165 | ns TRHOX Data hold after RD 0 - 0 - ns od Data float after RD = o7 = Breveu-70 ns wiv __ | ALE to valid data in = as E Brea 150 | ns iavov | Address to valid data in = 365 «f= Bac. 165 [ns i ALE to WA or RO. 200 300 Brcict-50 BrcLc.+50 ns, tavm | Address to WA or RD 203 [= arc 130 |= AS ‘wun | WRoor RD high to ALE high 3 123 [reua40 rece ns roowx | Data valid to WA transition ool = rou 50 = ns sown Data setup before WR 433 - eeuci-150 | ns ‘wiox | Data hold after WA 33 = ict 60 = ns mmaz [Address float afer FD = 0 = 0 18 External Clock Drive XTAL2 cic. | Oscillator period 7 - 83.3 833.3 ns 7x__| High time 5 = 20 exc reox | ns viex | Low time = 5 20 elo choR | As ier Rise time = = = 20 o me Fall time = = = 20 “ns, © Siemens Components, Inc, anSAB 8051A/8031A Family AC Characteristics for SAB 8051A/8031A-16 Voc = 5 V + 10%; Vss=OV (C.for port 0, ALE and PSEN outputs = 100 pF; Cor all other outputs Ta to + 70 °C for SAB 8051 A/8031A-16 Program Memory Characteristics Symbol] Parameter Limit Values Unit Clock Variable clock 1GMHzelock | thexot = 1.2 MHz to 16 MHz min. | mex. | min, max. TI ALE paleo width = ee 75 TE) Rares setup to ALE 3 = vae-30 [= ns iam) “Adress Rata afer ALE 2 7 racn3s = ie iv | ALE to valid instruction in 7 150 | ~ aac-100__| ns iu | ALE to PSEN 8 = raci-25 = 1 ine] PSEN pulse width a Baca |= ne ‘anv | PSEN to valid instruction in = 88 sac100 | ns ax | Input instruction hold after PSEN | 0 e 0 = ns imaz) | Input instruction float after PSEN |= @ = 1aa5 ne AddressvaidaterPSEN }60 |= rad - i| s ‘Address 10 valid instruction in| ~ 2 |- Braa-80 | ns ize. | Address float to PSEN ° 7 ° = ns *) Interfacing the SAB 8051A-16 to devices with fioat times up to 55 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. © Siemens Components, Inc.AC Characteristics for SAB 8051A/8031A-16 (cont'd) External Data Memory Characteristics ‘SAB 8051A/8031A Family Symbol | Parameter Limit Value Unit Clock Variable clock 1GMHzelock | tever = 1.2 MHz to 16 MHz min. min, max. PLR RO pulse width 275 - Bicrci- 100 = ns wut | WA pulse width 2s | Gec-100 - as LARD Address hold after ALE 90 i 2rcvc.- 35. = ns crunv | RD to valid data in = 48 |= Sec 165 [ns wmwox | Data hold ater AO 0 : ° : ns ‘mvoz _| Data float after AD = 55 = 2ecr-70 [ns nov ‘ALE to valid data in - 350 - Brcici- 150, ns ‘aver __| Address to valid data in = 398 (= ome 165 [ns uw_| ALE to WRor ib 138 [236 |Secs0 Seass0 [ns ‘awn __| Address to WA or RO aoe = ec 130 ns roan |WRorROhightoALEnign 29 -([103 [madd caadd (ro row _| Data valid to WR transition a LH meso ns ‘avn _ | Data setup batore WA 28 | Tec 150 — ns ‘wna | Data hold after WA 3 [- weno ns wuz | Address float ator RD : 0 = 0 ns External Clock Drive XTAL2 revel, Oscillator period - 7 25 833.3 ns ex] High time = = 5 meme — a max | Lowtime = = i ERR | ns iam _| ibe time = 7 = 1S 7S ToHCL Fall time = = = 5 ns © Siemens Components, in. 413‘SAB 8051A/8031A ily AC Characteristics tor SAB 8051A/8031A-20 Vor = 5 V + 10%; Ves=OV (Cufor port 0, ALE and PSEN outputs = 100 pF; C: for all other outputs = 80 pF) Ta= Oto + 70°C for SAB 8051A/8031A-20 Program Memory Characteristics ‘Symbol] Parameter Unit Clock Variable clock 20 MHiz clock min, | max. ruat__| ALE pulse width 60 5 ee vans | Address setup to ALE zou ee a ‘waxi_| Address hold after ALE 20 [= ce ru ALE to valid instruction in. - 100 7 4raci~100 ns ‘un_| ALE toPSEN oie |= raaes | he inen | PSEN pulse width ns [= arac-35 | - ns im __| PSEN to valid instruction in 7 7% |e gaa-75 | ns 1eex__| Input instruction hold after PSEN | 7 ° 7 ia ‘mv | Address valid after PSEN la ie rac 2 ns ronz? | Input instruction float ater PSEN |- «oi raa-10 rs vaav | Address to vai instruction in [= 15 |e Sac-76 | ne crud | accoas foal to REN) ea ssemel|ORMeea| ees (OWN tees ns *) Interfacing the SAB 8051-20 to devices with float times up to 45 ns is permissible. This limited bus contention will not cause any damage to port 0 drivers. © Siemens Components, Inc.SAB 8051A/8031A Family External Data Memory Characteristics ‘Symbol | Parameter Unit aoe wiz unet20 Whe min. max. max. TRH RD pulse width 200 - Graci-100 | — ns. uw WA pulse width 200 eS Gruci-100 | - ns rune | Aes hls ator ALE 70 aad |= a ‘uv __| AD to valid data in E 100 |- smict-150__| ns 1RHOX Data hold after RD 0 - 0 - ns mvcz | Data fiat after AD De Rever-60 | ns mu ALE to WR or RD | 100 200 Brovc.-50 Brove.+50 ns rave, Address to WR or RD 70 - 4rcct- 130 - ns rman | WRior AD high to ALE high 2 {60 |wan30 | racwa0 [as roWwx Data valid to WR transition 5 - ro.eL- 45, - ns owe Data setup before WR 200 - ‘Trevet-150 - ns awox Data hold after WA 10 - reiet-40 - ns. External Clock Drive Symbar Parameter Unt Clock Variable clock min, max, min. man aa asian paiad eee eee ase © Siemens Components, Inc 415SAB 8051A/8031A Family ROM Verification Characteristics for SAB 8051A/8031A Family a= 25 °C25 °C; voc = 5 V + 10%; vss = OV ‘Symbol Parameter Limit Values Unit min, max. iwor ‘Adress to valid data = aac ns iaov ENABLE to valid data . a rac ns ier Data float after ENABLE ° Baa ns Thao ‘Oscillator requency 4 6 Me | Figure 5 | ROM Verification PIO-P17 | Addi | P2.0-P2.3 (ses) Porto | | | P27 ENABLE weoocaza WMicrocontroter | Adcress Data Inputs SABBOS1A | P1.O-P1 Pon 0= Do- 07 |P2.4~P2.6, PSEN= vss aKx8 P20-P2 ALE, EA= You Rer/ve0 = vin 416 ‘© Siemens Components, inc.SAB 8051A/8031A Family Waveforms Figure 6 Program Memory Read Cycle Figure 7 Data Memory Read Cycle © Siemens Components, Ine. 417SAB 8051A/8031A Family Figure 8 Data Memory Write Cycle Figure 9 AC Testing Input, Output, Float Waveforms 24 Test Points 0.45 = Flot ————__», 2.0 20 te 0.8 0.8 0.45 90.45 wmeaon026 ‘AG. testing inputs are driven at 2.4 V for a logic "1" and 0.45 V for a logic "0" ‘Timing measurements are made at 2.0 V for a logic “1” and 0.8 V for a logic “0° For timing purposes, the float state is defined as the point at which a PO pin sinks 3.2 mA, oF sources 400A at the voltage test levels. © Siemens Components, Inc.SAB 8051A/8031A Family Figure 10 External Clock Cycle a ee Pose. wct00025 Figure 11 Recommended Oscillator Circuits C= 30pF £10pF Crystol Oscillator Mode Pin number in (. ..) are for PL-CC-44 package 19(21 . 18(20) Chock. ‘Signal Driving from External Source xTAL XTAL 2 esooons © Siemens Components, Inc. 419‘SAB 8051A/8031A Family 4.20 © Siemens Components, Inc.