"Empowerment through quality technical education"

AJEENKYA DY Patil School of Engineering

Dr. D. Y. Patil Knowledge City, Charholi Bk., Via. Lohegaon, Pune - 412 105.
Department of Electronics & Telecommunication Engineering
.

Experiment No: 01

Title : CMOS differential amplifier

Objective : Design and simulate single CMOS differential amplifier for CMRR of 40dB.

Theory:
The differential amplifier is one of the most versatile circuit designs. It serves as input
stage to most op-amps. Fig (a) shows a schematic model for a differential amplifier Voltages V 1,
V2 and Vout are called as single ended voltages. This means that they are defied with respect to
ground. The differential mode input voltage; Vid of the differential amplifier is defined as the
difference between V1 and V2. This voltage is defined between two terminals, neither of which is
ground. The common mode input voltage VIC is defined as average value of V 1 and V2. These
voltages are given as

Vid=V1-V2 Vic=V1+V2

Where, V1= Vic + Vid/2 

V2= Vic – Vid/2

However, the output voltage of the differential amplifier can be expressed in terms of its
differential mode and common mode input voltages as

V 1+V 2
Vout = Avd * Vid ± Avc ( 2 )
+

V1 +

V2+ Vout

_ _

(a)

M.E.VLSI & Embedded Systems (SEM-II) Lab Practice-II

 Vid/2

+ +

Vid/2 -

Vout

Vic

-
(b)
One fundamental difference which exists between differential amplifier and other amplifier is that
differential amplifier has two inputs where as other amplifier has one input ‘V+’ and ‘V-’. The
two output produced by differential amplifier are complementary to each other. Complementary
means whatever the value of ‘Vo+’ has ‘Vo-’ will be opposite of that in terms of phase.

 CMOS differential amplifier:-

The most common topology used for differential amplifier is shown in fig below.
This kind of topology is called as n-MOS input and p-MOS current mirror load type
differential amplifier. This is because input are provided to two n-MOS (V+ to M1 and V-
to M2) and transistor M3 and M4 are mirror connected acting like p-MOS load.

Vdd
Vdd
M3 M4

M1 M2

V+ V-

M6 M5

M.E.VLSI & Embedded Systems (SEM-II) Lab Practice-II

  Steps for calculating (w/L) ratio of each transistor of differential amplifier.
(1) Choose I5 to satisfy the slew rate knowing power dissipation, Pdiss

Slew rate (SR) = Io/CL

(Pdiss) Power dissipation = (Vdd + |Vss| )* Iss

(2) Check to see if Rout will satisfy the frequency response and if not, change I5 or modify the
circuit

2
Rout =
( λn+ λp )∗Iss

(3) Calculate W3/L3 Which is equal to W4/L4, to satisfy the upper ICMR

W3 2∗Id
i.e.; ( L 3 ) = μpCox ( Vgs−Vth ) 2

(4) Calculate W1/L1 which is equal to W2/L2, to satisfy the small signal differential voltage gain
A

gm1
Given , GBW =
2 Πc 1

W1
( L1 ) = 2
gm1 /2 Id μ n Cox

Or, given voltage gain =Av

gm 1
Av = gm1* Rout =
gds 2+ gds 4

(5) Calculate W5/L5, to satisfy the lower ICMR

Vic (min) =Vss + Vds(sat) +Vgs2

Vds (sat) =
√ 2 Id
β5
and Vgs2 =
2 Id
β1 √
+ Vthn

M.E.VLSI & Embedded Systems (SEM-II) Lab Practice-II

  For given specification :-
Slew rate = 20 V/μs GBW =30 MHz Load (CL) =4 pf
ICMR (+) =1.6 V ICMR (-) =0.8V Process technology =180nm
2
Kn = μ n Cox =222.50 μA/V
Vthn = 0.3725 Kp = μ p Cox =94.24 μA/V2 Vthp =0.3948

 Design CMOS differential amplifier :-

 Step 1: Slew rate =Io/CL=20 V/μs

Io = 20*106*4*10-12 =80μA≈82μA

 Step 2: Vds1 ≥Vgs1- Vth

Vds1≥ Vin (+) – Vth ≥ ICMR (+) –Vthn= 1.6V-0.3725
Vds1≥1.2275
Vds3= Vdd-Vds1=1.8V-1.25=0.55
W3 2∗Id 2∗41 μA
( L 3 ) = μpCox ( Vgs−Vth ) 2 = 94.24∗10−6∗0.55∗0.55
W3
( L 3 ) = 2.87

M.E.VLSI & Embedded Systems (SEM-II) Lab Practice-II

 

gm1
 Step 3: GBW =
2 Πc 1
gm1=GBW*2Π*CL
gm1=30*106*2 Π *4*10-12=7.539*10-4
W1
( L 1 ) = gm12 /2 Id μnCox =(7.539*10-4)2/2*41*10-6*222.50*10-6

= 31.15

 Step 4: Vic(min) =Vss + Vds(sat) +Vgs2

√
2 Id
Vgs2 = W 1 + Vthn
μnCox ( )
L1

=
√ 2∗41∗10−6
222.50∗10−6∗32
+ 0.3725

Vgs2 = 0.47

Vic(min) =Vss + Vds (sat) +Vgs2

√
2 Id
0.8V =0 + W5 + 0.47
μnCox ( )
L5

√
2 Id
0.33 = W5
μnCox ( )
L5

Squaring both sides

2∗82∗10−6
0.1089 = 6∗W 5
222.50∗10−
L5

M.E.VLSI & Embedded Systems (SEM-II) Lab Practice-II

 W5
L5 =6

 Process technology = 180nm

λ=0.18
L ˂ 2*λ
L ˂ 2*0.18 ; L≥0.36
W1
( L 1 ) =32, W1=32*0.36 μm =11.52 μm
W1 =W2=11.52μm
W3
=3
L3
W3=W4=3*0.36 μm=1.08 μm
W5
( L 5 ) =6 ; W5=6*0.36 μm=2.16 μm

Conclusion:

M.E.VLSI & Embedded Systems (SEM-II) Lab Practice-II

M.E.VLSI & Embedded Systems (SEM-II) Lab Practice-II