IEEE - 49239

Design of a High-Performance 2-bit Magnitude

Comparator Using Hybrid Logic Style
Afran Sorwar Elias Ahammad Sojib Md. Ashik Zafar Dipto
Department of Electrical and Computer Department of Electrical and Computer Department of Electrical and Computer
Engineering Engineering Engineering
North South University North South University North South University
Dhaka, Bangladesh Dhaka, Bangladesh Dhaka, Bangladesh
afran.sorwar@northsouth.edu elias.sojib@northsouth.edu ashik.zafar@northsouth.edu

Md. Mostak Tahmid Rangon Md. Sabbir Alam Chowdhury Abdul Hasib Siddique
Department of Electrical and Department of Electrical and Computer Department of Electrical and
Electronic Engineering Engineering Electronic Engineering
Northern University Bangladesh North South University University of Science and Technology
Dhaka, Bangladesh Dhaka, Bangladesh Chittagong, Bangladesh
tahmidrongon75@gmail.com sabbir.alam@northsouth.edu ahnion.ahs@gmail.com

Abstract—Design of a 2-bit binary Magnitude Comparator
(MC) is presented in this research. The proposed MC has been
designed using Conventional CMOS (CCMOS) logic, Pass
Transistor Logic (PTL). The design is simulated along with 5
other existing MC designs in order to carry out evaluation and
comparison. The proposed 2-bit MC displayed satisfactory level
of improvement in speed and power. For this reason, significant
enhancement in Power Delay Product (PDP) could have been
attained. Due to the significant enhancement in performance,
the proposed MC can be considered as a highly effective
alternative to the existing MC designs.
Keywords—magnitude comparator, binary comparator, bit
comparison, hybrid logic.
I. INTRODUCTION
The evaluation of modern highly complicated electronic
circuits and devices have led to the invention of several smart
systems [1-5]. These smart systems require highly effective
VLSI circuits which have high computation speed at a
satisfactory level of power loss [6-8]. Performance of VLSI
circuits plays important role in portable devices because of the
requirement of low power dissipation with acceptable speed.
Moreover, the modern microprocessors require highly
efficient circuits with limited area consumption to maintain
their high functionality and high integration density.
Therefore, design methodologies in VLSI circuits have gained
a tremendous amount of interest in the research community.
MC deign in VLSI circuits is an arithmetic component that
can decide if a binary number is equal, greater or less than a
another given binary number [9]. In short, MC is used for
binary number comparison [10]. Generally, MC takes two
binary numbers as inputs and provides the binary comparison
results as outputs. MC is massively used in instruction sorting
in microprocessors [11]. Digital signal and parallel processing
operations requires efficient MC circuits to maintain high
performance [12-13]. Hence, due to the application of MC in
high performance systems, using optimal MC design is highly
necessary.
Binary MC is an elementary level of operation in digital
VLSI circuits and systems. Binary 2-bit MC is considered as
basic block for implementation of wide word bit MCs.
Therefore, the efficient design of a 2-bit MC can bring about
massive changes in the performance. Therefore, in order to
build an efficient MC block, optimal design of 2-bit MC plays
quite significant role.
This work presents a 2-bit MC design using hybrid logic
style. Particularly, the design uses a mixture of 2 distinct
CMOS VLSI circuit design methodologies: CCMOS and
PTL. The effectiveness of the design has been evaluated by
performance comparison of the proposed MC with 5 other
designs. The MC presented in this work showed satisfactory
performance levels while maintaining low number of
transistors. For these reasons, the proposed MC is highly
effective for modern VLSI systems.
II. EXISTING DESIGNS
The rapid changes in circuit design has bring about various
design methodologies for VLSI circuit implementation such
as CCMOS [16], PTL [17] Transmission Gate Logic (TGL)
[18], Gate Diffusion Input Technique (GDI) [19] etc. For this
reason, various MC designs have been invented [20-21]. PTL
2-bit MC in [22] is implemented using 40 transistors. PTL
based design has a major disadvantage: voltage degradation.
This voltage degradation problem becomes quite severe in
lower CMOS technology nodes. For this reason, designs
solely implemented using PTL without swing restoring
transistors have become quite limited nowadays. This voltage
degradation leads to another major problem: weak drive
power. Due to various issues related to PTL, new designs have
emerged [23].
CCMOS logic solves voltage degradation and weak drive
power in PTL. CCMOS 2-bit MC in [24] is implemented with
66 transistors. However, the high number of transistors leads
to several other problems. These problems include high input
impedance of signals, high silicon area etc.
GDI based circuit design has become popular in modern
days due to the ability of implementing Boolean functions
expending fewer transistors [25-26]. However, unlike PTL,
inability to provide full swing output results in voltage
degradation, weak drive power and high DC power
consumption. GDI 2-bit MC deign in [27] is implemented
using only 28 transistors.

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 IEEE - 49239
TGL is another technique used by researchers to provide
full swing output in VLSI circuits [28]. Although, TGL has
better drive power than PTL, however, its drive power is less
than CCMOS logic. TGL 2-bit MC design in [29] is
implemented with 66 transistors.
TABLE I. OPERATION TABLE OF 2-BIT MC
Fig. 1. Block diagram of proposed 2-bit MC.
Fig. 2. Proposed 4-transistor XNOR circuit in PTL for 2-bit MC deisgn.
Hybrid design methodology uses more than one logic
method to implement Boolean functions [30-32].
Implementation of Boolean functions using hybrid design
method has become popular due to using the advantages of
various design methods. Hybrid 2-bit MC in [33] is
implemented using 42 transistors.
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III. PROPOSED DESIGN
Circuit design method of the proposed 2-bit MC is
described in the following sub-sections.
A. Boolean Function of 2-Bit MC:
The condition and operation of 2-bit MC can be expressed
as Table 1. In Table 1, the A and B terms are denoted as inputs.
AGB, ALB and AEB are denoted as outputs. Definition of
AGB, ALB and AEB are expressed in the last row of Table 1.
As per Table 1, boolean functions representing the operation
of 2-bit MC can be expressed as the below mentioned
equations.
AEB = XN0 XN1 (1)
ALB = B1 + B0 XN1 (2)
AGB = A1 + A0 XN1 (3)
where,
XN0 represents XNOR operation between A0 and B0
XN1 represents XNOR operation between A1 and B1.
Therefore, the above mentioned boolean equations (1)-(3)
and the statements XN0 and XN1 give insight that AND gate
and XNOR gates are required to be designed in order to
implement a 2-bit MC. Complex VLSI circuit would be
required in the end to generate outputs.
B. Block Diagram of porposed 2-bit MC:
The detailed block diagram of the proposed 2-bit MC can
is shown in Fig. 1. As per observations of Fig. 1, it can be
easily understood that the proposed 2-bit MC design uses
hybrid design method since it employs more than on VLSI
logic circuit design technique. PTL technique is used for
designing XNOR circuit. Although PTL is used, swing
restoring transistors are being used in the design for providing
full swing output, enhance circuit drive power and to reduce
DC power loss occurred in PTL due to threshold voltage loss.
Although the input circuit contains PTL, the output
terminals consist CCMOS based circuits in order to provide
high drive power in the output terminals. As the result of
combining PTL (input side) and CCMOS (output side),
number of transistor and DC power loss has been reduced
without effecting the drive power of the circuit. Hence, the
versatility of the circuit has been enhanced greatly.
C. XNOR gate design for porposed 2-bit MC:
Circuit diagram of the proposed XNOR gate is entirely
implemented using PTL method. The design is shown in Fig.
2. In can be seen from Fig. 2 that the proposed XNOR design
needs only 4 transistors to provide full swing output whereas
a CCMOS XNOR gate would have needed 12 transistors.
D. Schematic of porposed 2-bit MC:
Full schematic of the proposed 2-bit MC is shown in Fig.
3. The XNOR gates are implemented as per described in the
previous sub-section. For, AEB, CCMOS logic is used
although it requires high transistor count. The reason for using
CCMOS AND gate for AEB is this AND gate provides output
signal for which high drive power is required. ALB and AGB
are implemented using complex logic network implemented
in CCMOS logic using the equations (2)-(3). The transistor
counted from Fig. 3 is 46. Hence, the proposed 2-bit MC
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 IEEE - 49239

design needs only 46 transistors to fully implement its

operation.

Fig. 4. Power comparison of 2-bit MCs.

Fig. 3. Proposed 2-bit MC

TABLE II. SIMULATION RESULT OF 2-BIT MC

Fig. 5. Delay comparison of 2-bit MCs.
Comparator Ref no. TC Power Delay PDP
logic style (uW) (ns) (fJ)
PTL [22] 40 11.215 0.283 3.174
C-CMOS [24] 66 13.402 0.318 4.262
GDI [27] 28 7.094 0.519 3.682
TGL [29] 66 15.962 0.352 5.619
Hybrid [33] 46 7.908 0.216 1.708
Proposed …. 46 7.642 0.187 1.429

IV. PERFORMANCE COMPARISON AND DISCUSSION

The overall evaluation and effectiveness of the proposed
design can only be evaluated while compared with the existing
MC designs mentioned in literature review section. To do this,
all MC circuits were designed in Cadence Virtuoso. Then,
simulation was conducted in 90 nm CMOS technology.
Supply voltage for all cases is 1.0 V. All the circuits have been
simulated using the same simulation conditions so that a fair
judgement on the performance aspects of the 2-bit MC designs
could be obtained. The simulation results have been recorded
in Table 2. The graphical depiction of simulation results in
power, delay and Power Delay Product (PDP) are depicted Fig. 6. PDP comparison of 2-bit MCs.
utilizing Fig. 4-6.

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 IEEE - 49239
From Fig. 4, it is clear that the power consumption of
proposed Hybrid design in [33] is lowers whereas power of
TGL 2-bit MC in [29] is the highest. From Fig. 4, it can be
considered as low while compared with all the designs. Hence,
performance of proposed MC in terms of performance in
power can be considered satisfactory.
Now, if we move on to the point of speed, the proposed
MC design obtained the best performance. The Hybrid design
in [33] obtained second best result. GDI based 2-bit MC in
[27] obtained the highest delay.
In case of performance in PDP, the proposed design
achieved best result whereas TGL design-based MC in [29]
obtained worst results. Hybrid design in [33] have satisfactory
result in PDP.
V. CONCLUSION
A 2-bit MC design using PTL and CCMOS technique is
presented in this research. The design comprised of PTL
technique-based VLSI circuits for input terminals whereas
CCMOS logic based complex VLSI circuit have been placed
for output signals. The design in implemented and compared
with various other MC design to show the performance
evaluation of the design. The design displayed significant
enhancement in PDP and delay while maintaining quite
satisfactory power. As a result, the proposed MC design is
quite suitable for present day microprocessor design [30-37].
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