2020 IEEE 5th International Conference on Computing Communication and Automation (ICCCA)

Galgotias University, Greater Noida, UP, India. Oct 30-31, 2020

Performance Analysis of GDI based Arithmetic

Circuits
Vuppala Chandralekha
Department of ECE
Marri Laxman Reddy Institute of
Technology and Management
Hyderabad, India
Latchapatula Navya Kishore Sanapala* Neelam Syamala
Department of ECE Department of ECE Department of ECE
Marri Laxman Reddy Institute of Marri Laxman Reddy Institute of Marri Laxman Reddy Institute of
Technology and Management Technology and Management Technology and Management
Hyderabad, India. Hyderabad, India. Hyderabad, India
Kishore.technova@gmail.com

Abstract- From the past years, GDI logic circuits are gaining
more significance in obtaining lesser energy consumption. GDI is
a modern method of low power circuits. This method ensures less
power, propagation delay and area of digital circuits. A basic full
adder is the main arithmetic block in several digital circuit
applications. This paper presents the design of a full adder using
AND, OR and XOR gates that are full swing type to decrease
threshold voltage problem, two other adders based on GDI logic
and one adder using the CMOS design style. Different logic gate
circuits have been executed in GDI and CMOS styles. The
proposed logic using GDI is compared with the CMOS design
logic. Their properties are explained and simulation results are
stated.
A basic cell of GDI consists of 3 inputs: G-common input
to the both gates; N-input to the S or D of NMOS; P-input to
the S or D of PMOS. The functionality of the GDI in obtaining
different logic functions is already shown [3-6]. One major
distinctive feature among CMOS and GDI is that in GDI the
terminals could be given a supply voltage or can be grounded
or can be supplied with input signal depending on the
requirement of the circuit to design and consequently reducing
the amount of transistors utilized [4,5].

Index Terms: Adders, Energy, GDI technique, Power,

Propagation delay

I. INTRODUCTION
In the recent years’ portability has become important. In
systems which are operated using batteries, the energy reserved
inside a battery is definite. Hence, energy dissipation is the
important factor in battery powered devices, to improve the
average lifetime of the battery. Hence, circuits with low power
usage are anticipated to have smaller battery size, less weight
and longer battery life [1]. Energy dissipation is also important
in deep sub-micron technology. Advances in CMOS
fabrication technology has increased the amount of transistors
in every two years, according to Moore’s law [2]. Therefore,
the power dissipation per unit area increases, expanding the
chip area of the circuit. This excessive heat lowers the Fig. 1. Structure of GDI cell
reliability and life-time of the circuit design.
So currently we need low power circuits with high II. DESIGN OF GDI BASED LOGIC CIRCUITS
performance which in some cases may not be fulfilled by This section gives the design of two GDI based full adders
CMOS logic. GDI logic is a low power design approach that designed using the basic logic gates. The circuits are compared
can be used to design circuits with less number of transistors with the CMOS designs in terms of Power Dissipation, Delay,
[3-5]. Static power, Dynamic power and Energy.
A. Gate Diffusion Input logic A. 10T GDI based Full Adder
The fundamental cell structure of GDI is as shown in Fig. 1 XOR, XNOR, and Multiplexor are main blocks of the
[3-6]. It looks similar to a CMOS inverter. The source(S) and circuit. At the output two multiplexors are placed. Output sum
drain(D) diffusion input of both transistors are dissimilar. In a is obtained by using mux1 with XOR logic and carry output is
CMOS inverter the source(S) of PMOS is attached to voltage obtained by using mux2 with XNOR logic [3]. As only one
supply and the source(S) of NMOS is grounded [3-6]. mux is used in the path of carry propagation the delay is less
here.

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Fig. 2. 10T GDI Full Adder circuit

B. 14T GDI based Full Adder Fig. 4. CMOS full adder

The proposed full adder design comprises of mainly
fourteen transistors. It basically consists of five logic blocks D. CMOS based XOR Gate
which are XOR and XNOR blocks, two mux(s), a Swing Non-complementary inputs, A and B vectors, are derived
Restored Transmission block and a Swing Restored Pass so as to analyze the style in four cases 00, 01, 10, and 11. The
Transistor block [7]. GDI technique is used to design the XOR circuit operates according to its truth table whenever
XOR/XNOR blocks. The GDI mux1, multiplexes the output of input signals are same then the output signal is 0. If inputs are
the XOR block and the XNOR block with a control inpu, Cin totally distinct values, then the output signal is 1 [10].
to acquire the sum. Hence, the equation (1) can also be written
as (3) [7].
Sum = Cin.(AْB) + Cin.(AٖB) (3)
The output carry, Cout is realized by the mux2 that
multiplexes the Cin and B inputs also with control line from
the result of XNOR logic. Hence, the (2) is written as (4) [7].
Cout = (AٖB)Cin + (AٖB)B (4)

Fig. 5. CMOS based XOR gate

E. CMOS based AND Gate

An AND gate gives the output as 0 if any one of its inputs
is 0. If both the inputs are 1 then output is also 1.

Fig. 3. 14T GDI full adder

C. Conventional 28T CMOS based Full Adder

This conventional full adder has 28 transistors. Various
logic styles can be realized from various points of the circuit. It
has about fourteen PMOS pull up and fourteen NMOS pull Fig. 6. CMOS based AND gate
down transistors [8]. This circuit is mainly used to get the full
swing voltages. As the sum realizes from the carry signal F. CMOS based OR Gate
undesired delays are produced which is a disadvantage of the A OR gate gives the output as 1 if any one of its inputs are
circuit. Other drawbacks of this circuit are large area and high 1. If both the inputs are 0 then output is also 0.
power dissipation.

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Fig. 7. CMOS based OR gate

G. GDI based XOR Gate

The XOR circuit designed using GDI technique is as shown
in Fig.8, this circuit needs 2 PMOS and 2 NMOS transistors.
GDI XOR circuit use 4 transistors which are less when
compared to the traditional CMOS XOR as it uses 10
transistors.
Fig. 10. GDI based OR gate
III. RESULTS
In this section, results of the designed circuits are
presented. All the circuits proposed are designed using Mentor
Graphics tool with 130 nm technology. Thorough simulations
are done to get the required values for the suggested full adder
circuits at supply voltage of 1.2V at frequency of 200 MHz.
The simulation waveforms are plotted as shown below. From
the simulations, the performance metrics - Power, delay,
energy, static power and dynamic power are calculated and is
given in table 1.

Fig. 8. GDI based XOR gate

H. GDI based AND Gate

The AND gate developed using GDI technique needs 1
Fig. 11. 10T GDI Full Adder output
PMOS and 1 NMOS transistors. CMOS AND uses 6
transistors while GDI AND uses only 2 transistors.

Fig. 12. 14T GDI based Full Adder output

Fig. 9. GDI based AND gate

I. GDI based OR Gate

The OR gate developed with the help of GDI cell is as in
Fig.10, this gate is created using GDI technique needs 1 PMOS
and 1 NMOS transistors. CMOS OR uses 6 transistors while
GDI OR uses only 2.
Fig. 13. 28T Conventional CMOS Full Adder output

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Fig. 14. GDI XOR Gate output
Fig. 19. CMOS OR Gate output

TABLE I. COMPARISON OF PERFORMANCE PARAMETERS

Design Total Power Delay Energy Static power Dynamic
(ns) (aJ) power
10T 137.921nW 0.0568 7.8339aJ 1.2841nW 136.6369nW
GDI
FA
14T
GDI FA 114.901nW 0.0217 2.4933aJ 1.992nW 112.90nW

28T
Fig. 15. GDI AND Gate output CMOS 6.7723nW 0.8603 5.824aJ 3.5012nW 3.2711nW
Full
Adder
GDI 3.0118uW 0.00441 0.0069aJ 200.0899pW 1.3846nw
XOR
Gate
GDI 1.5744nW 0.0140 0.0000405aJ 13.0822pW 1.5613nW
AND
Gate
GDI 10.3370pW 0.00451 0.0000466aJ 2.8795pW 7.4575pW
OR
Gate
CMOS 3.3489nW 0.05825 0.1950aJ 376.7053pW 2.9721nW
XOR
Fig. 16. GDI OR Gate output
Gate
CMOS 581.496pW 0.05681 0.0272aJ 1.7776pW 579.7192pW
AND
Gate
CMOS 3.2489nW 0.0351 0.1143aJ 1.6060nW 1.6429nW
OR
Gate

IV. CONCLUSION
In this this we have suggested a low power circuit
designing technique called GDI technique. Mentor graphics
Fig. 17. CMOS XOR Gate output
tool is used to simulate the circuits at 45nm technology. Power
consumption, energy, delay, static power and dynamic power
are the constraints taken to compare the circuits. When
contrasted with other circuit designs the proposed designs have
lesser energy consumption and high performance than other
designs.
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