Module 1 8085 Microprocessors and Archit

Module-1 8085 Microprocessors & Architecture
Module I 8085 Microprocessors & Architecture
Microprocessors historical, perspective, 8085 pin diagram, architecture,

addressing modes, overview of 8085 instruction set, microprocessor
communication and bus timings, 8085 functional block diagram.
Microprocessor: It is an IC with all the functions of a CPU however, it

cannot be used stand alone since unlike a microcontroller it has no memory
or peripherals. It is a multipurpose, programmable, clock-driven, register-
based electronic device that reads binary instructions from a storage device
called memory, accepts binary data as input and processes data according
to those instructions and provide results as output.
Microprocessors can be classified based on the data bus width
❖ 4-Bit Microprocessors
1.History:
Microproces Bata Bus Pins No.Of

sor transi
Intel
4004 4-bit 640 bytes 16 2300 1971
8008 8-bit 16KB 18 3500
8080 8-bit 64KB 40 6000
8085 8-bit 64KB 40 1976
8086 16-bit 1MB 40 29000 1978
8088 8/16 bit 1MB 40 1979
80186 16-bit 1MB 68 1982
80286 16-bit 16MB real, 4 68 134000 1982
GB Virtual
80386 32-bit 4GB real, 132 PGA 275000 1986
64TB virtual
80486 32-bit 4GB real, 168 PGA 1200000 1989
64TB virtual
Pentium 64-bit 4GB real l 273 PGA 3.1 1993
Million
Pentium 64-bit 64 GB real 5.5 1995
pro Million
Pentium II 64-bit 64 GB real 7.5 1997
Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 1

Million
Pentium II 64-bit 1998
XEON
Pentium III 64-bit 1999
Pentium 64-bit 2000
IV
Dual Core 64-bit 2006
Core 2 2006
Core i7 2008
Core i5 2009
Core i3 2010
Motorola
6800 8-bit 64KB 40 1974
6809 8-bit 64KB 40 1978
68000 16-bit 16MB 64 1979
68020 32-bit 4GB 169 PGA 200000 1984
68030 32-bit 4GB 169 PGA
68040 32-bit 4GB
Zilog
z-80 8-bit 64KB 40
z-800 8-bit 500K
z-8000 16-bit 64KB
It is a 2nd generation microprocessor and is the base for studying and using
all the microprocessor available in the market.
2. Salient features of 8085 μp:
❖ It is an 8 bit microprocessor.
❖ It has 16(A0-A15) bit address lines (AB), hence can address up to 216 =
65536 (64K) memory locations.
❖ Data bus (DB) is a group of 8 lines D0 – D7.
❖ First 8 lines of AB & 8 lines of DBs are multiplexed AD0 – AD7.
❖ It supports 5 hardware interrupt & 8 software interrupt.
❖ A 16 bit program counter (PC)
❖ A 16 bit stack pointer (SP)
❖ Six 8-bit general purpose register arranged in pairs: BC, DE, HL.
❖ It requires a signal +5V power supply
❖ Max.clock Frequency= 3MHz and Min.clock Frequency=500kHz

System Bus
Bus is a group of conducting wires which carries information, all the

peripherals are connected to microprocessor through Bus. There are three
different types of buses.
❖ Address bus
❖ Data Bus
❖ Control Bus
Address bus –It is a group of conducting wires which carries address only.
AB is unidirectional because address flows in one direction, from μp to
memory or from μp to Input/output devices. The range of Address of 8085
μp is from 0000 H to FFFF H. The μp can address 65, 536 different memory
location. The Length of the AB determines the amount of memory can be
handled. Actual amount of memory can be accessed is usually much less
than this theoretical limit due to chipset and motherboard limitations.
Data bus –It is a group of conducting wires which carries Data only. DB is
bidirectional because data flow in both directions, from μp to memory or
Input/Output devices and from memory or Input/Output devices to μp. It is
ranging from 00 H to FF H. In write operation, the μp will put the data on
the DB, where as in read operation, the memory controller will get the data
from specific memory block and put it into the DB.

The width of the DB is directly related to the largest number that the bus
can carry, such as an 8 bit bus can represent 2 to the power of 8 unique
values, this equates to the number 0 to 255. A 16 bit bus can carry 0 to
65535.
Control bus –It is a group of conducting wires, which is used to generate

timing and control signals to control all the associated peripherals, μp uses
control bus to process data, that is what to do with selected memory
location. Some control signals are:
Memory read
Memory write
I/O read
I/O Write
Opcode fetch
If one line of control bus may be the read/write line. Low on this line
indicates the read operation, if this is high, it is write operation.
Control and Status Signals:
ALE (Address Latch Enable) signal: It goes high during first T state of a
every machine cycle and enables the lower 8-bits of the address, and for the
rest of the T states of the machine cycles the lower 8-bits are data nines.
IO/M’ – It is a status signal which determines whether the address is for

input-output or memory. When it is high (1) the address on the address bus
is for input-output devices. When it is low(0) the address on the address bus
is for the memory.
RD’ – It is a signal to control READ operation. When it is low the selected

memory or input-output device is read.
WR’ – It is a signal to control WRITE operation. When it goes low the data on
the data bus is written into the selected memory or I/O location.
SO, S1 – These are status signals. They distinguish the various types of
operations such as halt, reading, instruction fetching or writing.

IO/M’ S1 S0 RD’ WR’ Data Bus Status

X 0 0 High impedance Halt
X X X High impedance HOLD
X X X High impedance HLD
INTA’=1
0 0 1 1 0 Memory write
0 1 0 0 1 Memory read
0 1 1 0 1 Opcode fetch
1 0 1 1 0 I/O write
1 1 1 0 1 I/O read
1 1 1 INTA’=0 Interrupt acknowledge
READY – It senses whether a peripheral is ready to transfer data or not. If

READY is high (1) the peripheral is ready. If it is low (0) the microprocessor
waits till it goes high. It is useful for interfacing low speed devices.
Architecture:
Fig:8085 Architecture

(a) General Purpose Registers –
The 8085 has 6 general-purpose registers to store 8-bit data; these are
identified as- B, C, D, E, H, and L. They can be combined as register pairs –
BC, DE, and HL, to perform 16-bit operations. These registers are used to
store or copy temporary data during the execution of the program.
(b) Specific Purpose Registers –
Accumulator: The accumulator is an 8-bit register (can store 8-bit data)

that is the part of the arithmetic and logical unit (ALU). After performing
arithmetical or logical operations, the result is stored in accumulator.
Accumulator is also defined as register A.
Flag registers: It is a special purpose register and it is completely different

from other registers. It consists of 8 bits and only 5 of them are useful. The
other three are left vacant and are used in the future Intel versions.
The 5 flags are set or reset (1-set and 0-reset) after an operation according
to data condition of the result in the accumulator and other registers. The 5
flag registers are:
Fig: flag register
Sign Flag: It is 7thbit of the flag register, which is also known as the MSB.
It helps the programmer to know whether the number in the accumulator is
positive or negative. After any operation if the MSB of the result is 1, it
in indicates the number is negative and the sign flag becomes set, i.e.
1. If the MSB is 0, it indicates the number is positive and the sign flag
becomes reseti.e.0. from 00H to 7F, sign flag is 0 from 80H to FF, sign flag is
11- MSB is 1 (negative) 0- MSB is 0 (positive)
Example:
MVI A, 30H // A=30H

MVI B, 40 // B=40H
SUB B // (A = A – B)
A=-10H S=1
MVI A 40 // A=40H
// B=30H
MVI B 30 //(A = A – B)
SUB B A=10H S=0

Zero Flag:: 6th bit of the flag register. After any arithmetical or logical
operation if the result is 0 (00)H, the zero flag becomes set i.e. 1,
otherwise it becomes reset i.e. 0.00H zero flag is 1.from 01H to FFH zero flag
is 01- zero result, 0- non-zero result. It helps in determining if two numbers
are equal or not.
Example:
MVI A, 10 //A=10H
SUB A //(A = A – A)
A=00H and Z=1
Auxiliary Carry Flag (AC): It is 4th bit of the flag register. This flag is used
in BCD number system (0-9). If after any arithmetic or logical operation B(3)
generates any carry and passes on to B(4) this flag becomes set i.e. 1,
otherwise it becomes reset i.e. 0. Note –Flag register in 8085 which is not
accessible by user
Example:
MOV A, 2B //A=2BH
MOV B ,39 //B=39H
ADD B //(A = A + B)
A= , AC=11
Parity Flag: It is 2nd bit of the flag register. This flag tests for number of 1’s
in the accumulator. If after any arithmetic or logical operation the
result has even parity, if the accumulator holds even number of 1’s, it
is set, P=1. On the other hand if the number of 1’s is odd, then it is reset,
P=0, it is said to be odd parity.
Example: MVI A 05 //A=05H
BCD code of 05H is 00000101, hence P=1
Carry Flag: 0th bit of the flag register. Carry is generated when performing
n bit operations and the result is more than n bits, then this flag
becomes set i.e. 1, otherwise it becomes reset i.e. 0. During subtraction
(A-B), if A>B it becomes reset and if (A<B) it becomes set. Carry flag is also
called borrow flag.1-carry out from MSB bit on addition or borrow into
MSB bit on subtraction 0-no carry out or borrow into MSB bit

Example:
MVI A 30 //A=30H
MVI B 40 //B=40H
SUB B // (A = A – B)
since A<B,CY=1 as 30 – 40 generates a carry/borrow.
MVI A 40 //A=40H
MVI B 30 //B=30H
SUB B //(A = A – B)
since A>B,CY=0 as 40 – 30 generates a carry/borrow.
(c) Memory Registers –There are two 16-bit registers used to hold memory
addresses. The size of these registers is 16 bits because the memory
addresses are 16 bits. They are:-
Program Counter: This register is used to sequence the execution of the

instructions. The function of the program counter is to point to the memory
address from which the next byte is to be fetched. When a byte (machine
code) is being fetched, the program counter is incremented by one to
point to the next memory location.
Stack Pointer: It is used as a memory pointer. It points to a memory

location in read/write memory, called the stack. It is always
incremented/decremented by 2 during push and pop operation.
Pin diagram & Description
1 Address & data bus 16

2 Control & status signals 6
3 Power supply & Clock related signals 5
4 Interrupts & peripheral initiated signals 7
5 Reset signals 2
6 DMA signals 2
7 Serial I/O signals 2

Fig: Pin diagram
1. Address Bus & Data Bus: The AB is a group of sixteen lines i.e A0-A15.
The AB is unidirectional, i.e., bits flow in one direction from the
microprocessor unit to the peripheral devices and uses the high order
address bus.
2. Control and Status Signals:
ALE – Address Latch Enable signal. It goes high during first T state of a
machine cycle and enables the lower 8-bits of the address, if its value is
1 otherwise data bus is activated.
IO/M’ – It is a status signal which determines whether the address is for

input- output or memory. When it is high(1) the address on the
address bus is for input- output devices. When it is low(0) the address
on the address bus is for the memory.
SO, S1 –Status signals. They distinguish various types of operations such

as halt, reading, instruction fetching or writing. types of operations as
given below.

IO/M’ S1 S0 Operation
0 0 0 HALT
0 0 1 Memory WRITE
0 1 0 Memory READ
0 1 1 OPCODE FETCH
1 0 1 I/O Read
1 1 0 I/O Read
1 1 1 interrupt ack
RD’( To control READ operation): When it is low the selected memory or

input-output device is read.
WR’( To control WRITE operation): When it goes low the data on the data
bus is written into the selected memory or I/O location.
READY – It senses whether a peripheral is ready to transfer data or not. If

READY is high (1) the peripheral is ready. If it is low(0) the microprocessor
waits till it goes high. It is useful for interfacing low speed devices.
3. Power Supply and Clock Frequency
Vcc – +5v power supply
Vss – Ground Reference
XI, X2(CLK in) – A crystal is connected at these two pins. The frequency
is internally divided by two, therefore, to operate a system at 3MHZ the
crystal should have frequency of 6MHZ.
CLK OUT – This signal can be used as the system clock for other devices.
Fig:clock setup

4. Interrupts & Peripheral Initiated Signals:
The 8085 has five interrupt signals that can be used to interrupt a program
execution.
(i)INTR
(ii)RST 7.5
(iii) RST 6.5
(iv) RST 5.5
(v) TRAP
In addition to Interrupts, there are three externally initiated signals namely

RESET, HOLD and READY. To respond to HOLD request, it has one signal
called HLDA.
INTR – It is an interrupt request signal.
INTA’ – It is an interrupt acknowledgment sent by the microprocessor

after INTR is received.
5. Reset Signals:
RESET IN’ – When the signal on this pin is low(0), the program-counter is
set to zero, the buses are tristated and the microprocessor unit is reset.
RESET OUT – This signal indicates that the MPU is being reset. The
signal can be used to reset other devices.
6. DMA Signals:
HOLD – It indicates that another device is requesting the use of the

address and data bus. Having received HOLD request the
microprocessor relinquishes the use of the buses as soon as the
current machine cycle is completed. Internal processing may continue.
After the removal of the HOLD signal the processor regains the bus.
HLDA – It is a signal which indicates that the hold request has been
received after the removal of a HOLD request, the HLDA goes low.
7. Serial I/O Ports:
Serial transmission in 8085 is implemented by the two signals SID and SOD
SID is a data line for serial input
SOD is a data line for serial output.

Point form of 8085 registers
Fig:
Instruction set:
Instruction: it is a command to the processor to perform a given task on

specified data. It has two parts
❖ Opcode
❖ Operand
Opcode: The task to be performed
Operand: data to be operated on
T state: A portion of an operation carried out in one system clock period is

called as T-state

Machine cycle: Time required to access the memory or input/output

devices is called machine cycle
Instruction cycle: it is time required to complete the execution of the

instruction. It consists of 1-5 M/Cs. Fetch, decode and execute are sub
tasks of instruction cycle
Instruction set of 8085 is classified based on size and based on the

operation
There are classified according to the size
❖ Single byte instructions

❖ Two byte instructions
❖ Three byte instructions
1Byte instruction: these instructions requires only one memory location for the
storing in the memory.
Ex: MOV,ADD,SUB,ORA,ANA.INR,DCR
2 Byte instruction: these instructions requires two one memory location for the
Ex: All the instructions with ending letter ‘I’, except LXI

3 Byte instruction: these instructions requires only three memory location for the
Ex: All instructions which are followed by 16 bit address.
8085 processor instruction set can be classified into 5 categories
Data transfer instruction--13
Arithmetic instructions--20
Logical instructions--19
Branch transfer instructions--8
Machine control instructions--14
Data transfer(13) Arithmetic(19) Logical(18) Machine

control(14)
MOV RD,RS ADD R ANA R PUSH Rp
MOV M,RS ADD M ANA M PUSH PSW
MOV RD,M ADI 8 Bit Data ANI 8 Bit Data POP Rp
MVI RD, 8 Bit Data ADC R ORA R POP PSW
MVI M, 8 Bit Data ADC M ORA M SPHL
LDA 16 Bit Address ACI 8 Bit Data ORI 8 Bit XTHL
Data
STA SUB R XRA R NOP
LHLD SUB M XRA M HLT
SHLD SUI 8 Bit Data XRI 8 Bit Data EI
LDAX RP SBB R CMP R DI
STAX RP SBB M CMP M RIM
LXI RP, 16 Bit Address SBI 8 Bit Data CPI 8 Bit Data SIM
XCHG INR R RAR IN
INR M RRC OUT
INR RP RAL
DCR R RLC
DCR M STC
DCX RP CMC
DAD RP CMA
DAA

Branching(8)
JUMP conditional/unconditional
CALL conditional/unconditional
RET conditional/unconditional
PCHL
RST-N
Jump conditional CALL conditional RET conditional RST
• JC • CC • RC • RST 0
• JNC • CNC • RNC • RST 1
• JP • CP • RP • RST 2
• JM • CM • RM • RST 3
• JPE • CPE • RPE • RST 4
• JPO • CPO • RPO • RST 5
• JZ • CZ • RZ • RST 6
• JNZ • CNZ • RNZ • RST 7
Data transfer instructions: They copy the data from a register (i/o or
memory) called source to another register (memory or i/o) called the
destination. Destination and the source registers are any of the 7 general
purpose registers. Memory to memory transfer is not available. Data transfer
instructions will not modify any flag after execution of the instructions.
B= 000
MOV Rd,Rs: 1B-1M/C-4T
C= 001
OP-Code fetch machine cycle D= 010
E= 011
MOV B,C H= 100
L= 101
O1 000 001 M= 110
A= 111
MOV M,Rs: the content of the register is transferred to the memory whose
address is specified in the HL register pair without losing the source
content.

MOV M,A MOV R,M MOV A,M

01 110 111=77H 1B-2M/C-7T 01 111 110
1B-2M/C-7T OPCODE FETCH-4T
OP-Code fetch 4T MEMORY READ- 3T
Memory write 3T
MVI R, 8Bit data: this instruction directly copies the 8 bit data which is
available in the instruction itself in to the specified register.
MVI B,42H
2B-2M/C-7T
Opcode fetch -4T
Memory read-3T
MVI B-0000 0110-06H
MVI C-0000 1110-0EH
MVI D-0001 0110-16H
MVI E-0001 1110-1EH
MVI H-0010 0110-26H
MVI L-0010 1110-2EH
MVI M-0011 0110-36H
MVI L-0011 1110-3EH
A=47H=0100 0111
B=51H=0101 0001
------------------------- S Z - AC - P - CY
1 0 X 0 X 0 X 0
A=98H=1001 1000
A=76H=0111 0110
S Z - AC - P - CY
((HL))=A2H=1010 0010 0 0 X 0 X 1 X 1
-----------------------------

A=118H=1 0001 1000
ACI 57H
A=26H=0010 0110
S Z - AC - P - CY
57H=0101 0111 0 0 X 0 X 1 X 0
------------------------
A=7E=0111 1110
A=XXH,, B=24H,C=98H,D=54H AND E=A1

MOV A,C // A=98H
ADD E // A=A+E 98+A1=139H
MOV L,A // L=39H
MOV A,B // A=24H
ADC D // A=CY+A+D=1+24+54=79H
MOV H,A //H=79H
S Z - AC - P - CY
0 0 X 0 X 0 X 0
CY=1,A=26H
ACI 57H
A=26H=0010 0110 S Z - AC - P - CY
57H=0101 0111 0 0 X 0 X 1 X 0
CY=1= 1
-------------------------
A=7EH=0111 1110
-----------------------

SUB C
A=37H,C=40H,
A=37H=0011 0111------0011 0111 S Z - AC - P - CY
-C=40H=0100 0000-----1100 0000 1 0 X 0 X 0 X 0
------------------------- ----------------
F7H 1111 0111=-9
A=40H
SUI 37H
S Z - AC - P - CY
A=40H=0100 0000-------0100 0000 0 0 X 0 X 1 X 1
- 37H=0011 0111-------1100 1001

------------------------- --------------
A=03H= 1 0000 1001
INR R/M (Increment register/Memory by 1): The specified register or
memory content is incremented by one and is stored in the same place. No
flags are modified. All the flags are modified except carry flag.
INR R 1B-1M/C-4T Opcode fetch -4T
INR M 1B-3M/C-10T Opcode fetch -4T
Memory read-3T
Memory Write-3T
Ex: B=25H
INR B S Z - AC - P - CY
0 0 X 0 X 0 X 0
B=25H=0010 0101
+1H=0000 0001
-------------------------
B=26H=0010 0110
Ex: HL=3000H
3000H 71H
71H=0111 0001

+1H=0000 0001
---------------------- S Z - AC - P - CY
0 0 X 0 X 1 X 0
((HL))=A1H=0111 0010
INX Rp: (Increment register pair by 1): The specified register pair content
is incremented by one and is stored in the same place. No flags are modified.
INX Rp 1B-1M/C-6T Opcode fetch -6T
BC=9FFFH
INX B
BC=9FFFFH=1001 1111 1111 1111
+1=0000 0000 0000 0001
-------------------------------------------------
BC=A000H= 1010 0000 0000 0000
DCR R/M (Decrement register/Memory by 1): The specified register or

memory content is decremented by one and is stored in the same place. No
flags are modified. All the flags are modified except carry flag.
DCR R 1B-1M/C-4T Opcode fetch -4T
DCR M 1B-3M/C-10T Opcode fetch -4T
Memory read-3T
Memory Write-3T
Ex: B=00H
DCR B
B=00H=0000 0000 S Z - AC - P - CY
1 0 X 0 X 1 X 0
-1H=1111 1111
-------------------------
B=FFH=1111 1111

Ex: HL=3000H
A0H=1010 0000 3000H

A0H
-1H=1111 1111
----------------------
((HL))=9FH=1 1001 1111 S Z - AC - P - CY
1 0 X 0 X 1 X 0
DCX Rp(Decrement register pair by 1): the specified register pair content
is decremented by one and is stored in the same place. no flags are
modified.
DCX Rp 1B-1M/C-6T Opcode fetch -6T
Ex: DE=1FFFH
DCX D
DE=1FFFFH=0001 1111 1111 1111
-1=1111 1111 1111 1111
-------------------------------------------------
DE=1FFEH=1 0001 1111 1111 1110
DAD Rp: (Add register pair to HL) 16 bit addition: this instruction is used
to add the content of HL with the content of the register pair specified in the
instruction. If the result is greater than 16 bits, then the carry flag is set
and no other flags are modified. This instruction also used to multiply the
HL content by 2.
DADRp 1B-3M/C-10T Opcode fetch -4T

Bus ideal-3T
Bus ideal-3T
Ex: HL=0000; SP=2050

DAD SP
HL=0000H=0000 0000 0000 0000
+SP=2050H=0010 0000 0101 0000
---------------------------------------------
HL=2050H=0010 0000 0101 0000
Ex: HL=0242
DAD H
HL=0242H=0000 0010 0100 0010
+HL=0242H=0000 0010 0100 0010
---------------------------------------------
=0484H=0000 0100 1000 01000
DAA (Decimal Adjust Accumulator):
DAA 1B-1M/C-4T Opcode fetch -4T
Ex: BC=0012; HL=0039

DAD B //HL=HL+BC
DAA
HL=0039=0000 0000 0011 1001
BC=0012=0000 0000 0001 0010
-----------------------------------------
HL=0051=0000 0000 0100 1011
0110
--------------------------------------------
HL=0051=0000 0000 0101 0001

LOGICAL INSTRUCTIONS
µP is basically a programmable logic chip, hence it can perform all logical
functions through its instructions such as Rotate, AND,OR,EX-OR and NOT.
All the logic operations are performed in the accumulator.
1 AND 3 ANA,R
ANA,M
ANI,8 bit data
2 OR 3 ORA,R
ORA,M
ORI,8bit data
3 EX OR 3 XRA,R
XRA,M
XRI,8bit data
4 Rotate 4 RAR
RRC
RAL
RLC
5 NOT 3 STC
CMC
CMA
6 Compare 3 CMP,R
CMP,M
CPI,8 bit data
Addressing modes:
• To perform any operation, we have to give the corresponding
instructions to the microprocessor.
• In each instruction, programmer has to specify 3 things:
– Operation to be performed.
– Address of source of data.
– Address of destination of result.
The method by which the address of source of data or the address of
destination of result is given in the instruction is called Addressing Modes.

The term addressing mode refers to the way in which the operand of the
instruction is specified.
Types of addressing modes:
i) Immediate Addressing Mode
ii)Register Addressing Mode
iii) Direct Addressing Mode
iv) Register Indirect Addressing Mode
v)Implicit Addressing Mode
i)Immediate Addressing Mode: In immediate addressing mode the source
operand is always data. If the data is 8-bit, then the instruction will be of 2
bytes, if the data is of 16-bit then the instruction will be of 3 bytes.
Examples:
MVI B, 45 //B=45H
LXI H 3050 // HL=3050H
JMP address //jump to the operand address immediately
ii)Register Addressing Mode: In register addressing mode, the data to be

operated is available inside the register(s) and register(s) is(are) operands.
Therefore the operation is performed within various registers of the
microprocessor.
Examples:
MOV A, B // A=B
ADD B // A=A+B
INR A // A=A+1
iii)Direct Addressing Mode: In direct addressing mode, the data to be
operated is available inside a memory location and that memory location is
directly specified as an operand. The operand is directly available in the
instruction itself.
Examples:
LDA 2050 // (A)=(2050)
LHLD address //(HL)=(contents of 16-bit memory location)
IN 35 //(read the data from port whose address is 35)
iv)Register Indirect Addressing Mode: In register indirect addressing
mode, the data to be operated is available inside a memory location and that
memory location is indirectly specified b a register pair.

Examples:
MOV A, M //(A)=((HL))
LDAX B //(A)=(BC)
LXIH 9570 //(HL)=9570
v)Implied/Implicit Addressing Mode: In implied/implicit addressing mode
the operand is hidden and the data to be operated is available in the
instruction itself.
Examples:
CMA //(A)=1’s complement of the accumulator A)
RRC //(rotate accumulator A right by one bit)
RLC //(rotate accumulator A left by one bit)
Interrupt structure:
When the microprocessor receives any interrupt signal from peripheral(s)
which are requesting its services, it stops its current program execution and
program control is transferred to a sub-routine by generating a CALL signal
and after executing sub-routine by generating RET signal again the program
control is transferred to the main program from where it had stopped.
Mainly in the microprocessor based system the interrupts are used for data
transfer between the peripheral and the microprocessor.
Interrupts can be classified into various categories based on different
parameters:
i) Internally generate interrupts & externally generated interrupts
ii) Hardware & Software interrupts
iii) Maskable & non Maskable interrupts
iv) Vector and non vector interrupts
Internally generated interrupts: Interrupts arises due to the use of illegal
instructions or using of erroneous data. These are synchronous signals
Ex: register overflow, divide by zero, using of invalid operation
Externally generated interrupts: If the request is coming through
hardware pins they are called externally generated interrupts. These are
asynchronous signals
Ex: power supply failure, timing device signals
Hardware and Software Interrupts: When microprocessors receive
interrupt signals through pins (hardware) of microprocessor, they are
known as Hardware Interrupts. There are 5 Hardware Interrupts.

They are – INTR, RST 7.5, RST 6.5, RST 5.5, TRAP
Software Interrupts are those which are inserted in between the program
which means these are nemonics of microprocessor. There are 8 software
interrupts.
They are – RST 0, RST 1, RST 2, RST 3, RST 4, RST 5, RST 6, RST 7.
Non-Vectored Interrupts: the interrupts whose vector address is not yet
predefined. The interrupting device gives the address of sub-routine for
these interrupts.
Ex: INTR
Non-Vectored Interrupt address generation:
1. The interrupt process should be enabled using the EI instruction.

2. The 8085 checks for an interrupt during the execution of every
instruction.
3. If INTR is high, MP completes current instruction, disables the
interrupt and sends INTA (Interrupt acknowledge) signal to the device
that interrupted
4. INTA allows the I/O device to send a RST instruction through data
bus.
5. Upon receiving the INTA signal, MP saves the memory location of the
next instruction on the stack and the program is transferred to ‘call’
location (ISR Call) specified by the RST instruction
6. Microprocessor Performs the ISR.
7. ISR must include the ‘EI’ instruction to enable the further interrupt
within the program.
8. RET instruction at the end of the ISR allows the MP to retrieve the
return address from the stack and the program is transferred back to
where the program was interrupted.

Vectored Interrupts: Which have fixed vector address (starting address of

sub-routine) and after executing these, program control is transferred to
that address. Vector Addresses are calculated by the formula 8 * TYPE
Interrupt Decimal address Vector address
RST-0 0 0000H
RST-1 8 0008H
RST-2 16 0010H
RST-3 24 0018H
RST-4 32 0020H
TRAP 34 0024H
RST-5 40 0028H
RST-5.5 44 002CH
RST-6 48 0030H
RST-6.5 52 0034H
RST-7 56 0038H
RST-7.5 60 003CH
Maskable Interrupts: The interrupts which can be disabled or ignored by
the microprocessor. These interrupts are either edge-triggered or level-
triggered, so they can be disabled. Ex:INTR, RST 7.5, RST 6.5, RST 5.5
Fig: masking diagram

Non-Maskable Interrupts: The interrupts which cannot be disabled or

ignored by microprocessor. TRAP is a non-maskable interrupt. It consists
of both level as well as e dge triggering and is used in critical power failure
conditions.
Enable Interrupt (EI) – The interrupt enable flip-flop is set and all
interrupts are enabled following the execution of next instruction followed by
EI. No flags are affected. After a system reset, the interrupt enable flip-flop is
reset, thus disabling the interrupts. This instruction is necessary to enable
the interrupts again (except TRAP).
Disable Interrupt (DI) – This instruction is used to reset the value of enable
flip-flop hence disabling all the interrupts. No flags are affected by this
instruction.
Set Interrupt Mask (SIM) – It is used to implement the hardware interrupts
(RST 7.5, RST 6.5, RST 5.5) by setting various bits to form masks or
generate output data via the Serial Output Data (SOD) line. First the
required value is loaded in accumulator then SIM will take the bit pattern
from it.

RIM: This instruction is used to read the status of the hardware interrupts
(RST 7.5, RST 6.5, RST 5.5) by loading into the A register a byte which
defines the condition of the mask bits for the interrupts. It also reads the
condition of SID (Serial Input Data) bit on the microprocessor.

Interrupt priority

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Module-1 8085 Microprocessors & Architecture

Module I 8085 Microprocessors & Architecture

Microprocessors historical, perspective, 8085 pin diagram, architecture,

Microprocessor: It is an IC with all the functions of a CPU however, it

Microprocessors can be classified based on the data bus width

Microproces Bata Bus Pins No.Of

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 1

2. Salient features of 8085 μp:

❖ Data bus (DB) is a group of 8 lines D0 – D7.

❖ First 8 lines of AB & 8 lines of DBs are multiplexed AD0 – AD7.

❖ It supports 5 hardware interrupt & 8 software interrupt.

❖ A 16 bit program counter (PC)

❖ A 16 bit stack pointer (SP)

❖ It requires a signal +5V power supply

❖ Max.clock Frequency= 3MHz and Min.clock Frequency=500kHz

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 2

Bus is a group of conducting wires which carries information, all the

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 3

Control bus –It is a group of conducting wires, which is used to generate

Control and Status Signals:

IO/M’ – It is a status signal which determines whether the address is for

RD’ – It is a signal to control READ operation. When it is low the selected

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 4

IO/M’ S1 S0 RD’ WR’ Data Bus Status

READY – It senses whether a peripheral is ready to transfer data or not. If

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 5

(a) General Purpose Registers –

(b) Specific Purpose Registers –

Accumulator: The accumulator is an 8-bit register (can store 8-bit data)

Flag registers: It is a special purpose register and it is completely different

Fig: flag register

MVI A, 30H // A=30H

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 6

A=00H and Z=1

Example: MVI A 05 //A=05H

BCD code of 05H is 00000101, hence P=1

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 7

Program Counter: This register is used to sequence the execution of the

Stack Pointer: It is used as a memory pointer. It points to a memory

Pin diagram & Description

1 Address & data bus 16

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 8

Fig: Pin diagram

2. Control and Status Signals:

IO/M’ – It is a status signal which determines whether the address is for

SO, S1 –Status signals. They distinguish various types of operations such

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 9

RD’( To control READ operation): When it is low the selected memory or

READY – It senses whether a peripheral is ready to transfer data or not. If

3. Power Supply and Clock Frequency

Vcc – +5v power supply

Vss – Ground Reference

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 10

4. Interrupts & Peripheral Initiated Signals:

In addition to Interrupts, there are three externally initiated signals namely

INTR – It is an interrupt request signal.

INTA’ – It is an interrupt acknowledgment sent by the microprocessor

HOLD – It indicates that another device is requesting the use of the

7. Serial I/O Ports:

SID is a data line for serial input

SOD is a data line for serial output.

Dr.Sreenivasa Rao Ijjada, Dept of ECE,GIT, GITAM University Visakhapatnam. Page 11

Point form of 8085 registers

Instruction: it is a command to the processor to perform a given task on