20th INTERNATIONAL CONFERENCE ON MICRO/NANOTECHNOLOGIES AND ELECTRON DEVICES EDM 2019
Voltage Control of Autonomous Three-Phase
Four-Leg VSI Based on Scalar PR Controllers
Alexander G. Garganeev1, Raef Aboelsaud2, Student Member, IEEE, and A. Ibrahim3, Student Member, IEEE
1,2,3
National Research Tomsk Polytechnic University, Tomsk, Russia
2,3
Electrical Power & Machines Department, Faculty of Engineering, Zagazig University, Zagazig, Egypt
Abstract – A control of a three-phase four-leg autonomous
voltage inverter (VSI) based on scalar PR-controllers with as
part of an autonomous power supply system (APS) is
presented. The proposed method independently controls each
phase load voltage in the coordinate system ABC. The control
system of the VSI consists of an outer control loop for
controlling the load voltages and an inner control loop for
controlling the output current of the VSI. To analyze the
stability of the system and design the PR regulators, the root
locus and the Bode diagram are used. The control signals
applied for the VSI switches are provided by Scalar PWM.
Studies of operating modes of APS are carried out using
MATLAB/SIMULINK. The proposed method shows good
tracking of the reference output voltage in the static and
dynamic modes of APS.
Index Terms – power supply system, PR control, autonomous
inverter, Scalar PWM.
I. INTRODUCTION
R ECENTLY, POWER CONVERTERS have found
widespread applications in power supply systems
(APS) [1]–[7]. In APSs, the generated power is limited and
the loads are unpredictable both in terms of demand power
and in nature — loads can be single- or three-phase,
balanced (symmetrical) or unbalanced, linear or nonlinear.
Asymmetry and harmonic voltage distortions can cause
serious equipment problems, such as vibration, overvoltage,
overheating, etc [2].
The three-phase voltage source inverters with fourth leg
topology (4-leg VSI) can handle load unbalances in the
stand-alone four-wire systems. In this topology, the neutral
line is connected to the midpoint "n" between the transistor
switches Sn, S'n in the fourth leg (see Fig. 1); this reduces the
use of large and expensive dc link capacitors and provides a
lower DC link voltage ripple in comparison with the other
topologies.
For regulating the output voltage of this inverter type in
APS, a number of modulation methods based on pulse width
modulation (PWM) or on space vector modulation (SVM)
can be used. SVM methods provide good utilization of the
converter's capabilities, such as obtaining a maximum
output voltage for a given DC link voltage, as well as a low
978-1-7281-1753-9/19/$31.00 ©2019 IEEE
558
harmonic distortion of the output currents and voltages for a
given switching frequency [8]. However, despite these
advantages, these methods include a large number of
complex calculations [9]. PWM is simpler than SVM, but it
has some drawbacks, in particular, it provides a worse
harmonic composition and has no ability to modulate the
zero sequence voltage in the neutral line. To solve these
shortcomings, PWM varieties are proposed, such as digital,
discontinuous, and scalar PWM [10]–[12].
To achieve the high ability of inverters to compensate for
voltage imbalances and harmonic distortion, proper control
is required [13]. Linear regulators are well suited to control
the modulated voltage of VSIs. The most common
regulators used in these applications are Proportional-
Integral-Derivative (PID) regulators in the DQ0 reference
frame [14] and proportional-resonant (PR) regulators in the
αβ0 reference frame [15].
PID controllers operate with DC values, providing a zero
steady state error. Therefore, they are implemented in the
rotating frame DQ0 using the park transformation [16]. This
may be a disadvantage in the implementation due to the
additional resources of calculations. In addition, with PID-
control, compensation is needed for the mutual coupling
between the D and Q axes in the DQ0 coordinate system.
PR-regulators do not require rotational transformations and
can operate in the stationary coordinate system αβ0 with the
absence of coupling between the control signals. Moreover,
the PR controller has good robustness against the changes of
system parameters and has a fast dynamic response.
This paper presents an improved control scheme based on
scalar PR regulators for a three-phase four-leg VSI. The
presented scheme used to control the VSI to provide a
balanced (symmetrical) load voltage with low harmonic
distortion in conditions of load imbalances and nonlinearity.
The proposed control scheme consists of an external voltage
control loop and an internal current control loop. The voltage
loop is used to control the output voltages, and the internal
current loop is used to provide the scalar PWM reference
signals.
The main advantages of this method are simplicity, a small
amount of voltage tracking error, and a fast transient
process. The article explains the design of the proposed
control system, examines its effectiveness under various
load conditions. The theoretical results are verified by
simulation.
20th INTERNATIONAL CONFERENCE ON MICRO/NANOTECHNOLOGIES AND ELECTRON DEVICES EDM 2019

Fig. 1. Three-phase APS containing 4-leg VSI with output LC filter.

II. SYSTEM MODEL

Fig. 1 shows the APS circuit in which the neutral wire is
connected to the midpoint "n" in the fourth leg of the four-
leg inverter. Renewable power sources and their converters
in APS can be represented as an ideal DC voltage source
with internal resistance Rs. The LC filter is connected at the
Fig. 3. Block diagram of APS.
VSI output to eliminate high harmonic frequencies.
To synthesize the mathematical model of the inverter, it is Fig. 2 shows a single-phase representation of a three-phase
important to obtain the relation between the switching states APS with an LC-filter. The input voltage of the inverter is
and the output voltage of the VSI. There are four control modeled as an ideal voltage source (e), the impedance of the
switching signals for a four-leg inverter named by Sa, Sb, Sc load is represented by ZL [17]. The block diagram of APS
and Sn [1]. These signals form a total of 24 = 16 possible for each phase is shown in Fig. 3.
switching states of the converter.
The output voltages in accordance with the switching
signals are described as follows: III. PR-CONTROL STRUCTURE
ean = (Sa − Sn) Vdc, (1) The proposed control system consists of an external
ebn = (Sb − Sn) Vdc, (2) control circuit of the load voltage and an internal control
ecn = (Sc − Sn) Vdc, (3) circuit of the output current of the VSI. In the proposed
control strategy, the main task is to control the inverter to
where Vdc is the input DC voltage. The switching signals can
provide balanced (symmetric) voltages of three-phase loads
be expressed by:
with low harmonic distortion. The scalar PR-regulator
{
S k = 1, u p p er sw itch clo sed an d lo w er sw itch o p en ed , (4)
0, u p p er sw itch o p en ed an d lo w er sw itch clo sed
regulates the instantaneous voltage of the APS loads in the
ABC reference frame, whereas in the current control loop a
Where k = a,b,c,n. The mathematical model of the system simple proportional regulator is used.
in the ABC coordinate system can be expressed as: The transfer function of the PR controller is defined [18]:

e an  i oa  d i oa  v a  2 k i ωc s
ebn  = R i ob  + L i ob  + v b  , (5) G PR (s) = k p + (7)
ecn  i oc  dt i oc  v c 
    s + 2ωc s + ω n2
2

i oa  i a  d v a 
i ob  = i b  + C v  (6) Where kp is the proportional gain, and ki is the integral gain
i oc  i c  dt v bc 
  of the resonant regulator, ωn is the angular frequency of the
output signal, and ωc is the frequency of the resonance
bandwidth. The PR-regulator provides high gain at the main
frequency of the load voltage (ωn = 2*π*50 rad/s) and zero
gain for other frequencies. ωc is used to reduce the sensitivity
of the controller to any deviation of the frequency of the
reference signal under non-ideal conditions. The Bode plot
of the transfer function of the PR controller is shown in
Fig. 4, where kp = 1, ki = 100, ωn = 314 rad/s and ωc = 1 rad/s.
Fig. 2. Per-phase representation of APS.

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 20th INTERNATIONAL CONFERENCE ON MICRO/NANOTECHNOLOGIES AND ELECTRON DEVICES EDM 2019

* * *
Where v a , v b , and v c are reference values for load
voltage. The voltage control loop scheme can be obtained by
substituting (11) in (6):

i oa
*  v a* −v a 
 *  i a   * 
i ob  = i b  + G PR (s) v b* −v b  , (12)
*
i oc  i c  v c −v c 
   
By using expressions (10) and (12), the schematic diagram
of the APS with the proposed control scheme can be
synthesized in Fig. 5. The proposed control system operates
in ABC coordinates, which makes it possible to
independently regulate each phase load voltage. Moreover,
additional decoupling loops are not required, which
simplifies the design of the controller.

IV. PR-CONTROL DESIGN

Fig. 4. Bode plot of PR-regulator. A. Design of current control loop

A. Current Control Loop The model of the internal control loop current is shown in
Fig. 6. Root locus and Bode plot corresponding APS model
From (5) the voltage drop across the inductance of the LC with current control loop are shown in Fig. 7 and 8,
filter can be expressed as: respectively. The root locus shows that all the roots of the
system are on the left side, and the system is stable for all
v fa  i oa  d i oa  gain values of the proportional controller.
v fb  = R i ob  + L i ob  The open loop transfer function of the APS model with
v fc  i oc  dt i oc  , (8) the current control loop can be written as:
kZ L Cs
G1 (s) = (13)
If the proportional controller is employed to regulate the (CZ L s + 1)(Ls + R ) + Z L
voltage drop based on the current feedback control, i.e.
The gain of the proportional current controller can be
i oa
*
− i oa  obtained in accordance with the desired bandwidth
v fa   * 
v fb  = k − i ob  frequency using the Bode diagram [17]. The bandwidth
i ob (9) frequency ωbi can be maybe calculated based on the
v fc  *
i oc − i oc 
  expression:
* * * 20log(G ( j ωb i )) = − 20 dB , (14)
Where ioa, iob , and ioc are reference values for the
inverter output currents. Taking into account expression (9)
with (5), we will have:
i oa
*
− i oa  v 
e an   *  a
ebn  = ( k ) i ob − i ob  + + v b  , (10)
ecn  i oc − i oc  v c 
*
 

B. Voltage control loop

Similarly, to the previous circuit, when the PR-regulators
are used to regulate the voltage across the capacitors of the
LC filter, we have:
v a* −v a 
d v a   
C v b  = G PR (s) v b* −v b  (11)
dt v c  *
v c −v c 
 
Fig. 5. Schematic diagram of APS with PR-controller.

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20th INTERNATIONAL CONFERENCE ON MICRO/NANOTECHNOLOGIES AND ELECTRON DEVICES EDM 2019

The PR controller coefficients can be adjusted using the

Fig. 6. Block diagram of APS with the current control loop.
root locus and the Bode diagram in the MATLAB control
toolbox. In this article, the design requirements are defined
as follows:
- the settling time of the step response (tset) is not more
than 0.001 s;
- overshoot of single step response (% σ) not more than
5%;
- the system frequency bandwidth (ωbv) is selected as
one-tenth of the switching frequency (0.1 * fs).
Therefore, the PR controller coefficients are chosen as
kp = 0.3, ki = 150.
The Bode plot and the root locus of the open-loop transfer
function G (s) with the selected PR gain factors are shown
in Fig. 10 and 11.

Fig. 9. The block diagram of APS with current and voltage control loops.
Fig. 7. Root locus of the transfer function G1(s).

Fig. 8. Bode diagram of the transfer function G1(s).

In principle, the required bandwidth frequency should be

selected lower than the switching frequency (fs) to limit the
response of the current control loop to the switching noise. Fig. 10. Bode diagram of the transfer function G(s).
Accordingly, this frequency is chosen equal to a quarter of
the switching frequency, i.e., ωbi = 2π (0.25 × (fs =
5 kHz)) ≅ 8000 rad / s, and in accordance with expressions
(13) and (14), the proportional gain of the regulator is chosen
k ≅ 20.

B. Voltage Control Loop Design

The next step after determining the gain of the internal
current control loop is to design the outer voltage control
loop. The block diagram of the APS with current and voltage
control loops is shown in Fig. 9, where v* is the reference
voltage for the control system.
The open-loop transfer function of APS with the proposed
control system can be written as:
G ( s ) = GPR ( s )G1 ( s ) , (15)
Fig. 11. Root locus of the transfer function G(s).

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V. SCALAR PWM SCHEME

An additional (fourth) leg of the 4-leg inverter provides a
neutral wire, as well as regulate the zero sequence voltage
(ez). In the scalar PWM method, the zero sequence voltage
(ez) is added to the reference voltage (e*). Thus, the new
reference voltages are set:

e* = [e*a e*b e c* ] , (16)

*' *
e = e + ez ,
a a (17)
Fig.12. Topological scheme of scalar PWM.
*' *
e = e + ez ,
b b (18)
e*'c = e*c + e z (19)

Moreover, the zero sequence voltage is considered to be

the reference voltage of the fourth leg of the inverter, as
shown in Fig. 12. The zero-sequence voltage can be
expressed by the relation [12] [19]:

e z =V dc ( 0.5 − μ ) − ( 1 − μ )v Max − μ v Min (20)

v v
Where M ax and Min are the maximum and minimum
voltage values selected among the three reference voltages
Fig. 13. The topology of the three-phase nonlinear unbalanced loads.
for each sample time. μ is the distribution ratio through
which the access time to the "zero" voltage vectors TABLE I
("timing") is selected. In fact, the "timing" of the zero- SYSTEM PARAMETERS
voltage vectors is the period during which all the upper keys Parameters Values
of the VSI are closed or open. The distribution ratio should DC input voltage of the inverter Vdc = 640 V
be selected in the interval between 0 and 1 [19], and in this Internal resistance of the input
Rs = 0.5 Ω
voltage source
article, it is chosen to be 0.5.
Sampling time Ts = 20 µs
The scalar PWM can simply be realized with the Switching frequency fs = 5000Hz
calculation of the zero sequence voltage, as shown in the DC-link capacitance Cdc = 1000 µF
block diagram of Fig. 12. LC filter L = 2.5 mH, C= 80 µF
Balanced loads Ra = Rb = Rc = 20 Ω
VI. SIMULATION RESULTS TABLE II
Mathematical modeling and simulation are carried out in LOAD PARAMETERS
the MATLAB / SIMULINK environment. The parameters Case Load
used in the simulation are shown in Table I. Various case 1) Unbalanced resistive load Ra = 5Ω, Rb = 10Ω, Rc = ∞
studies of modeling under various loads are performed to Ra = 5Ω, Rb = 10Ω, Rc = ∞
2) Unbalanced inductive load
show the verification of the performance of the proposed La = 10mH, Lb = 30mH
scheme of the PR controller with the scalar PWM in steady La' = 50 mH, Ra'=20 Ω,
state and transient conditions. Rb1'=1 Ω, Rb2'=60 Ω,
3) Nonlinear unbalanced load Cb'=3000 µF,
A. Steady-state performance Lc'= 20 mH,
Rc'=70 Ω, Cc'= 5000 µF
For the static mode of operation of the APS, three
simulation studies are performed. Three-phase asymmetrical
resistive and inductive loads are connected to the inverter. In Due to the non-linearity of the load, the load current is
addition, single-phase non-linear loads is used, the topology substantially non-sinusoidal and the neutral current
of which is shown in Fig. 13. The parameters of the loads circulates through the neutral of the VSI as shown in Fig. 15.
used in the simulation are listed in Table II. At the same time, the output voltages of the APS remain
The load voltages and currents waveforms of 4-leg VSI sinusoidal and symmetrical. The Total Harmonic Distortion
under unbalanced resistive and inductive loads are shown in (THD) of the load voltage is within acceptable limits, not
Fig. 14. The results show that the control strategy is able to exceeding 0.9%. Although the system operates under non-
regulate the load voltage with low harmonic distortion. Load linear and asymmetrical loads, the proposed control
voltages follow the reference voltage well and are sinusoidal algorithm provides a slight voltage ripple in the DC link as
and symmetrical with low harmonic distortion. shown in Fig. 14 and 15.

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20th INTERNATIONAL CONFERENCE ON MICRO/NANOTECHNOLOGIES AND ELECTRON DEVICES EDM 2019

Fig. 14. Load voltages, load currents, neutral current, and voltage in the DC link: (a) Unbalanced resistive loads (b) Unbalanced inductive loads.

Fig. 16. Voltage and load currents of APS in transient mode.

Fig. 15. Load voltages, load currents, neutral current, and voltage in the
DC link: Nonlinear unbalanced load.
B. Transient performance
A step change from no-load to a balanced resistive load
(Ra = Rb = Rc = 10 Ω) at 0.2 s. is applied, the load voltages
and load currents are shown in Fig. 16. The results show that
the amplitude of the load voltages is not changed after
connecting the load to the inverter. Moreover, the transient
response is very fast with low overshoot level.

TABLE III VII. CONCLUSION

THE PERFORMANCE OF THE PROPOSED CONTROLLER
Case %THD
The results show that the proposed PR control scheme
% ΔVdc % LVUF provides good voltage regulation. The proposed control
va vb vc
1 1.5608 0.39 0.43 0.46 0.46 strategy improves the quality of the APS load voltages in
2 1.0901 0.55 0.57 0.54 0.54 static and dynamic modes when operating on both linear,
3 0.7059 0.75 0.86 0.85 0.85 non-linear and unbalanced loads. In addition, load voltages
remain sinusoidal and symmetrical under different load
To assess the effectiveness of the proposed control conditions, providing a fast dynamic response with a low
strategy, % voltage ripple in the DC link (% ΔVdc), THD and level of overshoot.
load voltage unbalance factor (LVUF) [20] were estimated
for all cases of load (see Table III).
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