EEE415 Week05 Micro Architecture

DRAFT 7/12/2023
EEE 415 - Microprocessors and Embedded Systems
EEE Micro Architecture

Building Blocks,
415 Performance Analysis,

Single Cycle Processor
Lecture 5.1
Week 5
Dr. Sajid Muhaimin Choudhury, Assistant Professor
Department of Electrical and Electronics Engineering
Bangladesh University of Engineering and Technology
Topics this Week

• Jumping up a few levels of abstraction
• Architecture: programmer’s view of computer
– Defined by instructions & operand locations

(Harris Chapter 6.1,6.2)
• Microarchitecture: how to implement an
architecture in hardware
(Harris Chapter 7)
Dr. Sajid Muhaimin Choudhury 2

EEE 415 - Department of EEE, BUET Digital Design and Computer Architecture: ARM® Edition © 2015
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DRAFT 7/12/2023
Architectural Set and Instruction Set

• Computer Architecture is defined by its instruction set and
architectural state. (For ARMv7 A, 16 32-bit registers and
status registers.)
• Based on the current architectural state, the processor
executes a particular instruction with a particular set of data to
produce a new architectural state.
• Architecture DOES NOT specify HOW the particular

instructions are implemented with underlying logic structure

Micro Architecture
• Microarchitecture is the connection between logic and architecture.
• Microarchitecture is the specific arrangement of registers, ALUs,
finite state machines (FSMs), memories, and other logic building
blocks needed to implement an architecture.
• A particular architecture, such as ARM, may have many different
microarchitectures, each with different trade-offs of performance,
cost, and complexity. They all run the same programs, but their
internal designs vary widely.

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DRAFT 7/12/2023

Building Blocks,

Lecture 5.1
Week 5
Pre-requisite / Recaps
B
• Combinational Logic Circuits B = 0
B
B = 1
• Sequential Logic Circuits
• Memory
CLK
D Q
Q

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Architectural State Elements

Determines everything about a processor:
• Architectural state:
– 16 registers (including PC)
– Status register
• Memory

ARM Architectural State Elements

CLK
4 4
CLK
Status CLK
CLK WE3
A1 RD1 WE
4 32
PC' PC
A RD A RD
32 32 32 32 A2 RD2 32 32
Instructi on
4 32 Data
Memory A3 Register Memory
4
WD3 File WD
32 32
R15
32

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DRAFT 7/12/2023
Architectural State Elements: Program Counter

CLK
4 4
CLK
Status CLK
CLK WE3
A1 RD1 WE
4 32
PC' PC
A RD A RD
32 32 32 32 A2 RD2 32 32
Instructi on
4 32 Data
4
WD3 File WD
32 32
R15
32
Although the program counter (PC) is logically part of the register

file, it is read and written on every cycle independent of the normal register file
operation and is more naturally built as a stand-alone 32-bit register.
Its output, PC, points to the current instruction.
Its input, PC′, indicates the address of the next instruction.

Architectural State Elements: Instruction Memory

CLK
4 4
CLK
Status CLK
CLK WE3
A1 RD1 WE
4 32
PC' PC
A RD A RD
32 32 32 32 A2 RD2 32 32
Instructi on
4 32 Data
4
WD3 File WD
32 32
R15
32
The instruction memory has a single read port.

It takes a 32-bit instruction address input, A
reads the 32-bit instruction from that address onto
the read data output, RD
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Architectural State Elements: Register File

CLK
4 4
CLK
Status CLK
CLK WE3
A1 RD1 WE
4 32
PC' PC
A RD A RD
32 32 32 32 A2 RD2 32 32
Instructi on
4 32 Data
4
WD3 File WD
32 32
R15
32
15-element × 32-bit register

2 read ports, 1 write port. Each 4 bit address for 16 registers

11
• The 15-element × 32-bit register file holds registers R0–R14 and has an
additional input to receive R15 from the PC.
• The register file has two read ports and one write port. The read ports take 4-bit
address inputs, A1 and A2, each specifying one of 24 = 16 registers as source
operands.
• They read the 32-bit register values onto read data outputs RD1 and RD2,
respectively.
• The write port takes a 4-bit address input, A3; a 32-bit write data input, WD3; a
write enable input, WE3; and a clock.
• If the write enable is asserted, then the register file writes the data into the
specified register on the rising edge of the clock.
• A read of R15 returns the value from the PC plus 8, and writes to R15 must be
specially handled to update the PC because it is separate from the register file
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Architectural State Elements: Data Memory

CLK
4 4
CLK
Status CLK
CLK WE3
A1 RD1 WE
4 32
PC' PC
A RD A RD
32 32 32 32 A2 RD2 32 32
Instructi on
4 32 Data
4
WD3 File WD
32 32
R15
32
The data memory has a single read/write port.

If, WE=1, writes data WD into address A on the rising edge of the clock.
If WE=0, then it reads address A onto RD
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Architectural State Elements: Arithmetic Logic Unit (ALU)
The ALU receives two operands, SrcA and SrcB. SrcA comes from the register
file, and SrcB comes from the extended immediate. The ALU can perform
many operations, (described in Section 5.2.4). The 2-bit ALUControl signal
specifies the operation. The ALU generates a 32-bit ALUResult.
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Synchronization
• The instruction memory, register file, and data memory
• Read: Asynchronous
• Write: Synchronous
• The state of the system is changed only at the clock edge.
• The address, data, and write enable must setup before the clock edge and must
remain stable until a hold time after the clock edge.
• Because the state elements change their state only on the rising edge of the
clock, they are synchronous sequential circuits (as covered in EEE 303).

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Building Blocks,

Lecture 5.1
Week 5
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Processor Performance
• Program execution time
• Definitions:
• CPI: Cycles/instruction
• clock period: seconds/cycle
• IPC: instructions/cycle = IPC
• Challenge is to satisfy constraints of:

• Cost
• Power
• Performance

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Microarchitecture
• Multiple implementations for a single architecture:
• Single-cycle: Each instruction executes in a single cycle
• Multicycle: Each instruction is broken up into series of shorter steps
• Pipelined: Each instruction broken up into series of steps & multiple instructions execute at
once

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ARM Processor
• We consider subset of ARM instructions:
• Data-processing instructions:
– ADD, SUB, AND, ORR
– with register and immediate Src2, but no shifts
• Memory instructions:
– LDR, STR
– with positive immediate offset
• Branch instructions:
–B

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Building Blocks,

Lecture 5.1
Week 5
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Microarchitecture
• Multiple implementations for a single architecture:
• Single-cycle: Each instruction executes in a single cycle
• Multicycle: Each instruction is broken up into series of shorter steps
• Pipelined: Each instruction broken up into series of steps & multiple instructions execute at
once

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Single-Cycle ARM Processor

• Datapath
• Control

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DRAFT 7/12/2023

• Datapath
• Control

23

• Datapath: start with LDR instruction
• Example: LDR R1, [R2, #5]
LDR Rd, [Rn, imm12]

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Single-Cycle Datapath: LDR fetch

STEP 1: Fetch instruction
CLK CLK
CLK
Instr
WE3 WE
PC' PC A1 RD1
A RD
A RD
Instruction A2 RD2
Memory Data
Memory
A3 Register
WD
WD3 File
R15
The program counter contains the address of the instruction to execute. The first step is
to read this instruction from instruction memory. Figure shows that the PC is simply
connected to the address input of the instruction memory. The instruction memory
reads out, or fetches, the 32-bit instruction, labeled Instr.
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Single-Cycle Datapath: LDR Reg Read

STEP 2: Read source operands from RF
CLK CLK
CLK
Instr
19:16 RA1 WE3 WE

PC' PC A1 RD1
A RD
A RD
Instruction A2 RD2
Memory Data
Memory
A3 Register
WD
WD3 File
R15
LDR Rd, [Rn, imm12]

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DRAFT 7/12/2023
Single-Cycle Datapath: LDR Immed.

STEP 3: Extend the immediate
CLK CLK
CLK
Instr
19:16 RA1 WE3 WE
PC' PC A1 RD1
A RD
A RD
Instructi on A2 RD2
Memory Data
15:12 Memory
A3 Register
WD
WD3 File
R15
11:0
Extend Ext Imm
LDR Rd, [Rn, imm12]

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Architectural State Elements: Arithmatic Logic Unit (ALU)
Zero extension simply means prepending leading zeros:

ImmExt31:12 = 0 and ImmExt11:0 = Instr11:0.

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DRAFT 7/12/2023
blue- control path

Single-Cycle Datapath: LDR Immed. bold- new datapath
ash- previous connection
STEP 3: Extend the immediate
CLK CLK
CLK
Instr
19:16 RA1 WE3 WE
PC' PC A1 RD1
A RD
A RD
Instructi on A2 RD2
Memory Data
15:12 Memory
A3 Register
WD
WD3 File
R15
11:0
Extend Ext Imm
LDR Rd, [Rn, imm12]

29
Single-Cycle Datapath: LDR Address

STEP 4: Compute the memory address
ALUControl should
ALUControl
00
be set to 00 to perform addition
CLK CLK
CLK
Instr
19:16 RA1 WE3 SrcA WE

PC' PC A1 RD1
A RD ALUResult
ALU
A RD
Instructi on A2 RD2 SrcB Data
Memory
15:12 Memory
A3 Register
WD
WD3 File
R15
Address = RD1+ExtImm
11:0
Extend ExtImm
LDR Rd, [Rn, imm12]

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DRAFT 7/12/2023
Single-Cycle Datapath: LDR Mem Read

STEP 5: Read data from memory and write it back to register file
RegWrite ALUControl
1 00
CLK CLK
CLK
Instr
PC' PC A1 RD1
A RD ALUResult ReadDat a
ALU
A RD
Memory
15:12 Memory
A3 Register
WD
WD3 File
R15
11:0
Extend Ext Imm
LDR Rd, [Rn, imm12]

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• While the instruction is being executed, the processor must compute the
address of the next instruction, PC′.
• Because instructions are 32 bits (4 bytes), the next instruction is at PC + 4
• We can use additional adder to compute the next address

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Single-Cycle Datapath: PC Increment

STEP 6: Determine address of next instruction
RegWrite ALUControl
1 00
CLK CLK
CLK Instr
o
PC' PC A1 RD1
ALU
A RD
Memory
15:12 Memory
A3 Register
WD
WD3 File
R15
PCPlus4
+
4
11:0
Extend Ext Imm

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Single-Cycle Datapath: Access to PC

PC can be source/destination of instruction
PCSrc RegWrite ALUControl

1 1 00
CLK CLK
CLK
Instr

1 PC' PC A1 RD1
A RD ALUResult ReadData
ALU
0 A RD
Memory
15:12 Memory
A3 Register
WD
WD3 File
4 PCPlus8
R15
+
PCPlus4
+
4
11:0
Extend ExtImm

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• Source: R15 must be available in Register File
• PC is read as the current PC plus 8

1 1 00
CLK CLK
CLK
Instr 19:16 RA1 WE3 SrcA WE
1 PC' PC A1 RD1
ALU
0 A RD
Memory
15:12 Memory
A3 Register
WD
WD3 File
4
PCPlus8
R15
+
PCPlus4
+
4
11:0
Extend ExtImm

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• Source: R15 must be available in Register File
• PC is read as the current PC plus 8
• Destination: Be able to write result to PC

1 1 00
CLK CLK
CLK
Instr

1 PC' PC A1 RD1
ALU
0 A RD
Memory
15:12 Memory
A3 Register
WD
WD3 File
4 PCPlus8
R15
+
PCPlus4
+
4
11:0
Extend ExtImm

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DRAFT 7/12/2023
Single-Cycle Datapath: STR

Expand datapath to handle STR:
• Write data in Rd to memory
PCSrc RegWrite ALUControl MemWrite
0 0 00 1
CLK CLK
CLK
Instr
1 PC' PC A1 RD1
ALU
0 A RD
Instructi on RA2
A2 RD2 SrcB Data
Memory
15:12 Memory
A3 Register WriteData
WD
WD3 File
4
PCPlus8
R15
+
PCPlus4
+
4
11:0
Extend ExtImm
STR Rd, [Rn, imm12]

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EEE Micro Architecture:

Single Cycle Processor:
415 Data Processing Instructions
Lecture 5.2
Week 5
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Single-Cycle Datapath: Data-processing

With immediate Src2:
• Read from Rn and Imm8 (ImmSrc chooses the zero-extended Imm8 instead of Imm12)
• Write ALUResult to register file
• Write to Rd
ADD Rd, Rn, imm8

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With immediate Src2:
• Read from Rn and Imm8 (ImmSrc chooses the zero-extended Imm8 instead of Imm12)
• Write to Rd
ALUFlags
PCSrc RegWrite ImmSrc ALUControl MemWrite MemtoReg

0 1 0 v aries 0 0
CLK CLK
CLK
Instr

1 PC' PC A1 RD1
ALU
0 A RD
Instructi on RA2
A2 RD2 SrcB Data
Memory
15:12 Memory
WD
WD3 File
4 1
PCPlus8
R15
+
PCPlus4 0
+
4
11:0
Extend Ext Imm
Result
ADD Rd, Rn, imm8

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DRAFT 7/12/2023

With register Src2:
• Read from Rn and Rm (instead of Imm8)
• Write to Rd
ADD Rd, Rn, Rm

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With register Src2:
• Read from Rn and Rm (instead of Imm8)
• Write to Rd
ALUFlags
PCSrc RegSrc RegWrite ImmSrc ALUSrc ALUControl MemWrite MemtoReg

0 0 1 X 0 varies 0 0
CLK CLK
CLK
Instr

1 PC' PC A1 RD1
ALU
0 3:0 A RD
Instruction 0 RA2
A2 RD2 0 SrcB Data
Memory 1
15:12 1 Memory
WD
4 WD3 File
PCPlus8 1
R15
+
PCPlus4 0
+
4
11:0
Extend Ext Imm
Result
ADD Rd, Rn, Rm

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Single-Cycle Datapath: B
Calculate branch target address:
BTA = (ExtImm) + (PC + 8)
ExtImm = Imm24 << 2 and sign-extended
ALUFlags
1 1 x 0 10 1 00 0 0
CLK CLK
CLK
19:16
Instr
0 RA1 WE3 SrcA WE
1 PC' PC A1 RD1
A RD 15 1 ALUResult ReadDat a
ALU
0 3:0 A RD
Instructi on 0 RA2
A2 RD2 0 SrcB Data
Memory 1
15:12 1 Memory
WD
WD3 File
4 1
PCPlus8
R15
+
PCPlus4 0
+
4
23:0
Extend Ext Imm
Result
B Label

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Single-Cycle Datapath: ExtImm

ALUFlags

1 1 x 0 10 1 00 0 0
CLK CLK
CLK
19:16
Instr
0 RA1 WE3 SrcA WE

1 PC' PC A1 RD1
ALU
0 3:0 A RD
Instructi on 0 RA2
A2 RD2 0 SrcB Data
Memory 1
15:12 1 Memory
WD
4 WD3 File
PCPlus8 1
R15
+
PCPlus4 0
+
4
23:0
Exten d ExtImm
Result
ImmSrc1:0 ExtImm Description

00 {24’b0, Instr7:0} Zero-extended imm8
01 {20’b0, Instr11:0} Zero-extended imm12
10 {6{Instr23}, Instr23:0} Sign-extended imm24

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Single-Cycle Datapath: Control
ALUFlags
1 1 x 0 10 1 00 0 0
CLK CLK
CLK
19:16
Instr
0 RA1 WE3 SrcA WE
1 PC' PC A1 RD1
ALU
0 3:0 A RD
Instructi on 0 RA2
A2 RD2 0 SrcB Data
Memory 1
15:12 1 Memory
WD
4 WD3 File
PCPlus8 1
R15
+
PCPlus4 0
+
4
23:0
Exten d ExtImm
Result

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PCSrc
Control
MemtoReg
Unit
31:28 MemWrite
Cond
27:26 ALUControl
Op
25:20 ALUSrc
Funct
15:12
Rd ImmSrc
RegWrite
Flags
ALUFlags
RegSrc
0 1 CLK CLK
CLK
19:16
Instr
0 RA1 WE3 SrcA WE

1 PC' PC A1 RD1
ALU
0 3:0 A RD
Instruction 0 RA2
A2 RD2 0 SrcB Data
Memory 1
15:12 1 Memory
WD
4 WD3 File
PCPlus8 1
R15
+
PCPlus4 0
+
4
23:0
Extend ExtImm
Result

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Single-Cycle Control
• These signals change the
state (PC, RF, Memory)
• If instruction shouldn’t
execute, forced to 0
Sent through
Conditional Logic
first, then to
datapath
Sent directly
to datapath
Control Unit
47
• FlagW1:0: Flag Write signal,
asserted when ALUFlags
should be saved (i.e., on
instruction with S=1)
• ADD, SUB update all flags
(NZCV)
• AND, ORR only update NZ
flags
• So, two bits needed:
FlagW1 = 1: NZ saved
(ALUFlags3:2 saved)
FlagW0 = 1: CV saved
(ALUFlags1:0 saved)

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Single-Cycle Control: Decoder

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Submodules:
• Main Decoder
• ALU Decoder
• PC Logic

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Submodules:
• Main Decoder
• ALU Decoder
• PC Logic

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DRAFT 7/12/2023
Control Unit: Main Decoder

Input Output
Op
Funct5
Funct0
Type
Branch
MemtoReg
MemW
ALUSrc
ImmSrc
RegW
RegSrc
ALUOp
00 0 X DP Reg 0 0 0 0 XX 1 00 1
00 1 X DP Imm 0 0 0 1 00 1 X0 1
01 X 0 STR 0 X 1 1 01 0 10 0
01 X 1 LDR 0 1 0 1 01 1 X0 0
11 X X B 1 0 0 1 10 0 X1 0

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Submodules:
• Main Decoder
• ALU Decoder
• PC Logic

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Review: ALU
ALUControl1:0 Function
00 Add
01 Subtract
10 AND
11 OR

55
Review: ALU

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Submodules:
• Main Decoder
• ALU Decoder
• PC Logic

57
Control Unit: ALU Decoder

from Main Decoder from Instr Output
ALUOp Funct4:1 Funct0 Type ALUControl1:0 FlagW1:0

(cmd) (S)
0 X X Not DP 00 00
1 0100 0 ADD 00 00
1 11
0010 0 SUB 01 00
1 11
0000 0 AND 10 00
1 10
1100 0 ORR 11 00
1 10
• FlagW1 = 1: NZ (Flags3:2) should be saved
• FlagW0 = 1: CV (Flags1:0) should be saved
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Submodules:
• Main Decoder
• ALU Decoder
• PC Logic

59
Single-Cycle Control: PC Logic

PCS = 1 if PC is written by an instruction or branch (B):
PCS = ((Rd == 15) & RegW) | Branch PCSrc
Control
MemtoReg
Unit
31:28 MemWrite
Cond
27:26 ALUControl
Op
25:20 ALUSrc
Funct
15:12
Rd ImmSrc
RegWrite
Flags
ALUFlags
RegSrc
0 1 CLK CLK
CLK
19:16
Instr
0 RA1 WE3 SrcA WE

1 PC' PC A1 RD1
A RD 15 1 ALUResult ReadData
ALU
0 3:0 A RD
Instructi on 0 RA2
A2 RD2 0 SrcB Data
Memory 1
15:12 1 Memory
WD
WD3 File
4 1
PCPlus8
R15
+
PCPlus4 0
+
4
23:0
Exten d ExtImm
Result
If instruction is executed: PCSrc = PCS

Else PCSrc = 0 (i.e., PC = PC + 4)

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61
Conditional Logic
Function:
1. Check if instruction should execute (if not, force PCSrc, RegWrite, and MemWrite to 0)
2. Possibly update Status Register (Flags3:0)

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Conditional Logic
Function:

63
Single-Cycle Control: Conditional Logic

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Conditional Logic: Conditional Execution
Flags3:0 is the
status register
Depending on condition mnemonic (Cond3:0) and condition flags

(Flags3:0) the instruction is executed (CondEx = 1)

65
Review: Condition Mnemonics

Cond3:0 Mnemonic Name CondEx
0000 EQ Equal 𝑍
0001 NE Not equal 𝑍̅
0010 CS / HS Carry set / Unsigned higher or same 𝐶
0011 CC / LO Carry clear / Unsigned lower 𝐶̅
0100 MI Minus / Negative 𝑁
0101 PL Plus / Positive of zero 𝑁
0110 VS Overflow / Overflow set 𝑉
0111 VC No overflow / Overflow clear 𝑉
1000 HI Unsigned higher 𝑍̅𝐶
1001 LS Unsigned lower or same 𝑍 𝑂𝑅 𝐶̅
1010 GE Signed greater than or equal 𝑁⊕𝑉
1011 LT Signed less than 𝑁⊕𝑉
1100 GT Signed greater than 𝑍̅(𝑁 ⊕ 𝑉)
1101 LE Signed less than or equal 𝑍 𝑂𝑅 (𝑁 ⊕ 𝑉)
1110 AL (or none) Always / unconditional ignored
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Flags3:0 = NZCV
Example: AND R1, R2, R3

Cond3:0=1110 (unconditional) => CondEx = 1

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Flags3:0 = NZCV
Example: EOREQ R5, R6, R7

Cond3:0=0000 (EQ): if Flags3:2=0100 => CondEx = 1

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Conditional Logic
Function:

69
Conditional Logic: Update (Set) Flags
Flags3:0 = NZCV
Flags3:0 updated (with ALUFlags3:0) if:

• FlagW is 1 (i.e., the instruction’s S-bit is 1) AND
• CondEx is 1 (the instruction should be executed)

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Review: ALU Decoder

ALUOp Funct4:1 Funct0 Type ALUControl1:0 FlagW1:0
(cmd) (S)
0 X X Not DP 00 00
1 0100 0 ADD 00 00
1 11
0010 0 SUB 01 00
1 11
0000 0 AND 10 00
1 10
1100 0 ORR 11 00
1 10
• FlagW1 = 1: NZ (Flags3:2) should be saved
• FlagW0 = 1: CV (Flags1:0) should be saved

71
All Flags
updated
Example: SUBS R5, R6, R7

FlagW1:0 = 11 AND CondEx = 1 (unconditional) => FlagWrite1:0 = 11

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Flags3:0 = NZCV
• Only Flags3:2
updated
• i.e., only NZ
Flags
updated
Example: ANDS R7, R1, R3

FlagW1:0 = 10 AND CondEx = 1 (unconditional) => FlagWrite1:0 = 10

73
Example: ORR
Op
Funct5
Funct0
Type
Branch
MemtoReg
MemW
ALUSrc
ImmSrc
RegW
RegSrc
ALUOp
00 0 X DP Reg 0 0 0 0 XX 1 00 1

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DRAFT 7/12/2023
Example: ORR

75
Extended Functionality: CMP

38
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DRAFT 7/12/2023
No change to datapath

77

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DRAFT 7/12/2023

ALUOp Funct4:1 Funct0 Type ALUControl1:0 FlagW1:0 NoWrite
(cmd) (S)
0 X X Not DP 00 00 0
1 0100 0 ADD 00 00 0
1 11 0
0010 0 SUB 01 00 0
1 11 0
0000 0 AND 10 00 0
1 10 0
1100 0 ORR 11 00 0
1 10 0
1010 1 CMP 01 11 1

79
Extended Functionality: Shifted Register
Assembly Code Field Values

31:28 27:26 25 24:21 20 19:16 15:12 11:7 6:5 4 3:0
ADD R7, R2, R12, LSR #5 14 0 0 4 0 2 7 5 012 0 12

cond op I cmd S rn rd shamt5 sh rm

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Extended Functionality: Shifted Register
No change to controller

81

415 Performance, Problems
Lecture 5.3
Week 5
41
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DRAFT 7/12/2023

Lecture 5.3
Week 5
83
Review: Processor Performance

Program Execution Time
= (#instructions)(cycles/instruction)(seconds/cycle)
= # instructions x CPI x TC

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DRAFT 7/12/2023
Single-Cycle Performance
tdec
tdec
tpcq_PC tmem tRFsetup tRFread tmem

tmux tALU
tmux tmux
tsext
TC limited by critical path (LDR)

85
Single-Cycle Performance
• Single-cycle critical path:
Tc1 = tpcq_PC + tmem + tdec + max[tmux + tRFread, tsext + tmux] + tALU + tmem + tmux + tRFsetup
• Typically, limiting paths are:

– memory, ALU, register file
– Tc1 = tpcq_PC + 2tmem + tdec + tRFread + tALU + 2tmux + tRFsetup

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DRAFT 7/12/2023
Single-Cycle Performance Example

Element Parameter Delay (ps)
Register clock-to-Q tpcq_PC 40
Register setup tsetup 50
Multiplexer tmux 25
ALU tALU 120
Decoder tdec 70
Memory read tmem 200
Register file read tRFread 100
Tc1 = ? Register file setup tRFsetup 60
Tc1 = tpcq_PC + 2tmem + tdec + tRFread + tALU + 2tmux + tRFsetup

= [50 + 2(200) + 70 + 100 + 120 + 2(25) + 60] ps
= 840 ps
87
Single-Cycle Performance Example

Program with 100 billion instructions:
Execution Time = # instructions x CPI x TC

= (100 × 109)(1)(840 × 10-12 s)
= 84 seconds

44
88
DRAFT 7/12/2023
Summary Single Cycle Control
Control Signals only Depend on Present State

89

Lecture 5.3
Week 5
45
90
DRAFT 7/12/2023

91
PCSrc
Control
MemtoReg
Unit
31:28 MemWrite
Cond
27:26 ALUControl
Op
25:20 ALUSrc
Funct
15:12
Rd ImmSrc
RegWrite
Flags
ALUFlags
Register never gets written! 0

RegSrc
0 1 CLK CLK
CLK
19:16
Instr
0 RA1 WE3 SrcA WE

1 PC' PC A1 RD1
ALU
0 3:0 A RD
Instruction 0 RA2
ADD, SUB, AND, ORR, LDR Memory 1
A2 RD2 0 SrcB Data
15:12 1 Memory
will not work A3 Register WriteData
WD
4 WD3 File
PCPlus8 1
R15
+
PCPlus4 0
+
4
23:0
Extend ExtImm
Result
46
92
DRAFT 7/12/2023
PCSrc
Control
MemtoReg
Unit
31:28 MemWrite
Cond
27:26 ALUControl
Op
25:20 ALUSrc
Funct
15:12
Rd ImmSrc
RegWrite
Flags
ALUFlags
ALU only adds! 00
RegSrc
0 1 CLK CLK
CLK
19:16
Instr
0 RA1 WE3 SrcA WE
1 PC' PC A1 RD1
ALU
0 3:0 A RD
0
SUB, AND, ORR will not work! Instruction
Memory 1
RA2
A2 RD2 0 SrcB Data
15:12 1 Memory
WD
4 WD3 File
PCPlus8 1
R15
+
PCPlus4 0
+
4
23:0
Extend ExtImm
Result
93
PCSrc
Control
MemtoReg
Unit
31:28 MemWrite
Cond
27:26 ALUControl
Op
25:20 ALUSrc
Funct
15:12
Rd ImmSrc
RegWrite
Flags
Memory Never gets written!

ALUFlags
0
RegSrc
0 1 CLK CLK
CLK
19:16
Instr
0 RA1 WE3 SrcA WE

1 PC' PC A1 RD1
ALU
0 3:0 A RD
0
STR will not work! Instruction
Memory 1
RA2
A2 RD2 0 SrcB Data
15:12 1 Memory
WD
4 WD3 File
PCPlus8 1
R15
+
PCPlus4 0
+
4
23:0
Extend ExtImm
Result
47
94
DRAFT 7/12/2023

95
PCSrc
Control
MemtoReg
Unit
31:28 MemWrite
Cond
27:26 ALUControl
Op
25:20 ALUSrc
Funct
15:12
Rd ImmSrc
RegWrite
Flags
ALUFlags
Register always gets written 1

RegSrc
0 1 CLK CLK
CLK
even when it should not!

19:16
Instr
0 RA1 WE3 SrcA WE

1 PC' PC A1 RD1
ALU
0 3:0 A RD
Instruction 0 RA2
A2 RD2 0 SrcB Data
Memory 1
1 Memory
STR, B: these instructions write
15:12
WD
WD3 File
to the register file when they 4
PCPlus8
R15
1
+
shouldn't PCPlus4 0
+
4
23:0
Extend ExtImm
Result
48
96
DRAFT 7/12/2023
PCSrc
Control
MemtoReg
Unit
31:28 MemWrite
Cond
27:26 ALUControl
Op
25:20 ALUSrc
Funct
15:12
Rd ImmSrc
RegWrite
Flags
ALUFlags
the ALU looks at the cmd field

11
RegSrc
0 1 CLK CLK
CLK
to determine the operation to
19:16
Instr
0 RA1 WE3 SrcA WE
1 PC' PC A1 RD1
A RD 15 1
perform. ALUResult ReadDat a
ALU
0 3:0 A RD
Instruction 0 RA2
A2 RD2 0 SrcB Data
ALU cannot perform addition
Memory 1
15:12 1 Memory
WD
4 WD3 File
PCPlus8 1
R15
+
PCPlus4 0
LDR, STR, B cannot work!
+
4
23:0
Extend ExtImm
Result
97
PCSrc
Control
MemtoReg
Unit
31:28 MemWrite
Cond
27:26 ALUControl
Op
25:20 ALUSrc
Funct
15:12
Rd ImmSrc
RegWrite
Flags
Memory Will be written even

ALUFlags
1
RegSrc
0 1 CLK CLK
CLK
when it should not!

19:16
Instr
0 RA1 WE3 SrcA WE

1 PC' PC A1 RD1
ALU
0 3:0 A RD
Instruction 0 RA2
A2 RD2 0 SrcB Data
Memory 1
1 Memory
ADD, SUB, AND, ORR, LDR, B
15:12
WD
WD3 File
these instructions inadvertently 4
PCPlus8
R15
1
+
write to the data PCPlus4 0

+
4
memory 23:0
Extend ExtImm
Result
49
98
DRAFT 7/12/2023

99
Will perform a logical AND operation. Update flags. but will not write the result

50
100
DRAFT 7/12/2023
Will perform a logical AND operation. Update flags. but will not write the result

101
Will shift the result of register 2 and use shifted result. Add shifter and MUX

51
102
DRAFT 7/12/2023

103

52
104
DRAFT 7/12/2023
The CMP instruction subtracts the value

of Operand2 from the value in Rn. This is the same as
a SUBS instruction, except that the result is discarded.
The CMN instruction adds the value of Operand2 to the

value in Rn. This is the same as an ADDS instruction,
except that the result is discarded.
https://developer.arm.com/documentation/dui0204/j/arm-and-thumb-
instructions/general-data-processing-instructions/cmp-and-cmn Dr. Sajid Muhaimin Choudhury 105
105

53
106
DRAFT 7/12/2023

107

54
108
DRAFT 7/12/2023
ADC=add with carry, carry flag should be added with ALU

109

55
110
DRAFT 7/12/2023

111

56
112
DRAFT 7/12/2023

113

57
114
DRAFT 7/12/2023
It is not possible to implement this instruction without either modifying the register
file or making the instruction take at least two cycles to execute.
Add WE1 and WD1 signals to the register file.
WE1 connects to the PostIndex signal (from control unit)
WD1 connects to ALUResult, which is the sum of Rn + Rm (or Rn + Src2, more
generally).
Add multiplexer before Data Memory Address to choose between (Rn + Src2) and
Rn. With post-indexing, the Data Memory Address input connects to Rn.
115

58
116
DRAFT 7/12/2023

117
It is not possible to implement this instruction without either modifying the register file or
making the instruction take at least two cycles to execute. We modify the register file and
datapath as shown below.
WE1 connects to the PreIndex signal (from control unit)
WD1 connects to ALUResult, which is the sum of Rn + Rm (or Rn + Src2, more generally)
59
118
DRAFT 7/12/2023

119

60
120
DRAFT 7/12/2023
It is not possible to implement this instruction without either modifying the register file or
making the instruction take at least two cycles to execute. We modify the register file and
datapath as shown below.
WE1 connects to the PreIndex signal (from control unit)
WD1 connects to ALUResult, which is the sum of Rn + Rm (or Rn + Src2, more generally)
121
(a) STR: it stores the value in the register

specified by bits 3:0 (Rm) instead of bits 15:12
(Rd).
(b) LDR, STR: the memory always reads the
value at the address specified by the PC,
instead of a data memory address.
(c) All instructions. PC+4 is never written to the
PC register.

61
122

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DRAFT 7/12/2023

EEE 415 - Microprocessors and Embedded Systems

EEE Micro Architecture

415 Performance Analysis,

Topics this Week

– Defined by instructions & operand locations

Dr. Sajid Muhaimin Choudhury 2

Architectural Set and Instruction Set

• Architecture DOES NOT specify HOW the particular

Dr. Sajid Muhaimin Choudhury 3

Dr. Sajid Muhaimin Choudhury 4

EEE 415 - Microprocessors and Embedded Systems

EEE Micro Architecture

415 Performance Analysis,

• Sequential Logic Circuits

Dr. Sajid Muhaimin Choudhury 6

Architectural State Elements

Dr. Sajid Muhaimin Choudhury 7

ARM Architectural State Elements

Dr. Sajid Muhaimin Choudhury 8

Architectural State Elements: Program Counter

Although the program counter (PC) is logically part of the register

Dr. Sajid Muhaimin Choudhury 9

Architectural State Elements: Instruction Memory

The instruction memory has a single read port.

Architectural State Elements: Register File

15-element × 32-bit register

Dr. Sajid Muhaimin Choudhury 11

Architectural State Elements: Data Memory

The data memory has a single read/write port.

Architectural State Elements: Arithmetic Logic Unit (ALU)

Dr. Sajid Muhaimin Choudhury 15

EEE 415 - Microprocessors and Embedded Systems

EEE Micro Architecture

415 Performance Analysis,

• Challenge is to satisfy constraints of:

Dr. Sajid Muhaimin Choudhury 17

Dr. Sajid Muhaimin Choudhury 18

Dr. Sajid Muhaimin Choudhury 19

EEE 415 - Microprocessors and Embedded Systems

EEE Micro Architecture

415 Performance Analysis,

Dr. Sajid Muhaimin Choudhury 21

Single-Cycle ARM Processor

Dr. Sajid Muhaimin Choudhury 22

Single-Cycle ARM Processor

Dr. Sajid Muhaimin Choudhury 23

Single-Cycle ARM Processor

Dr. Sajid Muhaimin Choudhury 24

Single-Cycle Datapath: LDR fetch

Single-Cycle Datapath: LDR Reg Read

19:16 RA1 WE3 WE

LDR Rd, [Rn, imm12]

Dr. Sajid Muhaimin Choudhury 26

Single-Cycle Datapath: LDR Immed.

LDR Rd, [Rn, imm12]

Dr. Sajid Muhaimin Choudhury 27

Architectural State Elements: Arithmatic Logic Unit (ALU)

Zero extension simply means prepending leading zeros:

Dr. Sajid Muhaimin Choudhury 28

blue- control path

LDR Rd, [Rn, imm12]

Dr. Sajid Muhaimin Choudhury 29

Single-Cycle Datapath: LDR Address