Triple-Speed Ethernet Intel® FPGA

IP Release Notes

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 Contents

Contents

1. Triple-Speed Ethernet Intel® FPGA IP Release Notes...................................................... 3

1.1. Triple-Speed Ethernet Intel FPGA IP v22.1.0..............................................................3
1.2. Triple-Speed Ethernet Intel FPGA IP v22.0.0..............................................................4
1.3. Triple-Speed Ethernet Intel FPGA IP v21.2.0..............................................................4
1.4. Triple-Speed Ethernet Intel FPGA IP v21.1.0..............................................................4
1.5. Triple-Speed Ethernet Intel FPGA IP v20.0.0..............................................................5
1.6. Triple-Speed Ethernet Intel FPGA IP v19.5.0..............................................................5
1.7. Triple-Speed Ethernet Intel FPGA IP v19.4.0..............................................................5
1.8. Triple-Speed Ethernet Intel FPGA IP v19.2.0..............................................................6
1.9. Triple-Speed Ethernet Intel FPGA IP v19.1................................................................ 6
1.10. Triple-Speed Ethernet Intel FPGA IP v18.0...............................................................6
1.11. Intel FPGA Triple Speed Ethernet IP Core v17.1........................................................7
1.12. Triple Speed Ethernet IP Core v15.1....................................................................... 7
1.13. Triple Speed Ethernet IP Core v15.0....................................................................... 8
1.14. Triple Speed Ethernet IP Core v14.0 Arria 10 Edition.................................................8
1.15. Triple Speed Ethernet IP Core v14.0....................................................................... 8
1.16. Triple Speed Ethernet IP Core v13.1 Arria 10 Edition.................................................8
1.17. Triple Speed Ethernet IP Core v13.1 ...................................................................... 8
1.18. Triple-Speed Ethernet Intel FPGA IP User Guide Archives...........................................9
1.19. Triple-Speed Ethernet Intel Stratix 10 FPGA IP Design Example User Guide Archives..... 9

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1. Triple-Speed Ethernet Intel® FPGA IP Release Notes

If a release note is not available for a specific IP version, the IP has no changes in that
version. For information on IP update releases up to v18.1, refer to the Intel®
Quartus® Prime Design Suite Update Release Notes.

Intel FPGA IP versions match the Intel Quartus Prime Design Suite software versions
until v19.1. Starting in Intel Quartus Prime Design Suite software version 19.2, Intel
FPGA IP has a new versioning scheme.

The Intel FPGA IP version (X.Y.Z) number can change with each Intel Quartus Prime
software version. A change in:

• X indicates a major revision of the IP. If you update the Intel Quartus Prime
software, you must regenerate the IP.
• Y indicates the IP includes new features. Regenerate your IP to include these new
features.
• Z indicates the IP includes minor changes. Regenerate your IP to include these
changes.

Related Information
• Intel Quartus Prime Design Suite Update Release Notes
• Triple-Speed Ethernet Intel FPGA IP User Guide
• F-Tile Triple-Speed Ethernet Intel FPGA IP User Guide
• Triple-Speed Ethernet Intel Stratix 10 FPGA IP Design Example User Guide
• Triple-Speed Ethernet Intel Agilex 7 FPGA IP Design Example User Guide
• Errata for the Triple-Speed Ethernet Intel FPGA IP in the Knowledge Base

1.1. Triple-Speed Ethernet Intel FPGA IP v22.1.0

Table 1. v22.1.0 2023.10.02
Intel Quartus Description Impact
Prime Version

23.3 • Added hardware support to the following design example in —

Intel Agilex® 7 F-Tile devices:
— 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI
PCS with F-Tile FGT Transceiver
• Updated the test procedure for hardware testing in the
following design example:
— Multiport 10/100/1000Mb Ethernet MAC with 1000BASE-X/
SGMII PCS with LVDS I/O

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Corporation or its subsidiaries. Intel warrants performance of its FPGA and semiconductor products to current
specifications in accordance with Intel's standard warranty, but reserves the right to make changes to any ISO
products and services at any time without notice. Intel assumes no responsibility or liability arising out of the 9001:2015
application or use of any information, product, or service described herein except as expressly agreed to in Registered
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*Other names and brands may be claimed as the property of others.
 1. Triple-Speed Ethernet Intel® FPGA IP Release Notes
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1.2. Triple-Speed Ethernet Intel FPGA IP v22.0.0

Table 2. v22.0.0 2023.06.26
Intel Quartus Description Impact
Prime Version

23.2 • Added two new output ports: tx_ready and rx_ready for —
10/100/1000 Ethernet MAC Without Internal FIFO Buffers with
IEEE 1588v2, 1000BASE-X/SGMII 2XTBI PCS, and Embedded
Serial PMA.
• Resolved intermittent accuracy error for 10/100/1000
Ethernet MAC Without Internal FIFO Buffers with IEEE 1588v2,
1000BASE-X/SGMII 2XTBI PCS, and Embedded Serial PMA in
100Mb speed mode.

1.3. Triple-Speed Ethernet Intel FPGA IP v21.2.0

Table 3. v21.2.0 2023.04.03
Intel Quartus Description Impact
Prime Version

23.1 • Added IEEE 1588v2 Precision Time Protocol (PTP) support for —
10/100/1000Mb Ethernet MAC with 1000BASE-X/SGMII 2XTBI
PCS with transceiver variant operating without internal FIFO
buffer in full-duplex mode on Intel Agilex 7 F-tile devices.
• SYSPLL is available for datapath clocking when Enable F-tile
Transceiver Dynamic Reconfiguration (SYSPLL MODE) is
turned on for MAC with 2xTBI and Embedded PMA TSE IP
variant on Intel Agilex 7 F-tile devices.
• Enable Datapath Avalon Interface & Enable PMA Avalon
Interface are available for both PMA and SYSPLL data path
clocking mode for MAC with 2XTBI and Embedded PMA TSE IP
Variant on Intel Agilex 7 F-tile devices.

MAC RX accepts 6-bytes and 7-bytes preamble frames.

1.4. Triple-Speed Ethernet Intel FPGA IP v21.1.0

Table 4. v21.1.0 2022.12.19
Intel Quartus Description Impact
Prime Version

22.4 Added 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII TBI —

(LVDS I/O only) PCS variant for Intel Stratix 10 devices.

MAC RX accepts 7-bytes preamble frames only.

Table 5. v21.1.0 2022.09.26

Intel Quartus Description Impact
Prime Version

22.3 Added the following design example for Intel Agilex 7 devices —
• Multiport 10/100/1000 Mbps Ethernet MAC (FIFOless) with
1000BASE-X/SGMII PCS with embedded PMA(LVDS I/O) and
Avalon® Streaming Multi-Channel Shared Memory FIFO core.

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1.5. Triple-Speed Ethernet Intel FPGA IP v20.0.0

Table 6. v20.0.0 2022.03.28
Intel Quartus Description Impact
Prime Version

22.1 Removed System PLL, which is previously embedded in the Triple- —

Speed Ethernet Intel FPGA IP.

1.6. Triple-Speed Ethernet Intel FPGA IP v19.5.0

Table 7. v19.5.0 2021.10.04
Intel Quartus Description Impact
Prime Version

21.3 Added support for Intel Agilex 7 F-tile devices for the following —
core variant:
• 10/100/1000 Ethernet MAC with 1000BASE-X/SGMII 2XTBI
PCS and embedded PMA

1.7. Triple-Speed Ethernet Intel FPGA IP v19.4.0

Table 8. v19.4.0 2021.06.23
Intel Quartus Description Impact
Prime Version

21.2 Added deterministic latency support for 10/100/1000 Mbps —

Ethernet MAC with 1000BASE-X/SGMII 2XTBI PCS and IEEE
1588v2 feature enabled variation operating without internal FIFO
buffer in full-duplex mode.
This feature is only supported in the Intel Stratix® 10 E-tile
devices.

Design Example for Triple-Speed Ethernet Intel FPGA IP: —

• Added the following design example for Intel Stratix 10 E-tile
devices:
— 10/100/1000Mb Ethernet MAC (Fifoless) with IEEE 1588v2
and 1000BASE-X/SGMII 2XTBI PCS with E-Tile GXB
Transceiver

Table 9. v19.4.0 2021.04.01

Intel Quartus Description Impact
Prime Version

21.1 Design Example for Triple-Speed Ethernet Intel FPGA IP: —

• Added the following design example for Intel Stratix 10 E-tile
devices:
— 10/100/1000 Mb Ethernet MAC (Fifoless) with 1000 BASE-
X/SGMII 2XTBI PCS with E-Tile GXB Transceiver

Table 10. v19.4.0 2020.12.14

Intel Quartus Description Impact
Prime Version

20.4 Added support for two new core variants for Intel Stratix 10 E-tile —
devices:

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Intel Quartus Description Impact

Prime Version

• 10/100/1000-Mbps Ethernet MAC without internal FIFO

buffers with 1000BASE-X/SGMII 2XTBI PCS
• 10/100/1000-Mbps Ethernet MAC without internal FIFO
buffers with IEEE 1588v2 and 1000BASE-X/SGMII 2XTBI PCS

Table 11. v19.4.0 2019.12.16

Intel Quartus Description Impact
Prime Version

19.4 Added support for the Intel Agilex 7 device family. —

1.8. Triple-Speed Ethernet Intel FPGA IP v19.2.0

Table 12. v19.2.0 2019.07.01
Intel Quartus Description Impact
Prime

19.2 Added support for two new core variants for Intel —
Stratix 10 E-tile devices:
• 10/100/1000-Mbps Ethernet MAC with
1000BASE-X/SGMII 2XTBI PCS
• 1000BASE-X/SGMII 2XTBI PCS

1.9. Triple-Speed Ethernet Intel FPGA IP v19.1

Table 13. v19.1 April 2019
Description Impact

Renamed the Enable Intel FPGA Debug Master —

Endpoint parameter to Enable Native PHY Debug
Master Endpoint (NPDME) as per Intel rebranding in the
Intel Quartus Prime Pro Edition software. The Intel Quartus
Prime Standard Edition software still uses Enable Intel
FPGA Debug Master Endpoint.

1.10. Triple-Speed Ethernet Intel FPGA IP v18.0

Table 14. v18.0 May 2018
Description Impact

Renamed Triple-Speed Ethernet IP core to Triple-Speed —

Ethernet Intel FPGA IP as per Intel rebranding.

Related Information
Errata for Intel FPGA Triple Speed Ethernet IP core in the Knowledge Base

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1.11. Intel FPGA Triple Speed Ethernet IP Core v17.1

Table 15. v17.1 November 2017
Description Impact

Added support for the Intel Stratix 10, Intel Cyclone® 10 GX, and Intel Cyclone 10 LP These devices are only
device families. available in Intel Quartus
Prime Pro Edition software
version 17.1 onwards.

In versions 17.0.2 and earlier of the Triple-Speed Ethernet IP core, the Triple-Speed To upgrade designs from
Ethernet IP variant with LVDS I/O for PMA implementation in Intel Arria® 10 devices may previous versions of the
experience performance risk. This issue is fixed in the Intel Quartus Prime software version Intel Quartus Prime software
17.1. to version 17.1, you must
regenerate the Triple-Speed
Ethernet IP core and
recompile the design in the
Intel Quartus Prime software
version 17.1. Refer to the
KDB page for more
information.

The number of ports supported for Triple-Speed Ethernet design with LVDS I/O targeting —
Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX is 8 per instance. You must not
promote the reference clock to global clock manually. Assign the number of ports supported
and its reference clock to the same I/O bank as inter-bank clock sharing is not allowed.

RGMII interface is not supported in Intel Stratix 10, Intel Arria 10, and Intel Cyclone 10 GX —
devices.

Related Information
• Errata for Intel FPGA Triple Speed Ethernet IP core in the Knowledge Base
• KDB Link: Performance Risk Running Triple Speed Ethernet LVDS in Arria 10
Devices

1.12. Triple Speed Ethernet IP Core v15.1

Table 16. v15.1 November 2015
Description Impact

Updated the ToD Clock module: These changes are optional.

• Added a new parameter—PERIOD_CLOCK_FREQUENCY. If you do not upgrade your
IP core, it does not have
Updated the ToD Synchronizer module: these new features.
• Added a new parameter—SAMPLE SIZE.
• Changed the parameter value of SYNC_MODE to "Between 0 to 15".
• Changed the frequency range to 390.625 MHz.

Related Information
Errata for Triple Speed Ethernet IP core in the Knowledge Base

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1.13. Triple Speed Ethernet IP Core v15.0

Table 17. v15.0 May 2015
Description Impact

You may observe hold time violation in designs targeting the Stratix V, Arria V, Cyclone V, Refer to the following errata
and Arria 10 (10AS066ES) devices in this release. for more information and the
workaround: Hold Time
Violation in Triple Speed
Ethernet IP Core.

1.14. Triple Speed Ethernet IP Core v14.0 Arria 10 Edition

Table 18. v14.0 Arria 10 Edition August 2014
Description Impact

Verified in the Quartus II software v14.0 Arria 10 Edition. (Added support for Arria 10 If you upgrade your IP core
devices). to the Quartus II software
v14.0 Arria 10 Edition , all of
the changes require that you
regenerate the IP core
manually and reconnect it in
your design.

1.15. Triple Speed Ethernet IP Core v14.0

Table 19. v14.0 June 2014
Description Impact

Upgraded to support the new IP Catalog. For more information about the IP Catalog, refer -
to IP Catalog and Parameter Editor in Introduction to Altera IP Cores.

Added ECC support for M20K blocks. Optional changes. If you do

not upgrade your IP core, it
Added 1588v2 support for LVDS variant. does not have these new
features:

1.16. Triple Speed Ethernet IP Core v13.1 Arria 10 Edition

Table 20. v13.1 Arria 10 Edition December 2014
Description impact

Added support for Arria 10 devices. -

1.17. Triple Speed Ethernet IP Core v13.1

Table 21. v13.1 November 2013
Description Impact

Removed support for the following devices: -

continued...

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Description Impact

• Arria GX
• Cyclone II
• HardCopy II, HardCopy III, and HardCopy IV
• Stratix II and Stratix II GX

Added 1588v2 support for Arria V, Arria V SoC, Cyclone V, Cyclone V SoC and Stratix V -
devices.

Added 1588v2 support for MAC-only variants -

Added ATX and CMU Tx PLL options for variations that include the PCS block targeting Arria -
V GZ and Stratix V devices.

Added SyncE support by separating Tx PLL and Rx PLL reference clock. -

The period in nanosecond for csr registers: tx_period, rx_period, Period, and -
AdjustPeriod, was changed from bit 16 to 19 to bit 16 to 24.

1.18. Triple-Speed Ethernet Intel FPGA IP User Guide Archives

For the latest and previous versions of this user guide, refer to Triple-Speed Ethernet
Intel FPGA IP User Guide. If an IP or software version is not listed, the user guide for
the previous IP or software version applies.

IP versions are the same as the Intel Quartus Prime Design Suite software versions up
to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IP
cores have a new IP versioning scheme.

1.19. Triple-Speed Ethernet Intel Stratix 10 FPGA IP Design

Example User Guide Archives
IP versions are the same as the Intel Quartus Prime Design Suite software versions up
to v19.1. From Intel Quartus Prime Design Suite software version 19.2 or later, IP
cores have a new IP versioning scheme.

If an IP core version is not listed, the user guide for the previous IP core version applies.

Intel Quartus Prime IP Core Version User Guide

Version

21.1 19.4.0 Triple-Speed Ethernet Intel Stratix 10 FPGA IP Design Example

User Guide

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