Tutorial 6

1. List all machine cycles in 8085.

 Opcode Fetch
 Memory Read
 Memory Write
 I/O Read
 I/O Write
 Interrupt Acknowledge
 Halt
 Hold
 Reset

2. What is the execution time for instruction LHLD 2089H if the clock frequency is 2MHz?

Period = 1 = 1
= 0.5µs
𝑓 2𝑀𝐻𝑧

T-state = 16 states
Execution time = Total T-state x Period
= 16 states x 0.5µs
= 8µs

3. For instruction MVI A,20H, calculate the time required to execute the Opcode Fetch,
Memory Read and entire instruction cycle if the clock frequency is 4MHz.

Period = 1 = 1
= 0.25µs
𝑓 4𝑀𝐻𝑧

T-state for Opcode Fetch = 4 states T-

state for Memory Read = 3 states Total
T-state = 4 + 3 = 7 states

Execution time for Opcode Fetch = T-state for Opcode Fetch x Period
= 4 states x 0.25µs
= 1µs
Execution time for Memory Read = T-state for Memory Read x Period
= 3 states x 0.25µs
= 0.75µs
Total execution time = 1 + 0.75 = 1.75µs
4. Identify the control and status signals for Opcode Fetch machine cycle.

Control signal:
̅𝑅̅𝐷̅ = 0

Status signal:
𝐼𝑂/𝑀̅ = 0
S1 = 1
S0 = 1

5. Identify the control and status signals for Memory Read machine cycle.

Control signal:
̅𝑅̅𝐷̅ = 0

Status signal:
𝐼𝑂/𝑀̅ = 0
S1 = 1
S0 = 0

6. Identify the control and status signals for Memory Write machine cycle.

Control signal:
̅𝑊̅𝑅̅ = 0

Status signal:
𝐼𝑂/𝑀̅ = 0
S1 = 0
S0 = 1
7. Identify the machine cycles in the following instructions. (You should be able to identify the
machine cycles even if you are not familiar with some of the instructions)
a) SUB B ; 1-byte, 4 T-states
; Subtract the contents of register B from the accumulator

Opcode fetch (4 T-states)

b) ADI 47H ; 2-byte, 7 (4, 3) T-states

; Add 47H to the contents of the accumulator

Opcode fetch (4 T-states)

Memory read (3 T-states)

c) STA 2050H ; 3-byte, 13 (4, 3, 3, 3) T-states

; Copies the contents of the accumulator into memory
; location 2050H

Opcode fetch (4 T-states)

Memory read (3 T-states)
Memory read (3 T-states)
Memory write (3 T-states)

d) PUSH B ; 1-byte, 12 (6, 3, 3) T-states

; Copies contents of BC register into two stack memory locations

Opcode fetch (6 T-states)

Memory write (3 T-states)
Memory write (3 T-states)

8. What are the important elements must be shown in the bus timings diagram for
instruction in Question 3?

Instruction: MVI A,20H

Name of machine cycles, T-states for each cycle, Clock, Address bus (high-order),
Address/Data bus (low-order), ALE, 𝐼𝑂/𝑀̅, S1, S0, 𝑅̅𝐷̅, ̅𝑊̅𝑅̅
9. Illustrate the bus timings for instruction in Question 3 if the instruction is stored in
memory at location

Instruction: MVI A,20H

a) 4090H

40H 40H

90H 91H 20H

b) 2010H

10H 11H 20H

10. Assume that memory location 2075H has a data byte 47H. Specify the contents of the address
bus AI5-A8 and the multiplexed bus AD7-AD0 when the MPU asserts the ̅𝑅̅𝐷̅ signal.

AI5-A8 : 20H
AD7-AD0 : 47H