INSTRUCTION SET AND EXECUTION IN 8085 51

added in the processor registers. The carry, if

generated, is ignored. The program
is shown in Table 3.13.

Table 3.13 Program for adding two numbers from memory

Memory Machine Labels Mnemonics with Comments
address codel operands
Opcode
8000 21 START: LXI H, 8500H InitializeHL register pair to point
8001 00 to the memory location of the
8002 85 first number.
8003 7E MOV A, M Load the first number in the
accumulator.
8004 23 INX H Increment the HL pair to point to
the memory location of the next
number.
8005 86 ADD M Add the two numbers.
8006 23 INX H Increment the HL pair to point to
the next memory location.
8007 77 MOV M, A Store the contents of the
accumulator in the memory location
pointed to by the HL register pair.
8008 76 HLT Terminate program execution.

3.5 INSTRUCTION EXECUTION AND TIMING DIAGRAMS

The 8085 microprocessor is designed to fetch the instruction pointed to by the
program counter, and then decode and execute the instruction within the processor.
If necessary, further operand fetch takes place before completing the execution.
Each instruction, as we have already seen, has two parts-operation code (known
as opcode) and operand. The opcode is a command such as ADD and the operand
is an object to be operated on, such as a byte or the contents of a register.
Instruction cycle is the time taken by the processor to complete the execution
of an instruction. An instruction cycle consists of one to six machine cycles.
Machine cycle is the time required to complete one operation-accessing either
the memory or an I/O device. A machine cycle consists of three to six T-states.
T-state is the time corresponding to one clock period. The T-state is the basic
unit used to calculate the time taken for execution of instructions and programs in
a processor.

To execute a program, the 8085 performs various operations such as opcode fetch,
operand fetch, and memory read/write or /O read/write. The microprocessor's
external communication function can be divided into three categories:
(i) Memory read/write (ii) I/O read/write
(ii) Interrupt request acknowledge
Table 3.14 gives the various possible states of the processor based on the
control signals 1O/M, s0, and S1.
52 MICROPROCESSORS AND MICROCONTROLLERS

Table 3.14 Processor states and control signals

Processor state
IO/M S1 SO

Z Halt
(high impedance) Memory write
0 0
VO write
0
Memory read
0
VO read
Opcode fetch
0 Interrupt acknowledge

fetch machine
T-states to execute the opcode
The 8085 microprocessor takes four
execute the memory
and I/O read/write cycles. The
cycle and three T-states to fetch cycle and is explained
acknowledge cycle is similar to the opcode
interrupt number of machine
8085 requires a definite
in Chapter 5. Every instruction of the instructions, dividing
the execution of some
cycles. Sections 3.5.1-3.5.5 explain
and further into many T-states.
them into the corresponding machine cycles
c o m m o n waveform
of the clock signal used in
Figure 3.6 shows the
is a square waveform of high frequency
microprocessor systems. The clock signal
of the clock signal can be clearly
in the range of MHz. The rising and falling edge low.
and time period is correspondingly very
seen, as its frequency is very high

Falling edge or negative edge 2

Rising edge or
positive edge

11-state

Time period T= 1, where f= internal clock frequency

Fig. 3.6 Clock signal for processors

the binary levels

The timing diagram for an instruction is obtained by drawing
of
on the various signals of the 8085. It is drawn with respect to the clock input
the microprocessor. It explains the execution of the instruction using the basic
machine cycles of that instruction.pxok gsar
3.5.1 Opcode Fetch Machine Cycle
The opcode fetch cycle is the first step in the execution of any instruction. In this
cycle, the microprocessor reads the opcode of an instruction from the memory.
The control and status signals for this machine cycle are IO/M= 0, S0 and SI=
1. This differentiates it from the memory read machine cycle. Every instruction
has a one-byte opcode, which is stored in the memory. Hence, every instruction
execution starts with opcode fetch machine cycle. The timing diagram for this
cycle is shown in Fig. 3.7
 INSTRUCTION SET AND EXECUTION IN 8085 53

SIGNAL T3 T4

CLOCK

AB-A15 Higher-order memorylacldress Unspecited

Lower-order
AD0-AD7 Opcode (D7-D0)
memory address

ALE

OM, S1, SO 1O/M= 0. S1 1S0 1

RD

Fig. 3.7 Timing diagram for opcode fetch cycle

The following points explain the various operations that take place and the
signals that are changed during the execution of the opcode fetch machine cycle:
During Tl clock cycle
) The content of the program counter is placed in the address bus. The lower
order address is placed in the ADO-AD7 lines and the higher-order address
is placed in the A8-A15 lines. The change of binary levels on these lines is
shown in the timing diagram by a cross.
i) 1OM signal goes low to indicate that a memory location is being accessed.
This signal is used by external devices to identify memory and I/O device
accesses for interfacing. The signals on the status lines SO and S1 are also
changed to the levels indicated in Table 3.14.
(1i) ALE signal becomes active high to indicate that the multiplexed AD0-AD7
lines are acting as the lower-order address bus.

During T2 clock cycle

6) The multiplexed lower-order address bus is now changed to the data bus. So,
the lower-order address bits in this bus are removed by the processor.
() The active low RD signal is made low by the processor. This signal makes
the memory devices load the data bus with the contents of the memory
location addressed by the processor.

During T3 clock cycle

the processor and moved to
0 The opcode available in the data bus is read by
the instruction register.
(i) After this, the control signal RD is deactivated by making it logic 1.
54 MICROPROCESSORS AND
MICROCONTROLLERS

During T4 clock cycle

i) The opcode placed in the instruction register is decoded by the processora
ranc
the necessary control signal is generated to execute the instruction. Basel.
on
the opcode of the instructíon, further operations such as fetching operand
writing into memory, etc., take place.
The time taken by the processor to execute the opcode fetch cycle is 4 T. The
first three T-states are used for fetching the opcode from memory and the remainine
T-state is used for internal instruction decoding and execution bytheprocessor

3.5.2 Memory Read Machine Cycle

The memory read machine cycle is executed by the processor to read a data byie
from memory. Instructions that are more than one byte long have the memory read
cycle to read the second byte of the instruction after the opcode fetch cycle.
The memory read machine cycle is exactly the same as the opcode fetch exce
for the following:
) It only has three T-states (ii) The S0 signal is set to 0.
The timing diagram for the memory read machine cycle is given in Fig. 3.8
The operations are similar to those in the opcode fetch cycle.
T2 T3
SIGNAL T1

3.
CLOCK The
por
A8-A15 Higher-order memoryladdress

Lower-order
Data(07-D0)
****

ADO-AD7 ***"*****

nemory address

ALE

OM=0, $1 1S00
OM, S1, S0

RD
 NSTRUCTION SET AND EXECUTION IN 8085 55

SIGNAL T1 T2

CLOCK

A8-A15 Higher-order memory address

ADO-AD7 Lower-order
Data|(D7-D0)
********

nemory address

ALE

OM, S1,$0 IOM= 0, $1 0 S0 1

WR

Fig. 3.9 Timing diagram for memory write cycle

3.5.4 UO Read Cycle
The 1O read cycle is executed by the processor to read a data byte from an VO
port or from a peripheral, which is 1/O-mapped in the system. The 8085 uses 8-bit

SIGNAL T1 T2 T3

CLOCK

ABA15 V0 port address

AD0-AD7 VO port address ******

***
Data (D7-D0)

ALE

IOM, S1, S0 1OM=0. |$1=1 S0 0

RD

Fig. 3.10 Timing diagram for VO read cycle

56 MCROPROCESSORS AND MICROCONTROLLERS

port addresses. So the port address is placed in the lower-order address bus. At the
he
same time, the port address is also placed in the higher-order address bus. Thie
facilitates easy design of hardware for address decoding. The processor takes three
T-states to execute this machine cycle. The IN instruction uses this machine cycle

The timing diagram is given in Fig. 3.10.

3.5.5 UO Write Cycle

The I/O write machine cycle is executed by the processor to write a data byte to

vo port or to a peripheral which mapped

is I/O in the system. The processor
an
takes three T-states to execute this machine cycle. The OUT instruction uses this

is given in Fig. 3.11.

machine cycle. The timing diagram
2 13
SIGNAL T1

CLOCK

A8-A15 Port address

ADO-AD7
Port address Datal(D7-D0) **

LE

WR

OM, S1, S0 IOM 1, $1 0 S0 1

Fig. 3.11 Timing diagram for /O write cycle

3.5.6 Timing Diagrams for Select Instructions

All 8085 instructions use a combination of the five basic machine cycles-opcode
fetch, memory read, memory write, VO read, and 1/0 write. Opcode fetch is
common to all instructions and is the first machine cycle in the execution of any
instruction. Depending on the instruction type, the execution may require further
machine cycles. Sections 3.5.6.1-3.5.6.4 discuss the timing diagrams of select
8085 microprocessor instructions.
3.5.6.1 Timing Diagram for STA 9000H
The STA instruction, upon execution, stores the accumulator contents in the
memory address given in the instruction. STA 9000H stores the accumulator
contents in the memory location 9000H. Since it is a three-byte instruction, it
 INSTRUCTION SET AND EXECUTIONIN 8085 557

is fetched in three different machine cycles. Instruction execution is completed

by a memory write machine cycle, which stores the accumulator contents in the
memory.
) During the first machine cycle, the program counter content (assumed to
be 800FH) is stored in the address bus and the opcode 32H is fetched and
decoded by the processor.
Gi) During the second machine cycle, the lower-order memory address 00H is
fetched by the processor.
ii) During the third machine cycle, the higher-order memory address 90H is
loaded in the processor.
iv) During the fourth machine cycle, the address 9000H is placed on the
address bus and the accumulator contents, 3FH in this case, is written in that
address.
STA requires four machine Table 3.15 STA instruction
and 13 T-states for
cycles Address Mnemonics
execution. The instruction and the Opcode
corresponding codes and memory 800F STA 9000OH 32
locations are given in Table 3.15. 8010 00
The instruction's timing 8011 90
diagram is given in Fig. 3.12.

Opcode fetch Memory read Memory read Memory write

T8 T10 T11 T12 113

CLK

ADO-ADT * * 10H |0OH 00H 3FH

B0H 80H 80H 90H

AB-A15

ALE

RD

WR

1OM, S0, S1 0,1,1 0,0,1 0,0,1 0,1,0

X

Fig. 3.12 Timing diagram for the STA instruction t ode bi

3.5.6.2 Timing Dlagram for IN 80H

The IN instruction is a two-byte instruction and has one opcode followed by the input
port address. This instruction requires three machine cycles-to read the instruction
and then to write the data from the input port address to the accumulator.
58 MICROPROCESSORS AND MICROcONTROLLERS

DBH is fetched from the

memor
0 During the first machine cycle, the opcode
decoded.
placed in the instruction register, and
address 80H is read from the nex
i) During the second machine cycle, the port
memory location. in the address bue
address 80H is placed
(ii) During the third machine cycle, the
is placed in the accumulator.
and the data read from that port address
Table 3.16 IN instruction
The instruction and the
corresponding codes and memory
Address
Mnemonics Opcode
locations are given in Table 3.16.
IN 80H DB
800F
The instruction's timing 80
8010
diagram is given in Fig. 3.13.
Memory read VO read
Opcode fetch

T9 T10
1 12 T3 T4 5 T

CLK

AD0-AD7XOFH DBH 10R

80R) 80H FFH

80H 80H
A8-A15 80H

ALE

RD

WR

1OM, SO, S1 0,1,1 0,0,1

1.01

Fig. 3.13 Timing diagram for the IN instruction

3.5.6.3 Timing Diagram for INR M
Table 3.17 INR instruction
INR M is a one-byte instruction
that increments the contents of a Address Mnemonics Opcode
memory location. The instruction 8100 INR M 34
and the corresponding code and
memory location are given in Table 3.17.
The memory content cannot be changed in the memory location itself. It has to
be read into the processor and then modified. After modification, it has to be written
into the same memory address. So this instruction requires three machine cycles.
i) During the first machine cycle, the opcode is fetched from the memory
location. In the example shown, the opcode 34H is fetched from the location
8100H.
i) During the second machine cycle, the contents of the HlL register pair are
 INSTRUCTION SET AND EXECUTION IN 8085 59

alaced in the address bus, the memory content is brought to the processor,
and its value is incremented.
During the third machine cycle, the incremented data is again written back
into the same address, as shown in the timing diagram given in Fig. 3.14.

Opcode fetch Memory read Memory write

CLK

ADO-AD7 00H 34 01H 13H

A8-A15 81H 90H 90H

ALE

RD

oM, SO,$1 0,1.1 0,0,1 0,1,0

Fig. 3.14 Timing diagram for the INR Minstruction

3.5.6.4 Timing Diagram for MVI B, 3FH

Let us study the execution of the instruction MVI B, 3FH. It has the code 06H,
followed by 3FH. The frst byte 06H represents the opcode for loading a byte into
register B. The second byte is the data to be loaded.
The 8085 needs two machine cycles to read these two bytes from memory
before it can execute the instruction. The first machine cycle is the opcode fetch,
as discussed earlier. The code 06His fetched from the memory location 8100H
to the instruction register. The second machine cycle is the memory read cycle.
The operand 3FH is read from the
Table 3.18 MVI instruction
memory location 8101H using the
memory read machine cycle. Address Mnemonics Opcode
The instruction and the
8100 MVIB, 3FH 06
corresponding codes and memory 8101 3F
locations are given in Table 3.18.
The timing diagram for the MVI instruction is given in Fig. 3.15.

3.6 DE-MULTIPLEXING ADO-AD7 a ygbad

The 8085 uses a
multiplexed data bus and lower-order address bus, This multiplexing
1s done to reduce the pin count of the device. However, external memory or VO
devices need the complete 16-bit address for decoding and selecting a device. So,
60 MICROPROCESSORS AND
MICROCONTROLLERS

M1 (Opcode fetch) M2 (Memory read

T1 2 3 T4 I1 2

CLK

A8-A15 81HHigher-order memory address Unspecified 81H Higher-order memoryladdress

Lower-order
Lower-order
01H 3FH
ADO-AD7 0OH 06H

Memory addreds Data

Memory address Opcode
ALE

IOM 0,1=1,S0 = 0 Status

OM S1, S0 Status OM 0, S1 1, S0= 1 Opcode fetch

RO

Fig. 3.15 Timing diagram for the MVI instruction

the multiplexed address and data bus must be de-multiplexed. The de-multiplexing
can be done with the help of the signal ALE given by the processor for this purpose.
The hardware needed for de-multiplexing is given in Fig. 3.16.

DO-D7

Latch
AD0-AD7 74LS373
A0-A7
ALE

8085
AB-A15

Fig. 3.16 Hardware interfacing for de-multiplexing lower-order address bus and data bus
During the first T-state in all the machine cycles, the ADO-AD7 lines act
on these lines. The
as address bus and the lower-order address is available
ADO-AD7 lines are converted into the data bus during the second T-state.
the
However, the memory devices require the lower-order address lines during
entire machine cycle. So, during the first T-state, the lower-order address lines sent
out by the microprocessor is stored into a separate latch or register. The common
this
74LS373 latch, which has inputs and outputs of 8 bits each, can be used for
address lines available in
purpose. The ALE control signal is used for latching the