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Microprocessor
Debashis Chakraborty
Intel 8085
Intel 8085
Pin
Configuration
3
Signals and I/O Pins
4
Intel 8085 CPU Block Diagram
5
The 8085 and Its Buses
The 8085 is an 8-bit general purpose microprocessor that can
address 64K Byte of memory.
It has 40 pins and uses +5V for power. It can run at a maximum
frequency of 3 MHz.
The pins on the chip can be grouped into 6 groups:
Address Bus.
Data Bus.
the address bits during the early part, then during the
late parts of the execution, they carry the 8 data bits.
In order to separate the address from the data, we can use a
8
The Control and Status
Signals
There are 4 main control and status signals. These are:
ALE: Address Latch Enable. This signal is a pulse that
circuit.
The frequency is internally divided by 2.
CLK (OUT): An output clock pin to drive the clock of the rest
of the system.
unsigned operation.
OV-Overflow flag
This flag is set when an overflow occurs after a signed
operation.
Now, Let us see how the different units
and bus systems stay connected:
Chip Selection
A15- A10 Circuit
8085
CS
A15-A8
ALE
A9- A0 1K Byte
AD7-AD0 Latch Memory
A7- A0 Chip
WR RD IO/M D7- D0
RD WR
More on the 8085 machine
cycles
The 8085 executes several types of instructions
with each requiring a different number of
operations of different types. However, the
operations can be grouped into a small set.
The three main types are:
Memory Read and Write.
Request Acknowledge.
“memory read” cycle, the control & status signals are set
as follows:
IO/M=0, s0 and s1 are both 1.
byte into the accumulator (MVI A), the second byte is the
data to be loaded.
The 8085 needs to read these two bytes from memory
before it can execute the instruction. Therefore, it will need
at least two machine cycles.
The first machine cycle is the opcode fetch discussed
earlier.
The second machine cycle is the Memory Read
Cycle.
Machine Cycles vs. Number of bytes
in the instruction
Machine cycles and instruction length, do not have a direct
relationship.
To illustrate, let’s look at the machine cycles needed to
Data Lines
ROM
RAM
Input Buffer WR
Address CS
Lines
Address CS
Lines
Output Buffer RD
Output Buffer RD
Date
Lines
Data Lines
address bus.
Part of the address bus will select the chip and the
chip.
What concerns us is the other part that must
decoder.
Putting all of the concepts together:
8085
CS
A15-A8
ALE
A9- A0 1K Byte
AD7-AD0 Latch Memory
A7- A0 Chip
WR RD IO/M D7- D0
RD WR
Control and Status Signals.
26
Interrupt Signals
8085 μp has several interrupt signals as shown in the following table.
27
Interrupt signals
An interrupt is a hardware-initiated subroutine CALL.
When interrupt pin is activated, an ISR will be called,
interrupting the program that is currently executing.
29
Interrupt
Vectors
30
A circuit that causes an RST4 instruction (E7) to be
executed in response to INTR.
When INTR is
asserted,
8085
response with
INTA pulse.
During INTA
pulse, 8085
expect to see
an instruction
applied to its
data bus.
31
RESET signal
Following are the two kind of RESET
signals:
RESET IN: an active low input signal, Program
Counter (PC) will be set to 0 and thus MPU will
reset.
RESET OUT: an output reset signal to indicate
that the μp was reset (i.e. RESET IN=0). It
also used to reset external devices.
32
RESET signal
33
Direct Memory Access (DMA)