Sony CXD2587Q

CXD2587Q
CD Digital Signal Processor with Built-in Digital Servo and DAC

For the availability of this product, please contact the sales office.
Description
The CXD2587Q is a digital signal processor LSI for 80 pin LQFP (Plastic)
CD players. This LSI incorporates a digital servo,
digital filter, zero detection circuit, 1-bit DAC and
analog low-pass filter.
Features
Digital Signal Processor (DSP) Block
• 1×, 2×, 4× speed playback supported
• 16K-RAM
• EFM data demodulation
Applications
• Enhanced EFM frame sync signal protection
CD players
• SEC strategy-based error correction
• Subcode demodulation and Sub Q data error
Structure
detection
Silicon gate CMOS IC
• Digital spindle servo
• 16-bit traverse counter
Absolute Maximum Ratings
• Asymmetry compensation circuit
• Supply voltage VDD –0.3 to +7.0 V
• CPU interface on serial bus
• Input voltage VI –0.3 to +7.0 V
• Error correction monitor signal, etc. output from a
(VSS – 0.3V to VDD + 0.3V)
new CPU interface
• Output voltage VO –0.3 to +7.0 V
• Servo auto sequencer
• Storage temperature Tstg –40 to +125 °C
• Digital audio interface outputs
• Supply voltage difference
• Digital level meter, peak meter
VSS – AVSS –0.3 to +0.3 V
• CD TEXT data demodulation
VDD – AVDD –0.3 to +0.3 V
Digital Servo (DSSP) Block Note) AVDD includes XVDD and AVSS includes XVSS.
• Microcomputer software-based flexible servo control
• Offset cancel function for servo error signal Recommended Operating Conditions
• Auto gain control function for servo loop • Supply voltage VDD∗ 3.0 to 4.0 V
• E:F balance, focus bias adjustment function • Operating temperature
• Surf jump function supporting micro two-axis Topr –20 to +75 °C
∗ The VDD for the CXD2587Q varies according to the
Digital Filter, DAC and Analog Low-pass Filter Blocks
playback speed.
• DBB (digital bass boost) function
• Double-speed playback supported Playback VDD [V]
• Digital de-emphasis speed CD-DSP block DAC block
• Digital attenuation
• 8Fs oversampling filter 4× 4.75 to 5.25
• S/N: 100dB or more (master clock: 384Fs, typ.) 2× 3.0 to 5.5 4.5 to 5.5
Logical value 109dB
1× 2.7 to 5.5 2.7 to 5.5
• THD + N: 0.007% or less (master clock 384Fs, typ.)
• Rejection band attenuation: –60dB or less
I/O Capacitance
• Input pin CI 11 (Max.) pF
• Output pin CO 11 (Max.) pF
• I/O pin CI/O 11 (Max.) pF
Note) Measurement conditions VDD = VI = 0V
fM = 1MHz
Sony reserves the right to change products and specifications without prior notice. This information does not convey any license by
any implication or otherwise under any patents or other right. Application circuits shown, if any, are typical examples illustrating the
operation of the devices. Sony cannot assume responsibility for any problems arising out of the use of these circuits.
–1–
E97518-PS
CXD2587Q
Block Diagram
WFCK
EMPH
PCMD
SYSM
C2PO
XUGF
LRCK
XTSL
GFS
BCK
DAC Block
TES1
TEST
Clock Error
XRST
Generator Corrector
EFM D/A Serial-In RMUT
RFAC demodurator Interface Interface LMUT
ASYI
ASYO Asymmetry Over Sampling Timing XTAI
Corrector Digital Filter Logic
BIAS XTAO
16K
RAM 3rd-Order
XPCK
Noise Shaper
FILO Sub Code Digital
Digital Processor OUT
FILI PWM PWM
PLL
PCO
CLTV
MDP Digital
LOCK CLV
SENS
DATA
XLAT Servo AOUT1
CPU
CLOK Auto AIN1
Interface
Sequencer
SPOA LOUT1
SPOB AOUT2
XLON AIN2
SCOR LOUT2
SQSO
SQCK DOUT
Signal Processor Block
Servo Block SCLK

SERVO COUT
Interface SSTP
ATSK
MIRR
MIRR
DFCT DFCT
RFDC FOK
FOK
CE
TE SERVO DSP PWM GENERATOR
FOCUS PWM FFDR
OPAmp A/D
SE FOCUS SERVO
Analog SW Converter GENERATOR FRDR
FE
TRACKING TRACKING PWM TFDR
VC SERVO GENERATOR
TRDR
IGEN
SLED PWM SFDR
SLED SERVO
GENERATOR
SRDR
ADIO
–2–
CXD2587Q
Pin Configuration
AVDD3
AVDD0
AVSS0
AVSS3
DOUT
RFAC
ASYO
RFDC
CLTV
ADIO
IGEN
BIAS
ASYI
PCO
FILO
VDD
VSS
FILI
CE
TE
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
LRCK 61 40 SE
PCMD 62 39 FE
BCK 63 38 VC
EMPH 64 37 XTSL
XVDD 65 36 TES1
XTAI 66 35 TEST
XTAO 67 34 VSS
XVSS 68 33 FRDR
AVDD1 69 32 FFDR
AOUT1 70 31 TRDR
AIN1 71 30 TFDR
LOUT1 72 29 SRDR
AVSS1 73 28 SFDR
AVSS2 74 27 SSTP
LOUT2 75 26 MDP
AIN2 76 25 LOCK
AOUT2 77 24 FOK
AVDD2 78 23 DFCT
RMUT 79 22 MIRR
LMUT 80 21 COUT
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
XPCK
ATSK
DATA
XUGF
VDD
SYSM
WFCK
SCLK
XRST
SCOR
XLON
SENS
SQCK
C2PO
SPOB
CLOK
SQSO
GFS
SPOA
XLAT
–3–
CXD2587Q
Pin Description
Pin Output
Symbol I/O Description
No. values
1 SQSO O 1, 0 Sub Q 80-bit, PCM peak and level data outputs. CD TEXT data output.
2 SQCK I SQSO readout clock input.
3 XRST I System reset. Reset when low.
4 SYSM I Mute input. Muted when high.
5 DATA I Serial data input from CPU.
6 XLAT I Latch input from CPU. Serial data is latched at the falling edge.
7 CLOK I Serial data transfer clock input from CPU.
8 SENS O 1, 0 SENS output to CPU.
9 SCLK I SENS serial data readout clock input.
10 VDD — — Digital power supply.
11 ATSK I/O 1, 0 Anti-shock input/output.
12 SPOA I Microcomputer extension interface (input A)
13 SPOB I Microcomputer extension interface (input B)
14 XLON O 1, 0 Microcomputer extension interface (output)
15 WFCK O 1, 0 WFCK output.
16 XUGF O 1, 0 XUGF output. MINT1 or RFCK is output by switching with the command.
17 XPCK O 1, 0 XPCK output. MNT0 is output by switching with the command.
18 GFS O 1, 0 GFS output. MNT3 or XROF is output by switching with the command.
19 C2PO O 1, 0 C2PO output. GTOP is output by switching with the command.
20 SCOR O 1, 0 Outputs a high signal when either subcode sync S0 or S1 is detected.
21 COUT I/O 1, 0 Track count signal input/output.
22 MIRR I/O 1, 0 Mirror signal input/output.
23 DFCT I/O 1, 0 Defect signal input/output.
24 FOK I/O 1, 0 Focus OK signal input/output.
GFS is sampled at 460Hz; when GFS is high, this pin outputs a high signal. If GFS
25 LOCK I/O 1, 0
is low eight consecutive samples, this pin outputs low. Or input when LKIN = 1.
26 MDP O 1, Z, 0 Spindle motor servo control output.
27 SSTP I Disc innermost track detection signal input.
28 SFDR O 1, 0 Sled drive output.
29 SRDR O 1, 0 Sled drive output.
30 TFDR O 1, 0 Tracking drive output.
31 TRDR O 1, 0 Tracking drive output.
32 FFDR O 1, 0 Focus drive output.
33 FRDR O 1, 0 Focus drive output.
34 VSS — — Digital GND.
35 TEST I Test pin. Normally, GND.
–4–
CXD2587Q
Pin Output
No. values
36 TES1 I Test pin. Normally, GND.
Crystal selection input. Low when the crystal is 16.9344MHz; high when the
37 XTSL I
crystal is 33.8688MHz.
38 VC I Center voltage input.
39 FE I Focus error signal input.
40 SE I Sled error signal input.
41 TE I Tracking error signal input.
42 CE I Center servo analog input.
43 RFDC I RF signal input.
44 ADIO O Analog Test pin. No connected.
45 AVSS0 — — Analog GND.
46 IGEN I Operational amplifier constant current input.
47 AVDD0 — — Analog power supply.
48 ASYO O 1, 0 EFM full-swing output. (low = Vss, high = VDD)
49 ASYI I Asymmetry comparator voltage input.
50 BIAS I Asymmetry circuit constant current input.
51 RFAC I EFM signal input.
53 CLTV I Multiplier VCO1 control voltage input.
54 FILO O Analog Master PLL filter output. (slave = digital PLL)
55 FILI I Master PLL filter input.
56 PCO O 1, Z, 0 Master PLL charge pump output.
58 VSS — — Digital GND.
59 VDD — — Digital power supply.
60 DOUT O 1, 0 Digital Out output.
61 LRCK O 1, 0 D/A interface. LR clock output f = Fs.
62 PCMD O 1, 0 D/A interface. Serial data output. (two's complement, MSB first)
63 BCK O 1, 0 D/A interface. Bit clock output.
Outputs a high signal when the playback disc has emphasis, and a low
64 EMPH O 1, 0
signal when there is no emphasis.
65 XVDD — — Master clock power supply.
66 XTAI I Crystal oscillation circuit input. Master clock is externally input from this pin.
67 XTAO O Crystal oscillation circuit output.
68 XVSS — — Master clock GND.
70 AOUT1 O L ch analog output.
71 AIN1 I L ch operational amplifier input.
–5–
CXD2587Q
Pin Output
No. values
72 LOUT1 O L ch LINE output.
75 LOUT2 O R ch LINE output.
76 AIN2 I R ch operational amplifier output.
77 AOUT2 O R ch analog output.
79 RMUT O 1, 0 R ch zero detection flag.
80 LMUT O 1, 0 L ch zero detection flag.
Notes) • PCMD is a MSB first, two's complement output.

• GTOP is used to monitor the frame sync protection status. (High: sync protection window released.)
• XUGF is the frame sync obtained from the EFM signal, and is negative pulse. It is the signal before
sync protection.
• XPCK is the inverse of the EFM PLL clock. The PLL is designed so that the falling edge and the
EFM signal transition point coincide.
• The GFS signal goes high when the frame sync and the insertion timing match.
• RFCK is derived from the crystal accuracy, and has a cycle of 136µs.
• C2PO represents the data error status.
• XROF is generated when the 16K RAM exceeds the ±4F jitter margin.
Monitor Pin Output Combinations

Command bit
Output data
MTSL1 MTSL0
0 0 XUGF XPCK GFS C2PO
0 1 MNT1 MNT0 MNT3 C2PO
1 0 RFCK XPCK XROF GTOP
–6–
CXD2587Q
Electrical Characteristics
1. DC Characteristics (VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Applicable
Item Conditions Min. Typ. Max. Unit
pins
Input High level input voltage VIH (1) 0.7VDD V

∗1, ∗9
voltage (1) Low level input voltage VIL (1) 0.3VDD V
Input High level input voltage VIH (2) 0.8VDD V

Schmitt input ∗2, ∗10
voltage (2) Low level input voltage VIL (2) 0.2VDD V
Input
Input voltage VIN (3) Analog input Vss VDD V ∗3, ∗7, ∗8
voltage (3)
Output High level output voltage VOH (1) IOH = –2mA VDD – 0.8 VDD V
∗4
voltage (1) Low level output voltage VOL (1) IOL = 4mA Vss 0.4 V
Output High level output voltage VOH (2) IOH = –6mA VDD – 0.8 VDD V
∗5
voltage (2) Low level output voltage VOL (2) IOL = 4mA Vss 0.4 V
Output High level output voltage VOH (3) IOH = –0.28mA VDD – 0.5 VDD V
∗6
voltage (3) Low level output voltage VOL (3) IOL = 0.36mA Vss 0.4 V
VIN = VSS
Input leak current (1) ILI (1) –10 10 µA ∗1, ∗2
or VDD
VIN = VSS
Input leak current (2) ILI (2) –40 40 µA ∗9, ∗10
or VDD
Input leak current (3) ILI (3) VI = 1.5 to 3.5V –20 20 µA ∗7
Input leak current (4) ILI (4) VI = 0 to 5.0V –40 600 µA ∗8
Applicable pins
∗1 SYSM, DATA, XLAT, SSTP, XTSL, TEST, TES1
∗2 SQCK, XRST, CLOK
∗3 ASYI, RFAC, CLTV, FILI
∗4 SQSO, SENS, ATSK, XLON, WFCK, XUGF, XPCK, GFS, C2PO, SCOR, COUT, MIRR, DFCT, FOK,
LOCK, SFDR, SRDR, TFDR, TRDR, FFDR, FRDR, ASYO, DOUT, LRCK, PCMD, BCK, EMPH, RMUT,
LMUT
∗5 MDP, PCO
∗6 FILO
∗7 VC, FE, SE, TE, CE
∗8 RFDC
∗9 ATSK, COUT, MIRR, DFCT, FOK, LOCK
∗10 SCLK, SPOA, SPOB
–7–
CXD2587Q
2. AC Characteristics
(1) XTAI pin
(a) When using self-excited oscillation

(Topr = –20 to +75°C, VDD = AVDD = 5.0V ± 5%)
Item Symbol Min. Typ. Max. Unit
Oscillation
fMAX 7 34 MHz
frequency
(b) When inputting pulses to XTAI pin


High level pulse
width
tWHX 13 500 ns
Low level pulse

width
tWLX 13 500 ns
Pulse cycle tCX 26 1000 ns
Input high level VIHX VDD – 1.0 V
Input low level VILX 0.8 V
Rise time,
fall time
tR, tF 10 ns
tCK
tWHX tWLX
VIHX
VIHX × 0.9
XTAI VDD/2
VIHX × 0.1
VILX
tR tF
(c) When inputting sine waves to XTAI pin via a capacitor

Item Symbol Min. Typ. Max. unit
Input amplitude VI 2.0 VDD + 0.3 Vp-p
–8–
CXD2587Q
(2) CLOK, DATA, XLAT and SQCK pin

(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Clock frequency fCK 0.65 MHz
Clock pulse width tWCK 750 ns
Setup time tSU 300 ns
Hold time tH 300 ns
Delay time tD 300 ns
Latch pulse width tWL 750 ns
SQCK frequency fT 0.65 Note) MHz
SQCK pulse width tWT 750 Note) ns
1/fCK
tWCK tWCK
CLOK
DATA
XLAT
tSU tH
tD tWL
SQCK
tWT tWT
1/fT
SQSO
tSU tH
Note) In quasi double-speed playback mode, except when SQSO is Sub Q Read, the SQCK maximum
operating frequency is 300kHz and its minimum pulse width is 1.5µs.
–9–
CXD2587Q
(3) SCLK pin
XLAT
tDLS tSPW
SCLK •••
1/fSCLK
Serial Read Out Data MSB ••• LSB

(SENS)

SCLK frequency fSCLK 16 MHz
SCLK pulse width tSPW 31.3 ns
Delay time tDLS 15 µs
(4) COUT, MIRR and DFCT pins

Operating frequency
(VDD = AVDD = 5.0V ± 5%, VSS = AVSS = 0V, Topr = –20 to +75°C)
Item Symbol Min. Typ. Max. Unit Conditions
COUT maximum operating frequency fCOUT 40 kHz ∗1
MIRR maximum operating frequency fMIRR 40 kHz ∗2
DFCT maximum operating frequency fDFCTH 5 kHz ∗3
∗1 When using a high-speed traverse TZC.

∗2
B
When the RF signal continuously satisfies the following conditions during the above traverse.
• A = 0.12VDD to 0.26VDD
B
• ≤ 25%
A+B
∗3 During complete RF signal omission.

When settings related to DFCT signal generation are Typ.
– 10 –
CXD2587Q
1-bit DAC and LPF Block Analog Characteristics

Analog characteristics (VDD = AVDD = 5.0V, VSS = AVSS = 0V, Ta = 25°C)
Item Symbol Conditions Crystal Min. Typ. Max. Unit
Total harmonic 384Fs 0.0050 0.0070

THD 1kHz, 0dB data %
distortion 768Fs 0.0045 0.0065
Signal-to-noise 1kHz, 0dB data 384Fs 96 100

S/N dB
ratio (Using A-weighting filter) 768Fs 96 100
Fs = 44.1kHz in all cases.

The total harmonic distortion and signal-to-noise ratio measurement circuits are shown below.
12k
AOUT1 (2)
680p
12k 12k SHIBASOKU (AM51A)

AIN1 (2)
150p
LOUT1 (2) Audio Analyzer

22µ
100k
LPF external circuit diagram
768Fs/384Fs
Rch A
DATA RF
TEST DISC CXD2587Q Audio Analyzer
Lch B
Block diagram of analog characteristics measurement
(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = –20 to +75°C)

Item Symbol Min. Typ. Max. Unit Applicable pins
Output voltage VOUT 1.12 Vrms ∗1
Load resistance RL 8 kΩ ∗1
∗ Measurement is conducted for the LPF external circuit diagram with the sine wave output of 1kHz and 0dB.
Applicable pins
∗1 LOUT1, LOUT2
– 11 –
CXD2587Q
Contents
§1. CPU Interface

§1-1. CPU Interface Timing ........................................................................................................................ 13
§1-2. CPU Interface Command Table ........................................................................................................ 13
§1-3. CPU Command Presets .................................................................................................................... 23
§1-4. Description of SENS Signals and Commands ................................................................................... 28
§2. Subcode Interface

§2-1. 80-bit Sub Q Readout ........................................................................................................................ 42
§3. Description of Other Functions

§3-1. Channel Clock Regeneration by the Digital PLL Circuit .................................................................... 45
§3-2. Frame Sync Protection ...................................................................................................................... 46
§3-3. Error Correction ................................................................................................................................. 46
§3-4. DA Interface ....................................................................................................................................... 47
§3-5. Digital Out .......................................................................................................................................... 49
§3-6. Servo Auto Sequence ....................................................................................................................... 49
§3-7. Digital CLV ......................................................................................................................................... 56
§3-8. CD-DSP Block Playback Speed ........................................................................................................ 57
§3-9. DAC Block Playback Speed .............................................................................................................. 57
§3-10. Description of DAC Block Functions .................................................................................................. 58
§3-11. LPF Block .......................................................................................................................................... 61
§3-12. Asymmetry Compensation ................................................................................................................ 62
§3-13. CD TEXT Data Demodulation ........................................................................................................... 63
§4. Description of Servo Signal Processing System Functions and Commands

§4-1. General Description of Servo Signal Processing System .................................................................. 65
§4-2. Digital Servo Block Master Clock (MCK) ........................................................................................... 66
§4-3. AVRG Measurement and Compensation .......................................................................................... 66
§4-4. E:F Balance Adjustment Function ..................................................................................................... 68
§4-5. FCS Bias Adjustment Function .......................................................................................................... 68
§4-6. AGCNTL Function ............................................................................................................................. 70
§4-7. FCS Servo and FCS Search ............................................................................................................. 72
§4-8. TRK and SLD Servo Control ............................................................................................................. 73
§4-9. MIRR and DFCT Signal Generation .................................................................................................. 74
§4-10. DFCT Countermeasure Circuit .......................................................................................................... 75
§4-11. Anti-Shock Circuit .............................................................................................................................. 75
§4-12. Brake Circuit ...................................................................................................................................... 76
§4-13. COUT Signal ..................................................................................................................................... 77
§4-14. Serial Readout Circuit ........................................................................................................................ 77
§4-15. Writing to the Coefficient RAM .......................................................................................................... 78
§4-16. PWM Output ...................................................................................................................................... 78
§4-17. Servo Status Changes Produced by the LOCK Signal ..................................................................... 80
§4-18. Description of Commands and Data Sets ......................................................................................... 80
§4-19. List of Servo Filter Coefficients .......................................................................................................... 95
§4-20. Filter Composition .............................................................................................................................. 97
§4-21. TRACKING and FOCUS Frequency Response .............................................................................. 104
§5. Application Circuit .................................................................................................................................. 105
Explanation of abbreviations AVRG: Average

AGCNTL: Auto gain control
FCS: Focus
TRK: Tracking
SLD: Sled
DFCT: Defect
– 12 –
CXD2587Q
§1. CPU Interface
§1-1. CPU Interface Timing

• CPU interface
This interface uses DATA, CLOK and XLAT to set the modes.
The interface timing chart is shown below.
750ns or more
CLOK
DATA D0 D1 D18 D19 D20 D21 D22 D23
750ns or more
XLAT
Registers Valid
• The internal registers are initialized by a reset when XRST = 0.

Note) Be sure to set SQCK to high when XLAT is low.
§1-2. CPU Interface Command Table
Total bit length for each register
Register Total bit length

0 to 2 8 bits
3 8 to 24 bits
4 to 6 8 bits
7 20 bits
8 28 bits
9 24 bits
A 28 bits
B 16 bits
C 8 bits
D 16 bits
E 20 bits
– 13 –
Command Table ($0X to 1X)
Address Data 1 Data 2 Data 3 Data 4 Data 5

Register Command
D23 to D20 D19 D18 D17 D16 D15 D14 D13 D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
FOCUS SERVO ON
1 0 — — — — — — — — — — — — — — — — — — (FOCUS GAIN
NORMAL)
FOCUS SERVO ON
1 1 — — — — — — — — — — — — — — — — — — (FOCUS GAIN
DOWN)
FOCUS SERVO OFF,
FOCUS 0 — 0 — — — — — — — — — — — — — — — — —
0 0000 0V OUT
CONTROL
FOCUS SERVO OFF,
0 — 1 — — — — — — — — — — — — — — — — — FOCUS SEARCH
VOLTAGE OUT
FOCUS SEARCH
0 — 1 0 — — — — — — — — — — — — — — — —
VOLTAGE DOWN
FOCUS SEACH
0 — 1 1 — — — — — — — — — — — — — — — —
VOLTAGE UP
1 0 — — — — — — — — — — — — — — — — — — ANTI SHOCK ON
– 14 –
0 — — — — — — — — — — — — — — — — — — — ANTI SHOCK OFF
— 1 — — — — — — — — — — — — — — — — — — BRAKE ON
— 0 — — — — — — — — — — — — — — — — — — BRAKE OFF
TRACKING
1 0001
CONTROL TRACKING GAIN
— — 0 — — — — — — — — — — — — — — — — —
NORMAL
— — 1 — — — — — — — — — — — — — — — — — TRACKING GAIN UP
TRACKING GAIN UP
— — — 1 — — — — — — — — — — — — — — — —
FILTER SELECT 1
TRACKING GAIN UP
— — — 0 — — — — — — — — — — — — — — — —
FILTER SELECT 2
—: Don’t care
CXD2587Q
Command Table ($2X to 3X)

Register Command
0 0 — — — — — — — — — — — — — — — — — — TRACKING SERVO OFF
0 1 — — — — — — — — — — — — — — — — — — TRACKING SERVO ON
1 0 — — — — — — — — — — — — — — — — — — FORWARD TRACK JUMP
1 1 — — — — — — — — — — — — — — — — — — REVERSE TRACK JUMP

2 TRACKING
0010
MODE
— — 0 0 — — — — — — — — — — — — — — — — SLED SERVO OFF
— — 0 1 — — — — — — — — — — — — — — — — SLED SERVO ON
— — 1 0 — — — — — — — — — — — — — — — — FORWARD SLED MOVE
— — 1 1 — — — — — — — — — — — — — — — — REVERSE SLED MOVE
– 15 –
Register Command
0 0 0 0 — — — — — — — — — — — — — — — — SLED KICK LEVEL

(±1 × basic value) (Default)
0 0 0 1 — — — — — — — — — — — — — — — — SLED KICK LEVEL

(±2 × basic value)
3 SELECT 0011
0 0 1 0 — — — — — — — — — — — — — — — — SLED KICK LEVEL
0 0 1 1 — — — — — — — — — — — — — — — — SLED KICK LEVEL

—: Don’t care
CXD2587Q
Command Table ($340X)
Address 1 Address 2 Address 3 Address 4 Data 1 Data 2
Register Command
D23 to D20 D19 to D16 D15 to D12 D11 D10 D9 D8 D7 D6 D5 D4 D3 D2 D1 D0
KRAM DATA (K00)

0 0 0 0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
SLED INPUT GAIN
KRAM DATA (K01)
SLED LOW BOOST FILTER A-H
KRAM DATA (K02)
SLED LOW BOOST FILTER A-L
KRAM DATA (K03)
SLED LOW BOOST FILTER B-H
KRAM DATA (K04)
SLED LOW BOOST FILTER B-L
KRAM DATA (K05)
SLED OUTPUT GAIN
KRAM DATA (K06)
FOCUS INPUT GAIN
KRAM DATA (K07)
SLED AUTO GAIN
3 SELECT 0011 0100 0000
– 16 –
KRAM DATA (K08)
FOCUS HIGH CUT FILTER A
KRAM DATA (K09)
FOCUS HIGH CUT FILTER B
KRAM DATA (K0A)
FOCUS LOW BOOST FILTER A-H
KRAM DATA (K0B)
FOCUS LOW BOOST FILTER A-L
KRAM DATA (K0C)
FOCUS LOW BOOST FILTER B-H
KRAM DATA (K0D)
FOCUS LOW BOOST FILTER B-L
KRAM DATA (K0E)
FOCUS PHASE COMPENSATE FILTER A
KRAM DATA (K0F)
FOCUS DEFECT HOLD GAIN
CXD2587Q

Register Command
KRAM DATA (K10)

FOCUS PHASE COMPENSATE FILTER B
KRAM DATA (K11)
FOCUS OUTPUT GAIN
KRAM DATA (K12)
ANTI SHOCK INPUT GAIN
KRAM DATA (K13)
FOCUS AUTO GAIN
KRAM DATA (K14)
HPTZC / AUTO GAIN HIGH PASS FILTER A
KRAM DATA (K15)
HPTZC / AUTO GAIN HIGH PASS FILTER B
KRAM DATA (K16)
ANTI SHOCK HIGH PASS FILTER A
KRAM DATA (K17)
HPTZC / AUTO GAIN LOW PASS FILTER B
3 SELECT 0011 0100 0001
– 17 –
KRAM DATA (K18)
FIX
KRAM DATA (K19)
TRACKING INPUT GAIN
KRAM DATA (K1A)
TRACKING HIGH CUT FILTER A
KRAM DATA (K1B)
TRACKING HIGH CUT FILTER B
KRAM DATA (K1C)
TRACKING LOW BOOST FILTER A-H
KRAM DATA (K1D)
TRACKING LOW BOOST FILTER A-L
KRAM DATA (K1E)
TRACKING LOW BOOST FILTER B-H
KRAM DATA (K1F)
TRACKING LOW BOOST FILTER B-L
CXD2587Q
Register Command
KRAM DATA (K20)

TRACKING PHASE COMPENSATE FILTER A
KRAM DATA (K21)
TRACKING PHASE COMPENSATE FILTER B
KRAM DATA (K22)
TRACKING OUTPUT GAIN
KRAM DATA (K23)
TRACKING AUTO GAIN
KRAM DATA (K24)
FOCUS GAIN DOWN HIGH CUT FILTER A
KRAM DATA (K25)
FOCUS GAIN DOWN HIGH CUT FILTER B
KRAM DATA (K26)
FOCUS GAIN DOWN LOW BOOST FILTER A-H
KRAM DATA (K27)
FOCUS GAIN DOWN LOW BOOST FILTER A-L
3 SELECT 0011 0100 0010
– 18 –
KRAM DATA (K28)
FOCUS GAIN DOWN LOW BOOST FILTER B-H
KRAM DATA (K29)
FOCUS GAIN DOWN LOW BOOST FILTER B-L
KRAM DATA (K2A)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
KRAM DATA (K2B)
FOCUS GAIN DOWN DEFECT HOLD GAIN
KRAM DATA (K2C)
FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
KRAM DATA (K2D)
FOCUS GAIN DOWN OUTPUT GAIN
KRAM DATA (K2E)
NOT USED
KRAM DATA (K2F)
NOT USED
CXD2587Q
Register Command
KRAM DATA (K30)

SLED INPUT GAIN (when SFSK = 1 TG up2)
KRAM DATA (K31)
ANTI SHOCK LOW PASS FILTER B
KRAM DATA (K32)
NOT USED
KRAM DATA (K33)
ANTI SHOCK HIGH PASS FILTER B-H
KRAM DATA (K34)
ANTI SHOCK HIGH PASS FILTER B-L
KRAM DATA (K35)
ANTI SHOCK FILTER COMPARATE GAIN
KRAM DATA (K36)
TRACKING GAIN UP2 HIGH CUT FILTER A
KRAM DATA (K37)
TRACKING GAIN UP2 HIGH CUT FILTER B
3 SELECT 0011 0100 0011
– 19 –
KRAM DATA (K38)
TRACKING GAIN UP2 LOW BOOST FILTER A-H
KRAM DATA (K39)
TRACKING GAIN UP2 LOW BOOST FILTER A-L
KRAM DATA (K3A)
TRACKING GAIN UP2 LOW BOOST FILTER B-H
KRAM DATA (K3B)
TRACKING GAIN UP2 LOW BOOST FILTER B-L
KRAM DATA (K3C)
TRACKING GAIN UP PHASE COMPENSATE FILTER A
KRAM DATA (K3D)
TRACKING GAIN UP PHASE COMPENSATE FILTER B
KRAM DATA (K3E)
TRACKING GAIN UP OUTPUT GAIN
KRAM DATA (K3F)
NOT USED
CXD2587Q

Register Command
KRAM DATA (K40)

TRACKING HOLD FILTER INPUT GAIN
KRAM DATA (K41)
TRACKING HOLD FILTER A-H
KRAM DATA (K42)
TRACKING HOLD FILTER A-L
KRAM DATA (K43)
TRACKING HOLD FILTER B-H
KRAM DATA (K44)
TRACKING HOLD FILTER B-L
KRAM DATA (K45)
TRACKING HOLD FILTER OUTPUT GAIN
KRAM DATA (K46)
TRACKING HOLD INPUT GAIN (when THSK = 1 TG up2)
KRAM DATA (K47)
NOT USED
3 SELECT 0011 0100 0100
– 20 –
KRAM DATA (K48)
FOCUS HOLD FILTER INPUT GAIN
KRAM DATA (K49)
FOCUS HOLD FILTER A-H
KRAM DATA (K4A)
FOCUS HOLD FILTER A-L
KRAM DATA (K4B)
FOCUS HOLD FILTER B-H
KRAM DATA (K4C)
FOCUS HOLD FILTER B-L
KRAM DATA (K4D)
FOCUS HOLD FILTER OUTPUT GAIN
KRAM DATA (K4E)
NOT USED
KRAM DATA (K4F)
NOT USED
CXD2587Q
Command Table ($34FX to 3FX)
Address 1 Address 2 Data 1 Data 2 Data 3
Register Command
0 1 0 0 1 1 1 1 1 0 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 — FOCUS BIAS LIMIT
0011 0 1 0 0 1 1 1 1 0 1 FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1 — FOCUS BIAS DATA
0 1 0 0 1 1 1 1 0 0 TV9 TV8 TV7 TV6 TV5 TV4 TV3 TV2 TV1 TV0 TRVSC DATA
Address Data 1 Data 2 Data 3 Data 4
FOCUS SEARCH SPEED/

0 1 0 1 FT1 FT0 FS5 FS4 FS3 FS2 FS1 FS0 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0
VOLTAGE/AUTO GAIN
DTZC/TRACK JUMP
0 1 1 0 TDZC DTZC TJ5 TJ4 TJ3 TJ2 TJ1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0
VOLTAGE/AUTO GAIN
FZSL/SLED MOVE/
0 1 1 1 FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT
Voltage/AUTO GAIN
3 SELECT LEVEL/AUTO GAIN/
1 0 0 0 VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0
DFSW/ (Initialize)
– 21 –
SERIAL DATA READ
1 0 0 1 DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0 0 0 0 0 0 0 0 0
MODE/SELECT
0011 1 0 1 0 0 FBON FBSS FBUP FBV1 FBV0 0 TJD0 FPS1 FPS0 TPS1 TPS0 0 SJHD INBK MTI0 FOCUS BIAS
Operation for MIRR/

1 0 1 1 SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT 0 0 0
DFCT/FOK
TZC/COUT
1 1 0 0 COSS COTS CETZ CETF COT2 COT1 MOT2 0 BTS1 BTS0 MRC1 MRC0 0 0 0 0
BOTTOM/MIRR
1 1 0 1 SFID SFSK THID THSK 0 TLD2 TLD1 TLD0 0 0 0 0 0 0 0 0 SLED FILTER
1 1 1 0 F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD 0 LKIN COIN MDFI MIRI XT1D Filter
1 1 1 1 0 AGG4 XT4D XT2D 0 DRR2 DRR1 DRR0 0 ASFG FTQ LPAS SRO1 0 AGHF ASOT Others
—: Don’t care
CXD2587Q
Command Table
Address Data 1 Data 2 Data 3 Data 4 Data 5 Data 6

Register Command
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
4 Auto sequence 0 1 0 0 AS3 AS2 AS1 AS0 — — — — — — — — — — — — — — — — — — — —
Blind (A, E), 0.18ms 0.09ms 0.05ms 0.02ms

5 Overflow (C) 0 1 0 1 — — — — — — — — — — — — — — — — — — — —
Brake (B) 0.36ms 0.18ms 0.09ms 0.05ms
6 Kick (D) 0 1 1 0 11.6ms 5.8ms 2.9ms 1.45ms — — — — — — — — — — — — — — — — — — — —
Auto sequence
7 (N) track jump 0 1 1 1 32768 16384 8192 4096 2048 1024 512 256 128 64 32 16 8 4 2 1 — — — — — — — —
count
Mode DOUT DOUT VCO

8 1 0 0 0 CDROM WSEL 0 SOCT 0 KSL3 KSL2 1 0 0 0 0 0 0 0 0 0 TXON TXOUT OUTL1 OUTL0
specification Mute ON/OFF SEL1
DSPB OPSL1
1 0 0 1 0 0 0 0 0 0 0 MCSL 0 0 ZDPL ZMUT — — — — — — — — — —
Function ON/OFF 0
9 specification
DSPB OPSL1
1 0 0 1 0 0 0 0 0 0 0 MCSL 0 0 ZDPL ZMUT 0 0 0 DCOF 0 0 — — — —
ON/OFF 1
– 22 –
OPSL2
1 0 1 0 0 0 Mute ATT 0 0 EMPH SMUT AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — —
0
A Audio CTRL
OPSL2
1 0 1 0 0 0 Mute ATT 0 0 EMPH SMUT AD10 AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FMUT LRWO BSBST BBSL
1
B Serial bus 1 0 1 1 SL1 SL0 CPUSR 0 TRMI TRMO MTSL1 MTSL0 0 0 0 0 — — — — — — — — — — — —

CTRL
Spindle servo Gain Gain Gain Gain

C coefficient 1 1 0 0 — — — — — — — — — — — — — — — — — — — —
setting MDP1 MDP0 MDS1 MDS0
Gain
D CLV CTRL 1 1 0 1 0 TB TP 1 1 1 0 0 0 0 0 — — — — — — — — — — — —
CLVS
E CLV MODE 1 1 1 0 CM3 CM2 CM1 CM0 0 0 0 0 0 0 0 0 0 0 0 0 — — — — — — — —

CXD2587Q
§1-3. CPU Command Presets
Command Preset Table ($0X to 34X)

Register Command
FOCUS FOCUS SERVO OFF,

0 0000 0 0 0 0 — — — — — — — — — — — — — — — —
CONTROL 0V OUT
TRACKING TRACKING GAIN UP
1 0001 0 0 0 1 — — — — — — — — — — — — — — — —
CONTROL FILTER SELECT 1
TRACKING TRACKING SERVO OFF
2 0010 0 0 0 0 — — — — — — — — — — — — — — — —
MODE SLED SERVO OFF

Register Command
SLED KICK LEVEL

0011 0 0 0 0 — — — — — — — — — — — — — — — —
(±1 × basic value) (Default)
Address 1 Address 2 Address 3 Data 1 Data 2

3 SELECT
– 23 –
KRAM DATA
0011 0 1 0 0 0 See "Coefficient ROM Preset Values Table".
($3400XX to $344fXX)
—: Don’t care
CXD2587Q
Command Preset Table ($34FX to 3FX)
Address 1 Address 2 Data 1 Data 2 Data 3
Register Command
0 1 0 0 1 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 FOCUS BIAS LIMIT
0011 0 1 0 0 1 1 1 1 0 1 0 0 0 0 0 0 0 0 0 0 FOCUS BIAS DATA
0 1 0 0 1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 TRVSC DATA
Address Data 1 Data 2 Data 3 Data 4
FOCUS SEARCH SPEED/

0 1 0 1 0 1 0 1 1 0 0 0 0 0 1 0 1 1 0 1
VOLTAGE AUTO GAIN
DTZC/TRACK JUMP
0 1 1 0 0 0 0 0 1 1 1 0 0 0 1 0 1 1 1 0
VOLTAGE AUTO GAIN
FZSL/SLED MOVE/
0 1 1 1 0 1 0 1 0 0 0 0 1 0 1 1 1 0 1 0
Voltage/AUTO GAIN
3 SELECT LEVEL/AUTO GAIN/

1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
DFSW/ (Initialize)
– 24 –
SERIAL DATA READ
1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
MODE/SELECT
0011 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 FOCUS BIAS
Operation for MIRR/

1 0 1 1 1 1 1 0 0 0 0 0 0 1 0 1 0 0 0 0
DFCT/FOK
TZC/COUT
1 1 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0
BOTTOM/MIRR
1 1 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 SLED FILTER
1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Filter
1 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 Others
—: Don’t care
CXD2587Q
Reset Initialization
Address Data 1 Data 2 Data 3 Data 4 Data 5 Data 6

Register Command
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
4 Auto sequence 0 1 0 0 0 0 0 0 — — — — — — — — — — — — — — — — — — — —
Blind (A, E),

5 Overflow (C, G) 0 1 0 1 0 1 0 1 — — — — — — — — — — — — — — — — — — — —
Brake (B),
Sled KICK,
6 BRAKE (D), 0 1 1 0 0 1 1 1 — — — — — — — — — — — — — — — — — — — —
KICK (F)
Auto sequence (N)
7 track jump 0 1 1 1 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 — — — — — — — —
count setting
8 MODE 1 0 0 0 0 0 0 0 0 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0
specification
9 Function 1 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 — — — —
specification
A Audio CTRL 1 0 1 0 0 0 1 1 0 0 0 0 0 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0
– 25 –
B Serial bus 1 0 1 1 0 0 1 0 0 1 0 0 0 0 0 0 — — — — — — — — — — — —
CTRL
C Spindle servo 1 1 0 0 0 1 1 0 — — — — — — — — — — — — — — — — — — — —
coefficient setting
D CLV CTRL 1 1 0 1 0 0 0 0 1 1 1 0 0 0 0 0 — — — — — — — — — — — —
E CLV mode 1 1 1 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 — — — — — — — —
CXD2587Q
CXD2587Q
<Coefficient ROM Preset Values Table (1)>
ADDRESS DATA CONTENTS

K00 E0 SLED INPUT GAIN
K01 81 SLED LOW BOOST FILTER A-H
K02 23 SLED LOW BOOST FILTER A-L
K03 7F SLED LOW BOOST FILTER B-H
K04 6A SLED LOW BOOST FILTER B-L
K05 10 SLED OUTPUT GAIN
K06 14 FOCUS INPUT GAIN
K07 30 SLED AUTO GAIN
K08 7F FOCUS HIGH CUT FILTER A
K09 46 FOCUS HIGH CUT FILTER B
K0A 81 FOCUS LOW BOOST FILTER A-H
K0B 1C FOCUS LOW BOOST FILTER A-L
K0C 7F FOCUS LOW BOOST FILTER B-H
K0D 58 FOCUS LOW BOOST FILTER B-L
K0E 82 FOCUS PHASE COMPENSATE FILTER A
K0F 7F FOCUS DEFECT HOLD GAIN
K10 4E FOCUS PHASE COMPENSATE FILTER B
K11 32 FOCUS OUTPUT GAIN
K12 20 ANTI SHOCK INPUT GAIN
K13 30 FOCUS AUTO GAIN
K14 80 HPTZC / Auto Gain HIGH PASS FILTER A
K15 77 HPTZC / Auto Gain HIGH PASS FILTER B
K16 80 ANTI SHOCK HIGH PASS FILTER A
K17 77 HPTZC / Auto Gain LOW PASS FILTER B
K18 00 Fix∗
K19 F1 TRACKING INPUT GAIN
K1A 7F TRACKING HIGH CUT FILTER A
K1B 3B TRACKING HIGH CUT FILTER B
K1C 81 TRACKING LOW BOOST FILTER A-H
K1D 44 TRACKING LOW BOOST FILTER A-L
K1E 7F TRACKING LOW BOOST FILTER B-H
K1F 5E TRACKING LOW BOOST FILTER B-L
K20 82 TRACKING PHASE COMPENSATE FILTER A
K21 44 TRACKING PHASE COMPENSATE FILTER B
K22 18 TRACKING OUTPUT GAIN
K23 30 TRACKING AUTO GAIN
K24 7F FOCUS GAIN DOWN HIGH CUT FILTER A
K25 46 FOCUS GAIN DOWN HIGH CUT FILTER B
K26 81 FOCUS GAIN DOWN LOW BOOST FILTER A-H
K27 3A FOCUS GAIN DOWN LOW BOOST FILTER A-L
K28 7F FOCUS GAIN DOWN LOW BOOST FILTER B-H
K29 66 FOCUS GAIN DOWN LOW BOOST FILTER B-L
K2A 82 FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
K2B 44 FOCUS GAIN DOWN DEFECT HOLD GAIN
K2C 4E FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
K2D 1B FOCUS GAIN DOWN OUTPUT GAIN
K2E 00 NOT USED
K2F 00 NOT USED
∗ Fix indicates that normal preset values should be used.
– 26 –
CXD2587Q
<Coefficient ROM Preset Values Table (2)>

K30 80 SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.)
K31 66 ANTI SHOCK LOW PASS FILTER B
K32 00 NOT USED
K33 7F ANTI SHOCK HIGH PASS FILTER B-H
K34 6E ANTI SHOCK HIGH PASS FILTER B-L
K35 20 ANTI SHOCK FILTER COMPARATE GAIN
K36 7F TRACKING GAIN UP2 HIGH CUT FILTER A
K37 3B TRACKING GAIN UP2 HIGH CUT FILTER B
K38 80 TRACKING GAIN UP2 LOW BOOST FILTER A-H
K39 44 TRACKING GAIN UP2 LOW BOOST FILTER A-L
K3A 7F TRACKING GAIN UP2 LOW BOOST FILTER B-H
K3B 77 TRACKING GAIN UP2 LOW BOOST FILTER B-L
K3C 86 TRACKING GAIN UP PHASE COMPENSATE FILTER A
K3D 0D TRACKING GAIN UP PHASE COMPENSATE FILTER B
K3E 57 TRACKING GAIN UP OUTPUT GAIN
K3F 00 NOT USED
K40 04 TRACKING HOLD FILTER INPUT GAIN
K41 7F TRACKING HOLD FILTER A-H
K42 7F TRACKING HOLD FILTER A-L
K43 79 TRACKING HOLD FILTER B-H
K44 17 TRACKING HOLD FILTER B-L
K45 6D TRACKING HOLD FILTER OUTPUT GAIN
K46 00 TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is accessed with THSK = 1.)
K47 00 NOT USED
K48 02 FOCUS HOLD FILTER INPUT GAIN
K49 7F FOCUS HOLD FILTER A-H
K4A 7F FOCUS HOLD FILTER A-L
K4B 79 FOCUS HOLD FILTER B-H
K4C 17 FOCUS HOLD FILTER B-L
K4D 54 FOCUS HOLD FILTER OUTPUT GAIN
K4E 00 NOT USED
K4F 00 NOT USED
– 27 –
CXD2587Q
§1-4. Description of SENS Signals and Commands
SENS output
Microcomputer serial
register (latching not SENS output Output data length
required)
$0X FZC —
$1X AS (Anti Shock) —
$2X TZC —
$30 to 37 SSTP —
$38 AGOK —
$38 XAVEBSY —
$3904 TE Avrg Reg. 9 bit
$3908 FE Avrg Reg. 9 bit
$390C VC Avrg Reg. 9 bit
$391C TRVSC Reg. 9 bit
$391D FB Reg. 9 bit
$391F RFDC Avrg Reg. 8 bit
$3A FBIAS count STOP —
$3B to 3F SSTP —
$4X XBUSY —
$5X FOK —
$6X, 7X, 8X, 9X 0 —
$AX GFS —
$BX 0 —
$CX COUT frequency division —
$DX 0 —
$EX OV64 —
$FX 0 —
Note) The SENS output can be read from the SQSO pin when SOCT = 0, SL1 = 1 and SL0 = 0.
$38 outputs AGOK during AGT and AGF command settings, and XAVEBSY during AVRG measurement.
SSTP is output in all other cases.
Description of SENS Signals

SENS output
XBUSY Low while the auto sequencer is in operation, high when the operation terminates.
Outputs the same signal as the FOK pin.
FOK
High for "focus OK".
GFS High when the regenerated frame sync is obtained with the correct timing.
Counts the number of tracks with frequeny division ratio set by $B. High when $C is
COUT latched, and toggles each time COUT is counted just for the frequency diviison ratio set
by $B.
Low when the EFM signal is lengthened by 64 channel clock pulses or more after passing
OV64
through the sync detection filter.
– 28 –
CXD2587Q
The meaning of the data for each address is explained below.

$4X commands
Command AS3 AS2 AS1 AS0

CANCEL 0 0 0 0
FOCUS-ON 0 1 1 1
1 TRACK JUMP 1 0 0 RXF
10 TRACK JUMP 1 0 1 RXF
2N TRACK JUMP 1 1 0 RXF
N TRACK MOVE 1 1 1 RXF
RXF = 0 FORWARD
RXF = 1 REVERSE
• When the Focus-on command ($47) is canceled, $02 is sent and the auto sequence is interrupted.
• When the Track jump/move commands ($48 to $4F) are canceled, $25 is sent and the auto sequence is
interrupted.
$5X commands
Auto sequence timer setting
Setting timers: A, E, C, B
Command D3 D2 D1 D0
Blind (A, E), Over flow (C) 0.18ms 0.09ms 0.05ms 0.02ms
Brake (B) 0.36ms 0.18ms 0.09ms 0.05ms
Ex.) D2 = D0 = 1, D3 = D1 = 0 (Initial Reset)
A = E = C = 0.11ms
B = 0.23ms
$6X commands
Auto sequence timer setting
Setting timer: D
Command D3 D2 D1 D0
KICK (D) 11.6ms 5.8ms 2.9ms 1.45ms
Ex.) D3 = 0, D2 = D1 = D0 = 1 (Initial Reset)

D = 10.15ms
$7X commands
Auto sequence track jump/move count setting (N)
Data 1 Data 2 Data 3 Data 4
Command
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Auto sequence track jump 15 14 13 12 11 10
2 2 2 2 2 2 29 28 27 26 25 24 23 22 21 20
count setting
This command is used to set N when a 2N-track jump and an N-track move are executed for auto sequence.
• The maximum track count is 65,535, but note that with a 2N-track jump the maximum track jump count
depends on the mechanical limitations of the optical system.
• The number of tracks jumped is counted according to the COUT signals.
– 29 –
CXD2587Q
$8X commands
Data 1 Data 2 Data 3
Command
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
MODE DOUT DOUT VCO
CDROM WSEL 0 SOCT 0 KSL3 KSL2 1 0
specification Mute ON/OFF SEL1
See the $BX commands.

D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
0 0 0 0 0 0 0 0 TXON TXOUT OUTL1 OUTL0
Command bit C2PO timing Processing

See Timing Chart CDROM mode; average value interpolation and pre-value hold
CDROM = 1
1-1. are not performed.
See Timing Chart Audio mode; average value interpolation and pre-value hold
CDROM = 0
1-1. are performed.
Command bit Processing

DOUT Mute = 1 Digital Out output is muted. (DA output is not muted.)
DOUT Mute = 0 When no other mute conditions are set, Digital Out output is not muted.

DOUT ON/OFF = 1 Digital Out is output from the DOUT pin.
DOUT ON/OFF = 0 Digital Out is not output from the DOUT pin.
Command bit Sync protection window width Application

WSEL = 1 ±26 channel clock∗1 Anti-rolling is enhanced.
WSEL = 0 ±6 channel clock Sync window protection is enhanced.
∗1 In normal-speed playback, channel clock = 4.3218MHz.
– 30 –
CXD2587Q
Command bit
Processing
VCOSEL1 KSL3 KSL2
Multiplier PLL VCO1 is set to normal speed, and the output is 1/1
0 0 0
frequency-divided.
0 0 1
frequency-divided.
0 1 0
frequency-divided.
0 1 1
frequency-divided.
Multiplier PLL VCO1 is set to high speed∗1, and the output is 1/1
1 0 0
frequency-divided.
1 0 1
frequency-divided.
1 1 0
frequency-divided.
1 1 1
frequency-divided.
∗1 Approximately twice the normal speed.

TXON = 0 When CD TEXT data is not demodulated, set TXON to 0.
TXON = 1 When CD TEXT data is demodulated, set TXON to 1.
∗ See "§3-13. CD TEXT Data Demodulation"

TXOUT = 0 Various signals except for CD TEXT is output from the SQSO pin.
TXOUT = 1 CD TEXT data is output from the SQSO pin.
∗ See "§3-13. CD TEXT Data Demodulation"

OUTL1 = 0 WFCK and XPCK are output.
OUTL1 = 1 WFCK and XPCK outputs are low.

OUTL0 = 0 PCMD, BCK, LRCK and EMPH are output.
OUTL0 = 1 PCMD, BCK, LRCK and EMPH outputs are low.
– 31 –
Timing Chart 1-1
LRCK
CDROM = 0
C2PO If C2 Pointer = 1,
Rch 16-bit C2 Pointer Lch 16-bit C2 Pointer data is NG
– 32 –
CDROM = 1
C2PO C2 Pointer for upper 8bits C2 Pointer for lower 8bits C2 Pointer for upper 8bits C2 Pointer for lower 8bits
Rch C2 Pointer Lch C2 Pointer

CXD2587Q
CXD2587Q
$9X commands (OPSL1= 0) ∗ Data 2 D0 and subsequent data are for DF/DAC function settings.

Command
D3 D2 D1 D0 D3 to D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Function DSPB
0 0 0 000 0 0 MCSL 0 0 ZDPL ZMUT — —
specification ON/OFF
OPSL1 Data 5
D3 D2 D1 D0
— — — —
$9X commands (OPSL1= 1) ∗ Data 2 D0 and subsequent data are for DF/DAC function settings.

Command
D3 D2 D1 D0 D3 to D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Function DSPB
0 0 0 000 0 1 MCSL 0 0 ZDPL ZMUT 0 0
specification ON/OFF
OPSL1 Data 5
D3 D2 D1 D0
0 DCOF 0 0

DSPB = 1 Double-speed playback (CD-DSP block)
DSPB = 0 Normal-speed playback (CD-DSP block)

OPSL1 = 1 DCOF can be set.
OPSL1 = 0 DCOF cannot be set.

MCSL = 1 DF/DAC block master clock selection. Crystal = 768Fs (33.8688MHz)
MCSL = 0 DF/DAC block master clock selection. Crystal = 384Fs (16.9344MHz)
– 33 –
CXD2587Q

ZDPL = 1 LMUT and RMUT pins are high when muted.
ZDPL = 0 LMUT and RMUT pins are low when muted.
∗ See "Mute flag output" for the mute flag output conditions.

ZMUT = 1 Zero detection mute is on.
ZMUT = 0 Zero detection mute is off.

DCOF = 1 DC offset is off.
DCOF = 0 DC offset is on.
∗ DCOF can be set when OPSL1 = 1.
∗ Set DC offset to off when zero detection mute is on.
$AX commands (OPSL2 = 0) ∗ Data 2 and subsequent data are for DF/DAC function settings.

Command
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2
Audio CTRL 0 0 Mute ATT 0 0 0 EMPH SMUT AD10
OPSL2

D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 — — — —
$AX commands (OPSL2 = 1) ∗ Data 2 and subsequent data are for DF/DAC function settings.

Command
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2
Audio CTRL 0 0 Mute ATT 0 0 1 EMPH SMUT AD10
OPSL2

D1 D0 D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
AD9 AD8 AD7 AD6 AD5 AD4 AD3 AD2 AD1 AD0 FMUT LRWO BSBST BBSL
– 34 –
CXD2587Q

Mute = 1 CD-DSP block mute is on. 0 data is output from the CD-DSP block.
Mute = 0 CD-DSP block mute is off.

ATT = 1 CD-DSP block output is attenuated (–12dB).
ATT = 0 CD-DSP block output attenuation is off.
Command bit Meaning

OPSL2 = 1 FMUT, LRWO, BSBST and BBSL can be set.
OPSL2 = 0 FMUT, LRWO, BSBST and BBSL cannot be set.

EMPH = 1 De-emphasis is on.
EMPH = 0 De-emphasis is off.
∗ If either the EMPHI pin or EMPH is high, de-emphasis is on.

SMUT = 1 Soft mute is on.
SMUT = 0 Soft mute is off.
∗ If either the SMUT pin or SMUT is high, soft mute is on.
Command bit Meaning

AD10 to 0 Attenuation data.
The attenuation data consists of 11 bits, and is set as follows.
Attenuation data Audio output The attenuation data (AD10 to AD0) consists of 11bits,
400h 0dB and can be set in 1024 different ways in the range of 000h
to 400h.
3FEh –0.0085dB
3FDh –0.0170dB The audio output from 001h to 400h is obtained using the
: following equation.
001h –60.206dB Attenuation data
Audio output = 20log [dB]
000h –∞ 1024
– 35 –
CXD2587Q
Command bit Meaning

FMUT = 1 Forced mute is on.
FMUT = 0 Forced mute is off.
∗ FMUT can be set when OPSL2 = 1.
Command bit Meaning

LRWO = 1 Forced synchronization mode Note)
LRWO = 0 Normal operation.
∗ LRWO can be set when OPSL2 = 1.
Note) Synchronization is performed at the first falling edge of LRCK during reset, so there is normally no need
to set this mode. However, synchronization can be forcibly performed by setting LRWO = 1.

BSBST = 1 Bass boost is on.
BSBST = 0 Bass boost is off.
∗ BSBST can be set when OPSL2 = 1.

BBSL = 1 Bass boost is Max.
BBSL = 0 Bass boost is Mid.
∗ BBSL can be set when OPSL2 = 1.
– 36 –
$BX commands
Data 1 Data 2
Command
D3 D2 D1 D0 D3 D2 D1 D0
Serial bus
SL1 SL0 CPUSR 0 TRM1 TRM0 MTSL1 MTSL0
CTRL
SOCT SL1 SL0 mode The SQSO pin output can be switched to the various
signals by setting the SOCT command of $8X and the SL1
0 0 0 SubQ
and SL0 commands of $BX. Set SQCK to high at the
0 0 1 Peak meter
falling edge of XLAT.
0 1 0 SENS Except for Sub Q and peak meter, the signals are loaded
0 1 1 D to the register when they are set at the falling edge of
1 0 0 SubQ XLAT. Sub Q is loaded to the register with each SCOR,
and Peak meter is loaded when a peak is detected.
1 0 1 A
1 1 0 B
1 1 C
– 37 –
1
—: don't care
XLAT
SQCK
mode A PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 C1F1 C1F2 0 C2F1 C2F2 0 FOK GFS LOCK EMPH ALOCK — — — — — — — —
mode B — — — — — — — — ALOCK C1F1 C1F2 0 C2F1 C2F2 0 FOK GFS LOCK EMPH
mode C PER0 PER1 PER2 PER3 PER4 PER5 PER6 PER7 0 C1F1 C1F2 0 C2F1 C2F2 0 FOK GFS LOCK EMPH
mode D SPOA SPOB 0 0 WFCK SCOR GFS GTOP EMPH FOK LOCK RFCK XRAOF C1F1 C1F2 C2F1 C2F2
Peak meter L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7
CXD2587Q
CXD2587Q
Signal Description
PER0 to 7 RF jitter amount (used to adjust the focus bias). 8-bit binary data in PER0 = LSB, PER7 = MSB.
FOK Focus OK
GFS High when the frame sync and the insertion protection timing match.
GFS is sampled at 460Hz; when GFS is high, a high signal is output. If GFS is low eight
LOCK
consecutive samples, a low signal is output.
EMPH High when the playback disc has emphasis.
GFS is sampled at 460Hz; when GFS is high eight consecutive samples, a high signal is
ALOCK
output. If GFS is low eight consecutive samples, a low signal is output.
SPOA, B SPOA and B pin inputs.
WFCK Write frame clock output.
SCOR High when either subcode sync S0 or S1 is detected.
GTOP High when the sync protection window is open.
RFCK Read frame clock output.
XRAOF Low when the built-in 16K RAM exceeds the ±4 frame jitter margin.
L0 to L7, Peak meter register output. L0 to 7 are the left-channel and R0 to 7 are the right-channel peak
R0 to R7 data. L0 and R0 are LSB.
C1F1 C1F2 C1 correction status C2F1 C2F2 C2 correction status

0 0 No Error 0 0 No Error
1 0 Single Error Correction 1 0 Single Error Correction
1 1 Irretrievable Error 1 1 Irretrievable Error

CPUSR = 1 XLON pin is high.
CPUSR = 0 XLON pin is low.
– 38 –
CXD2587Q
Peak meter
XLAT
SQCK
SQSO L0 L1 L2 L3 L4 L5 L6 L7 R0 R1 R2 R3 R4 R5 R6 R7
(Peak meter)
Setting the SOCT command of $8X to 0 and the SL1 and SL0 commands of $BX to 0 and 1, respectively,
results in peak detection mode. The SQSO output is connected to the peak register. The maximum PCM data
values (absolute value, upper 8bits) for the left and right channels can be read from SQSO by inputting 16
clocks to SQCK. Peak detection is not performed during SQCK input, and the peak register does not change
during readout. This SQCK input judgment uses a retriggerable monostable multivibrator with a time constant
of 270µs to 400µs. The time during which SQCK input is high should be 270µs or less. Also, peak detection is
restarted 270µs to 400µs after SQCK input.
The peak register is reset with each readout (16 clocks input to SQCK).
The maximum value in peak detection mode is detected and held in this status until the next readout. When
switching to peak detection mode, readout should be performed one time initially to reset the peak register.
Peak detection can also be performed for previous value hold and average value interpolation data.
Traverse monitor count value setting

These bits are set when monitoring the traverse condition of the SENS output according to the COUT
frequency division.

TRM1 TRM0
0 0 1/64 frequency division
Monitor output switching

The monitor output can be switched to the various signals by setting the MTSL1 and MTSL0 commands of $B.
Output data
Symbol
XUGF XPCK GFS C2PO
Command bit
MTSL1 MTSL0
0 0 XUGF XPCK GFS C2PO
0 1 MNT1 MNT0 MNT3 C2PO
1 0 RFCK XPCK XROF GTOP
– 39 –
CXD2587Q
$CX commands
Command D3 D2 D1 D0
Gain Gain Gain Gain
Servo coefficient setting
MDP1 MDP0 MDS1 MDS0
Gain
CLV CTRL ($DX)
CLVS
• CLV mode gain setting: GCLVS

Gain Gain Gain
GCLVS
MDS1 MDS0 CLVS
0 0 0 –12dB
0 0 1 –6dB
0 1 0 –6dB
0 1 1 0dB
1 0 0 0dB
1 0 1 +6dB
• CLVP mode gain setting: GMDP: GMDS

Gain Gain Gain Gain
GMDP GMDS
MDP1 MDP0 MDS1 MDS0
0 0 –6dB 0 0 –6dB
0 1 0dB 0 1 0dB
1 0 +6dB 1 0 +6dB
$DX commands
Command
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
Gain
CLV CTRL 0 TB TP 1 1 1 0 0 0 0 0
CLVS
See the $CX commands.
Command bit Description

TB = 0 Bottom hold at a cycle of RFCK/32 in CLVS mode.
TB = 1 Bottom hold at a cycle of RFCK/16 in CLVS mode.
TP = 0 Peak hold at a cycle of RFCK/4 in CLVS mode.
TP = 1 Peak hold at a cycle of RFCK/2 in CLVS mode.
– 40 –
CXD2587Q
$EX commands
Command
D3 D2 D1 D0 D3 D2 D1 D0 D3 D2 D1 D0
CLV mode CM3 CM2 CM1 CM0 0 0 0 0 0 0 0 0
Data 4
D3 D2 D1 D0
0 0 0 0
Command bit
Mode Description
CM3 CM2 CM1 CM0
0 0 0 0 STOP Spindle stop mode.∗1
1 0 0 0 KICK Spindle forward rotation mode.∗1
Spindle reverse rotation mode. Valid only when LPWR = 0
in any mode.∗1
1 0 1 0 BRAKE
Rough servo mode. When the RF-PLL circuit isn't locked,

1 1 1 0 CLVS this mode is used to pull the disc rotations within the RF-
PLL capture range.
1 1 1 1 CLVP PLL servo mode.
Automatic CLVS/CLVP switching mode.
0 1 1 0 CLVA
Used for normal playback.
∗1 See Timing Charts 1-2 and 1-3.
Timing Chart 1-2
KICK BRAKE STOP
H Z
MDP MDP MDP Z
Z L
KICK BRAKE STOP
Timing Chart 1-3
n · 236 (ns) n = 0 to 31
Acceleration
MDP Z
132kHz
7.6µs Deceleration
– 41 –
CXD2587Q
§2. Subcode Interface
In the CXD2587Q, only SubQ can be readout.

The subcodes P and R to W cannot be readout.
Sub Q can be read out after checking CRC of the 80 bits in the subcode frame.
Sub Q can be read out from the SQSO pin by inputting 80 clock pulses to the SQCK pin when SCOR comes
correctly and CRCF is high.
§2-1. 80-bit Sub Q Readout

Fig. 2-1 shows the peripheral block of the 80-bit Sub Q register.
• First, Sub Q, regenerated at one bit per frame, is input to the 80-bit serial/parallel register and the CRC check
circuit.
• 96-bit Sub Q is input, and if the CRC is OK, it is output to SQSO with CRCF = 1. In addition, 80 bits are
loaded into the parallel/serial register.
When SQSO goes high 400µs (monostable multivibrator time constant) or more after subcode readout, the
CPU determines that the new data (which passed the CRC check) has been loaded.
• The CRCF reset is performed by inputting SQCK. When the subcode data is discontinuous after track jump,
etc. CRCF is reset by inputting SQCK. Then, if CRCF =1, the CPU determines that the new data has been
loaded.
• When the 80-bit data is loaded, the order of the MSB and LSB is inverted within each byte. As a result,
although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.
• Once the 80-bit data load is confirmed, SQCK is input so that the data can be read.
The SQCK input is detected, and the retriggerable monostable multivibrator is reset while the input is low.
• The retriggerable monostable multivibrator has a time constant from 270 to 400µs. When the duration when
SQCK is high is less than this time constant, the monostable multivibrator is kept reset; during this interval,
the serial/parallel register is not loaded into the parallel/serial register.
• While the monostable multivibrator is being reset, data cannot be loaded in the 80-bit parallel/serial register.
In other words, while reading out with a clock cycle shorter than this time constant, the register will not be
rewritten by CRCOK and others. (See Timing Chart 2-2.)
• The high and low intervals for SQCK should be between 750ns and 120µs.
– 42 –
Block Diagram 2-1
(AFRAM) (ASEC) (AMIN) ADDRS CTRL
SIN
SUBQ 80bit S/P Register
A B C D E F G H
8 8 8 8 8 8 8 8 8
Order
Inversion
H G F E D C B A SO
80bit P/S Register
SI
LD
LD
LD
LD
LD
LD
LD
LD
– 43 –
SUBQ
CRCC Mono/Multi SHIFT

SHIFT SQCK
CRCF
SQSO
Mix
CXD2587Q
Timing Chart 2-2
1 2 3 91 92 93 94 95 96 97 98
1 2 3
WFCK
Order
SCOR Inversion
Determined by mode
SQSO CRCF1 L CRCF2
80 Clock
SQCK
Registere load forbidder
– 44 –
Mono/multi (Internal)
270 to 400µs when SQCK = high.

750ns to 120µs
SQCK
SQSO CRCF ADR0 ADR1 ADR2 ADR3 CTL0 CTL1 CTL2 CTL3
300ns max
CXD2587Q
CXD2587Q
§3. Description of Other Functions
§3-1. Channel Clock Regeneration by the Digital PLL Circuit

• The channel clock is necessary for demodulating the EFM signal regenerated by the optical system.
Assuming T as the channel clock cycle, the EFM signal is modulated in an integer multiple of T from 3T to
11T. In order to read the information in the EFM signal, this integer value must be read correctly. As a result,
T, that is the channel clock, is necessary.
In an actual player, a PLL is necessary for regenerating the channel clock because the fluctuation in the
spindle rotation alters the width of the EFM signal pulses.
The block diagram of this PLL is shown in Fig. 3-1.

The CXD2587Q has a built-in three-stage PLL.
• The first-stage PLL regenerates the high-frequency clock needed by the second-stage digital PLL.
• The second-stage PLL is a digital PLL that regenerates the actual channel clock.
Block Diagram 3-1
X'tal OSC
1/M
Phase comparator
PCO
XTSL
1/N
FILI
FILO
1/K CLTV
VCO1
(KSL3, 2)
VCOSEL1
Digital PLL
RFPLL
CXD2587Q
– 45 –
CXD2587Q
§3-2. Frame Sync Protection

• In normal-speed playback, a frame sync is recorded approximately every 136µs (7.35kHz). This signal is
used as a reference to recognize the data within a frame. Conversely, if the frame sync cannot be
recognized, the data is processed as error data because the data cannot be recognized. As a result,
recognizing the frame sync properly is extremely important for improving playability.
• In the CXD2587Q, window protection and forward protection/backward protection have been adopted for
frame sync protection. These functions achieve very powerful frame sync protection. There are two window
widths; one for cases where a rotational disturbance affects the player and the other for cases where there is
no rotational disturbance (WSEL = 0/1). In addition, the forward protection counter is fixed to 13, and the
backward protection counter to 3. Concretely, when the frame sync is being played back normally and then
cannot be detected due to scratches, a maximum of 13 frames are inserted. If the frame sync cannot be
detected for 13 frames or more, the window opens to resynchronize the frame sync.
In addition, immediately after the window opens and the resynchronization is executed, if a proper frame
sync cannot be detected within 3 frames, the window opens immediately.
§3-3. Error Correction

• In the CD format, one 8-bit data contains two error correction codes, C1 and C2. For C1 correction, the code
is created with 28-byte information and 4-byte C1 parity.
For C2 correction, the code is created with 24-byte information and 4-byte parity.
Both C1 and C2 are Reed Solomon codes with a minimum distance of 5.
• The CXD2587Q's SEC strategy uses powerful frame sync protection and C1 and C2 error correction to
achieve high playability.
• The correction status can be monitored externally. See Table 3-2.
• When the C2 pointer is high, the data in question was uncorrectable. Either the pre-value was held or an
average value interpolation was made for the data.
MNT3 MNT1 MNT0 Description

0 0 0 No C1 errors
0 0 1 One C1 error corrected
0 1 1 C1 correction impossible
1 0 0 No C2 errors
1 0 1 One C2 error corrected
1 1 0 C2 correction impossible
Table 3-2.
– 46 –
CXD2587Q
Timing Chart 3-3
Normal-speed PB
t = Dependent on error
condition
MNT3
C1 correction C2 correction
MNT1
MNT0
Strobe Strobe
§3-4. DA Interface
• The CXD2587Q's DA interface is as follows:
Interface includes 48 cycles of the bit clock within one LRCK cycle, and is MSB first.
When LRCK is high, the data is for the left channel.
– 47 –
Timing Chart 3-4
48-bit slot Normal-Speed Playback
LRCK
(44.1k)
1 2 3 4 5 6 7 8 9 10 11 12 24
BCK
(2.12M)
PCMD R0 Lch MSB (15) L14 L13 L12 L11 L10 L9 L8 L7 L6 L5 L4 L3 L2 L1 L0 RMSB
48-bit slot Double-Speed Playback
LRCK
– 48 –
(88.2k)
1 2 24
BCK
(4.23M)
PCMD Lch MSB (15) Rch MSB
R0 L0
CXD2587Q
CXD2587Q
§3-5. Digital Out

There are three Digital Out: the type 1 format for broadcasting stations, the type 2 form 1 format for home use,
and the type 2 form 2 format for the manufacture of software.
The CXD2587Q supports type 2 form 1.
Sub Q data which are matched twice in succession after a CRC check are input to the first four bits (bits 0 to 3)
of the channel status.
Digital Out C bit
0 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15
From sub Q
0 0 0 0 0 1 0 0 0 0 0 0 0
ID0 ID1 COPY Emph
16 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0 0
32
48
176
Bits 0 to 3 Sub Q control bits that matched twice with CRCOK
Table 3-5.
§3-6. Servo Auto Sequence

This function performs a series of controls, including auto focus and track jumps. When the auto sequence
command is received from the CPU, auto focus, 1-track jump, 2N-track jump and N-track move are executed
automatically.
The commands which enable transfer to the CXD2587Q during the execution of auto sequence are $4X to
$EX.
When CLOK goes from low to high while XBUSY is low, XBUSY does not become high for a maximum of
100µs after that point.
– 49 –
CXD2587Q
(a) Auto focus ($47)

Focus search-up is performed, FOK and FZC are checked, and the focus servo is turned on.
If $47 is received from the CPU, the focus servo is turned on according to Fig. 3-6. The auto focus starts with
focus search-up, and note that the pickup should be lowered beforehand (focus search down). In addition,
blind E of register 5 is used to eliminate FZC chattering. Concretely, the focus servo is turned on at the falling
edge of FZC after FZC has been continuously high for a longer time than E.
Auto focus
Focus search up
FOK = H
NO
YES
(Check whether FZC is continuously high

for the period of time E set with register 5.)
FZC = H
NO
YES
FZC = L
NO
YES
Focus servo ON
END
Fig. 3-6-(a). Auto Focus Flow Chart
– 50 –
CXD2587Q
$47latch
XLAT
FOK
(FZC)
BUSY
Command for
Blind E
DSSP
$03 $08
Fig. 3-6-(b). Auto Focus Timing Chart
(b) Track jump

1, 10 and 2N-track jumps are performed respectively. Always use this when the focus, tracking, and sled
servos are on. Note that tracking gain-up and braking-on should be sent beforehand because they are not
involved in this sequence.
• 1-track jump
When $48 ($49 for REV) is received from the CPU, a FWD (REV) 1-track jump is performed in accordance
with Fig. 3-7. Set blind A and brake B with register 5.
• 10-track jump
When $4A ($4B for REV) is received from the CPU, a FWD (REV) 10-track jump is performed in accordance
with Fig. 3-8. The principal difference from the 1-track jump is to kick the sled. In addition, after kicking the
actuator, when 5 tracks have been counted through COUT, the brake is applied to the actuator. Then, when
the actuator speed is found to have slowed up enough (determined by the COUT cycle becoming longer than
the overflow C set with register 5), the tracking and sled servos are turned on.
• 2N-track jump
When $4C ($4D for REV) is received from the CPU, a FWD (REV) 2N-track jump is performed in accordance
with Fig. 3-9. The track jump count N is set with register 7. Although N can be set to 216 tracks, note that the
setting is actually limited by the actuator. COUT is used for counting the number of jumps.
Although the 2N-track jump basically follows the same sequence as the 10-track jump, the one difference is
that after the tracking servo is turned on, the sled continues to move only for "D", set with register 6.
• N-track move
When $4E ($4F for REV) is received from the CPU, a FWD (REV) N-track move is performed in accordance
with Fig. 3-10. N can be set to 216 tracks. COUT is used for counting the number of jumps. The N-track move
is executed only by moving the sled, and is therefore suited for moving across several thousand to several
ten-thousand tracks.
– 51 –
CXD2587Q
Track
Track FWD kick (REV kick for

sled servo OFF REV jump)
WAIT
(Blind A)
COUT =
NO
YES
Track REV (FWD kick for
kick REV jump)
WAIT
(Brake B)
Track, sled
servo ON
END
Fig. 3-7-(a). 1-Track Jump Flow Chart
$48 (REV = $49) latch
XLAT
COUT
BUSY
Blind A Brake B
Command for
DSSP $28 ($2C) $2C ($28) $25
Fig. 3-7-(b). 1-Track Jump Timing Chart
– 52 –
CXD2587Q
10 Track
Track, sled
FWD kick
WAIT
(Blind A)
COUT = 5 ?
NO (Counts COUT × 5)
YES
Track, REV
kick
C = Overflow ?
NO (Check whether the COUT cycle
is longer than overflow C.)
YES
Track, sled
servo ON
END
Fig. 3-8-(a). 10-Track Jump Flow Chart
$4A (REV = $4B) latch
XLAT
COUT
BUSY
Blind A COUT 5 count

Overflow C
Command for
DSSP $2A ($2F) $2E ($2B) $25
Fig. 3-8-(b). 10-Track Jump Timing Chart
– 53 –
CXD2587Q
2N Track
Track, sled
FWD kick
WAIT
(Blind A)
COUT = N
NO
YES
Track REV
kick
C = Overflow
NO
YES
Track servo
ON
WAIT
(Kick D)
Sled servo
ON
END
Fig. 3-9-(a). 2N-Track Jump Flow Chart
$4C (REV = $4D) latch
XLAT
COUT
BUSY
Blind A COUT N count Overflow C Kick D

Command for
DSSP $2A ($2F) $2E ($2B) $26 ($27) $25
Fig. 3-9-(b). 2N-Track Jump Timing Chart

– 54 –
CXD2587Q
N Track move
Track servo OFF

Sled FWD kick
WAIT
(Blind A)
COUT = N
NO
YES
Track, sled
servo OFF
END
END
Fig. 3-10-(a). N-Track Move Flow Chart
$4E (REV = $4F) latch
XLAT
COUT
BUSY
Blind A COUT N count
Command for
DSSP $22 ($23) $20
Fig. 3-10-(b). N-Track Move Timing Chart
– 55 –
CXD2587Q
§3-7. Digital CLV

Fig. 3-11 shows the block diagram. Digital CLV outputs MDS error and MDP error signals with PWM, with the
sampling frequency increased up to 130kHz during normal-speed playback in CLVS, CLVP and other modes.
In addition, the digital spindle servo gain is variable.
Digital CLV
CLVS U/D MDS Error MDP Error
Measure Measure
Oversampling
CLV P/S 2/1 MUX Filter-1
Gain Gain
MDS MDP
1/2
MUX
CLV P/S
Oversampling
Filter-2
Noise Shape
KICK, BRAKE, STOP Modulation
MDP
CLVS U/D : Up/down signal from CLVS servo

MDS error: Frequency error for CLVP servo
MDP error: Phase error for CLVP servo
Fig. 3-11. Block Diagram
– 56 –
CXD2587Q
§3-8. CD-DSP Block Playback Speed

In the CXD2587Q, the following playback modes can be selected through different combinations of the crystal,
XTSL pin and the DSPB command of $9X.
CD-DSP block playback speed
Crystal XTSL DSPB CD-DSP block playback speed

768Fs 0 1 4×∗1
768Fs 1 0 1×
768Fs 1 1 2×
384Fs 0 0 1×
384Fs 0 1 2×
384Fs 1 1 1×∗2
Fs = 44.1kHz.
∗1 In 4× speed playback, the timer value for the auto sequence is halved.
∗2 Low power consumption mode. The CD-DSP processing speed is halved, allowing power consumption
to be reduced.
§3-9. DAC Block Playback Speed

The operation speed for the DAC block is determined by the crystal and the MCSL command of $9X
regardless of the CD-DSP operating conditions noted above. This allows the playback modes for the DAC and
CD-DSP blocks to be set independently.
1-bit DAC block playback speed
Crystal MCSL DAC block playback speed

768Fs 1 1×
768Fs 0 2×
384Fs 0 1×
Fs = 44.1kHz.
– 57 –
CXD2587Q
§3-10. Description of DAC Block Functions
Zero data detection

When the condition where the lower 4 bits of the input data are DC and the remaining upper bits are all "0" or
all "1" has continued about for 300ms, zero data is detected. Zero data detection is performed independently
for the left and right channels.
Mute flag output

The LMUT and RMUT pins go active when any one of the following conditions is met.
The polarity can be selected with the ZDPL command of $9X.
• When zero data is detected
• When a high signal is input to the SYSM pin
• When the SMUT command of $AX is set
Attenuation operation
Assuming attenuation data X1, X2 and X3 (X1 > X3 > X2), the corresponding audio outputs are Y1, Y2 and
Y3 (Y1 > Y3 > Y2). First, X1 is sent, followed by X2. If X2 is sent before X1 reaches Y1 (A in the figure), X1
continues approaching Y2. Next, if X3 is sent before X1 reaches Y2 (B or C in the figure), X1 then
approaches Y3 from the value (B or C in the figure) at that point.
0dB
3FF (H)
A
Y1
B
Y3
Y2
–∞
000 (H)
23.2 [ms]
– 58 –
CXD2587Q
DAC block mute operation

Soft mute
Soft mute results and the input data is attenuated to zero when any one of the following conditions is met.
• When attenuation data of "000" (high) is set
• When the SMUT command of $AX is set to 1
• When a high signal is input to the SYSM input pin
Soft mute off Soft mute on Soft mute off
0dB
– ∞dB
23.2 [ms] 23.2 [ms]
Forced mute
Forced mute results when the FMUT command of $AX is set to 1.
Forced mute fixes the PWM output that is input to the LPF block to low.
∗ When setting FMUT, set OPSL2 to 1. (See the $AX commands.)
Zero detection mute

Forced mute is applied when the ZMUT command of $9X is set to 1 and the zero data is detected for the
left and right channels.
(See "Zero data detection".)
When the ZMUT command of $9X is set to 1, the forced mute is applied even if the mute flag output
condition is met. When the zero detection mute is on, set the DCOF command of $9X to 1.
– 59 –
CXD2587Q
LRCK Synchronization
Synchronization is performed at the first falling edge of the LRCK input during reset.
After that, synchronization is lost when the LRCK input frequency changes and resynchronization must be
performed.
The LRCK input frequency changes when the master clock of the LSI is switched and the playback speed
changes such as the following cases.
• When the XTSL pin switches between high and low
• When the DSPB command of $9X setting changes
• When the MCSL command of $9X setting changes
LRCK switching may also be performed if there are other ICs between the CD-DSP block and the DAC
block. Resynchronization must be performed in this case as well.
For resynchronization, set the LRWO command of $AX to 1, wait for one LRCK cycle or more, and then set
LRWO to 0.
∗ When setting LRWO, set OPSL2 to 1. (See the $AX commands.)
Digital Bass Boost

Bass boost without external parts is possible using the built-in digital filter. The boost strength has two levels:
Mid. and Max. BSBST and BBSL of address A are used for the setting.
See Graph 3-12 for the digital bass boost frequency response.
10.00
8.00
Normal
6.00
DBB MID
4.00
DBB MAX
2.00
0.00
[dB]
–2.00
–4.00
–6.00
–8.00
–10.00
–12.00
–14.00
10 30 100 300 1k 3k 10k 30k
Digital Bass Boost Frequency Response [Hz]
Graph 3-12.
– 60 –
CXD2587Q
§3-11. LPF Block

The CXD2587Q contains an initial-stage secondary active LPF with numerous resistors and capacitors and an
operational amplifier with reference voltage.
The resistors and capacitors are attached externally, allowing the cut-off frequency fc to be determined flexibly.
The reference voltage (VC) is (AVDD – AVSS) × 0.43.
The LPF block application circuit is shown below.

In this circuit, the cut-off frequency is fc ≈ 40kHz.
The external capacitors' values when fc = 30kHz and 50kHz are noted below as a reference.
The resistors' values do not change at this time.
• When fc ≈ 30kHz:
C1 = 200pF, C2 = 910pF
• When fc ≈ 50kHz:
C1 = 120pF, C2 = 560pF
LPF Block Application Circuit
AOUT1 (2) 12k
C2
680p
AIN1 (2) 12k

Vc
C1 12k
150p
Analog out
LOUT1 (2)
Fig. 3-13. LPF External Circuit
– 61 –
CXD2587Q
§3-12. Asymmetry Compensation

Fig. 3-14 shows the block diagram and circuit example.
CXD2587Q
ASYO
R1
RFAC
R1
R2 R1
ASYI
R1
BIAS
R1 = 2
R2 5
Fig. 3-14. Asymmetry Compensation Application Circuit
– 62 –
CXD2587Q
§3-13. CD TEXT Data Demodulation

• In order to demodulate the CD TEXT data, set the command $8 Data 6 D3 TXON to 1.
It requires 26.7ms (max.) to demodulate the CD TEXT data correctly after TXON is set to 1.
• The CD TEXT data is output by switching the SQSO pin with the command. The CD TEXT data output is
enabled by setting the command $8 Data 6 D2 TXOUT to 1. To read data, the readout clock should be input
to SQCK.
• The readable data are the CRC counting results for the each pack and the CD TEXT data (16 bytes) except
for CRC data.
• When the CD TEXT data is read, the order of the MSB and LSB is inverted within each byte. As a result,
although the sequence of the bytes is the same, the bits within the bytes are now ordered LSB first.
• Data which can be stored in the LSI is 1 packet (4 packs).
CD TEXT
Decoder
Subcode
Decoder SQCK
SQSO
TXOUT
Fig. 3-15. Block Diagram of CD TEXT Demodulation Circuit
– 63 –
SCOR
Subcode Q Data 4 bits 4 bits 16 Bytes 16 Bytes 16 Bytes 16 Bytes
SQSO CRCF CRC 0 Pack1 Pack2 Pack3 Pack4 CRCF
80 clocks 520 clocks
SQCK
TXOUT
(command)
– 64 –
CRC Data ID1 (Pack1) ID2 (Pack1) ID3 (Pack1)
LSB MSB LSB MSB LSB

CRC CRC CRC CRC
SQSO 4 3 2 1
0 0 0 0 S2 R2 W1 V1 U1 T1 S1 R1 U3 T3 S3 R3 W2 V2 U2 T2 W4 V4 U4 T4 S4
SQCK
TXOUT
(command)
Fig. 3-16. CD TEXT DATA Timing Chart

CXD2587Q
CXD2587Q
§4. Description of Servo Signal Processing System Functions and Commands
§4-1. General Description of the Servo Signal Processing System (VDD: Supply voltage)
Focus servo
Sampling rate: 88.2kHz (when MCK = 128Fs)
Input range: 0.3VDD to 0.7VDD
Output format: 7-bit PWM
Other: Offset cancel
Focus bias adjustment
Focus search
Gain-down function
Defect countermeasure
Auto gain control
Tracking servo
Sampling rate: 88.2kHz (when MCK = 128Fs)
Other: Offset cancel
E:F balance adjustment
Track jump
Gain-up function
Defect countermeasure
Drive cancel
Auto gain control
Vibration countermeasure
Sled servo
Sampling rate: 345Hz (when MCK = 128Fs)
Other: Sled move
FOK, MIRR, DFCT signal generation

RF signal sampling rate: 1.4MHz (when MCK = 128Fs)
Input range: 0.43VDD to VDD
Other: RF zero level automatic measurement
– 65 –
CXD2587Q
§4-2. Digital Servo Block Master Clock (MCK)

The clock with the 2/3 frequency of the crystal is supplied to the digital servo block.
The XT4D and XT2D command can be set with D13 and D12 of $3F, and the XT1D command can be set with
D1 of $3E. (Default = 0)
The digital servo block is designed with an MCK frequency of 5.6448MHz (128Fs) as typical.
Mode XTLI Input to servo XTSL XT4D XT2D XT1D Frequency division ratio MCK
1 384Fs 256Fs ∗ ∗ ∗ 1 1 256Fs
2 384Fs 256Fs ∗ ∗ 1 0 1/2 128Fs
3 384Fs 256Fs 0 0 0 0 1/2 128Fs
4 768Fs 512Fs ∗ ∗ ∗ 1 1 512Fs
5 768Fs 512Fs ∗ ∗ 1 0 1/2 256Fs
6 768Fs 512Fs ∗ 1 0 0 1/4 128Fs
7 768Fs 512Fs 1 0 0 0 1/4 128Fs
Fs = 44.1kHz, ∗: Don’t care
Table 4-1.
§4-3. AVRG (Average) Measurement and Compensation

The CXD2587Q has a circuit that measures the averages of RFDC, VC, FE and TE and a circuit that
compensates these signals to control the servo effectively.
AVRG measurement and compensation is necessary to initialize the CXD2587Q, and is able to cancel the
offset.
The level applied to the VC, FE, RFDC and TE pins can be measured by setting D15 (VCLM), D13 (FLM), D11
(RFLM) and D4 (TCLM) of $38 respectively to 1.
AVRG measurement takes the level applied to each analog input pin as the average of 256 samples, and then
loads each value into the AVRG register.
AVRG measurement requires approximately 2.9ms to 5.8ms (when MCK = 128Fs) after the command is
received.
During AVRG measurement, if the upper 8 bits of the command register are 38 (Hex), the completion of AVRG
measurement operation can be confirmed through the SENS pin. (See Timing Chart 4-2.)
XLAT
2.9 to 5.8ms
SENS
(= XAVEBSY)
Max. 1µs AVRG measurement completed
Timing Chart 4-2.
– 66 –
CXD2587Q
<Measurement>
• VC AVRG
The offset can be canceled by measuring the VC level which is the center voltage for the system and using
that value to apply compensation to each input error signal.
• FE AVRG
The FE signal DC level is measured. In addition, compensation is applied to the FZC comparator level output
from the SENS pin during FCS SEARCH (focus search) using these measurement results.
• TE AVRG
The TE signal DC level is measured.
• RF AVRG
The MIRR, DFCT and FOK signals are generated from the RF signal. Since the FOK signal is generated by
comparing the RF signal at a certain level, it is necessary to establish a zero level which becomes the
comparator level reference. Therefore, the RF signal is measured before playback, and is compensated to
take this level as the zero level.
An example of sending AVRG measurement and compensation commands is shown below.

(Example) $380800 (RF AVRG measurement on)
$382000 (FE AVRG measurement on)
$380010 (TE AVRG measurement on)
$388000 (VC AVRG measurement on)
(Complete each AVRG measurement before starting the next.)
$38140A (RFLC, FLC0, FLC1 and TLC1 commands on)
(The required compensation should be turned on together; see Fig. 4-3.)
An interval of 5.8ms (when MCK = 128Fs) or more must be maintained between each command, or the SENS
pin must be monitored to confirm that the previous command has been completed before the next AVRG
command is sent.
<Compensation>
See Fig. 4-3 for the contents of each compensation below.
• RFLC
The difference by which the RF signal exceeds the RF AVRG value is input to the RF In register.
(00 is input when the RF signal is lower than the RF AVRG value.)
• TCL0
The value obtained by subtracting the VC AVRG value from the TE signal is input to the TRK In register.
• TCL1
The value obtained by subtracting the TE AVRG value from the TE signal is input to the TRK In register.
• VCLC
The value obtained by subtracting the VC AVRG value from the FE signal is input to the FCS In register.
• FLC1
The value obtained by subtracting the FE AVRG value from the FE signal is input to the FCS In register.
• FLC0
The value obtained by subtracting the FE AVRG value from the FE signal is input to the FZC register.
– 67 –
CXD2587Q
§4-4. E:F Balance Adjustment Function

When the disc is rotated with the laser on, and with the FCS (focus) servo on via FCS Search (focus search),
the traverse waveform appears in the TE signal due to disc eccentricity.
In this condition, the low-frequency component can be extracted from the TE signal using the built-in TRK hold
filter by setting D5 (TBLM) of $38 to 1.
The extracted low-frequency component is loaded into the TRVSC register as a digital value, and the TRVSC
register value is established when TBLM returns to 0.
Next, setting D2 (TLC2) of $38 to 1 compensates TE and SE values with the TRVSC register value
(subtraction), resulting the E:F balance offset to be adjusted. (See Fig. 4-3.)
§4-5. FCS Bias (Focus Bias) Adjustment Function

The FBIAS register value can be added to the FCS servo filter input by setting D14 (FBON) of $3A to 1. (See
Fig. 4-3.)
When the FBIAS register value is set when D11 = 0 and D10 = 1 with $34F, data can be written using the 9-bit
value of D9 to D1 (D9: MSB).
In addition, the RF jitter can be monitored by setting the SOCT command of $8 to 1. (See "DSP Block Timing
Chart".)
The FBIAS register can be used as a counter by setting D13 (FBSS) of $3A to 1. The FBIAS register functions
as an up counter when D12 (FBUP) of $3A = 1, and as a down counter when D12 (FBUP) of $3A = 0.
The number of up and down steps can be changed by setting D11 and D10 (FBV1 and FBV0) of $3A.
When using the FBIAS register as a counter, the counter stops if the FBIAS value and the value set beforehand
in FBL9 to 1 of $34 match. Also, if the upper 8 bits of the command register are $3A at this time, SENS
becomes high and the counter stop can be monitored.
Here, assume the FBIAS setting value FB9 to 1

and the FBIAS LIMIT value FBL9 to 1 like status
A. For example, if command registers FBUP = 0,
FBV1 = 0, FBV0 = 0 and FBSS = 1 are set from
A B C
this status, down count starts from status A and
FBIAS setting value (FB9 to 1) approaches the set LIMIT value. When the
FBIAS value matches FBL9 to 1, the counter
stops and the SENS pin goes to high. Note that
the up/down counter counts at each sampling
cycle of the focus servo filter. The number of
steps by which the count value changes can be
selected from 1, 2, 4 or 8 steps by FBV1 and
FBV0. When converted to FE input, 1 step
LIMIT value (FBL9 to 1)
corresponds to 1/512 × VDD × 0.4.
A: Register mode
SENS pin B: Counter mode
C: Counter mode (when stopped)
– 68 –
RFDC from A/D To RF In register
RF AVRG –
register RFLC
SE from A/D To SLD In register
– – –
TLC0 · TLD0 TLC1 · TLD1 TLC2 · TLD2
TE from A/D To TRK In register
– – –
TLC0
VC AVRG TE AVRG TRVSC

register register TLC1 register TLC2
– 69 –
VCLC
FE from A/D – To FCS In register
FE AVRG – FBIAS
register FLC1 register FBON
FLC0
– To FZC register
Fig. 4-3.
CXD2587Q
CXD2587Q
§4-6. AGCNTL (Automatic Gain Control) Function

The AGCNTL function automatically adjusts the filter internal gain in order to obtain the appropriate gain with
the servo loop. AGCNTL not only copes with the sensitivity variation of the actuator and photo diode, etc., but
also obtains the optimal gain for each disc.
The AGCNTL command is sent when each servo is turned on. During AGCNTL operation, if the upper 8 bits of
the command register are 38 (Hex), the completion of AGCNTL operation can be confirmed through the SENS
pin. (See Timing Chart 4-4 and "Description of SENS Signals".)
Setting D9 and D8 of $38 to 1 set FCS (focus) and TRK (tracking) respectively to AGCNTL operation.
Note) During AGCNTL operation, each servo filter gain must be normal, and the anti-shock circuit (described
hereafter) must be disabled.
XLAT
Max. 11.4µs
SENS
(= AGOK)
AGCNTL completion
Timing Chart 4-4.
Coefficient K13 changes for AGF (focus AGCNTL) and coefficients K23 and K07 change for AGT (tracking
AGCNTL) due to AGCNTL.
These coefficients change from 01 to 7F (Hex), and they must also be set within this range when written
externally.
After AGCNTL operation has completed, these coefficient values can be confirmed by reading them out from
the SENS pin with the serial readout function (described hereafter).
AGCNTL related settings

The following settings can be changed with $35, $36 and $37.
FG6 to FG0; AGF convergence gain setting, effective setting range: 00 to 57 (Hex)
TG6 to TG0; AGT convergence gain setting, effective setting range: 00 to 57 (Hex)
AGS; Self-stop on/off
AGJ; Convergence completion judgment time
AGGF; Internally generated sine wave amplitude (AGF)
AGGT; Internally generated sine wave amplitude (AGT)
AGV1; AGCNTL sensitivity 1 (during rough adjustment)
AGV2; AGCNTL sensitivity 2 (during fine adjustment)
AGHS; Rough adjustment on/off
AGHT; Fine adjustment time
Note) Converging servo loop gain values can be changed with the FG6 to 0 and TG6 to 0 setting values. In
addition, these setting values must be within the effective setting range. The default settings aim for 0
dB at 1kHz. However, since convergence values vary according to the characteristics of each
constituent element of the servo loop, FG and TG values should be set as necessary.
– 70 –
CXD2587Q
AGCNTL and default operation have two stages.

In the first stage, rough adjustment is performed with high sensitivity for a certain period of time (select
256/128ms with AGHT, when MCK = 128Fs), and the AGCNTL coefficient approaches the appropriate value.
The sensitivity at this time can be selected from two types with AGV1.
In the second stage, the AGCNTL coefficient is finely adjusted to approach more appropriate value with
relatively low sensitivity. The sensitivity for the second stage can be selected from two types with AGV2. In the
second stage of default operation, when the AGCNTL coefficient reaches the appropriate value and stops
changing, the CXD2587Q confirms that the AGCNTL coefficient has not changed for a certain period of time
(select 63/31ms with AGHJ, when MCK = 128Fs), and then completes AGCNTL operation. (Self-stop mode)
This self-stop mode can be canceled by setting AGS to 0.
In addition, the first stage is omitted for AGCNTL operation when AGHS is set to 0.
An example of AGCNTL coefficient transitions during AGCNTL in various settings are shown in Fig. 4-5.
Initial value
Slope AGV1
AGCNTL
coefficient value
Slope AGV2
Convergence value
AGHT AGJ
AGCNTL AGCNTL
Start completion
SENS
Fig. 4-5.
Note) Fig. 4-5 shows the example where the AGCNTL coefficient value converges to the smaller value from
the initial value.
– 71 –
CXD2587Q
§4-7. FCS Servo and FCS Search (Focus Search)

The FCS servo is controlled by the 8-bit serial command $0X. (See Table 4-6.)
Register name Command D23 to D20 D19 to D16

1 0 ∗ ∗ FOCUS SERVO ON (FOCUS GAIN NORMAL)
1 1 ∗ ∗ FOCUS SERVO ON (FOCUS GAIN DOWN)
FOCUS 0 ∗ 0 ∗ FOCUS SERVO OFF, 0V OUT

0 0 0 0 0
CONTROL 0 ∗ 1 ∗ FOCUS SERVO OFF, FOCUS SEARCH VOLTAGE OUT
0 ∗ 1 0 FOCUS SEARCH VOLTAGE DOWN
0 ∗ 1 1 FOCUS SEARCH VOLTAGE UP
∗: Don’t care
Table 4-6.
FCS Search
FCS search is required in the course of turning on the FCS servo.
Fig. 4-7 shows the signals for sending commands $00 → $02 → $03 and performing only FCS search operation.
Fig. 4-8 shows the signals for sending $08 (FCS on) after that.
$00 $02 $03 $00 $02 $03 $08
0
FCSDRV FCSDRV
RF RF
FOK FOK
FZC comparator level
FE FE
0 0
FZC FZC
Fig. 4-7. Fig. 4-8.
– 72 –
CXD2587Q
§4-8. TRK (Tracking) and SLD (Sled) Servo Control

The TRK and SLD servos are controlled by the 8-bit command $2X. (See Table 4-9.)
When the upper 4 bits of the serial data are 2 (Hex), TZC is output to the SENS pin.

0 0 ∗ ∗ TRACKING SERVO OFF
0 1 ∗ ∗ TRACKING SERVO ON
1 0 ∗ ∗ FORWARD TRACK JUMP
TRACKING 1 1 ∗ ∗ REVERSE TRACK JUMP

2 0 0 1 0
MODE ∗ ∗ 0 0 SLED SERVO OFF
∗ ∗ 0 1 SLED SERVO ON
∗ ∗ 1 0 FORWARD SLED MOVE
∗ ∗ 1 1 REVERSE SLED MOVE
∗: Don’t care
Table 4-9.
TRK Servo
The TRK JUMP (track jump) level can be set with 6 bits (D13 to D8) of $36.
In addition, when the TRK servo is on and D17 of $1 is set to 1, the TRK servo filter switches to gain-up mode.
The filter also switches to gain-up mode when the LOCK signal goes low or when vibration is detected with the
anti-shock circuit (described hereafter) enabled.
The CXD2587Q has 2 types of filters in TRK gain-up mode which can be selected by setting D16 of $1. (See
Table 4-17.)
SLD Servo
The SLD MOV (sled move) output, composed of a basic value from 6 bits (D13 to D8) of $37, is determined by
multiplying this value by 1×, 2×, 3× or 4× magnification set using D17 and D16 when D18 = D19 = 0 is set with
$3. (See Table 4-10.)
SLD MOV must be performed continuously for 50µs or more. In addition, if the LOCK input signal goes low
when the SLD servo is on, the SLD servo turns off.
Note) When the LOCK signal is low, the TRK servo switches to gain-up mode and the SLD servo is turned off
by the default. These operations are disabled by setting D6 (LKSW) of $38 to 1.

0 0 0 0 SLED KICK LEVEL (basic value × ±1)
3 SELECT 0 0 1 1
Table 4-10.
– 73 –
CXD2587Q
§4-9. MIRR and DFCT Signal Generation

The RF signal obtained from the RFDC pin is sampled at approximately 1.4MHz (when MCK = 128Fs) and
loaded. The MIRR and DFCT signals are generated from this RF signal.
MIRR Signal Generation

The loaded RF signal is applied to peak hold and bottom hold circuits.
An envelope is generated from the waveforms generated in these circuits, and the MIRR comparator level is
generated from the average of this envelope waveform.
The MIRR signal is generated by comparing the waveform generated by subtracting the bottom hold value
from the peak hold value with this MIRR comparator level. (See Fig. 4-11.)
The bottom hold speed and mirror sensitivity can be selected from 4 values using D7 and 6, and D5 and 4,
respectively, of $3C.
RF
Peak Hold
Bottom Hold
Peak Hold MIRR Comp

– Bottom Hold (Mirror comparator level)
H
MIRR
L
Fig. 4-11.
DFCT Signal Generation

The loaded RF signal is input to two peak hold circuits with different time constants, and the DFCT signal is
generated by comparing the difference between these two peak hold waveforms with the DFCT comparator
level. (See Fig. 4-12.)
The DFCT comparator level can be selected from four values using D13 and D12 of $3B.
RF
Peak Hold1
Peak Hold2
Peak Hold2
– Peak Hold1 SDF (Defect comparator level)
H
DFCT
L
Fig. 4-12.
– 74 –
CXD2587Q
§4-10. DFCT Countermeasure Circuit

The DFCT countermeasure circuit maintains the directionality of the servo so that the servo does not become
easily dislocated due to scratches or defects on discs.
Specifically, these operations are achieved by detecting scratch and defect with the DFCT signal generation
circuit, and when DFCT goes high, applying the low-frequency component of the error signal before DFCT
went high to the FCS and TRK servo filter inputs. (See Fig. 4-13.)
In addition, these operations are activated by the default. They can be disabled by setting D7 (DFSW) of $38
to 1.
Hold Filter
Error signal Input register Hold register
DFCT EN
Servo Filter
Fig. 4-13.
§4-11. Anti-Shock Circuit

When vibrations occurs in the CD player, this circuit forces the TRK filter to switch to gain-up mode so that the
servo does not become easily dislocated. This circuit is for systems which require vibration countermeasures.
Concretely, vibrations are detected using an internal anti-shock filter and comparator circuit, and the gain is
increased. (See Fig. 4-14.)
The comparator level is fixed to 1/16 of the maximum comparator input amplitude. However, the comparator
level is practically variable by adjusting the value of the anti-shock filter output coefficient K35.
This function can be turned on and off by D19 of $1 when the brake circuit (described hereafter) is off. (See
Table 4-17.)
This circuit can also support an external vibration detection circuit, and can set the TRK servo filter to gain-up
mode by inputting high level to the ATSK pin.
When the upper 4 bits of the command register are 1 (Hex), vibration detection can be monitored from the
SENS pin. It also can be monitored from the ATSK pin by setting the ASOT command of $3F to 1.
ATSK
Anti Shock Comparator SENS

TE
Filter
TRK Gain Up
Filter
TRK
PWM Gen
TRK Gain Normal
Filter
Fig. 4-14.
– 75 –
CXD2587Q
§4-12. Brake Circuit

Immediately after a long distance track jump it tends to be hard for the actuator to settle and for the servo to
turn on.
The brake circuit prevents these phenomenon.
The brake circuit is to use tracking drive as a brake by cutting unnecessary portions of it utilizing the 180°
offset in the RF envelope and tracking error phase relationship which occurs when the actuator traverses the
track in the radial direction from the inner track to the outer track and vice versa. (See Figs. 4-15 and 4-16.)
Concretely, this operation is achieved by masking the tracking drive using the TRKCNCL signal generated by
loading the MIRR signal at the edge of the TZC (Tracking Zero Cross) signal.
The brake circuit can be turned on and off by D18 of $1. (See Fig. 4-17.)
Inner track Outer track Outer track Inner track
FWD REV Servo ON REV FWD Servo ON

JMP JMP JMP JMP
TRK TRK
DRV DRV
RF RF
Trace Trace
MIRR MIRR
TE 0 TE 0
TZC TZC
Edge Edge
TRKCNCL TRKCNCL
TRK 0 TRK
DRV 0
DRV
SENS SENS
TZC out TZC out
Fig. 4-15. Fig. 4-16.

1 0 ∗ ∗ ANTI SHOCK ON
0 ∗ ∗ ∗ ANTI SHOCK OFF
∗ 1 ∗ ∗ BRAKE ON
TRACKING ∗ 0 ∗ ∗ BRAKE OFF

1 0 0 0 1
CONTROL ∗ ∗ 0 ∗ TRACKING GAIN NORMAL
∗ ∗ 1 ∗ TRACKING GAIN UP
∗ ∗ ∗ 1 TRACKING GAIN UP FILTER SELECT 1
∗ ∗ ∗ 0 TRACKING GAIN UP FILTER SELECT 2
∗: Don’t care
Fig. 4-17.
– 76 –
CXD2587Q
§4-13. COUT Signal

The COUT signal is output to count the number of tracks during traverse, etc. It is basically generated by
loading the MIRR signal at both edges of the TZC signal. And the used TZC signal can be selected among
three different phases for each COUT signal application.
• HPTZC: For 1-track jumps

Fast phase COUT signal generation with a fast phase TZC signal. (The TZC phase is advanced by a
cut-off 1kHz digital HPF; when MCK = 128Fs.)
• STZC: For COUT signal generation when MIRR is externally input and for applications other than
COUT generation.
This is generated from sampling TE at 700kHz. (when MCK = 128Fs)
• DTZC: For high-speed traverse
Reliable COUT signal generation with a delayed phase STZC signal.
Since it takes some time to generate the MIRR signal, it is necessary to delay the TZC signal in accordance
with the MIRR signal delay during high-speed traverse.
The COUT signal output method is switched with D15 and 14 of $3C.
When D15 = 1 : STZC
When D15 = 0 and D14 = 0 : HPTZC
When D15 = 0 and D14 = 1 : DTZC
When the DTZC is selected, the delay can be selected from two values with D14 of $36.
§4-14. Serial Readout Circuit

The following measurement and adjustment results can be read out from the SENS pin by inputting the
readout clock to the SCLK pin by $39. (See Fig. 4-18, Table 4-19 and "Description of SENS Signals".)
Specified commands
$390C: VC AVRG measurement result
$3908: FE AVRG measurement result
$3904: TE AVRG measurement result
$391F: RF AVRG measurement result
$3953: FCS AGCNTL coefficient result
$3963: TRK AGCNTL coefficient result
$391C: TRVSC adjustment result
$391D: FBIAS register value
XLAT
tSPW
tDLS
SCLK •••
1/fSCLK
Serial Read Out Data

MSB ••• LSB
(SENS)
Fig. 4-18.

SCLK frequency fSCLK 16 MHz
SCLK pulse width tSPW 31.3 ns
Delay time tDLS 15 µs
Table 4-19.
During readout, the upper 8 bits of the command register must be 39 (Hex).
– 77 –
CXD2587Q
§4-15. Writing to the Coefficient RAM

The coefficient RAM can be rewritten by $34. All coefficients have default values in the built-in ROM, and
transfer from the ROM to the RAM is completed approximately 40µs (when MCK = 128Fs) after the XRST pin
rises. (The coefficient RAM cannot be rewritten during this period.)
After that, the characteristics of each built-in filter can be finely adjusted by rewriting the data for each address
of the coefficient RAM.
The coefficient rewrite command is comprised of 24 bits, with D14 to D8 of $34 as the address (D15 = 0) and
D7 to D0 as data. Coefficient rewriting is completed 11.3µs (when MCK = 128Fs) after the command is
received. When rewriting multiple coefficients, be sure to wait 11.3µs (when MCK = 128Fs) before sending the
next rewrite command.
§4-16. PWM Output

FCS, TRK and SLD outputs are output as PWM waveforms.
A double oversampling noise shaper is used for FCS and TRK.
Timing Chart 4-20 and Fig. 4-21 show examples of output waveforms and drive circuits.
MCK
(5.6448MHz) ↑ ↑ ↑ ↑ ↑ ↑ ↑
Output value +A Output value –A Output value 0
SLD
64tMCK 64tMCK 64tMCK
SFDR AtMCK
SRDR AtMCK
FCS/TRK
32tMCK 32tMCK 32tMCK 32tMCK 32tMCK 32tMCK

FFDR/
TFDR A tMCK A tMCK
2 2
FRDR/
TRDR A tMCK A tMCK
2 2
1
tMCK = ≈ 180ns
5.6448MHz
Timing Chart 4-20.
– 78 –
CXD2587Q
Example of Driver Circuit
VCC
22k
22k
RDR DRV
FDR
22k
22k
VEE
Fig. 4-21. Driver Circuit
– 79 –
CXD2587Q
§4-17. Servo Status Changes Produced by the LOCK Signal

When the LOCK signal becomes low, the TRK servo switches to the gain-up mode and the SLD servo turns off
in order to prevent SLD free-running.
Setting D6 (LKSW) of $38 to 1 deactivates this function.
In other words, neither the TRK servo nor the SLD servo change even when the LOCK signal becomes low.
This enables microcomputer control.
§4-18. Description of Commands and Data Sets

The following description contains portions which convert internal voltages into the values when they are
output externally and describe them as input conversion or output conversion.
Input conversion converts these voltages into the voltages entering input pins before A/D conversion.
Output conversion converts PWM output values into analog voltage values.
– 80 –
CXD2587Q
$34

0 KA6 KA5 KA4 KA3 KA2 KA1 KA0 KD7 KD6 KD5 KD4 KD3 KD2 KD1 KD0
When D15 = 0
KA6 to KA0: Coefficient address
KD7 to KD0: Coefficient data

1 1 1 1 1 0 FBL9 FBL8 FBL7 FBL6 FBL5 FBL4 FBL3 FBL2 FBL1 —
When D15 = D14 = D13 = D12 = D11 = 1 ($34F)

D10 = 0
FBIAS LIMIT register write
FBL9 to FBL1: Data; data compared with FB9 to 1, FBL9 = MSB.
When using the FBIAS register in counter mode, counter operation stops when the
value of FB9 to 1 matches with FBL9 to 1.

1 1 1 1 0 1 FB9 FB8 FB7 FB6 FB5 FB4 FB3 FB2 FB1 —
When D15 = D14 = D13 = D12 = 1 ($34F)

D11 = 0, D10 = 1
FBIAS register write
FB9 to FB1: Data; FB9 is MSB two's complement data.
For FE input conversion, FB9 to FB1 = 011111111 corresponds to 255/256 × VDD/5 and
FB9 to FB1 = 100000000 to –256/256 × VDD/5 respectively. (VDD: supply voltage)
1 1 1 1 0 0 TV9 TV8 TV7 TV6 TV5 TV4 TV3 TV2 TV1 TV0
When D15 = D14 = D13 = D12 = 1 ($34F)

D11 = 0, D10 = 0
TRVSC register write
TV9 to TV0: Data; TV9 is MSB two's complement data.
For TE input conversion, TV9 to TV0 = 0011111111 corresponds to 255/256 × VDD/5
and TV9 to TV0 = 1100000000 to –256/256 × VDD/5 respectively. (VDD: supply voltage)
Note) • When the TRVSC register is read out, the data length is 9 bits. At this time, data corresponding to
each bit TV8 to TV0 during external write are read out.
• When reading out internally measured values and then writing these values externally, set TV9 the
same as TV8.
– 81 –
CXD2587Q
$35 (preset: $35 58 2D)

FT1 FT0 FS5 FS4 FS3 FS2 FS1 FS0 FTZ FG6 FG5 FG4 FG3 FG2 FG1 FG0
FT1, FT0, FTZ: Focus search-up speed

Default value: 010 (0.673 × VDD V/s)
Focus drive output conversion
FT1 FT0 FTZ Focus search speed [V/s]

0 0 0 1.35 × VDD
∗ 0 1 0 0.673 × VDD
1 0 0 0.449 × VDD
1 1 0 0.336 × VDD
0 0 1 1.79 × VDD
0 1 1 1.08 × VDD
1 0 1 0.897 × VDD
1 1 1 0.769 × VDD
∗: preset, VDD: PWM driver supply voltage
FS5 to FS0: Focus search limit voltage

Default value: 011000 (±24/64 × VDD, VDD: PWM driver supply voltage)
Focus drive output conversion
FG6 to FG0: AGF convergence gain setting value
Default value: 0101101
$36 (preset: $36 0E 2E)

TDZC DTZC TJ5 TJ4 TJ3 TJ2 TJ1 TJ0 SFJP TG6 TG5 TG4 TG3 TG2 TG1 TG0
TDZC: Selects the TZC signal for generating the TRKCNCL signal during brake circuit operation.
TDZC = 0: the edge of the HPTZC or STZC signal, whichever has the faster phase, is used.
TDZC = 1: the edge of the HPTZC or STZC signal or the tracking drive signal zero-cross,
whichever has the faster phase, is used. (See §4-12.)
DTZC: DTZC delay (8.5/4.25µs, when MCK = 128Fs)
Default value: 0 (4.25µs)
TJ5 to TJ0: Track jump voltage
Default value: 001110 (≈ ±14/64 × VDD, VDD: PWM driver supply voltage)
Tracking drive output conversion
SFJP: Surf jump mode on/off
The tracking PWM output is made by adding the tracking filter output and TJReg (TJ5 to 0), by
setting D7 to 1 (on)
TG6 to TG0: AGT convergence gain setting value
Default value: 0101110
– 82 –
CXD2587Q
$37 (preset: $37 50 BA)

FZSH FZSL SM5 SM4 SM3 SM2 SM1 SM0 AGS AGJ AGGF AGGT AGV1 AGV2 AGHS AGHT
FZSH, FZSL: FZC (Focus Zero Cross) slice level

Default value: 01 (1/8 × VDD × 0.4, VDD: supply voltage); FE input conversion
FZSH FZSL Slice level

0 0 1/4 × VDD × 0.4
∗ 0 1 1/8 × VDD × 0.4
1 0 1/16 × VDD × 0.4
1 1 1/32 × VDD × 0.4
∗: preset
SM5 to SM0: Sled move voltage
Default value: 010000 (≈ ±16/64 × VDD, VDD: PWM driver supply voltage)
Sled drive output conversion
AGS: AGCNTL self-stop on/off
Default value: 1 (on)
AGJ: AGCNTL convergence completion judgment time during low sensitivity adjustment (31/63ms,
when MCK = 128Fs)
Default value: 0 (63ms)
AGGF: Focus AGCNTL internally generated sine wave amplitude (small/large)
Default value: 1 (large)
AGGT: Tracking AGCNTL internally generated sine wave amplitude (small/large)
Default value: 1 (large)
FE/TE input conversion

0 (small) 1/32 × VDD × 0.4
AGGF
1 (large)∗ 1/16 × VDD × 0.4
0 (small) 1/16 × VDD × 0.4
AGGT
1 (large)∗ 1/8 × VDD × 0.4
∗: preset
AGV1: AGCNTL convergence sensitivity during high sensitivity adjustment; high/low

Default value: 1 (high)
AGV2: AGCNTL convergence sensitivity during low sensitivity adjustment; high/low
Default value: 0 (low)
AGHS: AGCNTL high sensitivity adjustment on/off
Default value: 1 (on)
AGHT: AGCNTL high sensitivity adjustment time (128/256ms, when MCK = 128Fs)
Default value: 0 (256ms)
– 83 –
CXD2587Q
$38 (preset: $38 00 00)

VCLM VCLC FLM FLC0 RFLM RFLC AGF AGT DFSW LKSW TBLM TCLM FLC1 TLC2 TLC1 TLC0
VCLM: VC level measurement (on/off)

VCLC: VC level compensation for FCS In register (on/off)
FLM: Focus zero level measurement (on/off)
FLC0: Focus zero level compensation for FZC register (on/off)
RFLM: RF zero level measurement (on/off)
RFLC: RF zero level compensation (on/off)
AGF: Focus auto gain adjustment (on/off)
AGT: Tracking auto gain adjustment (on/off)
DFSW: Defect disable switch (on/off)
Setting this switch to 1 (on) disables the defect countermeasure circuit.
LKSW: Lock switch (on/off)
Setting this switch to 1 (on) disables the sled free-running prevention circuit.
TBLM: Traverse center measurement (on/off)
TCLM: Tracking zero level measurement (on/off)
FLC1: Focus zero level compensation for FCS In register (on/off)
TLC2: Traverse center compensation (on/off)
TLC1: Tracking zero level compensation (on/off)
TLC0: VC level compensation for TRK/SLD In register (on/off)
Note) Commands marked with are accepted every 2.9ms. (when MCK = 128Fs)
All commands are on when set to 1.
– 84 –
CXD2587Q
$39
D15 D14 D13 D12 D11 D10 D9 D8

DAC SD6 SD5 SD4 SD3 SD2 SD1 SD0
DAC: Serial data readout DAC mode (on/off)

SD6 to SD0: Serial readout data select
SD6 SD5 Readout data Readout data length

1 Coefficient RAM data for address = SD5 to SD0 8 bits
0 1 Data RAM data for address = SD4 to SD0 16 bits
SD4 SD3 to SD0
1 1 1 1 RF AVRG register 8 bits $399F
1 1 1 0 RFDC input signal 8 bits $399E
1 1 0 1 FBIAS register 9 bits $399D
1 1 0 0 TRVSC register 9 bits $399C
1
0 0 1 1 RFDC envelope (bottom) 8 bits $3993
0 0 1 0 RFDC envelope (peak) 8 bits $3992
0 0 0 1 RFDC envelope 8 bits $3991
0 0
(peak) – (bottom)
1 1 ∗ ∗ VC AVRG register 9 bits $398C
1 0 ∗ ∗ FE AVRG register 9 bits $3988
0 1 ∗ ∗ TE AVRG register 9 bits $3984
0 0 0 1 1 FE input signal 8 bits $3983
0 0 1 0 TE input signal 8 bits $3982
0 0 0 1 SE input signal 8 bits $3981
0 0 0 0 VC input signal 8 bits $3980
Note) Coefficients K40 to K4F cannot be read out. ∗: Don't care

See the description for SRO1 of $3F concerning readout methods for the above data.
– 85 –
CXD2587Q
$3A (preset: $3A 00 00)

0 FBON FBSS FBUP FBV1 FBV0 0 TJD0 FPS1 FPS0 TPS1 TPS0 0 SJHD INBK MTI0
FBON: FBIAS (focus bias) register addition (on/off)

The FBIAS register value is added to the signal loaded into the FCS In register by FBON = 1
(on).
FBSS: FBIAS (focus bias) register/counter switching
FBSS = 0: register, FBSS = 1: counter.
FBUP: FBIAS (focus bias) counter up/down operation switching
This performs counter up/down control when FBSS = 1. FBUP = 0: down counter,
FBUP = 1: up counter.
FBV1, FBV0: FBIAS (focus bias) counter voltage switching
The number of FCS BIAS count-up/-down steps per cycle is decided by these bits.
The counter changes once for each
FBV1 FBV0 Number of steps per cycle
sampling cycle of the focus servo filter.
∗ 0 0 1
When MCK is 128Fs, the sampling
0 1 2 frequency is 88.2kHz. When converted
1 0 4 to FE input, 1 step is approximately 1/29
1 1 8 × VDD × 0.4, VDD = supply voltage.
∗: preset
TJD0: This sets the tracking servo filter data RAM to 0 when switched from track jump to servo on
only when SFJP = 1 (during surf jump operation).
FPS1, FPS0: Gain setting when transferring data from the focus filter to the PWM block.
TPS1, TPS0: Gain setting when transferring data from the tracking filter to the PWM block.
This is effective for increasing the overall gain in order to widen the servo band.
Operation when FPS1, FPS0 (TPS1, TPS0) = 00 is the same as usual (7-bit shift). However,
6dB, 12dB and 18dB can be selected independently for focus and tracking by setting the
relative gain to 0dB when FPS1, FPS0 (TPS1, TPS0) = 00.
FPS1 FPS0 Relative gain TPS1 TPS0 Relative gain

∗ 0 0 0dB 0 0 0dB ∗
0 1 +6dB 0 1 +6dB
1 0 +12dB 1 0 +12dB
1 1 +18dB 1 1 +18dB
∗: preset
SJHD: This holds the tracking filter output at the value when surf jump starts during surf jump.
INBK: When INBK = 0 (off), the brake circuit masks the tracking drive signal with TRKCNCL which is
generated by taking the MIRR signal at the TZC edge. When INBK = 1 (on), the tracking filter
input is masked instead of the drive output.
MTI0: The tracking filter input is masked when the MIRR signal is high by setting MTI0 = 1 (on).
– 86 –
CXD2587Q
$3B (preset: $3B E0 50)

SFO2 SFO1 SDF2 SDF1 MAX2 MAX1 SFOX BTF D2V2 D2V1 D1V2 D1V1 RINT 0 0 0
SFOX, SFO2, SFO1: FOK slice level

Default value: 011 (28/256 × VDD × 0.57, VDD = supply voltage)
RFDC input conversion
SFOX SFO2 SFO1 Slice level

0 0 0 16/256 × VDD × 0.57
0 0 1 20/256 × VDD × 0.57
0 1 0 24/256 × VDD × 0.57
∗ 0 1 1 28/256 × VDD × 0.57
1 0 0 32/256 × VDD × 0.57
1 0 1 40/256 × VDD × 0.57
1 1 0 48/256 × VDD × 0.57
1 1 1 50/256 × VDD × 0.57
∗: preset
SDF2, SDF1: DFCT slice level

Default value: 10 (0.0313 × VDD × 1.14V)
RFDC input conversion
SDF2 SDF1 Slice level

0 0 0.0156 × VDD × 1.14
0 1 0.0234 × VDD × 1.14
∗ 1 0 0.0313 × VDD × 1.14
1 1 0.0391 × VDD × 1.14
∗: preset, VDD: supply voltage
MAX2, MAX1: DFCT maximum time (MCK = 128Fs)

Default value: 00 (no timer limit)
MAX2 MAX1 DFCT maximum time

∗ 0 0 No timer limit
0 1 2.00ms
1 0 2.36
1 1 2.72
∗: preset
BTF: Bottom hold double-speed count-up mode for MIRR signal generation
On/off (default: off)
On when set to 1.
– 87 –
CXD2587Q
D2V2, D2V1: Peak hold 2 for DFCT signal generation

Count-down speed setting
Default value: 01 (0.086 × VDD × 1.14V/ms, 44.1kHz)
[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the
operating frequency of the internal counter.
Count-down speed
D2V2 D2V1
[V/ms] [kHz]
0 0 0.0431 × VDD × 1.14 22.05
∗ 0 1 0.0861 × VDD × 1.14 44.1
1 0 0.172 × VDD × 1.14 88.2
1 1 0.344 × VDD × 1.14 176.4
D1V2, D1V1: Peak hold 1 for DFCT signal generation

Count-down speed setting
Default value: 01 (0.688 × VDD × 1.14V/ms, 352.8kHz)
[V/ms] unit items indicate RFDC input conversion; [kHz] unit items indicate the
operating frequency of the internal counter.
Count-down speed
D2V2 D2V1
[V/ms] [kHz]
0 0 0.344 × VDD × 1.14 176.4
∗ 0 1 0.688 × VDD × 1.14 352.8
1 0 1.38 × VDD × 1.14 705.6
1 1 2.75 × VDD × 1.14 1411.2
RINT: This initializes the initial-state registers of the circuits which generate MIRR, DFCT and FOK.
– 88 –
CXD2587Q
$3C (preset: $3C 00 80)

COSS COTS CETZ CETF COT2 COT1 MOT2 0 BTS1 BTS0 MRC1 MRC0 0 0 0 0
COSS, COTS: These select the TZC signal used when generating the COUT signal.
Preset = HPTZC.
COSS COTS TZC

1 — STZC
∗ 0 0 HPTZC
0 1 DTZC
∗: preset, —: don't care
STZC is the TZC generated by sampling the TE signal at 700kHz. (when MCK = 128Fs)
DTZC is the delayed phase STZC. (The delay amount can be selected by D14 of $36.)
HPTZC is the fast phase TZC passed through a HPF with a cut-off frequency of 1kHz.
See §4-13.
CETZ: The input from the TE pin normally enters the TRK filter and is used to generate the TZC
signal. However, the input from the CE pin can also be used. This function is for the center
error servo.
When CETZ = 0, the TZC signal is generated by using the TE input signal.
When CETZ = 1, the TZC signal is generated by using the CE input signal.
CETF: When CETF = 0, the signal input to the TE pin is input to the TRK servo filter.
When CETF = 1, the signal input to the CE pin is input to the TRK servo filter.
These commands output the TZC signal.

COT2, COT1: This outputs the TZC signal from the COUT pin.
COT2 COT1 COUT pin output

1 — STZC
0 1 HPTZC
∗ 0 0 COUT
MOT2: The STZC signal is output from the MIRR pin by setting MOT2 to 1.
These commands set the MIRR signal generation circuit.

BTS1, BTS0: This sets the count-up speed for the bottom hold value of the MIRR generation circuit.
The time per step is approximately 708 ns (when MCK = 128Fs). The preset value is BTS1 = 1,
BTS0 = 0. However, this is valid only when BTF of $3B is 0.
MRC1, MRC0: This sets the minimum pulse width for masking the MIRR signal of the MIRR generation circuit.
As noted in §4-9, the MIRR signal is generated by comparing the waveform obtained by
subtracting the bottom hold value from the peak hold value with the MIRR comparator level.
Strictly speaking, however, for MIRR to become high, these levels must be compared
continuously for a certain time. This sets that time.
The preset value is MRC1 = 0, MRC0 = 0.
BTS1 BTS0 Number of count-up steps per cycle MRC1 MRC0 Setting time [µs]
0 0 1 0 0 5.669 ∗
0 1 2 0 1 11.338
∗ 1 0 4 1 0 22.675
1 1 8 1 1 45.351
∗: preset (when MCK = 128Fs)
– 89 –
CXD2587Q
$3D (preset: $3D 00 00)

SFID SFSK THID THSK 0 TLD2 TLD1 TLD0 0 0 0 0 0 0 0 0
SFID: SLED servo filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK
filter second-stage output.
When the low-frequency component of the tracking error signal obtained from the RF amplifier
is attenuated, the low frequency can be amplified and input to the SLD servo filter.
SFSK: Only during TRK servo gain up2 operation, coefficient K30 is used instead of K00. Normally
the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain
up2, and error occurs in the DC level at M0D. In this case, the DC level of the signal
transmitted to M00 can be kept uniform by adjusting the K30 value even during the above
switching.
THID: TRK hold filter input can be obtained not from SLD in Reg, but from M0D, which is the TRK
filter second-stage output.
When signals other than the tracking error signal from the RF amplifier are input to the SE input
pin, the signal transmitted from the TE pin can be obtained as TRK hold filter input.
THSK: Only during TRK servo gain up2 operation, coefficient K46 is used instead of K40. Normally
the DC gain between the TE input pin and M0D changes for TRK filter gain normal and gain up
2, and error occurs in the DC level at M0D. In this case, the DC level of the signal transmitted
to M18 can be kept uniform by adjusting the K46 value even during the above switching.
∗ Please refer to §4-20. Filter Composition, for further information on SFID, SFSK, THID and
THSK commands.
TLD0 to 2: SLD filter correction turns on and off independently of the TRK filter.
Please refer also to $38 (TLC0 to 2) and Figure 4-3.
Traverse center correction

TLC2 TLD2
TRK filter SLD filter
∗ 0 — OFF OFF
0 ON ON
1
1 ON OFF
Tracking zero level correction

TLC1 TLD1
∗ 0 — OFF OFF
0 ON ON
1
1 ON OFF
VC level correction
TLC0 TLD0
∗ 0 — OFF OFF
0 ON ON
1
1 ON OFF
∗: preset, — : Don't care
– 90 –
CXD2587Q
• Input coefficient inversion when SFID = 1 and THID = 1
The preset coefficients for the TRK filter are negative for input and positive for output. With this, the error input
and servo that outputs reversed phase drive can be hypothesized.
Negative input coefficient Positive output coefficient
TE TRK Filter
SE SLD Filter
Positive input coefficient Positive output coefficient
TRK Hold TRK Hold Filter
When SFID = 1, the TRK filter negative input coefficient is applied to the SLD filter, so invert the SLD input
coefficient (K00) code.
For the same reason, when THID = 1, invert the TRK hold input coefficient (K40) code.
TE TRK Filter
M0D
Positive input coefficient Positive output coefficient
SE SLD Filter
TRK Hold TRK Hold Filter
Please refer also to §4-20. Filter Composition.
– 91 –
CXD2587Q
$3E (preset: $3E 00 00)

F1NM F1DM F3NM F3DM T1NM T1UM T3NM T3UM DFIS TLCD 0 LKIN COIN MDFI MIRI XT1D
F1NM, F1DM: Quasi double accuracy setting for FCS servo filter first-stage
On when set to 1; default = 0.
F1NM: Gain normal
F1DM: Gain down
T1NM, T1UM: Quasi double accuracy setting for TRK servo filter first-stage
T1NM: Gain normal
T1UM: Gain up
F3NM, F3DM: Quasi double accuracy setting for FCS servo filter third-stage
Generally, the advance amount of the phase becomes large by partially setting the FCS servo
third-stage filter which is used as the phase compensation filter to double accuracy.
F3NM: Gain normal
F3DM: Gain down
T3NM, T3UM: Quasi double accuracy setting for TRK servo filter third-stage
Generally, the advance amount of the phase becomes large by partially setting the TRK servo
third-stage filter which is used as the phase compensation filter to double accuracy.
T3NM: Gain normal
T3UM: Gain up
Note) Filter first- and third-stage quasi double accuracy settings can be set individually.
See "Filter Composition" at the end of this specification concerning quasi double accuracy.
DFIS: FCS hold filter input extraction node selection

0: M05 (Data RAM address 05); default
1: M04 (Data RAM address 04)
TLCD: This command masks the TLC2 command set by D2 of $38 only when FOK is low.
On when set to 1; default = 0
LKIN: When 0, the internally generated LOCK signal is output to the LOCK pin. (default)
When 1, the LOCK signal can be input from an external source to the LOCK pin.
COIN: When 0, the internally generated COUT signal is output to the COUT pin. (default)
When 1, the COUT signal can be input from an external source to the COUT pin.
The MIRR, DFCT and FOK signals can also be input from an external source.
MDFI: When 0, the MIRR, DFCT and FOK signals are generated internally. (default)
When 1, the MIRR, DFCT and FOK signals can be input from an external source through the
MIRR, DFCT and FOK pins.
MIRI: When 0, the MIRR signal is generated internally. (default)
When 1, the MIRR signal can be input from an external source through the MIRR pin.
MDFI MIRI
∗ 0 0 MIRR, DFCT and FOK are all generated internally.
0 1 MIRR only is input from an external source.
1 — MIRR, DFCT and FOK are all input from an external source.
XT1D: The clock input from FSTI can be used without being frequency-divided as the master clock for
the servo block by setting D0 to 1. This command takes precedence over the XTSL pin, XT2D
and XT4D. See the description of $3F for XT2D and XT4D.
– 92 –
CXD2587Q
$3F (preset: $3F 00 00)

0 AGG4 XT4D XT2D 0 DRR2 DRR1 DRR0 0 ASFG FTQ LPAS SRO1 0 AGHF ASOT
AGG4: This varies the amplitude of the internally generated sine wave using the AGGF and AGGT
commands during AGC.
When AGG4 = 0, the default is used. When AGG4 = 1, the setting is as shown in the table below.
AGGF (MSB) AGGT (LSB) TE/FE input conversion These settings are the same for
both focus auto gain control and
∗ 0 0 1/64 × VDD × 0.4 [V] tracking auto gain control.
0 1 1/32 × VDD × 0.4
1 0 1/16 × VDD × 0.4
1 1 1/8 × VDD × 0.4
∗: preset
XT4D, XT2D: MCK (digital servo master clock) frequency division setting
This command forcibly sets the frequency division ratio to 1/4, 1/2 or 1/1 when MCK is
generated from the signal input to the FSTI pin. See the description of $3E for XT1D.
XT1D XT2D XT4D Frequency division ratio

∗ 0 0 0 According to XTSL
1 — — 1/1
0 1 — 1/2
0 0 1 1/4 ∗: preset, —: don't care
DRR2 to DRR0: Partially clears the Data RAM values (0 write).
The following values are cleared when set to 1 (on) respectively; default = 0
DRR2: M08, M09, M0A
DRR1: M00, M01, M02
DRR0: M00, M01, M02 only when LOCK = low
Note) Set DRR1 and DRR0 on for 50µs or more.
ASFG: When vibration detection is performed during anti-shock circuit operation, FCS servo filter is
forcibly set to gain normal status.
LPAS: Built-in analog buffer low-current consumption mode
This mode reduces the total analog buffer current consumption for the VC, TE, SE and FE
input analog buffers by using a single operational amplifier.
Note) When using this mode, first check whether each error signal is properly A/D converted
using the SRO1 and SRO0 commands of $3F.
SRO1: These commands are used to output various data externally continuously which have been
specified with the $39 command. (However, D15 (DAC) of $39 must be set to 1.)
Digital output (SOCK, XOLT and SOUT) can be obtained from three specified pins by setting
these commands to 1 respectively. The default is 0, 0. (no readout)
The output pins for each case are shown below.
SRO1 = 1
SOCK LMUT pin
XOLT WFCK pin
SOUT RMUT pin
(See "Description of Data Readout" on the following page.)
AGHF: This halves the frequency of the internally generated sine wave during AGC.
FTQ: The slope of the output during focus search is a quarter of the conventional output slope.
ASOT: The anti-shock signal, which is internally detected, is output from the ATSK pin.
Output when set to 1; default=0
Vibration detection when a high signal is output for the anti-shock signal output.
– 93 –
CXD2587Q
Description of Data Readout
SOCK ··· ··· ··· ···

(5.6448MHz)
XOLT
(88.2kHz)
SOUT MSB ··· LSB MSB ··· LSB
16-bit register for

serial/parallel 16-bit register
conversion for latch
SOUT LSB LSB

To the 7-segment LED
•
•
• •
•
•
To the 7-segment LED
MSB MSB
SOCK CLK CLK

Data is connected to the 7-segment LED by
4-bits at a time. This enables Hex display
using four 7-segment LEDs.
XOLT
SOUT Serial data input
D/A Analog To an oscilloscope, etc.

output
SOCK Clock input Offset adjustment,

gain adjustment
XOLT Latch enable input
Waveforms can be monitored with an oscilloscope using

a serial input-type D/A converter as shown above.
– 94 –
CXD2587Q
§4-19. List of Servo Filter Coefficients
<Coefficient Preset Value Table (1)>

K00 E0 SLED INPUT GAIN
K01 81 SLED LOW BOOST FILTER A-H
K02 23 SLED LOW BOOST FILTER A-L
K03 7F SLED LOW BOOST FILTER B-H
K04 6A SLED LOW BOOST FILTER B-L
K05 10 SLED OUTPUT GAIN
K06 14 FOCUS INPUT GAIN
K07 30 SLED AUTO GAIN
K08 7F FOCUS HIGH CUT FILTER A
K09 46 FOCUS HIGH CUT FILTER B
K0A 81 FOCUS LOW BOOST FILTER A-H
K0B 1C FOCUS LOW BOOST FILTER A-L
K0C 7F FOCUS LOW BOOST FILTER B-H
K0D 58 FOCUS LOW BOOST FILTER B-L
K0E 82 FOCUS PHASE COMPENSATE FILTER A
K0F 7F FOCUS DEFECT HOLD GAIN
K10 4E FOCUS PHASE COMPENSATE FILTER B
K11 32 FOCUS OUTPUT GAIN
K12 20 ANTI SHOCK INPUT GAIN
K13 30 FOCUS AUTO GAIN
K14 80 HPTZC / Auto Gain HIGH PASS FILTER A
K15 77 HPTZC / Auto Gain HIGH PASS FILTER B
K16 80 ANTI SHOCK HIGH PASS FILTER A
K17 77 HPTZC / Auto Gain LOW PASS FILTER B
K18 00 Fix∗
K19 F1 TRACKING INPUT GAIN
K1A 7F TRACKING HIGH CUT FILTER A
K1B 3B TRACKING HIGH CUT FILTER B
K1C 81 TRACKING LOW BOOST FILTER A-H
K1D 44 TRACKING LOW BOOST FILTER A-L
K1E 7F TRACKING LOW BOOST FILTER B-H
K1F 5E TRACKING LOW BOOST FILTER B-L
K20 82 TRACKING PHASE COMPENSATE FILTER A
K21 44 TRACKING PHASE COMPENSATE FILTER B
K22 18 TRACKING OUTPUT GAIN
K23 30 TRACKING AUTO GAIN
K24 7F FOCUS GAIN DOWN HIGH CUT FILTER A
K25 46 FOCUS GAIN DOWN HIGH CUT FILTER B
K26 81 FOCUS GAIN DOWN LOW BOOST FILTER A-H
K27 3A FOCUS GAIN DOWN LOW BOOST FILTER A-L
K28 7F FOCUS GAIN DOWN LOW BOOST FILTER B-H
K29 66 FOCUS GAIN DOWN LOW BOOST FILTER B-L
K2A 82 FOCUS GAIN DOWN PHASE COMPENSATE FILTER A
K2B 44 FOCUS GAIN DOWN DEFECT HOLD GAIN
K2C 4E FOCUS GAIN DOWN PHASE COMPENSATE FILTER B
K2D 1B FOCUS GAIN DOWN OUTPUT GAIN
K2E 00 NOT USED
K2F 00 NOT USED
∗ Fix indicates that normal preset values should be used.
– 95 –
CXD2587Q
<Coefficient Preset Value Table (2)>

K30 80 SLED INPUT GAIN (Only when TRK Gain Up2 is accessed with SFSK = 1.)
K31 66 ANTI SHOCK LOW PASS FILTER B
K32 00 NOT USED
K33 7F ANTI SHOCK HIGH PASS FILTER B-H
K34 6E ANTI SHOCK HIGH PASS FILTER B-L
K35 20 ANTI SHOCK FILTER COMPARATE GAIN
K36 7F TRACKING GAIN UP2 HIGH CUT FILTER A
K37 3B TRACKING GAIN UP2 HIGH CUT FILTER B
K38 80 TRACKING GAIN UP2 LOW BOOST FILTER A-H
K39 44 TRACKING GAIN UP2 LOW BOOST FILTER A-L
K3A 7F TRACKING GAIN UP2 LOW BOOST FILTER B-H
K3B 77 TRACKING GAIN UP2 LOW BOOST FILTER B-L
K3C 86 TRACKING GAIN UP PHASE COMPENSATE FILTER A
K3D 0D TRACKING GAIN UP PHASE COMPENSATE FILTER B
K3E 57 TRACKING GAIN UP OUTPUT GAIN
K3F 00 NOT USED
K40 04 TRACKING HOLD FILTER INPUT GAIN
K41 7F TRACKING HOLD FILTER A-H
K42 7F TRACKING HOLD FILTER A-L
K43 79 TRACKING HOLD FILTER B-H
K44 17 TRACKING HOLD FILTER B-L
K45 6D TRACKING HOLD FILTER OUTPUT GAIN
K46 00 TRACKING HOLD FILTER INPUT GAIN (Only when TRK Gain Up2 is accessed with THSK = 1.)
K47 00 NOT USED
K48 02 FOCUS HOLD FILTER INPUT GAIN
K49 7F FOCUS HOLD FILTER A-H
K4A 7F FOCUS HOLD FILTER A-L
K4B 79 FOCUS HOLD FILTER B-H
K4C 17 FOCUS HOLD FILTER B-L
K4D 54 FOCUS HOLD FILTER OUTPUT GAIN
K4E 00 NOT USED
K4F 00 NOT USED
– 96 –
CXD2587Q
§4-20. Filter Composition

The internal filter composition is shown below.
K∗∗ and M∗∗ indicate coefficient RAM and Data RAM address values respectively.
FCS Servo Gain Normal fs = 88.2kHz
FCS
Hold Reg 2 DFCT
2–1
FCS K06
In Reg
AGFON
Sin ROM
K06
FCS FCS
K0F Hold Reg 1 AUTO Gain
M03 M04 M05 M06 M07

K11 K13
Z–1 Z–1 Z–1 Z–1
K08 K09 K0A K0C K0E K10

27
2–7 2–7
FCS PWM
K0B K0D
FCS SRCH
Note) Set the MSB bit of the K0B and K0D coefficients to 0.
FCS Servo Gain Down fs = 88.2kHz
FCS
Hold Reg 2 DFCT
2–1
FCS K06
In Reg
FCS FCS
K2B Hold Reg 1 AUTO Gain
M03 M04 M05 M06 M07

K2D K13
Z–1 Z–1 Z–1 Z–1
K24 K25 K26 K28 K2A K2C

27
2–7 2–7
FCS PWM
K27 K29
FCS SRCH
Note) Set the MSB bit of the K27 and K29 coefficients to 0.
– 97 –
CXD2587Q
TRK Servo Gain Normal fs = 88.2kHz
TRK
Hold Reg DFCT
2–1
TRK K19
In Reg
AGTON
Sin ROM
K19
To SLD Servo, TRK Hold

TRK
AUTO Gain
M0B M0C M0D M0E M0F

K22 K23
Z–1 Z–1 Z–1 Z–1
K1A K1B K1C K1E K20 K21

27
2–7 2–7
TRK PWM
K1D K1F
TRK JMP
Note) Set the MSB bit of the K1D and K1F coefficients to 0.
TRK Servo Gain Up 1 fs = 88.2kHz
TRK
Hold Reg DFCT
2–1
TRK K19
In Reg
TRK
AUTO Gain
27
M0B M0C M0E M0F
K3E K23
TRK PWM
Z–1 Z–1 Z–1
TRK JMP
K1A K1B K3C K3D
– 98 –
CXD2587Q
TRK Servo Gain Up 2 fs = 88.2kHz
TRK
Hold Reg DFCT
2–1
TRK K19
In Reg
To SLD Servo, TRK Hold TRK

AUTO Gain
M0B M0C M0D M0E M0F

K3E K23
Z–1 Z–1 Z–1 Z–1
K36 K37 K38 K3A K3C K3D

27
2–7 2–7
TRK PWM
K39 K3B
TRK JMP
Note) Set the MSB bit of the K39 and K3B coefficients to 0.
SLD Servo fs = 345Hz
TRK SERVO FILTER

second-stage output
K30 TRK
M0D SFSK (only when TGUP2 is used) AUTO Gain
SFID
2–7
M00 M01 M02
2–1 K05 K07
SLD K00 SLD PWM
In Reg Z–1 Z–1
SLD MOV
K01 K03
2–7 2–7
K02 K04
HPTZC/Auto Gain fs = 88.2kHz
2–1
FCS Slice TZC Reg
In Reg AGFON
2–1 M08 M09 M0A AUTO Gain

TRK Slice
Reg
In Reg AGTON Z–1 Z–1 Z–1
AGFON
Sin ROM K14 K15 K17
– 99 –
CXD2587Q
Anti Shock fs = 88.2kHz
2–1
TRK M08 M09 M0A Anti Shock
K12 K35 Comp
In Reg Reg
Z–1 Z–1 Z–1
K31 K16 K33
2–7
K34
Note) Set the MSB bit of the K34 coefficient to 0.

The comparator input is 1/16 the maximum amplitude of the comparator input.
AVRG fs = 88.2kHz
2–1 2–7
VC, TE, FE, M08
AVRG Reg
RFDC
Z–1
TRK Hold fs = 345Hz
TRK SERVO FILTER

second-stage output
K46
M0D THSK (only when TGUP2 is used)
THID
M18 M19 TRK
2–1 K45
K40 Hold Reg
SLD
In Reg Z–1 Z–1
K41 K43
2–7 2–7
K42 K44
FCS Hold fs = 345Hz
FCS M10 M11 FCS

K48 K4D
Hold Reg 1 Hold Reg 2
Z–1 Z–1
K49 K4B
2–7 2–7
K4A K4C
Note) Set the MSB bit of the K4A and K4C coefficients to 0.
– 100 –
CXD2587Q
FCS Servo Gain Normal; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EAXX0)
FCS
Hold Reg 2 DFCT
2–1
FCS K06
In Reg
AGFON
Sin ROM
K06
FCS FCS
K0F Hold Reg 1 AUTO Gain
M03 M04 M05 M06 M07

K11 K13
Z–1 Z–1 Z–1 Z–1

∗ ∗ ∗
81H 7FH K0A K0C 80H K10
27
2–7 2–7 2–7 2–7 2–7
FCS PWM
K08 K09 K0B K0D K0E
FCS SRCH
∗ 81H, 7FH and 80H are each Hex display 8-bit fixed values when set to quasi double accuracy.
Note) Set the MSB bit of the K0B and K0D coefficients during normal operation, and of the K08, K09
and K0E coefficients during quasi double accuracy to 0.
FCS Servo Gain Down; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3E5XX0)
FCS
Hold Reg 2 DFCT
2–1
FCS K06
In Reg
FCS FCS
K2B Hold Reg 1 AUTO Gain
M03 M04 M05 M06 M07

K2D K13
Z–1 Z–1 Z–1 Z–1

∗ ∗ ∗
81H 7FH K26 K28 80H K2C
27
2–7 2–7 2–7 2–7 2–7
FCS PWM
K24 K25 K27 K29 K2A
FCS SRCH
Note) Set the MSB bit of the K27 and K29 coefficients during normal operation, and of the K24, K25
and K2A coefficients during quasi double accuracy to 0.
– 101 –
CXD2587Q
TRK Servo Gain Normal; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EXAX0)
TRK
Hold Reg DFCT
2–1
TRK K19
In Reg
AGTON
Sin ROM
K19
TRK
AUTO Gain
M0B M0C M0D M0E M0F

K22 K23
Z–1 Z–1 Z–1 Z–1

∗ ∗ ∗
81H 7FH K1C K1E 80H K21
27
2–7 2–7 2–7 2–7 2–7
TRK PWM
K1A K1B K1D K1F K20
TRK JMP
Note) Set the MSB bit of the K1D and K1F coefficients during normal operation, and of the K1A, K1B
and K20 coefficients during quasi double accuracy to 0.
TRK Servo Gain up 1; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0)
TRK
Hold Reg DFCT
2–1
TRK K19
In Reg
TRK
AUTO Gain
27
M0B M0C M0E M0F
K3E K23
TRK PWM
Z–1 Z–1 Z–1
∗ ∗ ∗ TRK JMP
81H 7FH 80H K3D
2–7 2–7 2–7

K1A K1B K3C
Note) Set the MSB bit of the K1A, K1B and K3C coefficients during quasi double accuracy to 0.
– 102 –
CXD2587Q
TRK Servo Gain up 2; Fs = 88.2kHz, during quasi double accuracy (Ex.: $3EX5X0)
TRK
Hold Reg DFCT
2–1
TRK K19
In Reg
TRK
AUTO Gain
M0B M0C M0D M0E M0F

K3E K23
Z–1 Z–1 Z–1 Z–1

∗ ∗ ∗
81H 7FH K38 K3A 80H K3D
27
2–7 2–7 2–7 2–7 2–7
TRK PWM
K36 K37 K39 K3B K3C
TRK JMP
Note) Set the MSB bit of the K39 and K3B coefficients during normal operation, and of the K36, K37
and K3C coefficients during quasi double accuracy to 0.
– 103 –
CXD2587Q
§4-21. TRACKING and FOCUS Frequency Response
TRACKING frequency response

40 180°
NORMAL
GAIN UP
30
90°
φ – Phase [degree]
G
G – Gain [dB]
20
0°
10 φ
–90°
0
–10 –180°
2.1 10 100 1K 20K
f – Frequency [Hz]
FOCUS frequency response

40 180°
NORMAL
GAIN DOWN
30
90°
φ – Phase [degree]
G – Gain [dB]
20
G
0°
10
φ
–90°
0
–10 –180°
2.1 10 100 1K 20K
f – Frequency [Hz]
– 104 –
Application Circuit
FG
TD
TG
FD
DOUT
LDON
Vcc
GND
60 59 58 57 56 55 54 53 52 51 50 49 48 47 46 45 44 43 42 41
RFO
FZC
TE
CE
VDD
FILI
VSS
PCO
FILO
ASYI
BIAS
ADIO
IGEN
CLTV
FE
ASYO
RFAC
RFDC
DOUT
AVDD0
AVSS0
AVSS3
AVDD3
LRCK 61 LRCK SE 40
TE
PCMD 62 PCMD FE 39 CE
BCK 63 BCK VC 38 VC
EMPH 64 EMPH XTSL 37
65 XVDD TES1 36
66 XTAI TEST 35
67 XTAO VSS 34
68 XVSS FRDR 33
69 AVDD1 FFDR 32
70 AOUT1 TRDR 31
+5V
71 AIN1 TFDR 30 SSTP
Driver Circuit
72 LOUT1 SRDR 29 SLED
73 AVSS1 SFDR 28 SPDL
– 105 –
GND
74 AVSS2 SSTP 27
75 LOUT2 MDP 26
76 AIN2 LOCK 25 LOCK
77 AOUT2 FOK 24
78 AVDD2 DFCT 23 DFCT
RMUT 79 RMUT MIRR 22 MIRR
LMUT 80 LMUT COUT 21 COUT
XUGF
VDD
SYSM
WFCK
SCLK
XRST
SCOR
XLON
SENS
SQCK
C2PO
SPOB
CLOK
SQSO
GFS
SPOA
XLAT
XPCK
ATSK
DATA
1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20
XLON
XUGF
C2PO
XPCK
WFCK
Application circuits shown are typical examples illustrating the operation of the
devices. Sony cannot assume responsibility for any problems arising out of the use of
SCOR
SENS
DATA
SQCK
GFS
CLOK
MUTE
SQSO
GND
FOK
SCLK
XLAT
XRST
LDON
VDD
these circuits or for any infringement of third party patent and other right due to same.
CXD2587Q
CXD2587Q
Package Outline Unit: mm
80PIN QFP (PLASTIC)
+ 0.35
1.5 – 0.15
+ 0.1
16.0 ± 0.4 0.127 – 0.05
+ 0.4
14.0 – 0.1
0.1
60 41
61 40
(15.0)
+ 0.15
80 21 0.1 – 0.1
1 20
+ 0.15
0.5 ± 0.2
0.65 0.3 – 0.1
0.24 M
0° to 10°
PACKAGE STRUCTURE
PACKAGE MATERIAL EPOXY RESIN
SONY CODE QFP-80P-L03 LEAD TREATMENT SOLDER PLATING
EIAJ CODE QFP080-P-1414 LEAD MATERIAL 42/COPPER ALLOY
JEDEC CODE PACKAGE MASS 0.6g
– 106 –
This datasheet has been download from:
www.datasheetcatalog.com
Datasheets for electronics components.

Sony CXD2587Q

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Sony CXD2587Q

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Copyright:

Available Formats

CXD2587Q

CD Digital Signal Processor with Built-in Digital Servo and DAC

Servo Block SCLK

Notes) • PCMD is a MSB first, two's complement output.

Monitor Pin Output Combinations

Input High level input voltage VIH (1) 0.7VDD V

Input High level input voltage VIH (2) 0.8VDD V

(a) When using self-excited oscillation

(b) When inputting pulses to XTAI pin

Item Symbol Min. Typ. Max. Unit

Low level pulse

Pulse cycle tCX 26 1000 ns

Input high level VIHX VDD – 1.0 V

Input low level VILX 0.8 V

(c) When inputting sine waves to XTAI pin via a capacitor

(2) CLOK, DATA, XLAT and SQCK pin

(3) SCLK pin

Serial Read Out Data MSB ••• LSB

Item Symbol Min. Typ. Max. Unit

(4) COUT, MIRR and DFCT pins

MIRR maximum operating frequency fMIRR 40 kHz ∗2

DFCT maximum operating frequency fDFCTH 5 kHz ∗3

∗1 When using a high-speed traverse TZC.

∗3 During complete RF signal omission.

1-bit DAC and LPF Block Analog Characteristics

Item Symbol Conditions Crystal Min. Typ. Max. Unit

Total harmonic 384Fs 0.0050 0.0070

Signal-to-noise 1kHz, 0dB data 384Fs 96 100

Fs = 44.1kHz in all cases.

12k 12k SHIBASOKU (AM51A)

LOUT1 (2) Audio Analyzer

LPF external circuit diagram

Block diagram of analog characteristics measurement

(VDD = AVDD = 5.0V, VSS = AVSS = 0V, Topr = –20 to +75°C)

§1. CPU Interface

§2. Subcode Interface

§3. Description of Other Functions

§4. Description of Servo Signal Processing System Functions and Commands

§5. Application Circuit .................................................................................................................................. 105

Explanation of abbreviations AVRG: Average

§1. CPU Interface

§1-1. CPU Interface Timing

DATA D0 D1 D18 D19 D20 D21 D22 D23

• The internal registers are initialized by a reset when XRST = 0.

§1-2. CPU Interface Command Table

Total bit length for each register

Register Total bit length

Address Data 1 Data 2 Data 3 Data 4 Data 5

Address Data 1 Data 2 Data 3 Data 4 Data 5

0 0 — — — — — — — — — — — — — — — — — — TRACKING SERVO OFF

1 0 — — — — — — — — — — — — — — — — — — FORWARD TRACK JUMP

1 1 — — — — — — — — — — — — — — — — — — REVERSE TRACK JUMP

— — 1 0 — — — — — — — — — — — — — — — — FORWARD SLED MOVE

— — 1 1 — — — — — — — — — — — — — — — — REVERSE SLED MOVE

0 0 0 0 — — — — — — — — — — — — — — — — SLED KICK LEVEL

0 0 0 1 — — — — — — — — — — — — — — — — SLED KICK LEVEL

0 0 1 1 — — — — — — — — — — — — — — — — SLED KICK LEVEL

KRAM DATA (K00)

Address 1 Address 2 Address 3 Address 4 Data 1 Data 2

KRAM DATA (K10)

KRAM DATA (K20)

KRAM DATA (K30)

Address 1 Address 2 Address 3 Address 4 Data 1 Data 2