Test Time Reduction through Minimum Execution of Tester-Hardware
Setting Instructions
Junichi Hirase
MATSUSHITA ELECTRIC INDUSTRIAL CO., LTD.
Abstract
The introduction of low-priced test systems and the
reduction of the test time are necessary in order to
decrease the testing costs that are included in the
cost of manufacturing VLSI. However, coupled with
the miniaturization of the fabrication process, the test
time tends to become considerably longer for
multi-functional and complex VLSI with high
integration.
In this paper, we present a new method enabling
the automatic reduction of the test time. This method
consists of shortening the test time by installing
virtual tester hardware on the tester CPU memory in
order to delete duplicate tester hardware setting
instructions. The efficiency of this method is proven
by experiments showing that a test time reduction of
5-25% could be obtained.
1. Introduction
While testing is becoming more and more
important following the miniaturization of the
fabrication process for VLSI, the technological
difficulties of this testing are becoming harder to
overcome. One of these problems is that the test time
tends to become considerably longer as the number
of gates increases. The following measures are
adopted as solutions.
1) Design for testability
Scan test patterns with scan design generally have
a shorter number of execution patterns than
functional test patterns. And performing parallel
tests through BIST can also further reduce the test
time.
2) Simultaneous measurements of several devices
In the case of mass production of identical VLSIs,
the testing efficiency can be substantially
improved by measuring several devices
simultaneously. [see Appendix ]
3) Assisted test time reduction
For example, in the case of DC tests, voltage (or
current) is applied to the VLSI terminal and is
then measured after a certain amount of time.
Optimizing the waiting time can thus shorten the
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test time.
In this paper, we will present a new TTO (Test
Time Optimizer) capable of reducing the test time
automatically, without the need for the assistance of
an operator.
2. Program Development: Situation and
Problems
2.1 Program Development
A test program, from the beginning to the end, was
created in the conventional manner by one person or
a small number of persons. This method of
development consisted of adding a new program to
an already completed one. Alternatively, the program
can be made by adding testing conditions specific to
a particular device to a skeleton program designed for
undefined testing conditions.
However, with the higher integration and the
resulting increase in the number and complexity of
functions, the above methods of creating programs
generate low development efficiency. The following
program development method is thus preferred.
1) One test module is prepared for each test item. The
test module itself operates as one test program.
And test modules are prepared for all test items.
2) Next, test modules are combined for each test
category (for example, input leak test, ,output
current test, etc.) or function (core test of a
microprocessor, scan test of a scan circuit, etc.)
and prepared into a single test module group.
3 ) The test program is completed by arranging the
test module groups according to a test flow, thus
producing a high test efficiency (for example,
priority is given to test module groups having a
high detection rate).
2.2 Problems
As shown in Fig. 1, programs composed of test
modules include duplicate instructions that
unnecessarily lengthen the test time.
Although Fig. 1 only shows the case of the voltage
setting, a large number of duplicate instructions can
 also be found for the pin condition configuration.
When the condition configuration is set by pin group
for each test module, one portion of the pins in the
pin group will have the same conditions as for the
previous test, making it necessary to perform a
duplicated hardware setting. Similarly, the hardware
configuration for the setting of the waveform and
timing of the input signal, the comparing timing of
the output signal, etc. (please see Fig.2), is time
consuming. Then deleting these duplicate instructions
would obviously have a considerable effect on the L
INPUT VOLTAGE
reduction of the test time. GENERATOR

TEST XXXX TEST XXXX

VDD=I .8V VDD=I .8V

VIH= 1.OV

VOL=0.8V

E S T WYY

VDD=I .8V
COMPARISON LEVEL

PG: PATTERN GENERATOR

WF: WAVE FORMATTER
FM: F.UL MEMORY
TG: TIMING GENERATOR
DC: DC MEASUREMENT UNIT
Fig. 1 Example of Program Composition PS: POWER SUPPLY UNIT

The execution time for these instructions, utilizing Fig.2 Outline of tester hardware
a tester that we do normally use, is indicated in table
1. In this table, we can observe that, while the CPU Table 1 Example of Tester Execution Time
Memory Setting Instructions and the Execution Time
Instruction
Measurement/Test Execution Instructions represent a (us)
short part of the CPU processing time, the Tester A=B+C 28
Hardware Setting Instructions require a long time JumD hstruction 11
amounting to a 0.3 - 1 ms.
Here, the reason why the tester-hardware setting
instructions take more times is that these instructions
must be executed according to the following
procedure including many contents. Settine
1) If tester CPU meets the tester-hardware setting
instruction, tester CPU sends the tester-hardware
address to the tester bus.
2) When the individual unit of the tester-hardware
can identify the address of tester bus as its own Pin Conditional Setting (1 pin) 281
address, it sends the acknowledgement of Pin Conditional Setting (5 pins) 815
receiving the data or of configuration mismatch Pattern Cycle Setting (4 conditions) 1, 230
to tester CPU. Waveform Timing Setting
3) Tester CPU sends the digital data to be set to 1, 013
(4 conditions)
tester bus again.
4) The corresponded unit receives the digital data

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 Here, we have stripped the comment sentences 3. New Method for Reducing the Test
from a program for a 65k-gate, embedded Time
microprocessor whose peripheral logic portion was
scan designed, and classified those instructions into In order to the duplicate Tester Hardware
Simple Tester ExecutioniMemory Setting Instructions, virtual tester hardware is first
Instructions, Tester Hardware Setting Instructions, installed on the memory. The tester
Measurement Waiting Time Instructions and hardware is composed of memory which houses the
Measurement’Test Execution Instructions7 as shown addresses that enable it to identify the different tester
in the following table 2. As can be Seen in table 2, the hardware units and the actual sett,ng Taking
Tester Hardware Setting Instructions represent 80% the example of the program shown in table the
Of instructions, and we can say that Of the
composition ofthe virtual tester hardware is shown in
test time is spent in the execution of the tester the following
hardware setting and the vector pattern.

Next, the Tester Hardware Setting Instructions of Code Hardware Address Value
the program above were analyzed again and
VDD 00017000 00018000
classified as shown in the following table 3.
VIH 00017100 00010000
We can see that a considerable test time reduction
could be achieved if the duplicate instructions could VOL 00017400 00008000
be removed from the Tester Hardware Setting I I I I
Instructions. In the example shown in table 3,
assuming that the average tester hardware setting The test program is then run according to the
lasts 0.5 ms, a test time reduction of more than 2 following procedure.
seconds would be possible. I ) Each instruction of the test program is interpreted
to determine whether this instruction is or is not a
Tester Hardware Setting Instruction.
Number of Percentage 2) If it is not a Tester Hardware Setting Instruction,
Instructions the instruction is executed and the program
Instructions (%) ~

proceeds to the next instruction.

Simple Tester CPU
3) If it is a Tester Hardware Setting Instruction, the
Execution Instructions
1, 125 9. 9 address of the virtual tester hardware is specified
Tester CPU Memory
and the value stored before the execution of this
Setting Instructions
instruction is compared to the value to be set.
Tester Hardware
9, 537 84. 1 4)If the values are the same, the program proceeds to
Setting Instructions
the next instruction.
IMeasurement Waiting
Time lnstnirtinns
I 1401 1. 21 5 ) Only in instances when the values differ, the
program runs again so as to set the value in the real
Measurement/Test tester hardware.
538 4. 8
Execution Instructions 6) Steps 1) to 5 ) are repeated for all instructions of
Total 11, 340 100 the test program.

Number Of be cut down. In addition, this method causes only a

Instructions
Instructions (“/.I short time increase for Tester Hardware Setting
duplicate 4, 428 46. 4 Instructions that are not duplicated, thereby enabling
Instructions a considerable reduction in the test time.
Non-duplicate
5, 109 53. 6
Instructions The outline of TTO operation is shown in Fig.2 and
I Total 9,537 100 the example of final execution instructions through

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 4. Corroborative Results
OPTIMIZED ( less than 1 p sec)
In order to demonstrate the test time reduction, we
TEST have installed a virtual tester hardware unit on the
PROGRAM memory of the tester CPU and created a utility
program that does not execute the duplicate hardware
POWER S.0V setting instructions included in the instructions of the
INPUT 2.4V/0.8V
test program.
TIMING 20ns
WAVE FORMA1
Rz Here, to fit the actual tester, TTO is carried out
according to the following procedures.
TEST 1 First, as a result of utilizing the Template that can
be used in common for all test engineers to develop
POWER s.nv test program and operate execution of program, the
INPUT 2.4V/0.8V
environment that they can use TTO is made more
TIMING Sons PROCESS
WAVE FORMA1 ( msec order)
simply. Namely, in a same template, we have
Rz programmed the instructions of taking in a
information of setting hardware and also of using the
TEST 2 taken-in data and then for the engineer, the execution
of TTO is possible with only CUI operation. In the
DEVICE case of taking in the information of setting hardware,
it takes in all information on registers at each testing
point and saves only the differential values from the
Fig.2 Outline of TTO operation before testing data as data file in the same template as
test program. Here if the differential value equals
zero, its hardware name and value are deleted from
data file. Once it creates data, it will be available
henceforth. Unless the flow of a test program is
TEST TEST changed, it is possible to continue using it.
PROGRAM PROGRAM Next, each engineer programs whether TTO is
executed or not in a template. In using TTO, for the
POWER S.0V POWER S.0V testing specification of setting hardware, it uses the
INPUT 2.4V/0.8V LNPUT 2.4V/0.8\
TIMING 2011s differential values in the data file. And then test time
rIMING 20ns
WAVE FORMAT is cut down in order to rewrite the minimum
WAVE FORMA?
Rz Rz changing values on tester hardware.
Consequently, the actual operation becomes the
TEST 1 followings.
rEST 1
1) Check PASS result of good device for usual
POWER 5.0V
INPUT 2 . 4 v 1 n . s ~
rIMING Sons mode.
TIMING Sons 2) Select collecting data mode from CUI and a
rEST 2 program is run.
WAVE FORMAT
RZ It is making a data file of differential values from
registers and if the differential value equals zero,
TEST 2 its hardware name and value are deleted from a
data file.
The operation of I ) and 2) are executed once
only a t start of testing.
Fig.3 Example of final execution instructions 3) Select using data mode from CUI and a program
through TTO is running for use the data that was collected in
TTO and the tester-hardware setting instructions
are omitted if their differential values equal zero.

The test time when this utility program is run and

the time required when it is not used are shown in the
following table 5 .
As can be seen from this table, the test time
reduction ratio obtained through the TTO amounts to
5-25%, thus demonstrating the effectiveness of the
present method.

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 function of the tester OS.
The following practical means of reducing the test
Number
time automatically by removing the duplicate Tester
Hardware Setting Instructions such as in the present
method can also be considered.
. The duplicate instructions are removed at the
I3 120.7 3.21 2.45 23.7 combination stage of the test modules in order to
generate a test program that does not include any
C 34.6 7.54 6.75 10.5
duplicate Tester Hardware Setting Instructions.
D 60.8 5.43 4.43 18.4 . The value that is already set on the real tester
E l 40.71 8.951 7.111 20.6 hardware section is compared with the value sent
1
F ! 300.31 2.671 2.471 7.5 from the tester CPU. If these values are identical, a
G 99.6 16.59 14.21 14.3 signal indicating that the setting is completed is
I1 36.4 7.36 7.01 4.8 immediately sent to the CPU. If the values differ, the
hardware value is set through hardware means.
I 150.6 9.85 7.41 24.8
Furthermore, extensions of the present method can
also produce a test time reduction with respect to the
power supply ON/OFF. Upon reception of the final
power-supply OFF instruction of one test module, the
power supply is not immediately turned OFF but is
5. Applications other than Test Time kept ON to proceed to the next test module. Then, if
Reduction the set voltage value for the next test module is the
same as the one of the previous module, the
The present method, which consists of installing power-supply ON instruction of this test module is
virtual tester hardware on the memory of the tester ignored and skipped. If the set voltage values differ,
CPU, could be employed for other applications as the power supply is first turned OFF at this point, the
well. Namely, it could be used for pre-debugging new value for the power-supply voltage is set and the
software, without using tester operation, for test power supply is turned back ON by a power-supply
programs that are composed of a combination of test ON instruction. The test time can thus be shortened
modules. The debugging contents are comprised of by cutting down the number of times the power
the following checks and document output. supply is turned ON and OFF.
A) Check of the presence of a resource in the tester
hardware 7. Acknowledgement
The Tester Hardware Setting Instructions are
interpreted to check whether there is a resource or not, We would like to express our appreciation to many
and whether there are any resources left. engineers of TERADYNE JAPAN Co. Ltd. for their
B) Check of the setting restrictions for the tester cooperation in helping us develop the utility program
hardware to realize our method.
Tester hardware generally has restrictions with
regard to setting values. The debugging software 8. References
checks whether these restrictions are observed. In
particular, while individual test modules do not [ 11 J. Hirase, ”Study on the cost of on-site VLSl testing,”
usually present a problem, transgressions of the Proc. International Test Conference, pp438-443,1995.
restrictions occurring when different test modules are [2] Von-Kyoung, T. Chen & M. Tegethoff, “ASIC
combined are difficult for human operators to spot. manufacturing test cost prediction at early stage,”
C) Document output of the setting values of the tester Proc. International Test Conference, pp356-361, 1997.
hardware [3] J. Hirase, “Economical Importance of the
Maximum Chip Area,” Proc. Seventh Asian Test
Test Specifications are automatically generated Symposium, pp64-68, 1998.
based on this document output.

6. Conclusion
The corroborative experiment has shown that the
TTO enabled us to obtain a test time reduction
amounting to 5 2 5 % thereby proving the
effectiveness of the present method. In the future, we
will focus on making this software more versatile by
widening its use from a utility program to a built-in

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 Appendix
Here, we will discuss the efficiency of numerous
simultaneous measurements.
We will first divide the test time for a single good
deviceT, according to the following equation (A-I ).

L M
T,=CA, + CB, ('4-1)
k= 1 k= 1
A,: Test time of test items for which
simultaneous measurements are possible
B,: Test time of test items for which
simultaneous measurements are not
possible
Test items for which simultaneous measurements
are not possible are items whose testing
specifications are determined based on the device
output results such as the AC test, and the linearity
test of the internal N D and D/A, etc. Assuming that
the test time for defective devices ends within half of
the test time for good devicesT,, the average single
test timeT,,, becomes the following equation (A-2)
[I].

When an N number of devices are measured

simultaneously, the test time for good devicesT, is
expressed by the following equation (A-3).

L M
T,=[l + (N - l)d](.ZAA, +2:BK)
K= 1 K= 1

M
+ ( N - 1) CB,
K=l
+ 1-1 (A-3)

Here, d represents the overhead time of numerous

simultaneous measurements, and 1-1 represents the
prober or handler index time and is valid only for
numerous simultaneous measurements employing 2
heads (for simultaneous measurements using 1 head,
H=O). The average test time for an N number of
simultaneous measurementsTNavis expressed by the
following equation (A-4).

TN[l - ( 1 - Y ) " 1 + Hl/N

64-41
Therefore the testing performance r) becomes the
following equation (A-5).

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