High Speed Ring Generators and Compactors of Test Data
Grzegorz Mrugalski, Janusz Rajski*, Jerzy Tyszer
*
Mentor Graphics Corporation
8005 S.W. Boeckman Road
Wilsonville, OR 97070, USA
Abstract
The paper presents a new highly modular architecture
of generators and compactors of test patterns. This struc-
ture has fewer levels of logic, smaller fan-out, reduced
area, and operates at faster speed than external feedback
LFSRs, internal feedback LFSRs, and cellular automata,
all implementing the same characteristic polynomial.
1. Introduction
High integration of system-on-a-chip designs is chal-
lenging the test realm in a number of ways. To be success-
ful, the newest test technologies must respond to a wide
spectrum of problems related to high performance, small
area, and modular implementations. Linear finite state
machines, structures commonly employed in test applica-
tions to produce or process test data, have to conform to
several requirements, including simple hardware and ease
of automation of its synthesis techniques. Consequently,
many schemes have been proposed to accomplish various
trade-offs. By far the most popular devices used to gener-
ate test sequences, encode test patterns, and compact test
responses are linear feedback shift registers (LSFRs) [3],
[6] and linear cellular automata (CAs) [4].
An n-bit LFSR consists of memory elements and XOR
gates, and can also be represented by its characteristic
polynomial hnxn + hn-1xn-1 + … + h0, where the term hixi
refers to the ith flip-flop of the register, so that, if hi = 1,
then there is a feedback tap taken from this flip-flop.
When proper tap connections are established, the modulo
2 sum of the selected stages is fed back to the first stage of
the LFSR. Such an implementation is called the external
feedback LFSR. An alternative LFSR implementation
with interspersed XOR gates is referred to as the internal
feedback LFSR. Its distinct feature is that the output of the
last stage of the LFSR is fed back to those stages which
are indicated by the characteristic polynomial.
Clearly, for high end systems high speed data genera-
tion and compression can only be achieved by high per-
formance circuits. Unfortunately, the speed of external
feedback LFSRs is limited by the depth of the linear logic
in their feedback paths. Furthermore, implementation of
internal feedback LFSRs involves a large fan-out on the
output of the last stage. In both cases, the limitations of
canonical forms of LFSRs are noticeable for polynomials
with large number of terms. Moreover, irregularity of their
Proceedings of the 21st IEEE VLSI Test Symposium (VTS’03)
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Poznan University of Technology
ul. Piotrowo 3a
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interconnection structures precludes these types of LFSRs
from becoming easily cascadable units. Cellular automata,
though modular, suffer significantly from the resulting
complexity due to at least one XOR gate occurring at each
stage.
Several attempts were made to improve performance of
conventional LFSRs. Papers available in the technical
literature as well as many patents disclose various con-
figurations aimed primarily at providing LFSRs with
higher operating speeds. In particular, the proposed solu-
tions include hybrid designs reducing the number of XOR
gates [13], windmill machines [14] consisting of several
generators with a common stage, decimation techniques
[1], [9] allowing one to sum up a number of m-sequences,
interconnections of several shift registers [8], [15], linear
finite state machines with embedded deterministic patterns
[5], and designs based on T-type flip-flops [1].
11 10 9 8 7 6 5 4 3 2 1 0
x8 x12 x14 x16 x21
12 13 14 15 + 16 17 + 18 + 19 + 20 21 + 22 23
Fig. 1. Ring generator implementing the primi-
24 21 16 14 12
tive polynomial x + x + x + x + x + x + 1
8
In this paper, we describe in depth an architecture of
optimized linear finite state machine called a ring genera-
tor (Fig. 1) and present a methodology to automate its
synthesis process. This novel, high speed modular struc-
ture is capable of generating a desired m-sequence while
having significantly reduced both number of levels of
logic and internal fan-out counts. Consequently, it features
minimal delays on critical paths and the reduced number
of elements driven by the same stem. We will show that in
virtually all practical cases the propagation delay intro-
duced by the feedback logic is reduced to only one 2-input
XOR gate placed between any pair of memory elements.
Moreover, the maximum internal fan-out is limited to only
2 devices fed by any stem in the register. Thus, a typical
ring generator has a smaller number of levels of logic than
a corresponding external feedback LFSR. It also features a
smaller fan-out than the original internal feedback LFSR.
It can, therefore, achieve higher performance than any
other LFSR-based device used so far. Furthermore, with-
out interfering with the feedback polynomial, the ring
 generators let designers minimize routing complexity,
optimize wire sizing, and make the overall layout as com-
pact as possible. Such timing- and layout-friendly struc- A B + C ... Y Z
a b c ... y 0
tures are obtained by transforming conventional LFSRs in α a b ... x y
such a way that many realizations having the same charac- β α a⊕y ... w x
teristic polynomial are generated. These solutions allow
designers to make further trade-offs and meet design ...
A + B C Y Z
goals. The paper also brings a detailed comparative study a b c ... y 0
of earlier schemes and ring generators, emphasizing α a⊕y b ... x y
β α⊕x a⊕y ... w x
modularized architecture of the latter ones. Finally, we
will demonstrate that appropriate phase shifters for ring Fig. 2. Elementary shift left transformation
generators can be synthesized in a time-efficient manner.
LFSR remains a maximum-length circuit. Note that its
state trajectory differs from the original one as an m-
2. Ring architecture sequence produced on flip-flop B has now different phase
Consider a maximum-length LFSR with n memory than before.
elements and a number of feedback connections. Each of As an example, consider a 32-bit internal feedback
the latter components is assumed to comprise a source tap LFSR implementing the primitive polynomial x32 + x18 +
(corresponding to the output of a storage device feeding x14 + x9 + 1, as shown in Fig. 3a. This LFSR has 3 feed-
the connection), the actual feedback line of a span defined back connections, all originating at the output of memory
by a primitive polynomial, and an XOR gate placed at the element 0. Note that the conventional, graphical layout of
destination of the feedback connection, that is, at the input the circuit has been modified by forming a ring structure.
to another storage device. This LFSR can be then trans- It will allow us to demonstrate the most essential changes
formed by moving its feedback connections across mem- after applying the m-sequence preserving transformations.
ory elements so that the original m-sequence is preserved. Fig. 3b illustrates a result of 7-step moving of all feedback
The transformation is said to preserve the m-sequence if lines in a counterclockwise direction. Subsequently, the
the transformed circuit produces on its outputs the same feedback lines associated with coefficients x9 and x14 are
m-sequence as the original LFSR does. moved counterclockwise by 2 positions (Fig. 3c). In a
Fig. 2 illustrates a simple transformation which is used similar manner, the feedback line x9 is further relocated by
to move a single connection line by one memory element 2 positions, what concludes the transformations. The
to the left (only the affected part of the LFSR is shown). resultant structure is shown in Fig. 3d. Circuits similar to
With no loss of generality we can assume that all flip- that one will be further referred to as ring generators.
flops but the rightmost one contain initial
values a, b, c, ... , y. The last memory 15 14 + 13 12 11 10 9 + 8 7 6 5 4 3 2 1 0
element shown in the figure is set to 0.
After one cycle the storage devices contain a)
values α, a, b, ... , x, y, as a new value α 16 17 + 18 19 20 21 22 23 24 25 26 27 28 29 30 31
enters the memory element A. Applying
the next cycle will result in the following 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

content of the storage devices: β , α, a ⊕ y,

... , w, x. The LFSR operation may con- b)
tinue in a similar manner. Now, one can + 16 17 18 19 20 + 21 22 23 24 + 25 26 27 28 29 30 31
move the XOR gate to the input of the
storage device B and relocate the source 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
tap of the feedback line to the output of
flip-flop Y, accordingly. Assuming the c)
same initial state as before, it can be ob- 16 17 + 18 19 20 21 22 + 23 24 + 25 26 27 28 29 30 31
served that the contents of the storage
devices spanned by the former feedback
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
line, that is, flip-flops C, ... , Y, Z, match
the values appearing at the outputs of the d)
same flip-flops in the original circuit, as
16 17 18 19 + 20 21 22 + 23 24 + 25 26 27 28 29 30 31
shown in Fig. 2. Consequently, m-sequen-
ces produced on the outputs of these mem- 32 18 14 9
ory elements are preserved, and the new Fig. 3. LFSRs implementing polynomial x + x + x + x + 1

Proceedings of the 21st IEEE VLSI Test Symposium (VTS’03)

1093-0167/03 $17.00 © 2003 IEEE
 Further examples of ring generators are shown in Fig.
4. These structures implement the primitive polynomials
x32 + x27 + x14 + x12 + 1 and x32 + x28 + x23 + x20 + x17 + x12 +
x8 + x4 + 1. They were obtained by using transformations
applied to internal feedback LFSRs as described earlier.
15 14 13 12 11 10 9 8 7 6 5 4 3 2
x12 x14
16 17 18 19 20 21 + 22 + 23 24 25 26 27 28 + 29
15 14 13 12 11 10 9 8 7 6 5 4 3 2
x4 x8 x12 x17 x20 x23
16 17 + 18 19 + 20 21 + 22 23 + 24 25 + 26 + 27 28 29 + 30
Fig. 4. Examples of ring generators
3. Comparative analysis
Performance and structural properties of internal and
external feedback LFSRs, hybrid LFSRs [13], linear CAs,
and the proposed ring generators are compared in this
section. The following criteria were adopted to compare
various classes of generators: the number of XOR gates
required to implement a given structure, the number of
levels of a feedback logic, the size of internal fan-outs,
and degree of regularity. In all cases, it is assumed that a
generator is to implement a primitive characteristic poly-
nomial of degree n featuring k feedback coefficients (coef-
ficients xn and x0 are not counted).
The number of 2-input XOR gates. Clearly, internal
and external feedback LFSRs require k 2-input XOR
gates. The same applies to the basic form of the ring gen-
erators. Linear cellular automata with null boundary con-
ditions may need 2 XOR gates per each slice except the
boundary stages, if implementation of a given primitive
polynomial consists of cells 150 only, i.e., xc(t+1) = xc-1(t)
⊕ xc(t) ⊕ xc+1(t), for c = 1, …, n-2. In such a case, the
total number of gates is equal to 2n - 2. As demonstrated
in [13], the number of 2-input XOR gates occurring in
hybrid LFSRs amounts to (k + 1)/2. It should be noted,
however, that this result remains valid only for certain
polynomials.
Levels of logic. The effective speed of each class of
generators is determined in terms of the number of 2-input
XOR gates signals have to propagate through which.
Since a feedback logic of external feedback LFSRs can be
implemented as a balanced XOR tree, the actual number
of levels of logic does not exceed the value of log2k. In-
ternal feedback LFSRs have their XOR gates interspersed
between memory elements. Thus, they are expected to be
faster than external feedback LFSRs. However, long feed-
back lines can effectively slow down the whole circuit [7].
Performance of hybrid LFSRs is typically placed between
the aforementioned quantities. Local neighborhood inter-
Proceedings of the 21st IEEE VLSI Test Symposium (VTS’03)
1093-0167/03 $17.00 © 2003 IEEE
actions in CA limit propagation delays to 2 XOR gates.
Indeed, at least one cell 150 must be employed as there
are no maximum length CA featuring rule 90 exclusively
[4]. Clearly, the ring generator is the fastest solution as it
has only one 2-input XOR gate delay and its short feed-
back lines do not cause frequency degradation.
1 0 The internal fan-outs. Since the output from
any switching device has a definite limit to the
x27
amount of current it can supply, there is also a
30 31 limit to the number of other devices that can be
driven by a single output from that switch. In
1 0 order to meet fan-out requirements, buffers are
x28 used to boost and sharpen signals that might
otherwise degrade below switching levels or be
31
distorted. These buffers, however, may further
deteriorate performance of the entire generator,
and therefore the presence of large fan-outs has
to be regarded as disadvantageous. In light of
this, internal feedback LFSRs are particularly susceptible
to delays of this type because of k + 1 fan-out branches
occurring on the output of one of their memory elements.
On the other hand, external feedback LFSRs and ring
generators have internal fan-outs confined to 2 branches.
For the sake of completeness, all quantities discussed
above are gathered in Table I. As can be seen, the superi-
ority of the ring generators is pronounced clearly. They
are the fastest devices, which, at the same time, provide
the best trade-offs between the crucial design factors.
Table I
XOR gates Levels of logic Fan-out
IF LFSR k log2k 2
EF LFSR k 1 k+1
H LFSR (k + 1)/2 (1, log2k) (2, k + 1)
CA 2n - 2 2 3
Rings k 1 2
Modularity. The ring generators (and circuits they
originate from) can also be characterized by their degree
of modularity. A typical modular design paradigm calls
for a clean separation and a well defined interface be-
tween successive components of a given circuit. This is,
therefore, appropriate to assume that any connection (a
wire) in a generator can be used as a cut between candi-
date modules provided it links only two memory elements,
and it does not feature any extra fan-outs. The entire cir-
cuit can be then represented by means of a multigraph
(i.e., having multiple edges between vertices) such that
each vertex corresponds to one module consisting of cer-
tain memory elements and XOR gates. Among various
designs, the one whose multigraph conforms best to a
regular graph (i.e., a graph with all vertices having the
same number of touching edges) is regarded as the most
modular one.
 taps satisfy the following formulas:
C D
15 + 14 13 12 11 10 9 8 7 + 6 5 4 3 2 1 0 Si = (L - Ti) / 2, Di = (Si + Ti) mod L.
A
Ti represents here the span of ith feedback tap, Si and Di
16 17 18 19 20 21 22 23 24 + 25 26 27 28 29 30 31
B are locations of the source and destination taps in the
resultant ring generator, respectively, and L is the size of
A B A B
the entire circuit. For instance, the polynomial x32 + x27 +
a) b)
x14 + x12 + 1 is represented by a sequence T1 = 12, T2 = 14,
D C D C T3 = 27 (entries 0 and 32 do not have to be processed as
they are not the subject of transformations). Hence, the
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
above equations yield the following architecture of the
ring generator: S1 = (32 - 12) / 2 = 10, D1 = 10 + 12 = 22,
A B C D
S2 = (32 - 14) / 2 = 9, D2 = 9 + 14 = 23, S3 = (32 - 27) / 2
16 17 18 + 19 20 21 22 + 23 24 25 26 27 + 28 29 30 31
= 2, D3 = 2 + 27 = 29. We will denote this structure as a
list of pairs: (10,22), (9,23), (2,29). A correspondence
Fig. 5. Modularity – 4 segments
between these numbers and the actual implementation can
Figures 5 and 6 illustrate an internal feedback LFSR be found easily in Fig. 4.
and the corresponding ring generator, both implementing In the sequel, the transformation described in section 2
the primitive polynomial x32 + x25 + x15 + x7 + 1, and both will be referred to as an elementary shift left – EL. In a
subject of partitions into 4 and 7, approximately equally similar manner transformation ER, elementary shift right,
sized modules, respectively. Their multigraphs are also can be applied. Assuming that flip-flop Z of Fig. 2 is
shown. As can be seen in Fig. 5b, the ring generator forms initially reset, all m-sequences produced on bits spanned
a regular graph, while its LFSR counterpart has much less by the feedback line after transformation will be preserved
regular structure (Fig. 5a). Similarly, partition of the regis- as it directly follows from the figure.
ters into 7 modules results in structures shown in Fig. 6, Transformations EL and ER can also handle cases in
with the ring generator again featuring much higher regu- which either an XOR gate or a source tap of a given feed-
larity. Here, the objective was to keep the number of wires back connection crosses another XOR gate or another
between any pair of modules not bigger than 2. Clearly, source tap, respectively. These situations are illustrated in
one may arrive with different partitions (and thus different Fig. 7 and 8. As can be seen, the shorter feedback line can
multigraphs). Typically, however, the ring generators be shifted to the left or to the right, and the circuit will
appear to be much more amenable to implementing modu- remain a maximum-length LFSR. Indeed, as the longer
lar configurations. feedback line keeps providing unaffected content to sev-
eral memory elements as shown in the figures, also this
E
15 + 14 13 12 11 10 9 8 7 + 6 5 4 3 2 1 0 form of the transformation will preserve the maximum-
C D F G length property of the circuit. In this proof we assume that
A
all storage devices are initialized in a manner similar to
16 17 18 19 20 21 22 23 24 + 25 26 27 28 29 30 31
B that of Fig. 2. In particular, flip-flop Q in Fig. 7 and flip-
flop Y in Fig. 8 are both set to 0 when performing trans-
B A G
formations EL and ER, respectively. There are also other
a)
transformations possible [10] which, in particular, can
C D E F change the number of XOR gates. Their application goes,
however, beyond the scope of this paper.
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0

A B C D E F G A B + C ... Q R ... X Y
16 17 18 + 19 20 21 22 + 23 24 25 26 27 + 28 29 30 31
a b c ... 0 r ... x y
α a b⊕x ... p 0 ... w x
b) A B C D E F G β α a⊕p⊕w ... n p ... v w

Fig. 6. Modularity – 7 segments A + B + C ... Q R ... X Y

a b c ... 0 r ... x y
4. Synthesis of ring generators α
β
a⊕p
α⊕n
b⊕x
a⊕p⊕w
...
...
p
n
0
p
...
...
w
v
x
w

It can be verified that in all cases presented in the pre-

vious sections, the ring generators were obtained in such a Fig. 7. Extension of EL (crossing XOR gate)
way that successive locations of source and destination

Proceedings of the 21st IEEE VLSI Test Symposium (VTS’03)

1093-0167/03 $17.00 © 2003 IEEE
 the former locations of the respective XOR gates.
A + B ... Q + R ... X Y Z
11 10 9 8 7 6 5 4 3 2 1 0

a b ... q r ... x 0 z
α a⊕x ... p q⊕x ... w x 0
β α⊕w ... n p⊕w ... v w x
12 13 + 14 15 16 + 17 18 19 20 21 + 22 23
A + B ... Q R + ... X Y Z a)

a b ... q r ... x 0 z
α a⊕x ... p q ... w x 0 11 10 9 + 8 7 6 + 5 4 3 2 + 1 0
β α⊕w ... n p ... v w x

Fig. 8. Extension of ER (crossing source tap)

12 13 14 15 16 17 18 19 20 21 22 23

It is worth noting that there are characteristic polyno- b)

mials for which internal fan-outs cannot be easily reduced.
This is because several non-zero coefficients of the feed-
back polynomial may be associated with consecutive
powers of x. The primitive polynomial x8 + x4 + x3 + x2 + 1
may serve as a good example here. An automated synthe-
sis of ring generators should, therefore, be polynomial
ware and rest on characteristic primitive polynomials
whose coefficients either differ at least by 2, or (prefera-
bly) are uniformly distributed. The latter polynomials
offer approximately the same separation between any two
of their consecutive feedback taps, and they are amenable
to implementing highly modular structures. An example of
such a primitive polynomial is x72 + x64 + x55 + x45 + x37 +
x27 + x18 + x9 + 1. It has been obtained as a result of a
large search program that was launched with the objective
of finding a comprehensive list of primitive polynomials
with uniformly scattered coefficients. Using a technique
described in [12], primitive polynomials featuring 5, 7 and
9 terms were identified for all degrees up to 660. They are
available at www.mentor.com/dft. All listed polynomials
are optimal in the sense of having the most uniformly
distributed taps among all primitive polynomials.
5. Associated phase shifters
Similarly to canonical forms of LFSRs, the standalone
ring generators are not free from structural dependencies
and linearly dependent positions in their output sequences.
As it becomes imperative both to eliminate such depend-
encies and to allow a large number of scan chains to be
driven by ring generators, phase shifters [2], [12] should
be placed between the generators and the serial inputs of
the scan chains they feed. The method of phase shifter
synthesis used here is based on an algorithm presented in
[12]. It generalizes the concept of duality, previously used
to obtain phase shifters for conventional LFSRs. Given
the structure of a ring generator (Fig. 9a), its dual form is
derived by reversing the direction of all feedback connec-
tions (see Fig. 9b). In other words, a dual ring generator
features XOR gates placed on the outputs of those flip-
flops that have been used to drive feedback taps in the
original circuit while the feedback lines originate now at
Fig. 9. Ring generator and its dual form
Let R and D be transition matrices of a given ring gen-
erator and its dual form, respectively. Using a detailed
analysis of the matrices it can be shown that RT = D-1,
where RT is the transpose of R, and D-1 is the inverse of
D. Having this proved, it follows from [12] that [ Rq ]T =
Dm holds, where m = 2n − 1 − q. The last formula indicates
that the contents of the first column of R after q multipli-
cations will also be seen in the first row of D after 2n − 1 −
q multiplications of this matrix by itself. Note that this
row of D can be regarded as the state of the dual ring
generator after 2n − 1 − q clock cycles (provided its initial
value was 10 ... 0). Consequently, in order to obtain the
phase shifter, matrix operations (such as those presented
in [3]) can be replaced with a simple logic simulation of
dual ring structures starting from the state having a single
logic 1 in a pre-selected stage k. In fact, this simulation
can be terminated after q cycles. The content of the dual
circuit, i.e., the locations of 1s, will then indicate which
outputs (called XOR taps) of the generator have to be
XOR-ed to produce a desired string of bits spaced q shifts
down the reference m-sequence, i.e., the m-sequence
originating from the designated stage k of the generator.
The XOR taps can also be generated randomly. The
above procedure is then used to carry out the channel
displacement verification. Let d be its required minimum
value. Lack of an overlap between already obtained se-
quences and a sequence produced by newly generated
XOR taps implies that from a binary combination β repre-
senting the new XOR taps onwards and backwards, for at
least d steps, there is no beginning of another sequence
generated by a linear combination of XOR taps already
included into a phase shifter network. Thus, starting from
the candidate XOR taps, every new combination obtained
during logic simulation of the dual ring generator is com-
pared with accepted XOR taps. If there is a match, the
candidate XOR taps must be rejected as the resulting m-
sequence would overlap with another sequence generated
by XOR taps included earlier into the phase shifter struc-
ture.

Proceedings of the 21st IEEE VLSI Test Symposium (VTS’03)

1093-0167/03 $17.00 © 2003 IEEE
 6. Further applications
Besides acting as sources of pseudo- 15 14 + 13
random test patterns, ring generators can
+ +
be also employed either to perform em-
bedded decompression of test patterns 16 17 + 18 + 19 + 20 21 + 22 + 23
[10], [11] or to act as test response com-
pactors by assuming the role of a MISR
[3]. In these applications, external data
are provided to the register in a form of 15 14 + 13
compressed deterministic test patterns or + +
test responses. In order to accept test data
in parallel, several inputs altogether with 16 17 + 18 + 19 + 20 21 + 22 + 23
additional XOR gates have to be placed
between the register flip-flops, as shown Fig. 10. Ring generator driven by external test data
in Fig. 10a for a 32-bit ring compactor
having 16 parallel inputs and using the primitive polyno-
mial x32 + x25 + x15 + x7 + 1. In many cases, additional
XOR gates may deteriorate the circuit performance as
they introduce extra delays between consecutive stages of
the register (see the input of flip-flop 27 in Fig. 10a).
Fortunately, this problem can be alleviated by applying
transformations to further adjust a feedback tap configura-
tion. This way, one can avoid undesired expansion of the
XOR logic at the inputs of some flip-flops. For instance,
due to transformations presented in the previous sections,
a feedback structure of the circuitry shown in Fig. 10a can
be now rearranged so that a destination tap and a parallel
input do not collide at the input of flip-flop 27, as pre-
sented in Fig. 10b for the same characteristic polynomial
as before. As a result, a single 2-input XOR gate appears
at the input of every flip-flop implementing either a feed-
back tap or a parallel input.
7. Conclusions
In this paper we have introduced a novel methodology
of designing generators and compactors of test data. The
essence of the proposed approach is to use a set of trans-
formations, which alter the structure of the conventional
LFSRs while preserving the maximum length property of
the original circuits. It is shown that after applying the m-
sequence preserving transformations in a certain order, the
resultant circuits feature significantly reduced number of
levels of XOR logic, minimized internal fan-outs, and
simplified circuit layout and routing, as compared to pre-
vious schemes based on LFSRs and CAs. Consequently,
the proposed ring devices can operate at higher speeds
than those of conventional solutions and become highly
modular structures.
References
[1] A.C. Arvillias and D.G. Maritsas, “Toggle-registers gen-
erating in parallel kth decimations of M-sequences Xr ⊗Xi
⊗1: design tables,” IEEE Trans. Comput., vol. 28, No. 2,
Proceedings of the 21st IEEE VLSI Test Symposium (VTS’03)
1093-0167/03 $17.00 © 2003 IEEE
12 + 11 10 + 9 8 + 7 6 + 5 4 + 3 2 + 1 0
+ 24 25 + 26 27 + + 28 29 + 30 31
a)
12 + 11 10 + 9 8 + 7 6 + 5 4 + 3 2 + 1 0
+ 24 25 + 26 + 27 + 28 29 + 30 31
b)
pp. 89-101, 1979.
[2] P.H. Bardell, “Design considerations for parallel pseudo-
random pattern generators,” J. of Electronic Testing: The-
ory and Applications, vol. 1, No. 1, pp. 73-87, 1990.
[3] P.H. Bardell, W.H. McAnney, and J. Savir, Built-in Test
for VLSI: Pseudorandom Techniques, John Wiley &
Sons, 1987.
[4] P.P. Chaudhuri, D.R. Chowdhury, S. Nandi, and S. Chat-
topadhyay, Additive Cellular Automata, IEEE Computer
Society Press, 1997.
[5] C. Dufaza and Y. Zorian, “On some theoretical properties
of LFSRs for BIST applications,” Proc. Int. On-Line Test-
ing Workshop, pp. 184-189, 1997.
[6] S.W. Golomb, Shift Register Sequences, Aegean Park
Press, 1982.
[7] K. Hatayama, M. Nakao, Y. Kiyoshige, and K. Natsume,
“Application of high-quality built-in test to industrial de-
signs,” Proc. ITC, pp. 1003-1012, 2002.
[8] W.J. Hurd, “Efficient generation of statistically good
pseudonoise by linearly interconnected shift registers,”
IEEE Trans. Comput., vol. 23, No. 2, pp. 146-152, 1974.
[9] A. Lempel and W.L. Eastman, “High speed generation of
maximal length sequences,” IEEE Trans. Comput., vol.
20, No. 2, pp. 227-229, 1971.
[10] J. Rajski, J. Tyszer, M. Kassab, and N. Mukherjee,
“Method for synthesizing linear finite state machines,”
USA patent, Serial No. 6,353,842, March 5, 2002.
[11] J. Rajski, J. Tyszer, M. Kassab, N. Mukherjee, R. Thomp-
son, H. Tsai, A. Hertwig, N. Tamarapalli, G. Mrugalski,
G. Eide, J. Qian, “Embedded deterministic test for low
cost manufacturing test,” Proc. ITC, pp. 301-310, 2002.
[12] J. Rajski, N. Tamarapalli, and J. Tyszer, “Automated
synthesis of phase shifters for built-in self-test applica-
tions,” IEEE Trans. CAD, vol. 19, No. 10, October 2000,
pp. 1175-1188.
[13] L-T. Wang and E.J. McCluskey, “Hybrid designs generat-
ing maximum-length sequences,” IEEE Trans. CAD, vol.
7, No. 1, pp. 91-99, 1988.
[14] W.W. Warlick and J.E. Hershey, “High-speed M-
sequence generators,” IEEE Trans. Comput., vol. 29, No.
5, pp. 398-400, 1980.
[15] V.N. Yarmolik and S.N. Demidenko, Generation and
Application of Pseudorandom Sequences for Random
Testing, John Wiley & Sons, 1988.