Results in Physics 54 (2023) 107085

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Results in Physics
journal homepage: www.elsevier.com/locate/rinp

Dynamical analysis and synchronization control of flux-controlled

memristive chaotic circuits and its FPGA-Based implementation
Jing Luo a , Wentao Tang a ,∗, Yao Chen b , Xue Chen a , Huan Zhou a
a
Academy of Electronic and Information Engineering, Jingchu University of Technology, Jingmen, 448000, China
b
Department of Electronics and Information Engineering, Central China Normal University, Wuhan, 430079, China

ARTICLE INFO ABSTRACT

Keywords: This paper focuses on addressing the synchronization control problem of memristive chaos through the
Memristive chaos investigation of a single feedback controller strategy. Our objective is to deploy this strategy on field-
Synchronization control programmable gate arrays (FPGA) with the aim of bolstering the security and reliability of memristive
DSP builder
chaotic synchronization control. Concurrently, we seek to enhance system performance and fulfill the diverse
Single-input feedback controller
requirements of various applications. Initially, the study utilizes chaos synchronization theory and the Routh–
FPGA circuit
Hurwitz stability criterion to devise a feedback controller with a single input. This controller plays a crucial
role in establishing a synchronization system specifically designed for memristive chaos. Subsequently, the
FPGA design approach utilizing DSP Builder is employed to create models for both the single-input feedback
controller and the memristive chaotic synchronization control system. This approach facilitates the efficient
translation of these theoretical concepts into practical digital circuit implementations. Finally, the paper
concludes with an experimental analysis that verifies the feasibility and practical applicability of the FPGA
circuit design for memristive chaotic synchronization control.

Introduction in various domains, including nonvolatile storage [4], logical opera-

Memristor, as the fourth fundamental component, possesses note-
worthy advantages such as rapid read and write speed, high integration
density, and low power consumption. In the realm of nonvolatile
memory storage, memristor demonstrates better circuit design benefits
due to their memory capability and power failure protection. In the
domain of nonlinear circuit and system, memristor serves as novel
circuit device, when combined with capacitor and inductor, can facili-
tate the realization of simple memristive chaotic systems. For instance,
Muthuswamy constructed a physical memristive chaotic analog circuit
composed of resistor, capacitor, inductor, and memristor based on
a memristor model [1]. This achievement has garnered widespread
attention from scholars and stimulated a surge of research in the field of
memristor. As an essentially nonlinear resistor with memory function-
ality, the characteristics of memristor have been successfully emulated
using solid-state devices by Ebong, who demonstrated its ability to
accurately replicate the nonlinear behavior of the memristor through
series and parallel experiments [2]. Furthermore, Chen developed an
artificial flexible visual memory system based on a UV-motivated mem-
ristor, capable of capturing and retaining light information [3]. The
nonlinear and memory attributes of memristor enable their pivotal role
tions [5], chaotic circuits [6–9], and neuromorphic computation [10,
11].
In recent years, the design of chaotic system, particularly those
based on memristor, has progressed rapidly, showing increasingly in-
tricate dynamic behaviors. Njimah introduced a four-vortex chaotic
system comprising two independent memristor-based Duffing oscil-
lators featuring memory nonlinearity. The stability of these chaotic
system was verified through circuit simulation experiments [12]. Ana-
log chaotic circuits built upon memristor are susceptible to exter-
nal interferences such as element aging, ambient temperature fluc-
tuations and noise. To further evaluate the feasibility of memristive
chaotic circuits, Zhang investigated a double memristive chaotic cir-
cuit based on a jerk system, unveiling its highly multistable nature
with respect to initial conditions [13]. Generally, memristive chaotic
system finds frequent application in secure communication due to
their distinct properties [14–16]. Achieving synchronization control
becomes a key challenge in secure communication systems relying
on chaos [17]. Several methods have been proposed to synchronize
memristive chaotic systems, including impulsive control [18,19], pin
control [20,21], adaptive sliding mode control [22–24] and simplified
control input technique [25,26]. Presently, synchronization primarily

∗ Corresponding author.
E-mail address: twt@whu.edu.cn (W. Tang).

https://doi.org/10.1016/j.rinp.2023.107085
Received 10 August 2023; Received in revised form 4 October 2023; Accepted 12 October 2023
Available online 14 October 2023
2211-3797/© 2023 The Author(s). Published by Elsevier B.V. This is an open access article under the CC BY-NC-ND license (http://creativecommons.org/licenses/by-
nc-nd/4.0/).
J. Luo et al.
Fig. 1. The memristive chaotic circuit.
Fig. 2. The phase diagrams: (a) 𝑥1 − 𝑥2 , (b) 𝑥1 − 𝑥3 , (c) 𝑥1 − 𝑥4 , (d) 𝑥2 − 𝑥3 .
Fig. 3. The Lyapunov exponents spectrum of (4) with initial value (0.1, 0, 1, 0.5).
focuses on the numerical simulation stage, with limited exploration of
an analog circuit implementation for chaotic synchronization. Min stud-
ied the mechanism of obtaining sufficient and necessary conditions for
chaotic synchronization under sinusoidal constraints, and verified the
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Results in Physics 54 (2023) 107085
validity of the results through circuit experiments [27]. However, digi-
tal circuits remain unaffected by device parameters and offer more ideal
outcomes compared to analog circuits. Consequently, the realization of
memristive chaotic systems using FPGA presents increased flexibility,
cost-effectiveness and the potential for parallel computation [28–34].
Nonetheless, the employment of FPGA technology for achieving chaotic
synchronization remains an ongoing area of research.
The memristive Chua’s circuit offers a multitude of advantages,
including nonlinear characteristics, a simple yet effective structure, a
wide operational bandwidth, tunability, and effective noise suppression
capabilities. These attributes render it a highly versatile tool, finding
extensive applications in chaotic system modeling, communication sys-
tems, signal processing, and various electronic devices. Combining the
previous analysis, in this work, various characteristics of a chaotic sys-
tem are examined by utilizing a cubic smooth nonlinear memristor. The
analysis includes an investigation of the bifurcation diagram of system,
Poincaré mapping, Lyapunov exponential spectrum and phase wave-
form diagram. By establishing models for the drive system, response
system and error system, we obtain valuable insights. Furthermore,
the synchronization control of memristive chaotic systems by using
a single-input feedback controller is explored. The effectiveness of
the designed synchronization controller is demonstrated by construct-
ing a memristive chaotic synchronization system under its control.
J. Luo et al. Results in Physics 54 (2023) 107085

Fig. 4. The memristive chaotic properties of (4) with parameter 𝛼: (a) The Lyapunov exponents, (b)The bifurcation diagram, (c) The Poincaré mapping of x2 =0, (d) The Lyapunov
dimension.

Additionally, the FPGA technology is employed to implement the mem- where the voltages 𝑉1 , 𝑉2 , the current 𝑖𝐿 are marked in Fig. 1, and
ristive chaotic synchronization. The research presents the following key 𝑀 represents the memristance of the cubic flux-controlled memristor,
contributions: which can be expressed as
(1) The chaos model of flux-controlled memristor is established, the 1 𝑑𝜑 1
memristive chaotic system is normalized and its dynamic characteris- 𝑀 (𝜑) = = = , (2)
𝑊 (𝜑) 𝑑𝑞 𝑎 + 3𝑏𝜑2
tics are analyzed.
(2) A single input controller algorithm is designed to realize syn- where 𝑊 (𝜑) is the memductance of memristor, 𝑎 and 𝑏 are the model
chronization control of memristive chaotic system, and the proposed parameters of the memristor, 𝜑 is the magnetic flux of the memristor,
controller effectively reduces the number of input controllers required. and 𝑞 is the charge amount of the memristor. And the relationship
(3) The memristive chaotic synchronization system is discretized between magnetic flux 𝜑 and voltage is
by Euler algorithm, and the numerical chaotic synchronization model 𝑑𝜑
= 𝑉𝑀 = 𝑉1 , (3)
is built in DSP builder. The feasibility of synchronization control is 𝑑𝑞
verified by FPGA development board. where 𝑉𝑀 is the voltage at both ends of memristor. Consequently, four
The paper is organized as: The model of flux-controlled memristive status variables can be identified: the voltage 𝑉1 , the voltage 𝑉2 , the
chaotic circuit is studied in Section ‘‘Model of flux-controlled mem- current 𝑖𝐿 , and the magnetic flux 𝜑. Based on the principle of circuit
ristive chaotic circuit’’. In Section ‘‘Dynamical analysis’’, the dynamic normalization, let 𝑥1 = 𝑉1 , 𝑥2 = 𝑉2 , 𝑥3 = 𝑖𝐿 , 𝑥4 = 𝜑, while selecting the
characteristics of memristive chaotic system are analyzed by Matlab parameters 𝑅 = 1, 𝐶1 = 𝛼, 𝐶2 = 1, 1∕𝐿 = 𝛽, the formula (1)–(3) can be
software. In Section ‘‘Synchronization of memristive chaotic systems’’, rewritten as
1

a single-input controller is given to realize synchronization control. In [ ( ) ]

Section ‘‘FPGA circuit implementation’’, the memristive chaotic syn- ⎧𝑥̇ 1 = 𝛼 𝑥2 − 𝑥1 − 𝑎 + 3𝑏𝑥24 𝑥1 ,
⎪
chronization control is studied by DSP builder. Finally, the conclusion ⎪𝑥̇ 2 = 𝑥1 − 𝑥2 + 𝑥3 ,
⎨ (4)
is summarized in Section ‘‘Conclusion’’.
⎪𝑥̇ 3 = −𝛽𝑥2 ,
⎪
Model of flux-controlled memristive chaotic circuit ⎩𝑥̇ 4 = 𝑥1 .
The phase diagrams of (4) are depicted in Fig. 2, with the initial
In the realm of electrical circuits, Muthuswamy has ingeniously values of (𝑥1 , 𝑥2 , 𝑥3 , 𝑥4 ) set as (0.1, 0, 1, 0.5). For 𝛼 = 9, 𝛽 = 14, 𝑎 =
fashioned a memristive chaotic circuit by substituting Chua’s diode −1.2, 𝑏 = 0.2, clear evidence of a chaotic attractor phenomenon is
within Chua’s chaotic circuit with a cubic smooth nonlinear memristor observed. To further confirm the presence of chaos, the Lyapunov
model [1], as visually represented in Fig. 1. exponents of (4) are calculated. By using a sampling interval of 0.02
From Fig. 1, it shows that the memristive chaotic circuit has a and a running time of 1000, the following Lyapunov exponents are
similar structure to Chua’s chaotic circuit. By applying Kirchhoff’s obtained using Wolf algorithm [35]: 𝐿𝐸1 = 0.2602, 𝐿𝐸2 = 0.0022,
circuit law, the memristive chaotic circuit can be derived as follows: 𝐿𝐸3 = −0.0046, 𝐿𝐸4 = −3.7964. These calculated results demonstrate
1 ( )
⎧ 𝑑𝑉1 1
that the system satisfies the requirements for chaos. The corresponding
⎪ 𝑑𝑡 = 𝑅𝐶1 𝑉2 − 𝑉1 − 𝑀𝐶1 1
𝑉 , Lyapunov exponent spectrum of (4) is presented in Fig. 3. Assume the
⎪ 𝑑𝑉2 1 ( ) 1 status variables 𝑥1 = 𝑥2 = 𝑥3 = 𝑥4 = 0, by calculation, the set of
⎨ 𝑑𝑡 = 𝑅𝐶2 𝑉1 − 𝑉2 + 𝑖 , (1)
𝐶2 𝐿
⎪ 𝑑𝑖 equilibrium points of (4) is 𝑆 = {𝑋 = (𝑥1 , 𝑥2 , 𝑥3 , 𝑥4 ) ∈ 𝑅4 ∣ 𝑥1 = 0, 𝑥2 =
⎪ 𝐿 = − 1 𝑉2 , 0, 𝑥3 = 0, 𝑥4 ∈ 𝑅}. That is, (4) has an infinite number of equilibrium
⎩ 𝑑𝑡 𝐿

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J. Luo et al. Results in Physics 54 (2023) 107085

Fig. 5. The attractors of (4): (a) Fixed point of 𝛼 = 3, (b) Limit cycle of 𝛼 = 7, (c) Two-dimensional quasi-periodic torus of 𝛼 = 8.1, (d) Chaotic trajectory of 𝛼 = 9.

points and possesses hidden attractor [32]. The Kaplan–Yorke fractal ristive chaotic dynamic system (4) mentioned earlier serves as the
𝐿𝐸 +𝐿𝐸 +𝐿𝐸
dimension of (4) is calculated as 𝐷𝐾𝑌 = 3 + 1 ∣𝐿𝐸2 ∣ 3 = 3.0679064. memristive chaotic driving system, while the corresponding response
4
system is represented by the following equation:
Dynamical analysis [ ( ) ]
⎧𝑦̇ 1 = 𝛼 𝑦2 − 𝑦1 − 𝑎 + 3𝑏𝑦24 𝑦1 + 𝑢,
⎪
In this section, we utilize Matlab for numerical simulation to exam- ⎪𝑦̇ 2 = 𝑦1 − 𝑦2 + 𝑦3 ,
⎨ (5)
ine the dynamic behavior of (4) with varying parameters and initial ⎪𝑦̇ 3 = −𝛽𝑦2 ,
conditions. Specifically, we set 𝛽 = 14, 𝑎 = −1.2, 𝑏 = 0.2, and the ⎪
⎩𝑦̇ 4 = 𝑦1 ,
initial values of (𝑥1 , 𝑥2 , 𝑥3 , 𝑥4 ) set as (0.1, 0, 1, 0.5). The results, including
where 𝛼 and 𝛽 denote the parameters of the chaotic system, 𝑎 and 𝑏 rep-
the Lyapunov exponents, the bifurcation diagram with respect to the
parameter 𝛼, the Poincaré diagram with x2 =0, and the Lyapunov resent the model parameters of the cubic smooth nonlinear memristor.
dimension, are presented in Fig. 4. From Fig. 4, it is evident that (4) In contrast to the drive system, the chaotic response system incorpo-
exhibits chaotic behavior within the range 𝛼 ∈ [8.15, 10], as depicted rates a feedback control variable 𝑢, where 𝑢 serves as the memristive
in Fig. 4(a). Additionally, Fig. 4(b) reveals that the points are clustered chaotic synchronization controller to be designed. The synchronization
around specific locations. The Poincaré section in Fig. 4(c) exhibits error is obtained by calculating the difference between Eqs. (4) and (5),
a two-dimensional pattern with the emergence of a fractal structure. which can be expressed as:
Furthermore, Fig. 4(d) demonstrates that the Lyapunov dimension 𝑒𝑖 = 𝑦 𝑖 − 𝑥 𝑖 , 𝑖 = 1, 2, 3, 4, (6)
exhibits a fractional dimension. Fig. 5 shows the phase diagram of (4)
transitioning from a fixed point to chaos as the system parameters 𝛼 where 𝑒𝑖 , 𝑖 = 1, 2, 3, 4 signifies the error signal of the status variable.
are successively chosen as 3, 7, 8.1, and 9. Then
Next, considering the initial values of (𝑥1 , 𝑥2 , 𝑥3 , 𝑥4 ) set as ( )
⎧𝑒̇ 1 = −(1 + 𝑎)𝛼𝑒1 + 𝛼𝑒2 + 3𝛼𝑏 𝑥1 𝑥24 − 𝑦1 𝑦24 + 𝑢,
(0.1, 0, 1, 0.5), we take 𝛼 = 9, 𝑎 = −1.2, 𝑏 = 0.2, when the parameter 𝛽 ∈ ⎪
[10, 15], the corresponding Lyapunov exponents and the bifurcation ⎪𝑒̇ 2 = 𝑒1 − 𝑒2 + 𝑒3 ,
⎨ (7)
diagram are depicted in Fig. 6. We take 𝛼 = 9, 𝛽 = 14, 𝑏 = 0.2, when ⎪𝑒̇ 3 = −𝛽𝑒2 ,
the parameter 𝑎 ∈ [−1.5, −1], the corresponding Lyapunov exponents ⎪
⎩𝑒̇ 4 = 𝑒1 .
and the bifurcation diagram are shown in Fig. 7. We take 𝛼 = 9,
𝛽 = 14, 𝑎 = −1.2, when the parameter 𝑏 ∈ [0.1, 0.5], the corresponding In this section, in order to sure that the error system (7) converges
Lyapunov exponents and the bifurcation diagram are depicted in Fig. 8. to zero under the influence of a single-input feedback controller. In this
way, the synchronization problem between the response system (5) and
Synchronization of memristive chaotic systems the drive system (4) is transformed into an analysis of the stability
of system (7). In other words, we need to devise control strategies
to guarantee lim𝑡→∞ 𝑒𝑖 = 0, (𝑖 = 1, 2, 3, 4), indicating that the chaotic
The chaos synchronization controller plays a crucial role in the
memristive chaotic synchronization control system, as its performance response system and the drive system can maintain synchronization.
directly affects the quality of chaotic synchronization control. In this Therefore, we construct a single-input controller as follows:
section, we aim to achieve memristive chaotic synchronization control 𝑢 = 𝜇1 𝑒1 + 𝜇2 𝑒4 + 𝜅, (8)
by designing a single-input controller based on the Routh–Hurwitz
( )
stability criterion and utilizing the drive-response model. The mem- where 𝜇1 , 𝜇2 are constants, and 𝜅 = −𝛼𝑒2 − 3𝛼𝑏 𝑥1 𝑥24 − 𝑦1 𝑦24 .

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J. Luo et al. Results in Physics 54 (2023) 107085

Fig. 6. The memristive chaotic properties of (4) with parameter 𝛽: (a) The Lyapunov exponents, (b) The bifurcation diagram.

Fig. 7. The memristive chaotic properties of (4) with parameter 𝑎: (a) The Lyapunov exponents, (b) The bifurcation diagram.

Fig. 8. The memristive chaotic properties of (4) with parameter 𝑏: (a) The Lyapunov exponents, (b) The bifurcation diagram.

Theorem 1. Assume that the parameters 𝜇1 , 𝜇2 in (8) satisfy Substituting (8) into (10) obtains
{
𝜇1 < −1.8, ⎧𝑒̇ 1 = (𝜇1 − 𝛼 − 𝑎𝛼)𝑒1 + 𝜇2 𝑒4 ,
(9) ⎪
𝜇2 < 0,
⎪𝑒̇ 4 = 𝑒1 ,
⎨ (11)
then under the proposed controller 𝑢, the error system (7) can converge ⎪𝜔̇ = 𝜁(𝑒1 , 𝜔),
asymptotically, that is, the chaotic response system (5) can synchronize with ⎪
⎩𝑦 = 𝑒 1 ,
the chaotic drive system (4).
( )𝑇 ( )𝑇
where 𝜔 = 𝜔1 , 𝜔2 and 𝜁(𝑒1 , 𝜔) = 𝑒1 − 𝜔1 + 𝜔2 , 𝛽𝜔1 .
Proof. Let 𝜔1 = 𝑒2 , 𝜔2 = 𝑒3 , (7) can be rewritten as
To ensure the minimum phase property of system (11), which
( )
⎧ 𝑒̇ 1 = −(1 + 𝑎)𝛼𝑒1 + 𝛼𝑒2 + 3𝛼𝑏 𝑥1 𝑥2 − 𝑦1 𝑦2 + 𝑢, involves the convergence and asymptotic stability of the zero dynamic
4 4
⎪
⎪𝜔̇ 1 = 𝑒1 − 𝜔1 + 𝜔2 , subsystem 𝜔̇ = 𝜁(0, 𝜔) at the origin, it is crucial to demonstrate that
⎪
⎨𝜔̇ 2 = 𝛽𝜔1 , (10) system (11) maintains internal stability even when the output 𝑦 is 0.
( )𝑇
⎪ Given that the subsystem 𝜔 = 𝜔1 , 𝜔2 is bounded, it is possible to
⎪ 𝑒̇ 4 = 𝑒1 ,
⎪ 𝑦=𝑒 . transform the zero dynamic subsystem as follows:
⎩ 1

where 𝑒1 is the output of system (7). 𝜔̇ = 𝐾𝜔, (12)

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J. Luo et al. Results in Physics 54 (2023) 107085

Fig. 9. The design of memristive chaotic circuit by DSP Builder.

Fig. 10. The phase diagram of x1 − x4 based on FPGA development board.

where the matrix 𝐾 can be represented where

[ ]
−1 1 𝜇 − 𝛼 − 𝑎𝛼 𝜇2
𝐾=[ ], (13) 𝐵= 1 . (15)
−𝛽 0 1 0
then the eigenvalue expression of matrix 𝐾 can be represented as Then, by substituting parameters, the characteristic equation of the
𝜆2 + 𝜆 + 14 = 0. As it is known that the real parts of the eigenvalues matrix 𝐵 is
of matrix 𝐵 are all negative, matrix 𝐾 can be classified as Hurwitz.
Consequently, (12) satisfies the Routh–Hurwitz stability condition. This 𝜆2 − (1.8 + 𝜇1 )𝜆 − 𝜇2 = 0. (16)
implies that the zero dynamic subsystem 𝜔̇ = 𝜁(0, 𝜔) can asymptotically
If all the real parts of the eigenvalues of matrix 𝐵 are negative,
converge to the origin. Thus, it is demonstrated that if the output 𝑦
indicating that matrix 𝐵 is a Hurwitz matrix, then system (14) satisfies
is 0, the subsystem 𝜔̇ = 𝜁(0, 𝜔) will also converge asymptotically to
the Routh–Hurwitz stability condition. Consequently, the errors 𝑒1 and
zero.
( )𝑇 𝑒4 can converge and asymptotically approach zero. Thus, it is necessary
Let 𝜃1 = 𝑒1 , 𝜃2 = 𝑒4 and 𝜃 = 𝜃1 , 𝜃2 , one has
to ensure that the controller parameters 𝜇1 and 𝜇2 satisfy the inequality
𝜃̇ = 𝐵𝜃, (14) (9), specifically, 𝜇1 < − − 1.8 and 𝜇2 < 0.

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J. Luo et al.
Fig. 11. DSP Builder model of the designed controller.
In summary, when the controller parameters 𝜇1 and 𝜇2 satisfy
the inequality (9), it guarantees that system (15) fulfills the Routh–
Hurwitz stability condition, resulting in the asymptotic convergence
of the errors 𝑒1 and 𝑒4 to zero. Furthermore, by constructing the zero
dynamic subsystem 𝜔̇ = 𝜁(0, 𝜔) and ensuring its convergence to zero,
the overall error system (7) achieves asymptotic stability. Thus, the
proof is concluded.
FPGA circuit implementation
Discretization of memristive chaotic synchronization control system
In this section, the crucial step for implementing the memristive
chaotic synchronization control system in FPGA is the discretization
process. To accomplish this, we employ the classical Euler method for
numerically solving the differential equations. As a result, the discrete
model of Eq. (4) can be obtained as follows:
⎧𝑥1(𝑛+1) = 𝑥1(𝑛) + (1.8𝑥1(𝑛) + 9𝑥2(𝑛) − 5.4𝑥24(𝑛) 𝑥1(𝑛) )𝑡,
⎪ data resolution of 14 bits, and the output voltage range is ±5V. The
⎪𝑥2(𝑛+1) = 𝑥2(𝑛) + (𝑥1(𝑛) − 𝑥2(𝑛) + 𝑥3(𝑛) )𝑡,
⎨ (17)
⎪𝑥3(𝑛+1) = 𝑥3(𝑛) + (−14𝑥2(𝑛) )𝑡,
⎪ worth noting that Fig. 10 reveals a double-scroll chaotic structure.
⎩𝑥4(𝑛+1) = 𝑥4(𝑛) + (𝑥1(𝑛) )𝑡,
and the corresponding response system is
⎧𝑦1(𝑛+1) = 𝑦1(𝑛) + (1.8𝑦1(𝑛) + 9𝑦2(𝑛) − 5.4𝑦24(𝑛) 𝑦1(𝑛) + 𝑢(𝑛) )𝑡,
⎪ gain modules.
⎪𝑦2(𝑛+1) = 𝑦2(𝑛) + (𝑦1(𝑛) − 𝑦2(𝑛) + 𝑦3(𝑛) )𝑡,
⎨ (18)
⎪𝑦3(𝑛+1) = 𝑦3(𝑛) + (−14𝑦2(𝑛) )𝑡,
⎪ an initial value of (0.1, 0.01, −0.1, 0). The controller module from Fig. 11
⎩𝑦4(𝑛+1) = 𝑦4(𝑛) + (𝑦1(𝑛) )𝑡.
Meantime, the discrete model of designed controller 𝑢 can be rewritten
as
𝑢(𝑛) = −9(𝑦1(𝑛) − 𝑥1(𝑛) ) − 9(𝑦2(𝑛) − 𝑥2(𝑛) ) − 9(𝑦4(𝑛) − 𝑥4(𝑛) )
(19)
+ 5.4(𝑦24(𝑛) 𝑦1(𝑛) − 𝑥24(𝑛) 𝑥1(𝑛) ).
FPGA implementation of memristive chaotic synchronization control system
To implement the memristive chaotic circuit in an FPGA, we se-
lected specific versions of development software: MATLAB 2013a,
Quartus II 13.0, and DSP Builder 13.0. DSP Builder plays a significant
role as part of a programmable system on a chip, bridging the gap
between simulation and RTL-level design. It enables the design of
DSP digital systems based on FPGA. For our implementation, we set
the initial condition to (0, 0.1, 0, 0) and constructed the discrete model
(17) of the memristive chaotic circuit using adders, digital multipliers,
proportional amplifiers, and multiplexers from the DSP Builder toolbox,
as depicted in Fig. 9. From Fig. 9, it is evident that the Multiplexer
serves as a data selector, enabling the iterative processing of data. It
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Results in Physics 54 (2023) 107085
returns the system’s value k times to the input, yielding the k+1 output
value. The Single Pulse, on the other hand, functions as a shock signal
generator, producing a stable 0/1 bit stream. This bit stream acts as
a reference clock for the iterative operations of the digital integrator.
Within this framework, you will find various modules such as the
Adder, Gain, Product, and AltBus. These modules function as adders,
multipliers, gain controllers, and buses, respectively. To initiate the
process, the initial value (0, 0.1, 0, 0) of the memristive chaotic circuit
is introduced into the input ports of four data selectors in sequence,
facilitated by the Constant module. Moreover, to ensure precision in the
digital-to-analog (DA) output, the Output module is configured with a
4-bit integer part and a 10-bit decimal part.
Next, we utilize the Signal Compiler module to analyze and synthe-
size the memristive chaotic circuit designed in DSP Builder, generating
a Quartus project using VHDL language. The main FPGA chip employed
is the Cyclone IV series EP4CE10F17C8N, while the DAC module
utilize a high-speed dual-channel DAC chip, DAC904E, capable of
outputting dual-channel digital-to-analog signals. Each channel has a
memristive chaotic hardware circuit is designed on the FPGA, and the
corresponding phase diagram of x1 − x4 is presented in Fig. 10. It is
Using the DSP Builder toolbox, we built the DSP Builder model
of the memristor chaotic synchronization controller, as depicted in
Fig. 11. This controller design comprises parallel adder subtractor and
Referring back to Fig. 9, we developed the discrete model (18) of the
memristive chaotic response circuit using the DSP Builder toolbox, with
was applied to the response circuit, while the DAC module was used to
output the driver and response status curves, as shown in Fig. 12. In
Fig. 12, we can see that under the influence of the controller, the error
status variables quickly converge and asymptotically stabilize at zero.
Conclusion
This paper introduces an FPGA implementation of a memristive
chaotic synchronization control circuit. Based on the traditional FPGA
design process, an FPGA implementation method based on DSP Builder
is proposed. Using this method, the FPGA implementation of the mem-
ristive chaotic system and the FPGA implementation of the memristive
chaotic synchronization control circuit under single input control are
carried out respectively. Based on the FPGA development board, the
actual memristive chaotic synchronization control circuit is built and
related experiments are carried out. The experimental results show that
the FPGA circuit of the designed chaotic synchronization controller has
good performance, and the FPGA circuit of the chaotic synchronization
control can quickly synchronize and maintain stability.
J. Luo et al. Results in Physics 54 (2023) 107085

Methodology, Software. Xue Chen: Conceptualization, Writing – re-

view & editing. Huan Zhou: Software, Supervision, Validation.

Declaration of competing interest

We declare that we have no financial and personal relationships

with other people or organizations that can inappropriately influence
our work, there is no professional or other personal interest of any
nature or kind in any product, service and/or company that could be
construed as influencing the position presented in, or the review of, the
manuscript entitled.

Data availability

No data was used for the research described in the article.

Acknowledgments

This work was jointly supported by the National Natural Science

Foundation of China (grants number: 42174189, 41974176), the Jing-
men science and technology planning project, China (grants number:
2022ZDYF017, 2022YFYB011), and the excellent young and middle-
aged scientific and technological innovation team project of universities
in Hubei Province, China (grant number: T2021028).

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