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FT-LFSR: A Fault Tolerant Architecture for Linear Feedback Shift Registers

Conference Paper · March 2021

DOI: 10.1109/CSICC52343.2021.9420598

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 FT-LFSR: A Fault Tolerant Architecture for
Linear Feedback Shift Registers
Mohammad Zaree
School of Electrical and Computer Engineering
Shiraz University
Shiraz, Iran
m.zaree@cse.shirazu.ac.ir
Abstract—Linear Feedback Shift Registers (LFSR) are exten-
sively used in variety of applications such as Built-In-Self-Test
circuits or Pseudo Random Number Generators. Hence, fault
tolerant design of LFSR is essential for the applications with
high reliability demands. Traditional fault tolerant LFSRs include
large number of Single-Point-of-Failures (SPoFs) in which any
fault results in the whole system failure. In this paper, a new
fault tolerant architecture for LFSR (named as FT-LFSR) is
proposed in which the number of SPoFs are significantly reduced
compared to the previous ones. To this end, a modified version of
Triple Modular Redundancy (TMR) empowered with some extra
controlling units for identifying the operational module is used.
In addition, a novel metric called Reliability-Area-Factor (RAF)
is introduced to evaluate the efficacy of the redundancy-based
fault tolerant techniques (such as FT-LFSR) in terms of number
of SPoFs and the area overhead. Experimental results show that,
the FT-LFSR is resilient to all single transient and permanent
faults except in its limited SPoFs and many patterns of multiple
faults.
Index Terms—LFSR, Fault tolerance, FPGA, TMR, Test, Built
in self test.
I. I NTRODUCTION
Linear Feedback Shift Register (LFSR) is the main com-
ponent of the embedded systems that are based on pseudo-
random bit sequences such as pseudo-random number and
pseudo-noise sequence generators, fast digital counters, and
Built-In-Self Tests [1], [2], [3], [4], [5]. In real-time and
safety-critical embedded applications, incorrect functionality
may cause catastrophic effects and thus, the fault-tolerance is
known as a traditional design requirement. In recent years, the
continuous reduction of the transistor dimensions and supply
voltage levels have led to an increase in the vulnerability
of Integrated Circuits (ICs) against various hardware faults.
Therefore, fault tolerant design of LFSR considering hardware
faults is very essential in safety-critical embedded applications.
The key concept of fault tolerance is redundancy; i.e. the
extra capabilities are added to the original design which are
not necessary in fault-free operation. The redundancy can be
spatial and/or temporal. Triple Modular Redundancy (TMR)
is a well-known and common fault tolerant technique based
on spatial redundancy [9]. In TMR, the design is triplicated to
perform a process in parallel and their result is processed by
a majority-voting system to produce a single output. Despite
its efficacy, there is a major vulnerability in TMR technique
Mohsen Raji
School of Electrical and Computer Engineering
Shiraz University
Shiraz, Iran
mraji@shirazu.ac.ir
called as Single-Point-of-Failure (SPoF). SPoF is defined as
the design point that will result in the entire system failure if it
fails [6]. The majority-voting system in TMR is accounted as
its SPoF. So, the number of SPoF is required to be considered
in TMR-based fault tolerant techniques. Some previous works
have proposed fault tolerant LFSR designs [7], [8] which are
based on TMR approach. Although, they have provided fault
tolerance against single fault, the number of SPoFs is increased
significantly by triplicating the majority-voting system, leading
to a considerable decrease in the reliability of the design.
In this paper, a new fault tolerant LFSR (named as FT-
LFSR) is proposed in which the number of SPoFs is sig-
nificantly reduced. To this end, a modified version of TMR
empowered with some extra controlling units for identifying
the operational module is used. We also introduce a novel
comparison metric called Relaibilty-Area-Factor (RAF) to
compare the TMR-based fault tolerance techniques in which
the number of SPoFs and area overhead of TMR approach is
taken into consideration. The proposed design is simulated
and implemented using Verilog on Xilinx Spartan 6. The
fault injection-based experimental results show that, FT-LFSR
tolerates all single transient and permanent faults (except the
ones which occur in its limited SPoFs) and many patterns of
multiple faults.
The rest of the paper is organized as follows: Section
II is about LFSR. Section III explains previous works in
which a fault tolerant LFSR is presented. Section IV explains
architecture of FT-LFSR. Section V introduces RAF. Section
VI is about RAF analysis of FT-LFSR. Section VII talks about
fault injection in different parts of FT-LFSR. Section VIII
shows simulation and report analysis with 16, 32 and 64 bit
LFSR and finally, section IX concludes the paper.
II. BACKGROUND
LFSR is a state machine composed of a shift register whose
input bit is a linear function of its previous state. There are two
main forms of LFSR; i.e. Galois and Fibonacci configurations.
In the Fibonacci implementation, the outputs from some of the
registers are XORed with each other and fed back to the input
of the shift register. In the Galois implementation, the gates
are placed between the registers. In Figure 1 the conventional
Fibonacci and Galois LFSR implementations are shown. n

Fig. 1. LFSR structure. (a) Fibonacci implementation; (b) Galois implemen-
tation.
denotes the length of the LFSR, i.e., the number of flip-flops,
DF0 , ..., DFn , in the register.
c0 , c1 , ..., cn are the binary coefficients that correspond to
n + 1 feedback terms. The numbering of the feedback for the
Galois implementation is the reverse of that for the Fibonacci
variant. The characteristic polynomial for the LFSR with n
flip-flops has the following form:
c0 .1 + c1 .x + c2 .x2 + ... + cn−1 .xn−1 + cn .xn
when ci = 1, It means that a connection exists and the
respective feedback is set. On the contrary when ci = 0
implies that no connection exists and the corresponding XOR
gate can be replaced by a direct connection from its input to
its output [8]. Both c0 and cn are always equal to one [13],
[14].
The initial value of the LFSR is called the seed. A LFSR
with a well-chosen feedback function can produce a sequence
of parallel words, which appears random in nature but has
a finite number of possible states with a very long repeating
cycle. The outputs that influence the inputs are named taps.
The sequences generated by both the Fibonacci and Galois
implementations go through all possible 2n − 1 states except
the forbidden all-zero state, in which case it will never change.
Only characteristic polynomials that are primitive (in the
mathematical sense) cause the LFSR to go through all possible
states and to repeat with a period of 2n − 1. The output of such
a LFSR configuration is called a maximum-length sequence.
In the sequel, we will focus on Fibonacci LFSRs. Such LFSRs
have been proven to be equivalent to Galois LFSR with respect
to the property of generating the same output vectors. [7], [8]
III. R ELATED W ORKS
In [7] and [8], the fault tolerant architecture shown in Fig 2
is proposed for LFSRs (which we call it P-LFSR), the TMR
technique is used in which the original design is triplicated
and similar inputs are fed into the modules. The final output
is obtained based on majority voting (which is not shown in
Fig 2) on the outputs of the three voters (voter 1, voter 2, and
voter 3). So, the last majority voter (which includes N one-
bit voters) is the SPoF of this architecture and any fault in
the last voter leads to the system failure. Therefore, although
this architecture tolerates the single faults in the intermediate
points of the circuit, its reliability is threatened by N SPoFs.
Fig. 2. P-LFSR structure
IV. FT-LFSR: T HE PROPOSED FAULT TOLERANT
(1) A RCHITECTURE FOR LFSR
In this section, we describe the fault tolerant architecture
proposed for LFSRs called FT-LFSR. The proposed archi-
tecture is shown in Fig 3. FT-LFSR has three PEs1 and
one voter based on TMR approach with Contorller module
which reduces the number of SPoFs. This architecture has
two outputs 2 and one input 3 :
1. out sel.
out sel comes from a module which controlls the FT-
LFSR (e.g. BIST4 ) and determines which PE must be
connected to FT LFSR out (selected PE).
2. FT LFSR out.
FT LFSR out is the N bit output of selected PE which
is the same as a conventional LFSR's output.
3. ready.
ready shows that FT LFSR out is valid or not. if ready
equals one, it means that FT LFSR out is valid and
otherwise it means invalid.
To demonstrate how this FT-LFSR works from when input
is given untill two outputs are ready, the following steps are
done respectively:
1 PE corresponds to Processing Element. Each PE is a conventional LFSR.
2 the second and third items
3 clock and reset are also the inputs of FT-LFSR but they are not shown in
the figure to not make it messy.
4 Built In Self Test
 Fig. 3. The block diagram of the proposed FT-LFSR
1. At first, out sel which is a 2-bit input for Controller, is
initialized. Then Controller decides which PE LFSR out
5
must be connected to FT LFSR out.
2. Now FT LFSR out is available. This output goes to PEs
to compare. Controller signals which PE is selected PE
by selectedA, selectedB and selectedC.
3. Each PE based on being selected or not determines to
compare its output with whom. Selected PE compares its
output with two other PE's outputs and other PEs com-
pare their outputs just with FT LFSR out (selected PE's
output). After comparison, each PE produces PE ready
that shows correctness of FT LFSR out based on its
point of view. If no mismatch in total N bits occurs then
P E ready = 1 ,otherwise P E ready = 0.
4. Finally, Voter which is a majority voter, votes between
PE readys of PE A, PE B and PE C and sets/resets
the ready output.
Now one period of FT-LFSR is finished.
Each PE is organized as shown in Fig 4. It has two main
parts:
1. LFSR: LFSR produces N bit pattern called
PE LFSR out.
2. Comparetor: Comparetor determines whether
FT LFSR out is correct or not based on its point
of view. This operation is done by comparing its LFSR's
output with other LFSR's outputs in other PEs if the
current PE is selected PE. If the current PE is not
selected PE, the LFSR's output is compared just with
the LFSR's output of selected PE.
PE outputs and inputs are:
1. PE LFSR out: PE LFSR out is the N bit pattern which
is produced by LFSR.
5 PE LFSR out is the N bit output of each PE which is the same as a
pettern that a conventional LFSR generates.
Fig. 4. PE Architecture
2. PE ready: PE ready shows the correctness of
FT LFSR out by current PE point of view. If
P E ready = 1 then FT LFSR out will have no
problem from current PE point of view and otherwise it
will have problem.
3. Second PE out and Third PE out: Second PE out and
Third PE out are the two other PE LFSR outs.
4. Selected: Selected comes from Controller and if it is
1, it means that the current PE is selected PE and
PE LFSR out connects to FT LFSR out and otherwise
it does not connect.
5. FT LFSR out: FT LFSR out is the feedback of FT-
LFSR output.
Controller is just a multiplexer and Voter is a combination
of simple gates [10], [11], [12]. LFSR in FT-LFSR can be of
any type of LFSR used in pseudo-random number sequence
generators.
V. R ELIABILITY-A REA -FACTOR (RAF) M ETRIC
In order to evaluate the efficacy of hardware redundancy-
based techniques, we propose a novel metric called Reliabilty-
Area-Factor (RAF) which integrates the number of SPoFs and
the area overhead of the techniques.
RAF is computed as:
RAF = S ∗ A (2)
where S and A respectively show the ratio of number of SPoFs
and the area in the original and fault tolerant architectures.
Parameter S is calculated as:
∑
N SOi
S = ∑i (3)
j N SFj
where N SOi shows the number of logic blocks in ith SPoF
in the original architecture and N SFj is the number of logic
blocks in j th SPoF in the fault tolerant architecture. Higher
parameter S is proportional to the higher reliability achieved Table I
by the fault tolerant architecture. Parameter A is calculated as: RAF value for different LFSRs

Nb LFSR RAF
A= (4) width FT-LFSR Conventional LFSR P-LFSR
Nf 16 5.33 1 0.33
where Nb and Nf respectively represent the total number of 32 10.66 1 0.33
64 21.33 1 0.33
logic blocks in the original and fault tolerant architectures.
The overhead imposed by the fault tolerant approach leads to
an increase in parameter A.
Therefor, RAF integrates the reliability improvement and the VII. Q UANTITATIVE FAULT A NALYSIS
imposed area overhead achieved by a fault tolerant technique. In this section, it is quantitatively shown that FT-LFSR is
Higher RAF means that the proposed fault tolerant architecture resilient to transient and permanent faults; i.e. the fault will
provides higher reliability in terms of less area overhead. More be either masked (when it occurs in an unselected PE and
precisely, a fault tolerant architecture is better than the original thus, will not destroy the FT LFSR out) or detected (by ready
one in terms of RAF if 1 < RAF < ∞ and it is worse if signal which causes the controller of BIST to change the
0 < RAF < 1. The fault tolerant architecture is as the same sel out). There are some main modules in FT-LFSR which
as original architecture if RAF = 1. should be evaluated in presence of faults as follows:
VI. E VALUATION OF FT-LFSR USING RAF 1. PE
If one fault occurs in one of PEs then the two others
In this section, we evaluate FT-LFSR and P-LFSR using the
will understand the occurence of fault by comparing their
RAF metric. The RAF is computed for FT-LFSR as follows:
∑ PE LFSR out (which is correct value) with the faulty
1. i N SBi = N , because a conventional LFSR has N flip PE LFSR out. If fault occurs in an selected PE it will
∑ that all of them are SPoFs.
flops be detected and if fault occurs in an unselected PE it will
2. j N SFj = V = 1, where V is the number of logic be masked.
blocks in Voter (because we have just one SPoF in 2. Controller
our architecture). As the occupied volume by Voter is If one fault occurs such that sel out changes, fault will be
approximately equivalent to occupied volume by one masked because all PEs are working correctly and if each
register, therefor V = 1. of them connects to sel out the result will be correct. It
3. Nb = N , because the base LFSR has just N FFs. is important to say that PE A is connected to sel out
4. Nf = ((3 ∗ N ) + M ) ≈ 3N , where M is the number of with two values of sel out because we want to ensure
extra logic blocks that is related to Voter, Comparetor and that FT LFSR out connects to one of PE outputs. If one
Controller that is negligible in front of occupied volume fault occurs in SelectedA, SelectedB and SelectedC the
by FFs. fault will be masked because they just determines each
So, RAF for FT-LFSR will be: PE must compare its output with one PE or two PEs
N N 1 N which is not important in this case because all PEs are
RAF = ( ) ∗ ( )=N∗ = (5)
1 3N 3 3 working correctly.
Therefor, FT-LFSR is better than the conventional LFSR if 3. Voter
N > 3. If one fault occurs in Voter such that the output of voter
The RAF analysis of the P-LFSR is as follows: is 1, it will be masked otherwise, it will not be detected.
∑ So Voter is a SPoF.
1. ∑i N SBi = N .
Therefor, FT-LFSR is resilient to all single (transient or
2. j N SFj = N , because this LFSR has N one-bit voters
that each of them are SPoFs. permanent) faults that occurs in any logic except the Voter. It
3. Nb = N . is notable that, FT-LFSR is also resilient to many patterns of
4. Nf = ((3 ∗ N ) + M ) ≈ 3N , where M is the number of multiple faults.
extra logic blocks that is related to voters and comparators VIII. E XPERIMENTAL R ESULTS
that are negligible in comparison to occupied volume by
FFs. This section investigates the efficacy of the proposed fault
tolerant LFSR in various aspects based on the extensive fault
Finally, RAF for the P-LFSR will be:
injection analysis. The proposed method is implemented in
N N 1 1 Verliog language, simulated by ISE tool, and synthesized on
RAF = ( )∗( )=1∗ = (6)
N 3N 3 3 Spartan 6 FPGA. Logic value upset is considered as the fault
In order to compare the RAF value for different widths and model for fault injection. In order to model transient faults,
based on the Equations of 5 and 6, the RAF value of different the logic upset is injected only for one clock cycle and then,
LFSRs are shown in Table I. As it is shown for all widths, becomes corrected in the next cycles while for permanent
FT-LFSR has higher RAF value and that is because of one faults, the logic upset remains in the circuit for more than
SPoF. one clock cycle. Faults have been injected in outputs of main
modules (PE, Controller and voter) and main inputs (sel out)
in two forms wrong zero and wrong one. The used polynomial
generators 6 have been brought in table II.

Table II
Polynomial generator for different LFSR widths

LFSR width Polynomial generator

16 x16 + x14 + x13 + x11 + 1

32 x32 + x22 + x2 + x1 + 1

64 x64 + x63 + 1

A. Single Faults Fig. 5. Multiple fault injections in different LFSRs.

The results of investigating resiliency of different architec-
tures for LFSR against single faults are reported in table III.
as a fair reliability metric in fault tolerant designs especially
The first column shows the widths of LFSRs and the second
when:
one indicates the number of injected faults. The next columns
represent the number of detected or masked faults and fault 1. Fault injection is hard.
coverage for FT-LFSR and the P-LFSR. 2. We want to compare some fault tolerant designs when
fault coverage of them are close together.
Table III D. Design Overheads
Resiliency of different LFSRs to single faults
FT-LFSR adds some extra logic to the original design lead-
LFSR Injected FT-LFSR P-LFSR ing to some area and delay overheads. The required hardware
Detected/ Fault Detected/ Fault for FT-LFSR is more than three times a conventional LFSR.
width faults Masked coverage Masked coverage
16 92 90 0.978 69 0.750 The proposed fault tolerant architecture imposes some delay
32 156 154 0.987 120 0.769 overhead to LFSR circuit. The critical path delay for different
64 284 282 0.993 217 0.764 architectures is shown in table IV based on the synthesis
report.
As shown in table III, the fault coverage of FT-LFSR is
more than P-LFSR because we used a one-bit voter in our Table IV
Clock period of different LFSRs in (ns)
architecture while P-LFSR includes an N one-bit voter (i.e.
N SPoFs). LFSR clock period
width FT-LFSR Conventional LFSR P-LFSR
B. Multiple Faults 16 8.591 1.273 5-10
32 8.941 1.273 5-10
The fault coverage of multiple (transient and permanent) 64 9.468 1.273 5-10
fault injections into FT-LFSR and P-LFSR is shown in Fig 5.
We have injected from 2 to 16 faults randomly in FT-LFSR and
P-LFSR for 1000 rounds for each number of fault injections. On of the important metrics to compare different designs is
Based on the results, as more faults are injected, fault coverage power. We expect that power consumption of FT-LFSR will
decreases in both architectures. Also, it is observed that in the be less than P-LFSR. It is becuase the number of logics in FT-
same width, FT-LFSR has higher fault coverage than the P- LFSR is less that P-LFSR based on different configurations.
LFSR. Additionally, it is notable that more larger LFSR width For a fair comparison all implementations for power are on
leads to more reliability in both. Virtex 4. As it can seen from Table V for 16 and 32 bit widths,
both static and dynamic powers for FT-LFSR are less than P-
C. RAF LFSR.
Higher RAF value of FT-LFSR (it can seen from table I) IX. C ONCLUSION
and higher fault coverage of it (based on table III and Fig 5)
In this paper, a new fault tolerant architecture for LFSRs
shows our claim that we can use RAF in hardware redundancy
called FT-LFSR is proposed which is applicable pseudo-
6 Polynomial generator determines the sequence of generated outputs of random sequence generators such as BIST structures and
LFSR. pseudo random number generators. The main superiority of
 Table V
Power consumption of different desings

LFSR width FT-LFSR Conventional LFSR P-LFSR

Static Dynamic Total Static Dynamic Total Static Dynamic Total
16 255.86 6.03 261.89 255.78 4.12 259.90 330.5 110.09 440.59
32 255.88 6.44 262.32 255.86 6.03 261.89 330.5 133.40 463.9

FT-LFSR over its counterparts is its less number of SPoFs.

This leads to high resiliency to single (transient and perma-
nent) faults and many patterns of multiple faults. We also intro-
duce a novel metric called RAF which integrates the reliability
improvement and area overhead of fault tolerant techniques in
digital designs. The fault tolerance of FT-LFSR is investigated
quantitatively and also through some experimental results on
Spartan 6 FPGA. The results show the high fault tolerance
of FT-LFSR against single and multiple faults in expense of
reasonable area and delay overhead.
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