2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India
Design and Implementation of Multibit LFSR on
FPGA to Generate Pseudorandom Sequence Number
Debarshi Datta, Bipa Datta
ECE Dept., Brainware Group of Institutions
MAKAUT
Kolkata, India
debarshidatta7@gmail.com1, bipa.datta@gmail.com2
Abstract—Pseudorandom number generators (PRNGs) are
important role in cryptography application. Hardware based
random number generators become faster. Field Programming
Gate Arrays (FPGA) is one of the most valuable devices in
hardware industry. This paper presents multibit linear feedback
shift register (LFSR) based PRNGs circuit designed with
hardware description languages (HDL). In multibit LFSR
system, multiple bits are shift in every clock cycle where a single
bit is shift in a conventional LFSR method. This technique is very
much applicable in cryptography area. The proposed various bit
length multibit LFSR architectures are synthesized using Xilinx
ISE 14.7 and Spartan 6 FPGA to target device XC6SLX45. The
result analysis indicates that 32-bit length multibit LFSR
architecture is better performance than other architectures.
Keywords—LFSR; multibit; FPGA; PRNG; HDL;
I. INTRODUCTION
Recently, FPGAs are gaining importance for an extremely
wide range of applications [3], mostly in Communication
system. In advancement of VLSI technology, modern FPGAs
are entire programmable systems on chip (SoC) which contain
reconfigurable logic blocks and Input-Output Blocks (I/O).
FPGAs are used in digital circuit to enhance hardware
performance. Low development cost and short time to market
of FPGAs are more attractive than application specific
integrated circuits (ASICs). Therefore, the reconfigurable
hardware devices are ideal choice for implementing real time
applications. Hence, hardware based random number
generators are widely employed. In this context, hardware
based PRGNs are highly demand in secure data
communication.
With rapid development of computer and communication
networks, the secure information is being main objective of
this technology. Random number generators (RNGs) are
significant role for this purpose. RNGs are generally useful in
security purposes systems like mobile communication, space
communication, bank security etc. RNGs are classified as
deterministic and true or non-deterministic types [1].
Deterministic type is termed as Deterministic Random
Number Generators (DRNGs) which generate pseudorandom
numbers algorithmically. The second type is termed as True
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346
Himadri Sekhar Dutta
IEEE Member
Kalyani Government Engineering College
Nadia, India
himadri.dutta@gmail.com
Random Number Generators (TRNGs). Basically, PRNGs
generate arbitrary sequences which are properties of random
numbers. PRNG algorithm use for mathematical formula to
generate random series. There are various methods of PRNGs
are describes in [2], but the LFSR based circuit provides high
speed binary sequences. LFSR generates binary sequences are
truly random binary sequences [2], [4]. Implementation of N-
bit LFSR based PRNGs on FPGA are explain in [5], [6]. The
changes of feedback path in the LFSR make a new polynomial
equation and also generate new random sequences. In paper
[8], the authors described the application of LFSR based
PRNGs for micro-electro-mechanical system (MEMS) testing.
The LFSR was described in HDL to implement on FPGA.
This paper presents implementation of multibit LFSR
based random number generators which are more secure than
conventional LFSR based random number generator. The
remainder of this paper is presented as follows: Section II
presents LFSR algorithm. Section III proposed multibit LFSR
algorithm. Section IV describes implementation of multibit
LFSR. Simulation results are discussed in section V. At last,
section VI gives the conclusion of this paper.
II. LINEAR FEEDBACK SHIFT REGISTERS ALGORITHM
LFSR is shift register which generates sequence of binary
values. The sequences are repetitive in nature known as
pseudorandom sequences. Feedback paths are established
after registers in the LFSR structure called taps and constitutes
exclusive-OR or exclusive-NOR to make random series. Fig. 1
shows LFSR with XOR configuration. Here D flip-flops are
used as registers and Q is the output of the each register.
Fig. 1. Linear Feedback Shift Register [8]
Flip-flops operate as standard shift registers and generate
repetitive sequences of pseudorandom value. The taps values
 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 347

determine the polynomial equation and give the repetitive From this state-space methodology compute the new values x(t
sequences. The generate sequence is independent on any + 1) with the help of the actual values x(t) and the transition
other element, so that it is random. The sequence is matrix A. For calculation the value for x(t+2), simply calculate
deterministic because after specific elements it again starts its x(t+2)=Ax(t+1)=A2x(t). In this way, the next repetition
original value. Hence, it is called pseudo. If one knows the provides x(t+3)= A3x(t). The n step-at-once equation of a
present state as well as the positions of the XORs gate in the LFSR can be evaluated by An modulus 2. For n = 4 it will be
LFSR architecture, one can predict the next state. The input A4 mod 2. Table II shows four step-at-once transition matrixes.
bits are linear function of previous step and function coming
from XORs or XNORs are also linear. An LFSR generates a TABLE II. FOUR STEP-AT-ONCE TRANSITION MATRIXES
pseudorandom sequence of length (2n-1) states where n is the
number of shift registers used in the given LFSR architecture. 00011111
An LFSR generates all possible values of (2n-1) states are
00111111
called maximal length sequence. A maximal length sequence
can be obtained by combination of more than a taps in a LFSR 01111111
system. A 4-bit shift register with feedback taps at the 3rd and
A mod 2
4
11111110
4th bits is maximal sequence.
The LFSR sequence depends upon initial values (seed 11111101
value), tap positions and feedback types. There are two 11111011
methods for realization of LFSR system. One is Fibonacci
configuration and the other one is Galois configuration shown 11110111
in Fig. 2. 11101111

IV. IMPLEMENTATION OF MULTIBIT LFSR ALGORITHM

An 8-bit multibit simple polynomial, y = x8+x+1, generate
random sequences. In multibit technique, four new bits are
Fig. 2. (a) Fibonacci configuration (b) Galois configuration [9]
generated in every clock cycle. Hence, in every clock cycle a
bit is shifted from register x8 to x5 and EXOR operation is
III. MULTIBIT LFSR BASED ALGORITHMS occurred from register x1 to x4. The fig.3 describes VHDL
In LFSR based method, n clock cycles are required to (VHSIC Hardware Description Language, VHSIC is acronym
generate n number of random binary bits. This is not a good for Very High Scale Integration Circuits) code for four step
characteristic of random properties and less acceptable for LFSR of length-8.
cryptographic security application. But it is possible to shift n-
bits in one clock cycle and generate new random series. The
state-space method can easily be estimated the LFSR equation.
Consider an 8-bit multibit LFSR based PRNG, consider, y =
x8+x+1. The job is to calculate modified four new bits in every
clock cycle. The desired equation can be obtained from the
state-space methodology. First LFSR must be computed in the
form of x(t + 1) =Ax(t), where A is transition matrix. Table I
shows the state-space methodology of 8-bit LFSR.

TABLE I. STATE-SPACE DESCRIPTION 8-BIT LFSR

X8(t+1) 00000001 X8(t)
X7(t+1) 00000011 X7(t)

X6(t+1) 00000111 X6(t)

X5(t+1) 00001111 X5(t)

X4(t+1) 00011111 X4(t)

X3(t+1) 00111111 X3(t)

X2(t+1) 01111111 X2(t)

Fig. 3 VHDL code for four step length-8 LFSR
X1(t+1) 11111110 X1(t)
*

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 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 348

V. EXPERIMENTAL RESULTS
The simulation waveform of multibit LFSRs process using
Xilinx 14.7 simulator and all the design algorithms are
implemented on Spartan-6 FPGA based hardware. Xilinx ISE
14.7 tools are used for checking synthesis, Map and Place &
Route reports. Here multibit LFSRs are four step of length-8
LFSR, eight step of length-16 LFSR and sixteen step of length-
32 LFSR. Figures [4,5,6] shows timing simulation of four step
of length-8 LFSR, eight step of length-16 LFSR and sixteen
step of length-32 LFSR methods respectively.

Fig. 4. Four step of length-8 LFSR simulation waveform

Fig. 7 Four step-at-once of length-8 LFSR RTL schematic

The maximum performance can be obtained after synthesis the

design. The hardware resources occupy on the FPGA board is
tabulated as in table III. The data in the table III show the
nominal utility of the hardware resources prompts to carry out
the entire multibit LFSR generators.

TABLE III. DEVICE UTILIZATION SUMMARY OF MULTIBIT LFSR

Fig. 5. Eight step of length-16 LFSR simulation waveform
GENERATORS AT DIFFERENT BIT LENGTH
Synthesis Parameter Used in Used in 8- Used in
4-step step 16-step
8-bit 16-bit 32-bit
length length length
Number Slice Registers 8 16 32

Number of Slice LUT 4 8 16

Number of used as logic 4 8 16

Number of occupied Slice 1 2 4

Fig. 6. Sixteen step of length-32 LFSR simulation waveform

The register transfer language (RTL) schematic that is Number of LUT Flip Flop 4 8 16
obtained with the aid of the ISE 14.7 simulator is shown in Fig. pairs used
7 for four step-at-once of length-8 LFSR.
Number of IOBs 9 17 33

The maximum operating frequency, delay and power are

calculated for 16 step-at-once of 32-bit length LFSR generator
as shown in table IV. The power is measured from Xilinx
XPower Analyzer (XPA). The result analysis shows that the
computation time requires for this multibit LFSR
implementation in the order of nanoseconds which replicate
that FPGA have high speed implementation.

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 2017 Devices for Integrated Circuit (DevIC), 23-24 March, 2017, Kalyani, India 349

TABLE IV. TIMING AND POWER REPORT FOR 16 STEP-AT ONCE ACKNOWLEDGMENT
32-BIT LENGTH LFSR BASED PRNG
The authors would like to thank the Department of
Parameter Estimate Value for
Electronics and Communication, Brainware Group of
16-step 32-bit Length LFSR Institutions and Kalyani Govt. Engineering College for
Family Spartan 6 providing the ISE design suite 14.7 and Spartan 6 FPGA board.
Target Device XC6SLX45
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