A Hierarchical Technique for Minimum-Width Layout of Two-Dimensional CMOS Cells

Avaneendra Gupta and John P. Hayes

{avigupta, jhayes}@eecs.umich.edu

Advanced Computer Architecture Lab. Dept. of EECS, University of Michigan Ann Arbor, MI 48109, U.S.A. Abstract

Design Technology, Intel Corporation 2200 Mission College Blvd. Santa Clara, CA 95052, U.S.A.

We present a hierarchical technique, based on integer linear programming (ILP), to generate area-efcient layouts of relatively large complex CMOS cells in the twodimensional (2-D or multi-row) style. First, the CMOS circuit is partitioned into subcircuits called clusters. Next, the set of all minimum-width 1-D placements (chain covers) are generated for each cluster, and form the input to the ILP model. The model aims at selecting exactly one cover for each cluster such that the overall 2-D cell width is minimized. In the process, all possible diffusion sharing between transistor chains belonging to clusters are considered; the inter-row connections that contribute to the overall cell width are also reduced. Experimental results demonstrate that the technique reduces run times by several orders of magnitude over non-hierarchical methods, and yields optimal or near-optimal layouts in most cases.

a b c d e f g h

b a b c

out
d

out f g g h h

e d

(a)

e f

(b)

(c)

1 Introduction
Cell synthesis techniques can increase design productivity by automating the generation of cell layout. However, to be useful, they should generate efcient designs in a practical amount of time. Fast, heuristic methods often yield poorquality layouts that are unacceptable in many applications. Practical methods that extend exact optimization techniques to larger circuits while generating layouts that are at or near the optimum are therefore highly desirable. In this paper, we propose an efcient hierarchical technique for width minimization of CMOS cells and cell arrays in the two-dimensional (2-D or multi-row) layout style. The 2-D stylea generalization of the more restricted one-dimensional (1-D or linear) styleallows multiple parallel rows of P and N diffusions. It is not only necessary in several domains such as datapath cell layout, but can also yield area and performance advantages over the 1-D style [5].
This

(d)

(e)

Figure 1: (a) 8-input NAND gate, (b) its transistor-level design with five clusters (shaded), and its hierarchical layouts with (c) one, (d) two, and (e) three P/N rows

research was supported by a grant from Intel Corporation.

Hierarchical methods partition the circuit into subcircuits or clusters, thereby decomposing the layout problem into two interdependent problems: generate a layout for each cluster, and nd a 2-D placement of the cluster layouts so that the overall cell width is minimized. If the partitioning is at the boundaries of logic gates, this approach ensures that the fundamental problem of diffusion sharing, which is concentrated within each gate, is rst solved locally. Figure 1 illustrates the advantages of hierarchical techniques using a multi-level implementation of an 8-input NAND function from [11]. One, two, and three-row layouts

generated using the hierarchical technique proposed here are shown in Fig. 1. As discussed later, the proposed method produces minimum-width 2-D layouts for all these cases. While the non-hierarchical technique of [5] requires 3, 19, and 58 seconds of CPU time, respectively, for one, two, and three-row layouts, our hierarchical technique requires only 0.03, 0.05, and 0.07 seconds. For larger circuits, such hierarchical techniques offer similarly dramatic speed-ups, while yielding layouts that are close to optimal and much better than those generated by heuristic techniques applied to the entire circuit. Unlike the extensively studied 1-D style [3, 4, 7, 8, 10, 13], 2-D cell layout generation has received little attention and the few techniques proposed are largely ad hoc [12, 14, 15]. In recent work [5], the authors have developed an exact layout method based on integer linear programming (ILP) for 2-D cell width minimization. The ILP approach generates optimal width layouts and has run times in minutes for practical CMOS cells of up to 25 transistors. However, for larger cells, the run times of this and other exact approaches increase rapidly, making hierarchical techniques attractive. In any hierarchical approach, the layout of individual clusters signicantly affects the overall cell layout. For example, diffusion sharing between transistors belonging to different clusters depends on transistor placement within each cluster. Hence, hierarchical techniques [7, 10, 14] that treat the generation of intra and inter-cluster layouts in two sequential stages can yield sub-optimal results. Sadakane et al. [11] propose a method that rst generates the set of all minimum-width 1-D placements for each cluster, and then simultaneously selects a layout for each cluster and a placement of the clusters so that the overall 1-D width is reduced. In the 2-D realm, the hierarchical technique proposed by Tani et al. [12] for layout of 2-D cell arrays also decouples the intra- and inter-cluster placement stages. Moreover, none of the above methods consider diffusion sharing between the chains of each cluster. As our results here indicate, such sharing can greatly reduce the total number of diffusion gaps, so that the resulting layouts often have widths at or near the optimum. For a given partitioned CMOS circuit, two types of hierarchical cell synthesis problems can be dened based on the nal layout desired: 1. Hierarchically generate a minimum-width 2-D layout by placing the transistors of the entire circuit into a single 2-D cell. 2. Generate cell layouts for the individual clusters and place them in a 2-D array of minimum width. In this paper, we present a novel ILP-based technique to solve both problems. Given a partitioned circuit, we rst generate a set of all minimum-width 1-D transistor placements (minimum chain covers) for each cluster. The gener-

1. The cell to be laid out is a dual CMOS circuit of xed structure. 2. Alternate P/N rows are ipped to allow the power rails to be shared among adjacent diffusion rows. 3. P and N transistors of a pair are vertically aligned so that their terminals on common nets can be connected using vertical wires. 4. Routing is restricted to polysilicon and metal1 which can be used in the vertical or horizontal direction. Power rails are routed in metal2. 5. Two terminals that are on transistors placed in adjacent diffusion rows are connected using routes in the channel between the rows. 6. Diffusion gaps do not allow a metal1 wire to be routed through them. Also, no wires are routed over diffusions. Hence, all routes between P/N rows are routed along the sides of the cell.

Table 1: Assumptions underlying the 2-D cell width minimization problem

Gnd

P/N row 2

N row P row
Vcc

P/N row 1

P row N row
Gnd Diffusion gap Diffusion sharing

Figure 2: The 2-D cell layout style

ation of a minimum-width 2-D placement is then formulated as an ILP model; the set of all minimal covers for each cluster form the input to the model. When the circuit hierarchy is attened to the transistor level, our technique reduces to the non-hierarchical method of [5]. The proposed technique has several advantages over other heuristic methods: 1. It considers all diffusion sharing possibilities among transistor chains in different clusters, and selects a cover for each cluster that tends to maximize the sharing and minimize the inter-row connections. 2. For a given set of chain covers for each cluster, it guarantees a minimum-width 2-D placement. 3. It is applicable to most CMOS circuit types, including series-parallel and non-series-parallel cells. 4. It can easily accommodate other constraints such as transistor folding and cell height minimization. Section 2 denes the width minimization problem for 1D and 2-D layouts and discusses the factors that inuence 2-D cell widths. The ILP formulation for 2-D layout of single CMOS cells proposed in our earlier work [5] is reviewed in Section 3. Section 4 outlines the proposed ILP technique for hierarchical 2-D cell width minimization. Experimental results for representative CMOS circuits are presented in Section 5.

2 Cell Width Minimization

The 2-D cell layout style is illustrated in Fig. 2, with its

assumptions summarized in Table 1. It allows multiple rows of P and N diffusions, which are called P/N rows. Two adjacent transistors that have their diffusion terminals on the same net are connected by diffusion sharing; otherwise they have a diffusion gap between them. A linear sequence of transistors connected by diffusion sharing is called a transistor chain. A P/N pair shares diffusion with another pair if and only if both the P and N transistors of the two pairs share their diffusions. The number of pairs in a chain is called its length. Chains that have the same pairs but in different orders are called equivalent chains. Since the 2-D style is basically the same for both single cells and array of cells, we will only consider single-cell layouts in the subsequent discussion. For example, Fig. 2 shows two cells, each with two P/N rows, placed adjacent to each other. The cell boundary is half a diffusion gap from the diffusion area of the cell. Hence, when two cells are abutted, their diffusions are one diffusion gap apart. However, in such an abutment of two cells, if the diffusion terminals facing each other are on the same net, they are merged via diffusion sharing. If Wr is the width of the r-th P/N row, then the 2-D cellwidth minimization problem can be stated as follows: Minimize the cell width Wcell by placing the pairs in a given number of rows so that the maximum width among all rows is minimized, that is, minimize Wcell, where
Wcell = max {Wr: for each P/N row r = 1, 2, ...} (1)

Parameters

Interpretation

1.P, C, R Number of pairs, chains, and rows, respectively 2.pairs, chains, nets The set of pairs, chains, and nets, respectively 3.Pnets, Nnets Pnets[p] = {gate, source, drain nets of P trans. of pair p} (Nnets is similarly dened) 4.pairCover pairCover[c, p] is 1 iff chain c contains pair p 5.nDiffAtBottom A decision variable that is 1 (0) if the N diffusion is placed at the cell bottom (top) 6.gates, covers The set of gates and covers for each gate 7.Psrc, Pdrn, Nsrc, Nets on the source / drain ends of the P and N Ndrn parts of each chain 8.orients orients[c] = Set of possible orientations of chain c 9.chainCover chainCover[cc, c] = 1 iff cover cc contains chain c

Table 2: Input data to the 2-D ILP models: (15) nonhierarchical model; (19) hierarchical model

of diffusion sharing among pairs; the row in which each chain should be placed; an ordering of the rows that minimizes the number of inter-row connections; and, the diffusion type, P or N, to be placed at the bottom of the cell.

3 Non-Hierarchical 2-D Cell Model

The general mixed integer linear programming (MILP) problem is stated below using matrix notation [9].
Minimize cx + dy subject to Ax + Dy b, x 0, y 0

As discussed in [5], Wcell for a 2-D layout depends on several factors: 1. Chain cover or diffusion sharing: The selection of the chain cover affects Wcell since covers that yield optimum 1D widths do not also guarantee minimum 2-D widths. 2. Inter-row connections: Wires may be needed to connect terminals of transistors placed in different rows. These inter-row wires contribute to Wcell. 3. Bottom diffusion row: The placement of the P or the N diffusion island at the bottom of the cell affects the number of inter-row wires and hence Wcell. A P/N row r with cr chains has cr 1 diffusion gaps. Assuming a virtual grid in which each pair and diffusion gap has unit width, the width Wr of row r can be expressed as follows, where tr, cr, and vr are the numbers of pairs, chains, and inter-row connections, respectively, in row r:
Wr = tr + cr 1 + vr (2)

In the special case of a 1-D layout, Wcell is dened by the equation below, which implies that a minimum chain cover (or min-cover), which has the fewest chains in it, guarantees a layout of minimum width.
Wcell = t + c 1 (3)

Its goal is to minimize a linear cost function while satisfying a set of linear constraints. Here c and d are cost vectors; A and D are constraint matrices; and b, x, and y are vectors of constants, integer variables, and real variables, respectively. An MILP problem with no integer variables reduces to a linear programming (LP) problem while an ILP problem has no real variables. A binary ILP problem has all its variables restricted to 0 or 1 values. A fundamental sub-problem is to determine the position of each pair in the 2-D plane by considering pairwise diffusion sharing. This is modeled implicitly by generating the set of all transistor chains. We use the chain generation algorithm proposed for the XPRESS cell synthesis tool [4] since it is applicable to most types of CMOS circuits. The width minimization problem then translates into a covering problem: Find a subset of chains that covers every pair and has the minimum 2-D cell width. Items 15 in Table 2 are the input circuit parameters. We use an array X of binary variables, where X[c, r] = 1 if chain c is included in a solution and placed in row r. The primary constraints in the model are reviewed below: 1. Pair inclusion: Each P/N pair is included exactly once.
c chains r rows

pairCover[c, p] X[c, r] = 1 X[c, r] 1

p pairs c chains r rows

2. Chain inclusion: Each chain is included at most once.

r rows

Hence, in order to minimize Wcell in a 2-D layout, the following characteristics need to be incorporated into appropriate constraints in the ILP formulation: the extent

3. Row occupancy: A row must contain at least one chain.

c chains

X[c, r] 1

Logical constraint
z = x or y or w z = x and y z = x and not y z = x and y and not w

Equivalent linear constraints

z(x+y+w) z(x+y+w)/3 z(x+y)/2 z(x+y1)/2 z(xy+1)/2 z(xy)/2 z(x+yw+1)/3 z(x+yw1)/3 d a a b

Bridge
e 4 5 e 2 3 c b 1 d c o

Inverter

(a)

Bridge
dc ba 4 1 4 1 e 45 23 e 4 5 2 3

Inverter
1 o vcc o gnd vcc 3

Bridge
dab c e 4 2 5 vcc gnd gnd

Inverter
1 o vcc o gnd

Table 3: Linearization of some logical constraints

4. Cost function linearization: The nonlinear cost function (1) is made linear using a linear inequality for each row:
Wcell (X[c,r]chainCost[c]) + X[c,r] + V[r,n] 1
c chains c chains n nets

Flip
d c ab 4 1 4 1 1 o vcc o gnd vcc 3 dab 5 e c 1 4 vcc o gnd o

Flip

5. Inter-row connectivity: If the variable V[r, n] = 1 denotes that net n must be routed vertically along row r, then its value can be defined by the following logic equation [5]:
V[r, n] = (above[r, n] and below[r, n] and not top[r, n]) or (above[r, n] and bottom[r, n] and not top[r, n]) or (below[r, n] and not bottom[r, n] and top[r, n])

gnd 2

(b)

(c)

Here, above[r, n], below[r, n], top[r, n], and bottom[r, n] are binary variables that take the value 1 if net n appears above, below, in the top diffusion, or in the bottom diffusion, respectively, of the r-th P/N row. They can, in turn, be expressed as logic equations over the parameters that dene the nets in a given chain. All the above constraints are non-linear since they involve logic operations such as and, or, and not; hence, they have to be linearized, as shown in Table 3, to be included in an ILP model.

Figure 3: (a) A bridge circuit [15] with inverted output; its hierarchical layouts using two different min-covers, (b) {dcba, e} and (c) {dab, ce}

4 Hierarchical 2-D Cell Model

We now present the hierarchical ILP technique whose goal is to generate minimum-width 2-D cell layouts. The input circuit is rst partitioned into clusters, typically logic gates, using known methods [4, 11]. Next, the set of all min-coversthe smallest set of chains that covers the circuitis generated for each cluster. We use the min-cover algorithm described in [4] for XPRESS. The combined set of min-covers for each cluster forms the input to the ILP model. Although min-covers do not necessarily minimize 2-D cell width, our results indicate that they can yield areaefcient, and often minimum-width layouts, especially when the average cluster size is small. When cluster size, or the number of rows increase, it may be desirable to include sub-optimal covers as well. We motivate the hierarchical layout technique using the circuit in Fig. 3a for a placement in a single row. It consists of a non-series-parallel bridge circuit, taken from [15], with inverted output. The bridge circuit has several mincovers, each with two chains, while the inverter has a single cover for its P/N pair. In Fig. 3b, the min-cover {dcba, e} has been combined with the inverters layout; the resulting layout has three chains and a width of 6 + (3 1) = 8. In contrast, Fig. 3c uses a different min-cover {dab, ce}.

The chain ce and the inverters layout can both be ipped to share diffusions, so the nal layout has only two chains and a smaller width of 6 + (2 1) = 7. Thus, even for such a small circuit, we observe that the choice of a min-cover for each cluster and exploring diffusion sharing between chains of each cover can yield better layouts. Given a set of chain covers for each cluster, the hierarchical 2-D layout problem is as follows: Select a unique cover for each cluster, and determine a placement of the chains in the selected covers, such that the overall 2-D cell width Wcell is a minimum. The width Wr of each row r in this hierarchical 2-D cell model is dened as follows:
Wr = length of chains in row r + #wires + #gaps in row r (4) = length of chains in row r + #vertical wires + (#chains in row r 1 #diffusion abutments in row r)

Circuit parameters and variables: The input parameters are listed in Table 2. Any chain can be placed in two orientations (ipped or unipped) since both the P and the N parts of the chain must be oriented similarly. There are two exceptions to this rule: Chains with a single pair can be placed in four orientations; And if the P or N parts of a chain contain transistors connected in parallel, these transistors can be ipped in place individually, regardless of the orientation of the other part of the chain. From the circuit values for Pdrn, Ndrn, Psrc, and Nsrc, we derive the parameter array share, where share[ci, oi, cj, oj] = 1 if chains ci and cj can share diffusion in orientations oi and oj, respectively, when chain cj is placed to the immediate right of chain ci. We also derive two other integer parameters: chainCost[c], the number of pairs in chain c; and coverCost[cc], the number of chains in cover cc.

Given the set of covers for each cluster, the 2-D layout characteristics to be determined are: a unique cover for each cluster; the row in which each chain is placed; the diffusion sharing among the chains in each row (and hence, their orientation and linear ordering); and the nets to be routed between rows. We introduce the following sets of binary variables: (a) X[chains, rows], where X[c, r] = 1 if chain c is placed in row r; (b) Y[chains, orients], where Y[c, o] = 1 if chain c is placed in orientation o; (c) Z[covers], where Z[cc] = 1 if the chain cover cc is included in the solution; and (d) merged[chains, chains, rows], where merged[c1, c2, r] = 1 if chains c1 and c2 are placed in row r such that c2 is to the right of c1 and they can share their adjacent P and N diffusions. Thus, merged enforces an implicit linear ordering on the chains in each row. Constraints described later ensure that each chain can be merged with at most one chain on either side, and that the inter-chain diffusion sharing is acyclic. Constraints: The set of constraints in the hierarchical ILP model are now described. 1. Gate inclusion: A gate must be included exactly once.
cc covers[g]

..., ck> that are placed contiguously in the same row and share their adjacent diffusions, we assign a topological ordering using variables called slots. Thus, if merged[ci, ci+1, r] = 1, then chain ci+1 placed to the immediate right of ci with diffusion sharing is assigned slots[ci+1] = slots[ci] + 1. Since each chain is assigned a unique value of slots, this constraint makes it impossible to have a cyclic placement such as <c1, c2, c3, c1> where slots[c1] would need two distinct values. This relation is described by the constraint below, one for each pair of chains ci and cj.
if merged[ci, cj, r] = 1 then slots[cj] = slots[ci] + 1 (6)

The logical constraints (5) and (6) must be linearized to be included in an ILP model. The sum-of-products expression in (5) can be made linear in several ways by introducing an intermediate binary variable for each product term and then linearizing these variables using linear inequalities from Table 3. We have developed a model that exploits some inherent characteristics of (5) to linearize it without introducing any intermediate variables as follows:
4 merged[c1, c2, r] X[c1, r] + X[c2, r] + Y[c1, o1] + Y[c2, o2] + 2 Y[c1, o11]
o2 orients[c2] o11 orients[c1]

Z[cc] = 1

g gates

2. Cover inclusion: All chains of a cover must be included.

c chains r rows

(X[c, r] chainCover[cc, c]) cc covers coverCost[cc] (2 Z[cc] 1)

Constraint (6) is equivalent to the two linear inequalities below:

slots[cj] slots[ci] (1 + S) merged[ci, cj, r] S slots[cj] slots[ci] (1 S) merged[ci, cj, r] + S

3. Chain inclusion: A chain can be included at most once in any solution, and must have an orientation.
o orients[c]

Y[c, o] =

r rows

X[c, r] 1

c chains r rows

4. Row occupancy: A row must contain at least one chain.

c chains

X[c, r] 1

5. Diffusion sharing: For every pair of chains ci and cj, and for each row r, merged[ci, cj, r] determines if they are placed in orientations such that ci can share its diffusions with cj placed to its immediate right.
merged[ci, cj, r] = (5) or {X[ci, r] and X[cj, r] and Y[ci, oi] and Y[cj, oj] : oi O[ci], oj O[cj], share[ci, oi, cj, oj]}

Here, S is the maximum number of slots required. To be used in a 0-1 model, the integer variables slots are made binary by representing them as an array of 0-1 variables. 6. Inter-row connectivity: These constraints are similar to those described in Section 3 for the non-hierarchical 2-D cell layout model. Cost function: The objective of the hierarchical model is the same as that of the non-hierarchical model, that is,
Minimize Wcell = max {Wr: for each P/N row r rows},

where, the width Wr of each row r given by equation (4) can be formulated as follows:
Wr =
c chains

(X[c, r] chainCost[c])
c1, c2 chains

We also need to ensure that a chain can be merged with at most one chain on its immediate left and right.
r rows cj chains, cj ci r rows cj chains, ci cj

c chains

+ X[c, r]

merged[c1, c2, r] + V[r, n] 1

n nets

merged[ci, cj, r] 1 merged[cj, ci, r] 1

ci chains ci chains

5 Experimental Results
The hierarchical 0-1 ILP model has been solved using OPBDP (Optimization with Pseudo-Boolean Davis-Putnam) [1], a specialized solver for binary ILPs. Table 4 presents our results for placements in one through four P/N rows for typical circuits with up to 100 transistors. Where feasible, we also present the optimal cell width obtained with our non-hierarchical method [5]. When the optimum widths are not known, Table 4 presents a lower bound for Wcell, which ignores the effects of the inter-row connectiv-

Finally, we need to prevent cyclic conditions in diffusion sharing. For example, if chains c1, c2, and c3 are placed in row r, then merged[c1, c2, r] = merged[c2, c3, r] = merged[c3, c1, r] = 1 implies the impossible cyclic placement <c1, c2, c3, c1>. To prevent such cycles, we extend the basic model as follows: For each set of chains <ci, ci+1,

#
1.

Circuit
8-input NAND [11]

No. of No. Lower Non-hiera [5] Hierarchical trans. of bound Run CPU / P/N on Opt. time time clusters rows Wcell Wcell (secs) Wcell (secs)
24 / 5 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 1 2 3 4 14 7 5 4 16 8 5 5 22 12 7 5 23 11 7 5 27 13 9 6 33 16 11 8 46 23 15 11 52 26 17 13 58 29 19 14 14 7 5 4 16 8 5 5 22 12 * * 23 * * * * * * * * * * * * * * * * * * * * * * * 3 19 58 231 13 150 226 3,072 447 22,150 * * 4,454 * * * * * * * * * * * * * * * * * * * * * * * 14 7 5 4 16 8 7 7 22 12 9 9 23 11 8 5 27 14 9 7 33 16 11 8 46 23 16 13 52 26 17 13 58 29 20 14 0.03 0.05 0.07 0.1 0.01 0.02 0.03 0.05 0.02 0.1 0.3 0.5 5 3 10 3 0.01 0.03 0.05 0.08 0.2 3.3 0.6 2 0.2 8 46 172 0.05 21 280 906 0.5 1 5 15

6 Conclusions
We have presented a new hierarchical technique to generate minimum-width layouts of complex CMOS cells in the two-dimensional style. The problem is formulated as an integer linear program that models the various factors that inuence 2-D cell width. It extends the non-hierarchical ILP-based approach for 2-D layouts [5] to much larger circuits while producing area-efcient layouts in practical time. It is also applicable to the layout of 2-D cell arrays, where the layout of each cluster is maintained as a group and diffusion sharing must be considered only between the chains that appear at either end of each cluster layout. The technique has proven to be more efcient, both in terms of the nal layout and run time, than prior methods.

2.

Full adder [2]

28 / 4

4-to-1 3. multiplexer with enable [6] 4-bit parity 4. stage (5-bit parity circuit) [6] 5. 2-to-4 decoder [6]

34 / 4

40 / 8

7 References
[1] P. Barth, A Davis-Putnam Based Enumeration Algorithm for Linear Pseudo-Boolean Optimization, Tech. report MIP-I95-2-003, Max-Planck-Institut Fur Informatik, Jan. 1995. [2] D. G. Baltus and J. Allen, SOLO: A Generator of Efcient Layouts From Optimized MOS Circuit Schematics, Proc. 25th Design Automation Conf., pp. 445-452, June 1988. [3] C. C. Chen and S. L. Chow, The Layout Synthesizer: An Automatic Netlist-to-Layout System, Proc. 26th Design Automation Conf., pp. 232-238, June 1989. [4] A. Gupta, S-C. The, and J. P. Hayes, XPRESS: A Cell Layout Generator with Integrated Transistor Folding, Proc. European Design & Test Conf., pp. 393-400, March 1996. [5] A. Gupta and J. P. Hayes, Width Minimization of TwoDimensional CMOS Cells Using Integer Programming, Proc. Intl Conf. on CAD, Nov. 1996, to appear. [6] D. V. Heinbuch, CMOS3 Cell Library, Addison-Wesley, Englewood Cliffs, NJ, 1988. [7] Y-C Hsieh, C-Y Hwang, Y-L Lin, and Y-C Hsu, LiB: A CMOS Cell Compiler, IEEE Trans. on CAD, Vol. 10, pp. 994-1005, Aug. 1991. [8] R. L. Maziasz and J. P. Hayes, Layout Minimization of CMOS Cells, Kluwer, Boston, 1992. [9] G. L. Nemhauser and L. A. Wolsey, Integer and Combinatorial Optimization, John Wiley, New York, 1988. [10] C.L. Ong, J.T. Li, and C.Y. Lo, GENAC: An Automatic Cell Synthesis Tool, Proc. 26th Design Automation Conf., pp. 239-244, June 1989. [11] T. Sadakane, H. Nakao, and M. Terai, A New Hierarchical Algorithm for Transistor Placement in CMOS Macro Cell Design, Proc. Custom Integrated Circuits Conf., pp. 461464, 1995. [12] K. Tani, et al., Two-Dimensional Layout Synthesis for Large-Scale CMOS Circuits, Proc. Intl Conf. on CAD, pp. 490-493, Nov. 1991. [13] T. Uehara and W.M. VanCleemput, Optimal Layout of CMOS Functional Arrays, IEEE Trans. on Computers, Vol. C-30, pp. 305-312, May 1981. [14] S. Wimer, R.Y. Pinter, and J.A. Feldman, Optimal Chaining of CMOS Transistors in a Functional Cell, IEEE Trans. on CAD, Vol. CAD-6, pp. 795-801, Sept. 1987. [15] H. Zhang and K. Asada, An Improved Algorithm of Transistors Pairing for Compact Layout of Non-Series-Parallel CMOS Networks, Proc. Custom Integrated Circuits Conf., pp. 17.2.1-17.2.4, 1993.

42 / 7

6.

2-bit adder

56 / 8

8-to-1 7. multiplexer with enable [6]

72 / 7

8. 3-bit carry look-ahead 76 / 13 circuit [6] 9. 3-to-8 decoder [6] 94 / 12

Table 4: Comparison of non-hierarchical and hierarchical 2-D cell layouts

a. An asterisk indicates that OPBDP did not terminate after 5,000 seconds.

ity in equation (2) on the cell width. For a circuit with p P/ N pairs that requires g diffusion gaps in an optimal 1-D placement, the lower bound on Wcell for a 2-D placement in r rows is given by (p + g r + 1) / r, since each P/N row effectively eliminates a diffusion gap. Run times were obtained with the OPBDP solver (version 1.0 with the h103 variable selection heuristic) on the HP 9000/735 work-station. As these results indicate, the proposed method yields optimal 1-D cell widths in all cases with run times that are in seconds, several orders of magnitude better than those of the 1-D hierarchical technique of Sadakane et al. [11]. Moreover, unlike [11], our technique guarantees a layout of minimum width for a given set of covers, and solves the 2-D layout problem as well. For most circuits, the resulting 2-D layouts have widths that are close to the lower bound; they are optimal in over 60% of the cases. The average deviation from the conservative lower bound is only 10%. In most cases, the run times are several orders of magnitude less than those of the non-hierarchical approach.