Signal Integrity for High Speed Digital Design

Introduction

Gustaaf Sutorius Application Engineer

Agenda
Signal Integrity for High Speed Digital Design : introduction

1. Introduction Agilent 2. Typical Digital Development Process + Example 3. What is Signal Integrity? 4. 3 Es: Signal Conditioning & Measuring 5. Agilent Solutions for Signal Integrity 6. Signal Integrity & IO Standards

Agenda
Signal Integrity for High Speed Digital Design : introduction

1. Introduction Agilent 2. Typical Digital Development Process + Example 3. What is Signal Integrity? 4. 3 Es: Signal Conditioning & Measuring 5. Agilent Solutions for Signal Integrity 6. Signal Integrity & IO Standards

Agilent Markets
44 billion measurement market Electronic Measurement
Communications Aerospace/Defense General purpose

Bio-Analytical Measurement Bio-Analytical Measurement

Life science Chemical analysis

Agilent Laboratories
Applied research Research in existing businesses Research in new businesses

Signal Integrity June 2010

Agilents FY09 Revenue -- 4.5 Billion

Primary Businesses
FY09 Revenue: 2.4B FY09 Revenue: 0.9B FY09 Revenue: 1.2B

Electronic LTM Revenue* Measurement Group

Chemical Analysis LTM Revenue* Group

2.7B

1.1B

Life Sciences LTM Revenue* Group

1.0B

above reflects new segmentation that will take effect in Q1 2010

Currently Reported Segmentation (until new segmentation above reported in Q1 2010)

Electronic Measurement FY09 Revenue: 2.2B Semi & Board Test: 0.2B Bio-Analytical Measurement FY09 Revenue: 2.1B
to be reported separately as life sciences and chemical analysis

to be combined under electronic measurement

Signal Integrity Page 5 June 2010

Agenda
Signal Integrity for High Speed Digital Design : introduction

1. Introduction Agilent 2. Typical Digital Development Process + Example 3. What is Signal Integrity? 4. 3 Es: Signal Conditioning & Measuring 5. Agilent Solutions for Signal Integrity 6. Signal Integrity & IO Standards

Typical Digital Development Process

System Design

Interconnect Design

Active Signal Analysis

Compliance Test

Accurate Models & Simulations Accurate Design Analysis Hardware & Software Correlation

Accurate Models Accurate Simulations Hardware & Software Correlation

Measure

Accurate Design Analysis Test & Analysis Capability Measurement Automation

Increased Team Effectiveness Measurement Automation Test & Analysis Capability

Signal Integrity Solutions Portfolio (assisting this digital development process)

Actual Development Example: SDR in FPGA

System Design

Interconnect Design

Active Signal Analysis

Compliance Test

Accurate Models & Simulations Accurate Design Analysis Hardware & Software Correlation

Accurate Design Analysis Test & Analysis Capability Measurement Automation

Example: SDR Design implemented on XILINX Spartan 3E Demo Board

Xilinx Spartan 3E

SDR Model created in SystemVue VHDL code automatically generated from Fix-point representation of the model ISE Projects generated with VHDL code Compilation of Designs onto Spartan 3E Evaluation Board *.bit and *.cdc files created to use ATC2 and ILA core FPGA probing
Output Pins JTAG

Thomas Kirchner

Flow
1. Develop a model for a digital Software Defined Radio Design using SystemVue from Agilent eeSof 2. Verification of model (modulated IQ-signal) using VSA SW in SystemVue 3. Generate VHDL code from SystemVue Model 4. Create a XILINX ISE Project with VHDL code from SystemVue. And put this in the Spartan 3E 5. Insert ILA core and debug FPGA design using XILINX Chipscope 6. Insert Agilent ATC2 core and debug design using Agilent dynamic FPGA probe in Logic Analyzer 7. Verify design and decode digital IQ data using Agilent Logic Analyzer and IQ demodulator (VSA 89601A SW)
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Why this Flow

Software Defined Radio Design is complex and needs to be flexible to adjust feature to requirements High level System Design Model is needed and the ability of automated VHDL code generation Complex Designs require Debug- and Verification using Timing-, Stateand PHYS Layer Characterization

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Thomas Kirchner

Example: SDR model in SystemVue:

Fixed Point Mapper with different modulation formats, like:
QAM16 BPSK QPSK ... User Defined

Thomas Kirchner

Short demonstration uSystemVue SystemVue: QAM16_complete_tb(schematic) VSA 89601A: PRBS_set_gustaaf.set

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Thomas Kirchner

Verification of modulated IQ-signal using VSA SW in SystemVue:

Thomas Kirchner

Automated VHDL code generation from model and start of Co-Simulation e.g. with ModelSim

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Thomas Kirchner

Verification on hardware using Chipscope (ILA Core and FPGA Block RAM)
FPGA JTAG Probe points
Merits:
No additional pins required Inexpensive Select many nets

ILA

Block RAM

Tradeoffs:
Consumes FPGA RAM Synchronous capture Limited memory depth (32 k)

Note: Not just consumption of important FPGA memory. As with all cores, inclusion of a logic analyzer core will have an impact on the design itself. For this reason, many engineers prefer to leave the core in the FPGA even after the design is debugged.

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Verification on hardware using Agilent Trace Core (ATC2) ATC2

Output to FPGA pins for debug
4 -128

Selection MUX Selection MUX

Up to 64 signal banks All banks have identical width (4 to 128 signals wide)

4 - 128 4 - 128 4 - 128

clk

4 -128

clk

Change signal bank selection from MSO`

Rapid Debug of FPGA-based Systems using Page 18 MSOs, 4/2/2011

JTAG Select

Up to 16 digital channels on MSOs 128 channels on Logic Analyzer

Verification on hardware using ATC2 Logic Analyzer with B4655A FPGA Dynamic Probe
FPGA Dynamic Probe SW application

Probe core output

Parallel

PC Board

FPGA
Insert ATC2 core with Core Inserter Control access to new signals via JTAG
ATC2

JTAG

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Hardware Connection To Logic Analyzer

Step 1. Connect any logic analyzer pod to flying lead probes or Soft Touch Pro probe adapter. You dont need to connect a specific pod to the flying lead cables as the automated pin mapping portion of the demo will take care of bit assignments to the correct pod. You do need to hook the flying lead Clk lead to the specific vertical pin as shown because the clock signal comes to that pin. Any twelve flying leads can be connected to pins with data signals as shown below (note, 3 grounds are marked and ground wires can be connected, and do not hook leads to locations marked as Vcc) Alternatively, if using Soft Touch Pro Series, connect a Soft Touch Pro probe adapter (end with micro-spring pins) to the Soft Touch footprint on the board. Align Agilent with Agilent. There should be a retention module soldered in. If not, use a retention module supplied with the probe. USB cable connection point to board, other end to logic analyzer USB input

Clk must go here

Flying Lead Connection

Verification of hardware using Logic analyzer with VSA SW

Thomas Kirchner

Short demonstration using N5406A FPGA dynamic probe on oscilloscope

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Thomas Kirchner

Assign signals as shown below in the window Pin Mapping

Analysis of PRBS-Generator with Chipscope ILA

PRBS Signal is captured by Chipscope ILA Core and stored in Block RAM Data are read out to Chipscope Program on PC Cost effective solution does not require LA or MSO RAM Resources are rare and limited size No correlation to external signals possible For changes of Trigger, new compilation of the ILA Core has to be done This Example: Comparison of PRBS Polynom with reference from Agilent Pattern Generator

Thomas Kirchner

Analysis of PRBS-Generator with ATC2 core and LA

Agilent Eye Finder: good for >100Mbit/s data rate Optimize sample point and threshold Individual adjustment possible Good for skew measurements All signals simulatenously measured Data stored on LA with upto 256MSa/ch

Thomas Kirchner

Agenda
Signal Integrity for High Speed Digital Design : introduction

1. Introduction Agilent 2. Typical Digital Development Process + Example 3. What is Signal Integrity? 4. 3 Es: Signal Conditioning & Measuring 5. Agilent Solutions for Signal Integrity 6. Signal Integrity & IO Standards

What Is Signal Integrity- Wikipedia

http://en.wikipedia.org/wiki/Signal_integrity

Signal integrity or SI is a measure of the quality of an electrical signal. In digital electronics, a stream of binary values is represented by a voltage (or current) waveform. Over short distances and at low bit rates, a simple conductor can transmit this with sufficient fidelity. However, at high bit rates and over longer distances, various effects can degrade the electrical signal to the point where errors occur, and the system or device fails. Signal integrity engineering is the task of analyzing and mitigating these impairments. Signal integrity engineering is at all levels of electronics packaging, from internal connections of an IC through the package, the printed circuit board (PCB), the backplane, and inter-system connections. Some of the main issues of concern for signal integrity are ringing, crosstalk, ground bounce, and power supply noise.

Signal Integrity- Challenges In Digital Design Today

Higher Data Rates Are Causing Signal Integrity (SI) Problems:
Need to include high-frequency effects like interconnects in simulation and layout Need high quality probes and fixtures Need to minimize jitter

FPGAs Are Commonplace:

Cant use a Reference Design without some analysis Harder to simulate the overall performance Need to characterize the I/O buffers

Standards Evolve Every 2-3 Years:

Leveraging existing designs gets harder Measurement requirements get tighter Need to buy new equipment each time

PCI Express
5 Gb/s 2.5 Gb/s 2003 2008

8 Gb/s

2009 2014 2006 2011

Data Rates Of Key Serial I/O Technologies

USB PCI Express Serial ATA SAS Fibre Channel Ethernet HDMI DisplayPort FB-DIMM DDR Available Planned 0 1G 1 1.6G 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Gb/s 480M 2.5G 1.5G 1.5G 1G 1G 1.6G 2.7G 3G 3G 2G 4G 3.125 (XAUI) 3.4G 5.4G 4.8G 9.6G 5G 5G 6G 6G 8G 10G 16G 8G

Signal Integrity is important

Current Serial Applications And Their Rise Time

Application Signal Rate 480Mbps Up to 800MT/s Up to 1.6GT/s 1.5Gbps 3Gbps 1.5Gbps 3Gbps 6Gbps 2.5Gbps 5Gbps 2.5Gbps 4.25Gbps 8.5Gbps 3.125Gbps 3.4Gbps 1.65Gbps 2.7Gbps 4.8Gbps 9.6Gbps Fundamental Freq 240MHz 400MHz 800MHz 750MHz 1.5GHz 750MHz 1.5GHz 3GHz 1.25GHz 2.5GHz 1.25GHz 2.125GHz 4.25GHz 1.5625MHz 1.7GHz 825MHz 1.35GHz 2.4GHz 4.8GHz 35ps 25ps?? 50ps 45ps 50ps 75ps 60ps 60ps 75ps 75ps 75ps 45ps 45ps Rise Time
Base (at GBA) CEM/Probing Point

Optimum scope Bandwidth & Sample Rate Brickwall S.Rate 3.6GSa/s 5.8GSa/s 13.9GSa/s 13.5GSa/s 20.2GSa/s 20.2GSa/s 20.2GSa/s 28.1GSa/s 13.4GSa/s 30GSa/s 13.4GSa/s 18GSa/s 22GSa/s 22GSa/s 18GSa/s 18GSa/s 18GSa/s 30GSa/s Gaussian 2.0GHz 3.3GHz 7.9GHz 7.9GHz 11.3GHz 11.3GHz 11.3GHz 15.9GHz 7.9GHz 17GHz 7.9GHz 10.1GHz 12.7GHz 12.7GHz 10.1GHz 10.1GHz 10.1GHz 17GHz 17GHz S.Rate 8GSa/s 13.2GSa/s 31/5GSa/s 30.5GSa/s 45.2GSa/s 45.2GSa/s 45.2GSa/s 63.6GSa/s 31.6GSa/s 68GSa/s 31.6GSa/s 40.4GSa/S 50.8GSa/s 50.8GSa/s 40.4GSa/S 40.4GSa/S 40.4GSa/S 68GSa/s 68GSa/s

USB2.0 DDR2 DDR3 Serial ATA I Serial ATA II SAS150 SAS300 SATA III / SAS600 PCI Express Gen I PCI Express Gen II ExpressCard Fibre Channel 4G Fibre Channel 8G XAUI HDMI 1.3 DVI DisplayPort FBD I FBD II

500ps (10-90%) 288ps (10-90%) 120ps (10-90%) 100ps 67ps 67ps 67ps 47.7ps 100ps TBD 100ps

1.5GHz 2.4GHz 5.8GHz 5.6GHz 8.4GHz 8.4GHz 8.4GHz 11.7GHz 5.6GHz 12.5GHz 5.6GHz 7.5GHz 9.3GHz 9.3GHz 7.5GHz 7.5GHz 7.5GHz 12.5GHz

12.5GHz 30GSa/s DSA90000A

Note Gustaaf : 20-80 % risetimes recently measured with an 90.000 X oscilloscope 32 GHz 13.4 picoSecond, 16 GHz bandwidth 19.4 pico Second, 12 GHz 25.8 picoSecond, 4 GHz 84 psec, 1 GHz 271 picosecond

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What Is Signal Integrity- Time Domain

driver driver

3 PCB Trace

receiver

3 PCB Trace
Series termination (~40 Ohms)

Signal Integrity = Where the electrical properties of the interconnects can cause significant distortions in digital signals. >1 GHz of bandwidth <1 ns risetime Typically >2 Gb/s data rate with embedded clock Signal Integrity = Paying attention to RF effects, ie. impedance

What Is Signal Integrity - Four Signal Integrity Problems And Their Causes
1. Poor signal quality of one net: reflections and distortions from impedance discontinuities in the signal or return path 2. Crosstalk between multiple nets: mutual C and mutual L coupling 3. Rail collapse (Ground Bounce) in the power distribution system: voltage drops across impedance in the power/ground network 4. Jitter from causes listed above and variety of other sources including clock distribution, data dependent effects, and EMI

What Is Signal Integrity- Eye Diagram

FR4 is showing its limitations
FR4 is common, low cost and easy to manufacture BUT it has problems:
Reflections at high speeds Dispersion varies with frequency High Insertion Loss ISI induced Jitter Effects vary with temperature and humidity What Works Today
3.125 Gb/s

Gets Worse The Next Time

6.25 Gb/s

No longer usable

12.5 Gb/s

Agenda
Signal Integrity for High Speed Digital Design : introduction

1. Introduction Agilent 2. Typical Digital Development Process + Example 3. What is Signal Integrity? 4. 3 Es: Signal Conditioning & Measuring 5. Agilent Solutions for Signal Integrity 6. Signal Integrity & IO Standards

Signal Conditioning Basics

TX Channel RX

Source Signal Modify signal to anticipate highfrequency loss

Frequency Response Reduce trace lengths and discontinuities

Received Signal Post-process signal to estimate real bit levels

3 Es: Signal Conditioning & Measuring

TX Channel RX

Emphasis: Pre-emphasis De-emphasis

Embedding: De-embed path Emulate path

Equalization: Passive (Linear Feedforward Eq.) Active (Decision Feedback Eq.)

Agenda
Signal Integrity for High Speed Digital Design : introduction

1. Introduction Agilent 2. Typical Digital Development Process + Example 3. What is Signal Integrity? 4. 3 Es: Signal Conditioning & Measuring 5. Agilent Solutions for Signal Integrity 6. Signal Integrity & IO Standards

Agilents Signal Integrity Solutions

Advanced Design System

Infiniium 90000 X-Series

N1930B Physical Layer Test System (PLTS)

Pulse Pattern Generator 16900 Series Logic Analyzers

Bit Error Ratio Testers (BERTs)

86100D Infiniium DCA-X

ENA-TDR

Agilent Oscilloscope Portfolio

Agilent is the fastest growing oscilloscope vendor since 1999, with accelerating growth
Source: Prime Data Market Share Analysis

DCA-J X-Series

90000 X-Series

90000 Series

9000 Series 7000B Series 5000Series U1600A Series U2700 Series 1000 Series 6000 Series

Agilent Infiniium Series of Oscilloscopes

Specification Bandwidth Sample Rate Standard Memory Max Memory

Infiniium 9000A 600MHz 4GHz 20GSa/s / 10GSa/s 10M 1G

Specification Bandwidth Sample Rate Standard Memory Max Memory

Infiniium 90000A 2.5GHz 13GHz 40GSa/s / 20GSa/s 10M 1G

Specification Bandwidth Sample Rate Standard Memory Max Memory

Infiniium 90000-X 16GHz 32GHz 80GSa/s / 40GSa/s 10M 2G

600MHz

1GHz

2.5GHz

4GHz

6GHz

8GHz

12GHz

13GHz

16GHz

20GHz

32GHz

40

Infiniium 90000 X-Series Oscilloscopes

Engineered for true analog bandwidth that delivers The highest real-time scope measurement accuracy Complete 30 GHz oscilloscope probing system The industrys most comprehensive applicationspecific measurement software
Bandwidth upgradeable for investment protection 6 New Scope Models DSO/DSA91604A DSO/DSA92004A DSO/DSA92504A DSO/DSA92804A DSO/DSA93204A Analog Bandwidth (2 ch) 16 GHz 20 GHz 25 GHz 28 GHz 32 GHz Max Sample Rate (2 ch/4 ch) 80/40 GSA/s 80/40 GSA/s 80/40 GSA/s 80/40 GSA/s 80/40 GSA/s Std Memory 10M 10M 10M 10M 10M Max Memory 2 Gpts 2 Gpts 2 Gpts 2 Gpts 2 Gpts Noise @ 50mV/div 1.34 mV 1.53 mV 1.77 mV 1.89 mV 2.08 mV Jitter Measurement Floor 150 fs rms 150 fs rms 150 fs rms 150 fs rms 150 fs rms Base Price DSO Model 131,000 160,000 199,000 226,000 266,000 Base Price DSA Model * 148,000 178,000 217,000 245,000 286,000

Note Gustaaf: achieved jitter specs now similar to 86100 repetitive sampling scopes

Probing Methods
InfiniiMax Active Differential Probes
30 GHz Solder-in, Socket, Browser, SMA, ZIF Differential or Single-ended Use with Real-time Scope, DCA-J & BERT

Soft Touch Probes:

No PCB layout modification required No remaining stubs or sockets Use with 16800/16900 Series Logic Analyzers, E2960 Series PCI Express Tools

DDR2/3 BGA Probes:

Access Command & Data signals Use with Scopes & Logic Analyzers

Interconnect Modeling & Simulation

Differential Measurements:
TDR for first order model VNA for higher accuracy PLTS for automated calibration & differential measurements

Simulation:
Use measured data in ADS Optimize model for measured vs. simulated correlation Virtual probing to assess hard to measure signals EM analysis of layout

86100D DCA-X/TDR

20GHz PNA-L

PLTS Software

Advanced Design System (ADS)

EDA Signal Integrity Analysis Tools

Pre-layout and Post-layout design and verification

Circuit Simulation
Linear, Nonlinear Simulators IBIS I/O Models S-parameter Models Multilayer Transmission Line Models FPGA I/O Design Kits

Package and Board Level Simulation

Method-of-Moments 3DEM Simulation Technology for Traceand-via Geometry

High Speed Channel Design

Bit-by-bit and statistical modes Eye diagram measurements and analysis

Bond Wire, Solder ball, and Connector Simulation

Finite Element Method and FiniteDifference Time-Domain EM Simulation Technologies for Arbitrary 3D Geometry

Adaptive Equalization
Automatic tap optimization

Agenda
Signal Integrity for High Speed Digital Design : introduction

1. Introduction Agilent 2. Typical Digital Development Process + Example 3. What is Signal Integrity? 4. 3 Es: Signal Conditioning & Measuring 5. Agilent Solutions for Signal Integrity 6. Signal Integrity & IO Standards

Typical Digital Development Process

System Design

Interconnect Design

Active Signal Analysis

Compliance Test

Increased Team Effectiveness Measurement Automation Test & Analysis Capability

Signal Integrity vs. I/O Standards

Design Methodology vs. Design Specifications

Technology Technology

Signal Integrity

Agilent Digital Standards Program

Our solutions are driven and supported by Agilent experts involved in international standards committees: Joint Electronic Devices Engineering Council (JEDEC) PCI Special Interest Group (PCI-SIG) Video Electronics Standards Association (VESA) Serial ATA International Organization (SATA-IO) USB-Implementers Forum (USB-IF) Mobile Industry Processor Interface (MIPI) Alliance Optical Internetworking Forum (OIF) Were active in standards meetings, workshops, plugfests, and seminars Our customers test with highest confidence and achieve compliance faster
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Agilent Digital Standards Program

Industrys most comprehensive application-specific measurement software: Pre-built compliance testing software with our applications experts
Best measurement accuracy means better design margins for faster compliance verification Set-up wizards and full automated reporting free engineering resources Industry leading 2 GPts of memory allows longer test patterns for better stress testing Agilent experts on standards committees ensure proper testing

Compliance Testing
Ethernet compliance application PCI EXPRESS compliance application HDMI compliance application SAS compliance application DisplayPort compliance application MIPI D-PHY compliance application 10GBASE-T Automated Test Application WiMedia Wrapper Compliance Test Application SATA 6Gb/s Compliance User Defined Application USB 3.0 Compliance Software

Agilent Digital Standards Program: SATA example

Functional Validation: PCI Express example

Debug Analysis:
EyeFinder and EyeScan to trigger on desired system event Find parametric, timing and protocol violations

Protocol Test:
Emulate live traffic Analyze traffic with multiple views Stress test by forcing errors

16900 Logic Analysis System

E2960B PCI Express Protocol Test Tools

Questions?

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