TCC8200 v0.2 20060425

SPECIFICATION
TCC8200
32-bit RISC
Microprocessor
For
Multimedia Applications
Rev. 0.20
Apr. 18 2006
DISCLAIMER
All information and data contained in this datasheet are without any commitment, are not to
be considered as an offer for conclusion of a contract, nor shall they be construed as to
create any liability. Any new issue of this datasheet invalidates previous issues. Product
availability and delivery are exclusively subject to our respective order confirmation form;
the same applies to orders based on development samples delivered. By this publication,
Telechips, Inc. does not assume responsibility for patent infringements or other rights of
third parties that may result from its use.
Further, Telechips, Inc. reserves the right to revise this publication and to make changes to
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transmitted without the express written consent of Telechips, Inc.
Important Notice
This product may include technology owned by Microsoft Corporation and in this case it cannot be used or distributed
without a license from Microsoft Licensing, GP.
For customers who use licensed Codec ICs and/or licensed codec firmware of mp3:
“Supply of this product does not convey a license nor imply any right to distribute content created with this
product in revenue-generating broadcast systems (terrestrial. Satellite, cable and/or other distribution channels),
streaming applications(via internet, intranets and/or other networks), other content distribution systems(pay-
audio or audio-on-demand applications and the like) or on physical media(compact discs, digital versatile discs,
semiconductor chips, hard drives, memory cards and the like). An independent license for such use is required.
For details, please visit http://mp3licensing.com”
For customers who use other firmware of mp3:
“Supply of this product does not convey a license under the relevant intellectual property of Thomson and/or
Fraunhofer Gesellschaft nor imply any right to use this product in any finished end user or ready-to-use final
product. An independent license for such use is required. For details, please visit http://mp3licensing.com”
Revision History
Date Version Description

2006-2-27 0.10 Initial release
2006-3-9 0.11 Table1.19 RTC_VDD1 ball number M9 -> N8
Introduction
TCC8200 Specification
Multimedia Application Processor INTRODUCTION
1 INTRODUCTION
TCC82xx series are system LSI for multimedia application processor based on the ARM946E-S, ARM’s
proprietary 32-bit RISC CPU core. It can decode and encode (M)JPEG, MPEG4, MP3 or other types of audio /
voice / video / image compression / decompression standards by software based architecture. The on-chip USB
2.0 compliant controller enables the data transmission between a personal computer and storage device such as
NAND flash, SD.
Table 1.1 Derivatives of TCC82xx

Name Package Description
TCC822x 160-FBGA-0808 System LSI for Multimedia Mobile Applications.
TCC8200 256-FBGA-1313 System LSI for Multimedia Portable Applications.
1.1 Features
• General features
ARM946E-S CPU core ( 16KB instruction/data cache, operating up to 200MHz )

8K bytes of internal boot ROM with various boot procedure (NAND, USB, EHI) and security
64K bytes of internal SRAM for general usage
4K bytes of data TCM (Tightly Coupled Memory) for fast data access
2M / 4M / 8M / … byte stacked SDRAM
Separate Storage Bus for high speed up-load or down-load.
USB2.0 Device (high, full speed)
ECC generator for SLC and MLC NAND Flash
I2S interface for external audio
2 channel UART
1 channel SPI, supports master & slave mode.
GPIO for various purposes
Support 4 external interrupts
I2C compatible serial bus for audio CODEC & CCD/CMOS sensor control
3-Channel general DMA controller for transferring a bulk of data
1-Channel dedicated USB DMA controller for fast access via USB interface
Four 16bit timer/counters and two 20bit timers
32-bit 1Hz counter
JTAG interface for code debugging
RTC (Real Time Clock) for battery backup
EHI (External Host Interface) for parallel host interface
SecureDigital Card (SD)
MultiMedia Card (MMC)
SLC / MLC NAND Flash Memory
1-1
• Multimedia features
¾ Sensor
CCIR601, CCIR656, YCbCr4:2:2 8bit interface
Up-to 3M pixel
Image windowing
1 sensor overlay
Image downscaling ( X/32 and Y/32 )
Zooming ( x 8 )
Image effect (Gray / Negative / Sepia / Emboss / Sketch & ETC. )
¾ LCD
supports STN and TFT LCD
CCIR601, CCIR656 interface
Overlay and alpha blending ( 2 overlay )
2 LCD ( main.QVGA, sub.QVGA ) 8, 12, 16, 18-bit interface
Display image up/down scaling ( x2, x3, x4, x8 )
YCbCr-to-RGB and RGB-to-YCbCr color space converting
Max 30fps QVGA preview
90°, 180°, 270° Rotate Preview Support
Display image up/down scaling ( x2, x3, x4, x8 )
¾ 2D Accelerator
BitBLT (16 Raster Operations)
Mirror, Flip, 90°, 180°, 270° rotate
Color space converting
Memory-to-memory image scaling ( downscaling /32 X, Y independently, 8x zooming )
¾ Still Image
JPEG encoding 4:2:2/4:2:0 ( up-to 3M pixel )
90°, 180°, 270° rotate capture support up to VGA (depends on the stacked SDRAM capacity.)
JPEG decoding 4:4:4/4:2:2/4:2:0/4:1:1 ( free size decoding under 4096x4096 )
¾ Moving Picture
JPEG encoding 4:2:2/4:2:0 ( up-to 3M pixel )
H/W MJPEG encoding/decoding 15fps ( up-to QVGA )
S/W MPEG4 encoding 15fps ( up-to QCIF )/decoding 15fps (up-to QVGA)
* MPEG4 en/decoding H/W accelerator: DCT/IDCT, SAD, VLC/VLD Table
• 0.13um low power CMOS process
• 1.1V ~ 1.3V for core, 1.8V ~ 3.3V for I/O port
1.2 Applications
y Multimedia Mobile
y Portable Media Player
1-2
1.3 Block Diagram
Figure 1.1 Functional Block Diagram of TCC82xx
1-3
1.4 Pin Description
The TCC82xx is a CMOS device. Floating level on input signals cause unstable device operation and abnormal
current consumption. Pull-up or pull-down resistors should be used appropriately for input or bidirectional pins.
Notation
I: Input
O: Output
I/O: Bidirectional
AI: Analog Input
AO: Analog Output
P: Power
G: Ground
Table 1.1 JTAG Interface Pins
Signal Name Type Description

RTCK O Clock synchronization signal for ARM946E-S
TDI I JTAG serial data input for ARM946E-S
TMS I JTAG test mode select for ARM946E-S
TCK I JTAG test clock for ARM946E-S
TDO O JTAG serial data output for ARM946E-S
nTRST I Reset signal for boundary scan logic. Active low.
Table 1.2 Host Interface & System Pins

TEST I Test mode
RESETn I System reset
CPZB I EHI port protection
BPEN I LCD bypass enable
EHI_D[17:0] I/O EHI data bus
EHI_INT O EHI interrupt
EHI_XA I EHI address
EHI_CSN I EHI chip select
EHI_WEN I EHI write enable
EHI_OEN I EHI output enable
EHI_CSSEL I EHI CS signal selection
1-4
Table 1.3 Serial I/O & External Interrupt

UT0_RXD I UART0 Rx Data
UT0_TXD O UART0 Tx Data
UT0_nCTS I UART0 CTS
UT0_nRTS O UART0 RTS
UT1_RXD I UART0 Rx Data
UT1_TXD O UART0 Tx Data
UT1_nCTS I UART0 CTS
UT1_nRTS O UART0 RTS
SDI I SPI Data In
SDO O SPI Data Out
SCK I/O SPI clock
FRM I/O SPI Frame
Table 1.4 NAND Interface

ND_D[7:0] I/O NAND data
ND_CS[0] O NAND chip select 0
ND_CS[1] O NAND chip select 1
ND_WEN O NAND write enable
ND_OEN O NAND ouput enable
ND_CLE O NAND control latch enable
ND_ALE O NAND address latch enable
ND_READY0 I NAND ready 0
ND_READY1 I NAND read 1
Table 1.5 SD Interface

SD_D[3:0] I/O SD data
SD_CLK O NAND chip select 0
SD_CMD O NAND chip select 1
SD_INS O NAND write enable
SD_WPROT O NAND ouput enable
Table 1.6 AUDIO Interface

BCLK I/O SD data
LRCLK I/O NAND chip select 0
MCLK I/O NAND chip select 1
SDI I NAND write enable
SDO O NAND ouput enable
SDA Audio Codec control I2C SDA
SCL Audio Codec control I2C SCL
1-5
Table 1.7 SENSOR Interface

CIF_D[7:0] I/O Sensor data
CIF_MCLK O Sensor clock
CIF_PCLK I Sensor pixel clock
CIF_VS I Sensor vertical sync
CIF_HS O Sensor horizontal sync
CIF_PWDN O Sensor power down
SDA Sensor control I2C SDA
SCL Sensor control I2C SCL
Table 1.8 PLL

Filter 0 I/O PLL0 filter Cap
Filter 1 O PLL1 filter Cap
Table 1.9 RTC

XTIN - 32.768KHz XTAL IN
XTOUT - 32.768KHz XTAL OUT
Table 1.10 USB

DM - USB DM
DP - USB DP
REXT - REXT
XI - 12MHz XTAL IN
XO - 12MHz XTAL OUT
ATEST - USB Analog Test
1-6
1.5 Ball Assignment
Table 1.11 GPIO Group A

Name Ball Function 1 Function 2 Function 3 Bypass Mode Comments
GPIO_A[0] D3 HPXD[0] NFC_D[0] HDD_D[0] LCD_D[0]
GPIO_A[1] C1 HPXD[1] NFC_D[1] HDD_D[1] LCD_D[1]
GPIO_A[4] E4 HPXD[4] NFC_D[4] HDD_D[4] LCD_D[4]
GPIO_A[9] F4 HPXD[9] NFC_D[9] HDD_D[9] LCD_D[9]
GPIO_A[14] G5 HPXD[14] NFC_D[14] HDD_D[14] LCD_D[14]
GPIO_A[15] G4 HPXD[15] NFC_D[15] HDD_D[15] LCD_D[15]
GPIO_A[16] G3 GPIO_A[16] GPIO_A[16] GPIO_A[16] LCD_D[16]
GPIO_A[17] G2 GPIO_A[17] GPIO_A[17] GPIO_A[17] LCD_D[17]
GPIO_A[18] G1 HPINT NFC_NCS[0] HDD_nCS[0]
GPIO_A[19] H5 HPXA NFC_NCS[1] HDD_nCS[1] LCD_XA
GPIO_A[20] H1 HPCSN NFC_NWE HDD_nDIOW LCD_CSN
GPIO_A[21] H4 HPWEN NFC_NOE HDD_nDIOR LCD_WEN
GPIO_A[22] H3 HPOEN NFC_CLE HDD_DA[0] LCD_OEN
GPIO_A[23] H2 - NFC_ALE HDD_DA[1] LCD_CSN_SEL
GPIO_A[24] J5 GPIO_A[24] NFC_READY0 HDD_DA[2]
GPIO_A[25] J4 GPIO_A[25] NRF_READY1 HDD_IORDY
GPIO_A[26] J1 MBOOT[0] GPIO_A[26] GPIO_A[26]
GPIO_A[27] J2 MBOOT[1] GPIO_A[27] GPIO_A[27]
GIO_EN C3
BPEN B1
BMSEL C2
VDD_IO_A H6 GPIO_A Group I/O power (1.8 - 3.3V)
VSS_IO_A G6 GPIO_A Group I/O ground
1-7
Table 1.12 GPIO Group B

NAME BALL Function 1 Function 2 Function 3 Comments
GPIO_B[0] L2 UART0_RXD SPI_SDI
GPIO_B[1] L4 UART0_TXD SPI_SCK
GPIO_B[2] M1 UART0_CTS SPI_FRM
GPIO_B[3] M2 UART0_RTS SPI_SDO
GPIO_B[4] M5 UART1_RXD EINT[0]
GPIO_B[5] M4 UART1_TXD EINT[1]
GPIO_B[6] L3 UART1_CTS EINT[2] IDE CSN0
GPIO_B[7] N1 UART1_RTS EINT[3] ND_nWE
GPIO_B[8] P1 UART0_RXD EINT[0]
GPIO_B[9] N2 UART0_TXD EINT[1]
GPIO_B[10] M3 UART0_CTS EINT[2]
GPIO_B[11] P2 UART0_RTS EINT[3]
GPIO_B[12] T1 UART1_RXD SPI_SDI
GPIO_B[13] N3 UART1_TXD SPI_SCK
GPIO_B[14] R2 UART1_CTS SPI_FRM
GPIO_B[15] T2 UART1_RTS SPI_SDO
VDD_IO_B R1 GPIO_B Group I/O power (1.8 - 3.3V)
VSS_IO_B N4 GPIO_B Group I/O ground
1-8
Table 1.13 GPIO Group C

GPIO_C[0] M10 NFC_D[0] HDD_D[0] SD_XD[0]
GPIO_C[1] P9 NFC_D[1] HDD_D[1] SD_XD[1]
GPIO_C[2] P10 NFC_D[2] HDD_D[2] SD_XD[2]
GPIO_C[3] T11 NFC_D[3] HDD_D[3] SD_XD[3]
GPIO_C[4] N10 NFC_D[4] HDD_D[4] SD_CLK
GPIO_C[5] R11 NFC_D[5] HDD_D[5] SD_CMD
GPIO_C[6] M11 NFC_D[6] HDD_D[6] GPIO_C[6]
GPIO_C[7] P11 NFC_D[7] HDD_D[7] GPIO_C[7]
GPIO_C[8] N11 NFC_D[8] HDD_D[8] GPIO_C[8]
GPIO_C[9] T12 NFC_D[9] HDD_D[9] GPIO_C[9]
GPIO_C[10] R12 NFC_D[10] HDD_D[10] GPIO_C[10]
GPIO_C[12] P12 NFC_D[12] HDD_D[12] GPIO_C[12]
GPIO_C[14] R14 NFC_D[14] HDD_D[14] GPIO_C[14]
GPIO_C[15] N12 NFC_D[15] HDD_D[15] GPIO_C[15]
GPIO_C[16] P13 NFC_NCS[0] HDD_nCS[0] SD_XD[4]
GPIO_C[17] T16 NFC_NCS[1] HDD_nCS[1] SD_XD[5]
GPIO_C[18] P14 NFC_NWE HDD_nDIOW SD_XD[6]
GPIO_C[19] N13 NFC_NOE HDD_nDIOR SD_XD[7]
GPIO_C[20] N14 NFC_CLE HDD_DA[0] GPIO_C[20]
GPIO_C[21] R15 NFC_ALE HDD_DA[1] GPIO_C[21]
GPIO_C[22] M13 NFC_READY0 HDD_DA[2] GPIO_C[22]
GPIO_C[23] P15 NRF_READY1 HDD_IORDY GPIO_C[23]
VDD_IO_C T14 GPIO_C Group I/O power (1.8 - 3.3V)
VSS_IO_C R13 GPIO_C Group I/O ground
1-9
Table 1.14 GPIO Group E

GPIO_E[0] P3 DAI_BCLK
GPIO_E[1] R3 DAI_LRCLK
GPIO_E[2] P4 DAI_MCLK
GPIO_E[3] T3 DAI_SDI
GPIO_E[4] R4 DAI_SDO
GPIO_E[5] T4 I2C_SDA
GPIO_E[6] P5 I2C_SCL
GPIO_E[7] N5 GPIO_E[7]
VDD_IO_E L7 GPIO_E Group power (1.8 - 3.3V)
VSS_IO_E0 K6 GPIO_E Group ground
VSS_IO_E1 L6 GPIO_E Group ground
VSS_IO_E2 K8 GPIO_E Group ground
Table 1.15 GPIO Group F

GPIO_F[0] M12 CIF_DATA[0] UART0_RXD SPI_SDI
GPIO_F[1] M14 CIF_DATA[1] UART0_TXD SPI_SCK
GPIO_F[2] L12 CIF_DATA[2] UART0_CTS SPI_FRM
GPIO_F[3] R16 CIF_DATA[3] UART0_RTS SPI_SDO
GPIO_F[4] L13 CIF_DATA[4] UART1_RXD EINT[0]
GPIO_F[5] N15 CIF_DATA[5] UART1_TXD EINT[1]
GPIO_F[6] P16 CIF_DATA[6] UART1_CTS EINT[2] IDE CSN0
GPIO_F[7] L14 CIF_DATA[7] UART1_RTS EINT[3] ND_nWE
GPIO_F[8] M15 CIF_MCLK UART0_RXD EINT[0]
GPIO_F[9] N16 CIF_PCLK UART0_TXD EINT[1]
GPIO_F[10] L15 CIF_VS UART0_CTS EINT[2]
GPIO_F[11] K13 CIF_HS UART0_RTS EINT[3]
GPIO_F[12] K12 CIF_PWDN UART1_RXD SPI_SDI
GPIO_F[13] M16 GPIO_F[13] UART1_TXD SPI_SCK
GPIO_F[14] K14 I2C_SDA UART1_CTS SPI_FRM
GPIO_F[15] L16 I2C_SCL UART1_RTS SPI_SDO
VDD_IO_F J11 GPIO_F Group power (1.8 - 3.3V)
VSS_IO_F K11 GPIO_F Group ground
1-10
Table 1.16 GPIO Group G

GPIO_G[0] C8 LCD_SI_DATA[0] LCD_DATA[0]
GPIO_G[1] D8 LCD_SI_DATA[1] LCD_DATA[1]
GPIO_G[2] A7 LCD_SI_DATA[2] LCD_DATA[2]
GPIO_G[3] E7 LCD_SI_DATA[3] LCD_DATA[3]
GPIO_G[4] B7 LCD_SI_DATA[4] LCD_DATA[4]
GPIO_G[9] E6 LCD_SI_DATA[9] LCD_DATA[9]
GPIO_G[13] F6 LCD_SI_DATA[13] LCD_DATA[13]
GPIO_G[18] D4 LCD_CSN[0] LVSYNC
GPIO_G[19] C4 LCD_CSN[1] LHSYNC
GPIO_G[20] B3 LCD_RDN LACBIAS
GPIO_G[21] A2 LCD_WRN LCD_CLK
GPIO_G[22] A1 LCD_XA GPIO_G[22] LCD_RS
GPIO_G[23] B2 GPIO_G[23] GPIO_G[23]
VDD_IO_G D6 GPIO_G Group power (1.8 - 3.3V)
VSS_IO_G C6 GPIO_G Group ground
1-11
Table 1.17 SYSTEM & JTAG

NRESET K1
TDI K2
TDO K3
NTRST K4
TEST K5
TMS L1
RTCK L5
TCK J3
Table 1.18 ADC

ADIN0 R5
ADIN1 T5
VDDA_ADC R7
VSSA_ADC N6
Table 1.19 RTC

PMWKUP P8
XTIN P7
XTOUT R6
VDD_RTC0 M8
VDD_RTC1 N8
Table 1.20 PLL

FILTER0 M6
FILTER1 T6
VDDAD_PLL0 M7
VDDAD_PLL1 N7
VSSA_PLL0 P6
VSSA_PLL1 T7
VSSD_PLL K7
1-12
Table 1.21 USB

USB_DP T8
USB_DM T9
USB_REXT R10
UTM_ATEST T10
UTM_XI N9
UTM_XO M9
VDDAC_USB R9 3V USB analog common power
VSSAC_USB R8 USB analog common ground
VDDAT_USB L10 3V USB analog total power
VSSAT_USB K9 USB analog common ground
VDDD_USB L9 1.2 V USB digital power
VSSD_USB L8 USB digital ground
Table 1.22 Memory

Static Memory SDRAM
XA[0] K15 XA[0] XA[0]
XA[1] K16 XA[1] XA[1]
XA[2] J14 XA[2] XA[2]
XA[3] J15 XA[3] XA[3]
XA[4] J13 XA[4] XA[4]
XA[5] J16 XA[5] XA[5]
XA[6] J12 XA[6] XA[6]
XA[7] H14 XA[7] XA[7]
XA[8] H16 XA[8] XA[8]
XA[9] H15 XA[9] XA[9]
XA[10] H13 XA[10] XA[10]
XA[11] G16 XA[11] XA[11]
XA[12] H12 XA[12] XA[12]
XA[13] G15 XA[13] BA[0]
XA[14] G14 XA[14] BA[1]
XA[15] G13 XA[15] -
XA[16] F16 XA[16] -
XA[17] G12 XA[17] -
XA[18] F12 XA[18] -
XA[19] F15 XA[19] -
XA[20] F14 XA[20] DQM[3]
XA[21] F13 XA[21] DQM[2]
XA[22] E16 XA[22] DQM[1]
XA[23] E15 XA[23] DQM[0]
XA[24] E12 nOE -
XA[25] E13 nWE nWE
XA[26] E14 - SDR_nCS
XA[27] D16 - SDR_CLK
1-13
XA[28] D15 - SDR_CKE
XA[29] C16 nCS[0] -
XA[30] D14 nCS[1] -
XA[31] B16 nCS[2] -
XA[32] C15 nCS[3] -
XD[0] C14
XD[1] B15
XD[2] A16
XD[3] B14
XD[4] C13
XD[5] A15
XD[6] D13
XD[7] A14
XD[8] B13
XD[9] C12
XD[10] A13
XD[11] D12
XD[12] B12
XD[13] A12
XD[14] C11
XD[15] D11
XD[16] B11
XD[17] E11
XD[18] A11
XD[19] D10
XD[20] C10
XD[21] B10
XD[22] A10
XD[23] E10
XD[24] E9
XD[25] C9
XD[26] D9
XD[27] B9
XD[28] A9
XD[29] E8
XD[30] A8
XD[31] B8
VDD_IO_X0 F9
VDD_IO_X1 H11
1.8 - 3.3V memory bus I/O power
VDD_IO_X2 G11
VDD_IO_X3 F11
VSS_IO_X0 F10
VSS_IO_X1 J10
memory bus I/O ground
VSS_IO_X2 H10
VSS_IO_X3 G10
1-14
Table 1.23 CORE power

VDD_CO0 J6
VDD_CO1 F8
VDD_CO2 G9
VDD_CO3 H9 1.1 - 1.3V core power
VDD_CO4 J9
VDD_CO5 K10
VDD_CO6 L11
VSS_CO0 F7
VSS_CO1 G7
VSS_CO2 H7
VSS_CO3 J7 core ground
VSS_CO4 G8
VSS_CO5 H8
VSS_CO6 J8
1-15
1.6 Package (TOP VIEW)
LEFT
1 2 3 4 5 6 7 8
A GP_G22 GP_G21 GP_G17 GP_G12 GP_G10 GP_G7 GP_G2 XD30
B BPEN GP_G23 GP_G20 GP_G16 GP_G11 GP_G8 GP_G4 XD31
C GP_A1 BMSEL GIO_EN GP_G19 GP_G15 VSS_IO_G GP_G5 GP_G0
D GP_A3 GP_A2 GP_A0 GP_G18 GP_G14 VDD_IO_G GP_G6 GP_G1
E GP_A8 GP_A7 GP_A6 GP_A4 GP_A5 GP_G9 GP_G3 XD29
F GP_A13 GP_A12 GP_A11 GP_A9 GP_A10 GP_G13 VSS_CO0 VDD_CO1
G GP_A18 GP_A17 GP_A16 GP_A15 GP_A14 VSS_IO_A VSS_CO1 VSS_CO4
H GP_A20 GP_A23 GP_A22 GP_A21 GP_A19 VDD_IO_A VSS_CO2 VSS_CO5
J GP_A26 GP_A27 TCK GP_A25 GP_A24 VDD_CO0 VSS_C03 VSS_CO6
K NRESET TDI TDO NTRST TEST VSS_IO_E0 VSSD_PLL VSS_IO_E2
L TMS GP_B0 GP_B6 GP_B1 RTCK VSS_IO_E1 VDD_IO_E VSSD_USB
M GP_B2 GP_B3 GP_B10 GP_B5 GP_B4 FILTER0 VDDAD_PLL0 VDD_RTC0
N GP_B7 GP_B9 GP_B13 VSS_IO_B GP_E7 VSSA_ADC VDDAD_PLL1 VDD_RTC1
P GP_B8 GP_B11 GP_E0 GP_E2 GP_E6 VSSA_PLL0 XTIN PMWKUP
R VDD_IO_B GP_B14 GP_E1 GP_E4 ADIN0 XTOUT VDDA_ADC VSSAC_USB
T GP_B12 GP_B15 GP_E3 GP_E5 ADIN1 FILTER1 VSSA_PLL1 USB_DP
1 2 3 4 5 6 7 8
Figure 1.2 Package Diagram of TCC8200 (256-BGA-1313) – Left Half
1-16
RIGHT
9 10 11 12 13 14 15 16
XD28 XD22 XD18 XD13 XD10 XD7 XD5 XD2 A
XD27 XD21 XD16 XD12 XD8 XD3 XD1 CS_NCS2 B
XD25 XD20 XD14 XD9 XD4 XD0 CS_NCS3 CS_NCS0 C
XD26 XD19 XD15 XD11 XD6 CS_NCS1 SDR_CKE SDR_CLK D
XD24 XD23 XD17 NOE NWE SDR_NCS XA23 XA22 E
VDD_IO_X0 VSS_IO_X0 VDD_IO_X3 XA18 XA21 XA20 XA19 XA16 F
VDD_C02 VSS_IO_X3 VDD_IO_X2 XA17 XA15 XA14 XA13 XA11 G
VDD_CO3 VSS_IO_X2 VDD_IO_X1 XA12 XA10 XA7 XA9 XA8 H
VDD_CO4 VSS_IO_X1 VDD_IO_F XA6 XA4 XA2 XA3 XA5 J
VSSAT_USB VDD_CO5 VSS_IO_F GP_F12 GP_F11 GP_F14 XA0 XA1 K
VDDD_USB VDDAT_USB VDD_CO6 GP_F2 GP_F4 GP_F7 GP_F10 GP_F15 L
UTM_XO GP_C0 GP_C6 GP_F0 GP_C22 GP_F1 GP_F8 GP_F13 M
UTM_XI GP_C4 GP_C8 GP_C15 GP_C19 GP_C20 GP_F5 GP_F9 N
GP_C1 GP_C2 GP_C7 GP_C12 GP_C16 GP_C18 GP_C23 GP_F6 P
VDDAC_USB USB_REXT GP_C5 GP_C10 VSS_IO_C GP_C14 GP_C21 GP_F3 R
UTM_ATE
USB_DM GP_C3 GP_C9 GP_C11 VDD_IO_C GP_C13 GP_C17 T
ST
9 10 11 12 13 14 15 16
Figure 1.2 Package Diagram of TCC8200 (256-FBGA-1313) – Right Half
1-17
TCC82xx
Part 1. Common
Chapter 1. Address
Chapter 2. CPU core
Chapter 3. Port
Chapter 4. Boot mode
Chapter 5. JTAG
Chapter 6. Electrical Data
Chapter 7. Package
Rev. 0.20
Apr. 24 2006
TCC82xx Specification
Multimedia Application Processor PART 1. COMMON
Revision History

ii
Address & Register Map
Multimedia Application Processor ADDRESS & REGISTER MAP
1. ADDRESS & REGISTER MAP
1.1 Address Map
The TCC82xx has fixed address maps for digital audio en-decoder system. The address space is separated MSB
4bits of address bus, the following table represents overall address space of TCC82xx system.
Table 1.1 Address Allocation Map of TCC82xx

Address Space Device Name
1) if Remap is 0, External ROM of chip select 3 or internal ROM.
2) if Remap is 1, Other type memory according to base value.
0x00000000 ~ 0x0FFFFFFF
3) if any other type of memory is not assigned to this area, then
Internal SRAM is assigned.
0x10000000 ~ 0x1FFFFFFF Not Used
0x20000000 ~ 0x2FFFFFFF Assigned to SDRAM initially.
0x30000000 ~ 0x3FFFFFFF Assigned to internal SRAM
Assigned to chip select 0
0x40000000 ~ 0x4FFFFFFF
Initially the configuration register is set to SRAM
0x50000000 ~ 0x5FFFFFFF
Initially the configuration register is set to IDE type device
0x60000000 ~ 0x6FFFFFFF
Initially the configuration register is set to NAND flash
0x70000000 ~ 0x7FFFFFFF
Initially the configuration register is set to ROM
0x80000000 ~ 0x8FFFFFFF Various internal peripheral devices
0x90000000 ~ 0x9FFFFFFF Various internal peripheral devices
0xA0000000 ~ 0xAFFFFFFF Data TCM
0xB0000000 ~ 0xBFFFFFFF
0xC0000000 ~ 0xCFFFFFFF Not Used
0xD0000000 ~ 0xDFFFFFFF
0xE0000000 ~ 0xEFFFFFFF Assigned to internal boot ROM
0xF0000000 ~ 0xFFFFFFFF Assigned to memory controller configuration register space
The address space (0x00000000 ~ 0x0FFFFFFF) is initially allocated to internal or external PROM for booting
procedure, and a special flag exists in memory controller unit for remapping this space to other type of memories.
That is, if the remap flag is set to 1, this space is released from the external ROM of chip select 3 or internal boot
ROM. Refer to the description of memory controller for detailed operation.
TCC82xx has one chip select for SDRAM, and four chip selects for other type of memories. Their address space
is dependent on the configuration registers for each chip selects. The above address map is only at the initial
state of TCC82xx; these maps can be changed at user requests.
TCC82xx has various peripherals for controlling a digital audio en-decoder system. These peripherals can be
configured appropriately by it’s own registers that can be accessed through specially allocated address. These
address maps are represented in the following table. In case of memory controller, its space is separated for
preventing illegal accessing.
Refer to corresponding sections for detail information of each peripheral.
1
Table 1.2 Address Allocations for Internal Peripherals (Base = 0x80000000)

Offset Address Space Peripheral
0x0000 ~ 0x0FFF DAI
0x1000 ~ 0x1FFF Program Interrupt Controller
0x2000 ~ 0x2FFF Timer Counter
0x3000 ~ 0x3FFF GPIO
0x4000 ~ 0x4FFF Clock Generator & Power Management
0x5000 ~ 0x5FFF UART1
0x6000 ~ 0x6FFF UART0
0x7000 ~ 0x7FFF Reserved
0x8000 ~ 0x8FFF I2C
0x9000 ~ 0x9FFF ECC
0xA000 ~ 0xAFFF ADC Control
0xB000 ~ 0xBFFF RTC (Real Time Counter)
0xC000 ~ 0xCFFF Reserved
0xD000 ~ 0xDFFF USB Device & DMA
0xE000 ~ 0xEFFF General Purpose 3.Ch DMA Controller
0xF000 ~ 0xFFFF System Configuration
Table 1.3 Address Allocations for Internal Peripherals (Base = 0x90000000)

Offset Address Space Peripheral
0x0000 ~ 0x0FFF NAND Flash Controller
0x1000 ~ 0x1FFF SD (Sequre Digital) Card / MMC (MultiMedia Card) Controller
0x3000 ~ 0x3FFF SPI
0x4000 ~ 0x4FFF Camera Interface
0x5000 ~ 0x5FFF 2D Accelerator
0x6000 ~ 0x6FFF JPEG Codec (DCT/IDCT calculator)
0x8000 ~ 0x8FFF EHI (External Host Interface)
0x9000 ~ 0x9FFF IDE
0xA000 ~ 0xAFFF SAD calculator
0xB000 ~ 0xBFFF Reserved
0xC000 ~ 0xCFFF Scaler
0xD000 ~ 0xDFFF LCD controller
0xE000 ~ 0xEFFF Reserved
0xF000 ~ 0xFFFF Reserved
y Address decoding logic only monitors base address (for example, 0x8xxxxxxx, 0x9xxxxxxx, etc.), and
bit15~bit12 of accessing address bus. There can be a lot of mirror images of address space that are
repeated at every 4Kbyte boundary, user can access certain registers by these mirror images also, so care
must be taken not to modify these registers unintentionally.
2
1.2 Register Map
Table 1.4 DAI Register Map (Base Address = 0x80000000)

Name Address Type Reset Description
DADI_L0 0x00 R - Digital Audio Left Input Register 0
DADI_R0 0x04 R - Digital Audio Right Input Register 0
DADI_R1 0x0C R - Digital Audio Right Input Register 1
DADO_L0 0x20 R/W - Digital Audio Left Output Register 0
DADO_R0 0x24 R/W - Digital Audio Right Output Register 0
DADO_R1 0x2C R/W - Digital Audio Right Output Register 1
DAMR 0x40 R/W 0x00000000 Digital Audio Mode Register
DAVC 0x44 R/W 0x0000 Digital Audio Volume Control Register
Table 1.5 Interrupt Controller Register Map (Base Address = 0x80001000)

IEN 0x00 R/W 0x00000000 Interrupt Enable Register
CREQ 0x04 W - Clear Interrupt Request Register
IREQ 0x08 R 0x00000000 Interrupt Request Flag Register
IRQSEL 0x0C R/W 0x00000000 IRQ / FIQ Select Register
ICFG 0x10 R/W 0x00000000 External Interrupt Configuration Register
MREQ 0x14 R 0x00000000 Masked Interrupt Request Flag Register
TSTREQ 0x18 R/W 0x00000000 Test Mode Register (must be remained zero)
IRQ 0x20 R - IRQ Raw Status (IREQ & IRQSEL)
FIQ 0x24 R - FIQ Raw Status (~IREQ & IRQSEL)
MIRQ 0x28 R - Masked IRQ Status (IRQ & IEN)
MFIQ 0x2C R - Masked FIQ Status (FIQ & IEN)
TMODE 0x30 W 0x000007C0 Trigger Mode (0: edge, 1:level)
SYNC 0x34 W 0x00000000 Synchronizer Control
WKUP 0x38 W 0x00000000 Wakeup Control
3
Table 1.6 Timer/Counter Register Map (Base Address = 0x80002000)

TCFG0 0x00 R/W 0x00 Timer/Counter 0 Configuration Register
TCNT0 0x04 R/W 0x0000 Timer/Counter 0 Counter Register
TREF0 0x08 R/W 0xFFFF Timer/Counter 0 Reference Register
TMREF0 0x0C R/W 0x0000 Timer/Counter 0 Middle Reference Register
TREF4 0x48 R/W 0xFFFFF Timer/Counter 4 Reference Register
TIREQ 0x60 R/W 0x0000 Timer/Counter n Interrupt Request Register
TWDCFG 0x70 R/W 0x0000 Watchdog Timer Configuration Register
TWDCLR 0x74 W - Watchdog Timer Clear Register
TC32EN 0x80 R/W 0x00007FFF 32-bit Counter Enable / Pre-scale Value
TC32LDV 0x84 R/W 0x00000000 32-bit Counter Load Value
TC32CMP0 0x88 R/W 0x00000000 32-bit Counter Match Value 0
TC32CMP1 0x8C R/W 0x00000000 32-bit Counter Match Value 1
TC32PCNT 0x90 R/W - 32-bit Counter Current Value (pre-scale counter)
TC32MCNT 0x94 R/W - 32-bit Counter Current Value (main counter)
TC32IRQ 0x98 R/W 0x0000---- 32-bit Counter Interrupt Control
4
Table Table 1.7 GPIO Register Map (Base Address = 0x80003000)

Name Addr Type Reset Description
GDATA_A 0x00 R/W 0x00000000 GPIO_A Data Register
GIOCON_A 0x04 R/W 0x00000000 GPIO_A Direction Control Register
GSEL_A 0x08 R/W 0x00000000 GPIO_A Function Select Register
GDATA_B 0x10 R/W 0x00000000 GPIO_B Data Register
GIOCON_B 0x14 R/W 0x00000000 GPIO_B Direction Control Register
GSEL_B 0x18 R/W 0x000003FE GPIO_B Function Select Register
GDATA_C 0x20 R/W 0x00000000 GPIO_C Data Register
GIOCON_C 0x24 R/W 0x00000000 GPIO_C Direction Control Register
GSEL_C 0x28 R/W 0x00000000 GPIO_C Function Select Register
GDATA_E 0x40 R/W 0x00000000 GPIO_E Data Register
GIOCON_E 0x44 R/W 0x00000000 GPIO_E Direction Control Register
GSEL_E 0x48 R/W 0x00000000 GPIO_E Function Select Register
GDATA_F 0x50 R/W 0x00000000 GPIO_F Data Register
GIOCON_F 0x54 R/W 0x00000000 GPIO_F Direction Control Register
GSEL_F 0x58 R/W 0x00000000 GPIO_F Function Select Register
GDATA_G 0x60 R/W 0x00000000 GPIO_G Data Register
GIOCON_G 0x64 R/W 0x00000000 GPIO_G Direction Control Register
GSEL_G 0x68 R/W 0x00000000 GPIO_G Function Select Register
GDATA_XA 0x70 R/W 0x00000000 GPIO_XA Data Register
GIOCON_XA 0x74 R/W 0x00000000 GPIO_XA Direction Control Register
GSEL_XA 0x78 R/W 0xEFFF_FFFF GPIO_XA Function Select Register
GDATA_XD 0x80 R/W 0x00000000 GPIO_XD Data Register
GIOCON_XD 0x84 R/W 0x00000000 GPIO_XD Direction Control Register
GSEL_XD 0x88 R/W 0x00000000 GPIO_XD Function Select Register
GPIOB_PE 0xB8 R/W 0x00000000 GPIO_B pull Enable Register
GPIOB_PS 0xBC R/W 0x00000000 GPIO_B pull Select Register
GPIOC_PE 0xC0 R/W 0x00000000 GPIO_C pull Enable Register
GPIOC_PS 0xC4 R/W 0x00000000 GPIO_C pull Select Register
GPIOE_PE 0xD0 R/W 0x00000000 GPIO_E pull Enable Register
GPIOE_PS 0xD0 R/W 0x00000000 GPIO_E pull Select Register
GPIOF_PE 0xD0 R/W 0x00000000 GPIO_F pull Enable Register
GPIOF_PS 0xD0 R/W 0x00000000 GPIO_F pull Select Register
GPIOG_PE 0xE0 R/W 0x00000000 GPIO_G pull Enable Register
GPIOG_PS 0xE4 R/W 0x00000000 GPIO_G pull Select Register
XA_PE 0xE8 R/W 0x00000000 XA pull Enable Register
XA_PS 0xEC R/W 0x00000000 XA pull Select Register
XD_PE 0xF0 R/W 0x00000000 XD pull Enable Register
XD_PS 0xFC R/W 0x00000000 XD pull Select Register
5
Table 1.8 CKC Register Map (Base Address = 0x80004000)

CLKCTRL 0x00 R/W 0x80000014 CPU & Bus Clock Control Register
PLL0CFG 0x04 R/W 0x8001E50C PLL0 Configuration Register
CLKDIVC 0x0C R/W 0xE0E0E0E0 Divided Clock Configuration Register
MODECTR 0x10 R/W 0x00000000 Operating Mode Control Register
BCLKCTR 0x14 R/W 0x0FFFFFFF Bus Clock Enable Register
SWRESET 0x18 R/W 0xFFFFFFFF Software Reset Control Register
PCLKCFG0 0x1C R/W 0x40000000 SDRAM Refresh Clock Control Reigster
PCLKCFG1 0x20 R/W 0x40000000 I2C Clock Control Register
PCLKCFG2 0x24 R/W 0x40000000 SPI Clock Control Register
PCLKCFG3 0x28 R/W 0x40004000 UART1/UART0 Clock Control Register
PCLKCFG4 0x2C R/W 0x40004000 Timer T-Clock Control Register
PCLKCFG5 0x30 R/W 0x40004000 Timer X-Clock/Z-Clock Control Register
PCLKCFG6 0x34 R/W 0x40004000 DAI0/ADC Clock Control Register
PCLKCFG7 0x38 R/W 0x00080000 DAI1 Clock Control Register
PCLKCFG8 0x3C R/W 0x40004000 CIF Scaler Clock Control Register
PCLKCFG9 0x40 R/W 0x40000000 LCD Clock Control Register
Table 1.9 UART0 / UART1 Register Map

(UART0 Base Address = 0x80006000)
RBR 0x00 R Unknown Reciver Buffer Register(DLAB = 0)
THR 0x00 W 0x00 Transmitter Holding Register (DLAB=0)
DLL 0x00 R/W 0x00 Divisor Latch (LSB) (DLAB=1)
IER 0x04 R/W 0x00 Interrupt Enable Register (DLAB=0)
DLM 0x04 R/W 0x00 Divisor Latch (MSB) (DLAB=1)
IIR 0x08 R Unknown Interrupt Ident. Register (DLAB=0)
FCR 0x08 W 0xC0 FIFO Control Register (DLAB=1)
LCR 0x0C R/W 0x03 Line Control Register
MCR 0x10 R/W 0x40 MODEM Control Register
LSR 0x14 R Unknown Line Status Register
MSR 0x18 R Unknown MODEM Status Register
SCR 0x1C R/W 0x00 Scratch Register
AFT 0x20 R/W 0x00 AFC Trigger Level Register
UCR 0x24 R/W 0x00 UART Control Register
SRBR 0x40 R Unknown Rx Buffer Register
STHR 0x44 W 0x00 Transmitter Holding Register
SDLL 0x48 R/W 0x00 Divisor Latch (LSB)
SDLM 0x4C R/W 0x00 Divisor Latch (MSB)
SIER 0x50 R/W 0x00 Interrupt Enable Register
IRCFG 0x80 R/W 0x00 IRDA Configuration Register
6
Table 1.10 I2C Register Map (Base Address = 0x80008000)

PRES 0x00 R/W 0xFFFF Clock Prescale register
CTRL 0x04 R/W 0x0000 Control Register
TXR 0x08 W 0x0000 Transmit Register
CMD 0x0C W 0x0000 Command Register
RXR 0x10 R 0x0000 Receive Register
SR 0x14 R 0x0000 Status Register
Table 1.11 ECC Register Map (Base Address = 0x80009000)

ECC_CTRL 0x00 R/W 0x00000000 ECC Control Register
ECC_BASE 0x04 R/W 0x00000000 Base Address for ECC Calculation
ECC_MASK 0x08 R/W 0x00000000 Address mask for ECC area.
ECC_CLR 0x0C W - Clear ECC output register
SLC_ECC0 0x10 R 0x00000000 1st Block ECC output for SLC NAND
SLC_ECC1 0x14 R 0x00000000 2nd Block ECC output for SLC NAND
SLC_ECC2 0x18 R 0x00000000 3rd Block ECC output for SLC NAND
SLC_ECC3 0x1C R 0x00000000 4th Block ECC output for SLC NAND
SLC_ECC4 0x20 R 0x00000000 5th Block ECC output for SLC NAND
MLC_ECC0W 0x30 W - MLC NAND ECC calculation register 0
MLC_ECC0R 0x40 R 0x00000000 Calculated ECC output 0 for MLC NAND
CORR_START 0x4C W - MLC ECC4 Correction Start Register
ERRADDR0 0x50 R 0x00000000 MLC ECC4 Error Address Register0
ERRADDR3 0x5C R 0x00000000 MLC ECC4 Error Address Register3
ERRDATA0 0x60 R 0x00000000 MLC ECC4 Error Data Register0
ERRDATA3 0x6C R 0x00000000 MLC ECC4 Error Data Register3
ERR_NUM 0x70 R 0x00000004 MLC ECC4 Error Number Register
7
Table 1.12 ADC Controller Register Map (Base Address = 0x8000A000)

ADCCON 0x00 R/W 0x00000018 ADC Control Register
ADCDATA 0x04 R Unknown ADC Data Register
ADCCONA 0x80 R/W 0x00000018 ADC Control Register A
ADCSTATUS 0x84 R/W Unknown ADC Status Register
ADCCFG 0x88 R/W 0x00002400 ADC Configuration Register
Table 1.13 RTC Register Map (Base Address = 0x8000B000)

Register Address R/W Reset value Description
RTCCON 0x00 R/W 0x00 RTC Control Register
INTCON 0x04 R/W - RTC Interrupt Control Register
RTCALM 0x08 R/W - RTC Alarm Control Register
ALMSEC 0x0C R/W - Alarm Second Data Register
ALMMIN 0x10 R/W - Alarm Minute Data Register
ALMHOUR 0x14 R/W - Alarm Hour Data Register
ALMDATE 0x18 R/W - Alarm Date Data Register
ALMDAY 0x1C R/W - Alarm Day of Week Data Register
ALMMON 0x20 R/W - Alarm Month Data Register
ALMYEAR 0x24 R/W - Alarm Year Data Register
BCDSEC 0x28 R/W - BCD Second Register
BCDMIN 0x2C R/W - BCD Minute Register
BCDHOUR 0x30 R/W - BCD Hour Register
BCDDATE 0x34 R/W - BCD Date Register
BCDDAY 0x38 R/W - BCD Day of Week Register
BCDMON 0x3C R/W - BCD Month Register
BCDYEAR 0x40 R/W - BCD Year Register
RTCIM 0x44 R/W - RTC Interrupt Mode Register
RTCPEND 0x48 R/W - RTC Interrupt Pending Register
8
Table 1.14 USB Register Map (Base Address = 0x8000D000)
Non-Indexed Registers Indexed Registers
Name Abbr. Address Name Abbr. Address
Endpoints Status
Index Register IR 0x00 ESR 0x2C
Register
Endpoint Interrupt Endpoint Control
EIR 0x04 ECR 0x30
Register Register
Endpoint Interrupt Byte Read Count
EIER 0x08 BRCR 0x34
Register Register
Function Address Byte Write Count
FAR 0x0C BWCR 0x38
Register Register
Endpoint Direction Max Packet
EDR 0x14 MPR 0x3C
Register Register
System Status DMA Control

SSR 0x1C DCR 0x40
Register Register
System Control DMA Transfer

SCR 0x20 DTCR 0x44
Register Counter Register
EP0 Status
EP0SR 0x24 DMA FIFO Counter Register DFCR 0x48
Register
EP0 Control DMA Total Transfer

EP0CR 0x28 DTTCR1 0x4C
Register Counter1 Register
DMA Total Transfer

EP0 Buffer Register EP0BUF 0x60 DTTCR2 0x50
Counter2 Register
EP1 Buffer Register EP1BUF 0x64 DMA MCU Address Register 1/2 DMAR1/2 0xA0/A4
EP2 Buffer Register EP2BUF 0x68 DMA Transfer Status Register DTSR 0xC0
EP3 Buffer Register EP3BUF 0x6C
9
Table 1.15 usbDMA Controller Register Map (Base Address = 0x8000D800)

ST_SADR0 0x00 R/W 0x00000000 Start Address of Source Block
C SPARAM0 0x04 R/W 0x00000000 Parameter of Source Block
H C_SADR0 0x0C R 0x00000000 Current Address of Source Block
A ST_DADR0 0x10 R/W 0x00000000 Start Address of Destination Block
N DPARAM0 0x14 R/W 0x00000000 Parameter of Destination Block
N C_DADR0 0x1C R 0x00000000 Current Address of Destination Block
E HCOUNT0 0x20 R/W 0x00000000 Initial and Current Hop count
L CHCTRL0 0x24 R/W 0x00000000 Channel Control Register
0 RPTCTRL0 0x28 R/W 0x00000000 Repeate Control Register
CHCONFIG 0x2C R/W 0x00000000 Channel Configuration Register
Table 1.16 General DMA Controller Register Map (Base Address = 0x8000E000)
C
SPARAM0 0x04 R/W 0x00000000 Parameter of Source Block
H
C_SADR0 0x0C R 0x00000000 Current Address of Source Block
A
ST_DADR0 0x10 R/W 0x00000000 Start Address of Destination Block
N
DPARAM0 0x14 R/W 0x00000000 Parameter of Destination Block
N
E C_DADR0 0x1C R 0x00000000 Current Address of Destination Block
L HCOUNT0 0x20 R/W 0x00000000 Initial and Current Hop count
0 CHCTRL0 0x24 R/W 0x00000000 Channel Control Register
RPTCTRL0 0x28 R/W 0x00000000 Repeate Control Register
C
H
A
N
N
C
SPARAM2 0x64/0x68 R/W 0x00000000 Parameter of Source Block
H
A
N
DPARAM2 0x74/0x78 R/W 0x00000000 Parameter of Destination Block
N
10
Table 1.17 I2C Register Map (Base Address = 0x8000F000)

BMI 0x00 R 0x---- Boot Mode Indication Register
Table 1.18 Nand Flash Controller Register Map (Base Address = 0x90000000)
NFC_CMD 0x00 W - Nand Flash Command Register
NFC_LADDR 0x04 W - Nand Flash Linear Address Register
NFC_BADDR 0x08 W - Nand Flash Block Address Register
NFC_SADDR 0x0C W - Nand Flash Signal Address Register
NFC_WDATA 0x1x R/W 0x00000000 Nand Flash Word Data Register
NFC_LDATA 0x2x/3x R/W UnKnown Nand Flash Linear Data Register
NFC_SDATA 0x40 R/W 0x00000000 Nand Flash Single Data Register
NFC_CTRL 0x50 R/W 0x00f00111 Nand Flash Control Register
NFC_PSTART 0x54 W - Nand Flash Program Start Register
NFC_RSTART 0x58 W - Nand Flash Read Start Register
NFC_DSIZE 0x5C R/W 0x0000ffff Nand Flash Data Size Register
NFC_IREQ 0x60 R/W 0x00000000 Nand Flash Interrupt Request Register
NFC_RST 0x64 W - Nand Flash Controller Reset Register
Table 1.19 SD/MMC Controller Register Map (Base Address = 0x90001000)

SDICLK 0x04 R/W 0x3000 Clock control register
SDIARGU 0x08 R/W 0x0 Command argument register
SDICMD 0x0C R/W 0x20000 Command index and type register
SDIRSPCMD 0x10 R Response index register
SDIRSPARGU0 0x14 R Response argument register
SDIRSPARGU2 0x1C R Response argument register
SDIDTIMER 0x24 R/W 0x40FFFF Wait cycles for data transfer
SDIDCTRL2 0x28 R/W 0x0 Data path control register
SDIDCTRL 0x2C R/W 0xFF1490 Data path control register
SDISTATUS 0x30 R Status register
SDIIFLAG 0x34 R/W 0x0 Interrupt flag register
SDIWDATA 0x38 R/W 0x0 Transmit data register
SDIRDATA 0x3C R Receive data register
SDIIENABLE 0x40 R/W 0x0 Interrupt enable register
11
Table 1.20 GSIO/SPIS Register Map (Base Address = 0x90003000)

SDO 0x00 R/W 0x0000 SPI Output Data Register
SDI 0x04 R 0x0000 SPI Input Data Register
SBCR 0x08 R/W 0x0000 SPI Base Clock Register
SCR 0x0C R/W 0x0000 SPI Control Register
SPCTRL 0x10 R/W 0x0000 SPI Interrupt Control Register
SPSTS 0x14 R 0x0000 SPI Interrupt Status Register
Table 1.21 CIF Register Map (Base Address = 0x90004000)

ICPCR1 0x00 W/R 0x00000000 Input Image Color/Pattern Configuration Register 1
656FCR1 0x04 W/R 0x06ff0000 CCIR656 Format Configuration Register 1
656FCR2 0x08 W/R 0x010b CCIR656 Format Configuration Register 2
IIS 0x0C W/R 0x00000000 Input Image Size
IIW1 0x10 W/R 0x00000000 Input Image Windowing 1
CDCR1 0x18 W/R 0x0003 DMA Configuration Register 1
CDCR2 0x1C W/R 0x00000000 DMA Configuration Register 2
FIFOSTATE 0x34 R 0x00000000 FIFO Status Register
CIRQ 0x38 W/R 0x00000000 Interrupt & Status register
OCTRL1 0x3C W/R 0x37000000 Overlay Control 1
OCTRL2 0x40 W/R 0x00000000 Overlay Control 2
OIS 0x4C W/R 0x00000000 Overlay Image Size
OIW1 0x50 W/R 0x00000000 Overlay Image Windowing 1
COBA 0x58 W/R 0x00000000 Overlay Base Address
CDS 0x5C W/R 0x00000000 Camera Down Scaler
CCM1 0x60 W/R 0x00000000 Capture Mode Configuration 1
CESA 0x64 W/R 0x00000000 Point Encoding Start Address
CR2Y 0x6C W/R 0x00000000 RGB2YUV Format converter Configuration
CCYA 0x70 R - Current Y Address
CCYU 0x74 R - Current U Address
CCYV 0x78 R - Current V Address
CCLC 0x7C R Current Line count
12
Table 1-22 2D DMA Register Map (Base Address = 0x90005000)

SRCA_F 0x00 R/W 0x00000000 Front Source Address Register
SRCOFF_F 0x04 R/W 0x00000000 Front Source Offset Register
DSTA_F 0x08 R/W 0x00000000 Front Destination Address Register
DSTOFF_F 0x0C R/W 0x00000000 Front Destination Offset Register
NUMT_F 0x10 R/W 0x00000000 Front Transfer Count Number Register
SRCA_B 0x14 R/W 0x00000000 Back Source Address Register
SRCOFF_B 0x18 R/W 0x00000000 Back Source Offset Register
DSTA_B 0x1C R/W 0x00000000 Back Destination Address Register
DSTOFF_B 0x20 R/W 0x00000000 Back Destination Offset Register
NUMT_B 0x24 R/W 0x00000000 Back Transfer Count Number Register
SRC1A_R 0x28 R/W 0x00000000 ROP Source 1 Address Register
SRC1OFF_R 0x2C R/W 0x00000000 ROP Source 1 Offset Register
SRC2A_R 0x30 R/W 0x00000000 ROP Source 2 (Y) Address Register
SRC2OFF_R 0x34 R/W 0x00000000 ROP Source 2 Offset Register
SRC2CBA_R 0x38 R/W 0x00000000 ROP Source 2 Cb Address Register
SRC2CRA_R 0x3C R/W 0x00000000 ROP Source 2 Cr Address Register
DSTA_R 0x40 R/W 0x00000000 ROP Destination (Y) Address Register
DSTOFF_R 0x44 R/W 0x00000000 ROP Destination Offset Register
DSTCBA_R 0x48 R/W 0x00000000 ROP Destination Cb Address Register
DSTCRA_R 0x4C R/W 0x00000000 ROP Destination Cr Address Register
IMGSIZE 0x50 R/W 0x00000000 Image Size Register
MEMADDR 0x54 R/W 0x00000000 Buffer Memory Address Register
LOCAL 0x58 R/W 0x00000000 Local Region Configuration Register
FPVALUE 0x5C R/W 0x00000000 Fill / Pattern Value Register
IMGFM_R 0x60 R/W 0x00000000 ROP Image Format Register
CHROMA_R 0x64 R/W 0x00000000 ROP Chroma Value Register
CONTROL 0x70 R/W 0x00000000 Control Register
INT 0x74 R/W 0x00000000 Interrupt Register
INTEN 0x78 R/W 0x00000000 Interrupt Enable Register
13
Table 1-23 JPEG & DCT/IDCT Registers (Base Address = 0x90006000)

Name Addr Type Mode Reset Description
JP_RST 0x000 W ALL 0x00000000 JPEG block soft reset register
JP_MOD 0x004 R/W ALL 0x00000000 JPEG codec mode register
JP_INT_MASK 0x008 R/W ALL 0x0000001f Interrupt mask register
JP_INT_LEVEL 0x00c R/W SLV 0x000000ff FIFO interrupt level register
JP_TRG_MOD 0x010 R/W ALL 0x00000000 Polling or Interrupt mode selection register
R_YBUF_ADDR 0x020 R/W JP 0x00000000 Raw data buffer Y address register
R_UBUF_ADDR 0x024 R/W JP 0x00000000 Raw data buffer U address register
R_VBUF_ADDR 0x028 R/W JP 0x00000000 Raw data V address register
R_BUF_INFO 0x02c R/W JP 0x00000000 Raw data buffer information register
JP_SIZE 0x030 R/W JP 0x00000000 Image size information register
JP_CHROMA 0x034 R/W JP 0x00000000 Image format information register
JP_CBUF_ADDR 0x38 R/W JP 0x00000000 Coded data buffer address register
JP_CBUF_SIZE 0x03c R/W JP 0x00000fff Coded data buffer size register
JPD_TBL_ID 0x050 R/W JPD 0x00000000 Decoder table index register
JPD_RST_INTV 0x054 R/W JPD 0x00000000 Decoder reset interval register
JPD_OUT_SCL 0x058 R/W JPD 0x00000000 Decoder output scaling register
JP_SBUF_RP_A 0x060 R/W JPC 0x00000000 Source read pointer address register
JP_DBUF_WP_A 0x064 R/W JPD 0x00000000 Desination write pointer address register
JP_START 0x070 W ALL 0x00000000 Codec start command register
JP_SBUF_WCNT 0x080 R/W MST 0x00000000 Source buffer write count register
JP_SBUF_RCNT 0x084 R MST 0x00000000 Source buffer read count register
JP_DBUF_WCNT 0x088 R MST 0x00000000 Destination buffer write count register
JP_DBUF_RCNT 0x08c R/W MST 0x00000000 Destination buffer read count register
JP_IFIFO_ST 0x090 R SLV 0x00000000 Input FIFO status register
JP_OFIFO_ST 0x094 R SLV 0x00000000 Output FIFO status register
JP_INT_FLAG 0x0a0 R ALL 0x00000000 Interrupt flag register
JP_INT_ACK 0x0a4 R ALL 0x00000000 Interrupt ack register
JP_IFIFO_WD 0x0c0 W SLV 0x00000000 Input FIFO write data register
JP_OFIFO_RD 0x0e0 R SLV 0x00000000 Output FIFO read data register
Table 1.24 EHIF register map (Base Address = 0x90008000)

Name Offset Int. Ext. Reset Description
EHST 0x00 R/W R/W 0x00000000 Status register
EHIINT 0x04 R/W R/W 0x00000000 Internal interrupt control register
EHEINT 0x08 R/W R/W 0x00000000 External interrupt control register
EHA 0x0C R R/W 0x00000000 Address register
EHAM 0x10 R/W R 0x00000000 Address masking register
EHD 0x14 R/W R/W 0x00000000 Data register
EHSEM 0x18 R/W R/W 0x00000000 Semaphore register
EHCFG 0x1C R/W R/W 0x00000000 Configuration registers
EHIND 0x20 R W 0x00000000 Index register
EHRWCS 0x24 R R/W 0x00000000 Read/Write Control/Status register
14
Table 1.25 IDE Controller Register Map (Base Address = 0x90009000)

CS0n 0x00~ 0x1F R/W - PIO CS0n Access Register
CS1n 0x20 ~0x3F R/W - PIO CS1n Access Register
PIOCTRL 0x00 R/W 0x00600000 PIO Mode Control Register
.
Table 1.26 SAD DMAC register map
Name Offset TYPE Reset Description
REFADR 0x00 R/W 0x00000000 Start address of the reference 20x20 image.
CURADR 0x04 R/W 0x00000000 Start address of the current macroblock.
OFFSET 0x08 R/W 0x00000000 Stride line register in word size.
STATUS 0x0C R/C 0x00000000 Status register
CONTROL 0x10 R/W 0x00000000 DMA control register
SAD result value (DF = 0)
SADOUT 0x14 R 0x00000000 DEV result value (DF = 1)
MEAN result value (MF = 1)
Block0, 1 SAD8 result value (DF = 0)
SAD8_B01OUT 0x18 R 0x00000000
Block0, 1 DEV8 result value (DF = 1)
SAD8_B23OUT 0x1C R 0x00000000
SADSTATUS 0x20 R/C 0x00000000 Status register
Table 1-27 Scaler Registers (Base Address = 0x9000C000)

SRC_Y_BASE 0x000 R/W 0x00000000 Scaler source image Y base address register
SRC_U_BASE 0x004 R/W 0x00000000 Scaler source image U base address register
SRC_V_BASE 0x008 R/W 0x00000000 Scaler source image V base address register
SRC_SIZE 0x00c R/W 0x00000000 Source image size register
SRC_OFFSET 0x010 R/W 0x00000000 Source image line offset register
SRC_CONFIG 0x014 R/W 0x00000000 Source image configuration register
DST_Y_BASE 0x020 R/W 0x00000000 Scaler destination image Y base address register
DST_U_BASE 0x024 R/W 0x00000000 Scaler destination image U base address register
DST_V_BASE 0x028 R/W 0x00000000 Scaler destination image V base address register
DST_SIZE 0x02c R/W 0x00000000 Destination image size register
DST_OFFSET 0x030 R/W 0x00000000 Destination image line offset register
DST_CONFIG 0x034 R/W 0x00000000 Destination image configuration register
SCALE_RATIO 0x040 R/W 0x00000000 Scale ratio register
SCALE_CTRL 0x044 R/W 0x00000000 Scaler control register
STATUS 0x048 R 0x00000000 Scaler status register
15
Table 1-28 LCDC Register Map (Base Address = 0x9000D000)

LCTRL 0x00 W 0x00000000 LCD Control Register
LBC 0x04 W 0x00000000 LCD Background Color Register
LCLKDIV 0x08 W 0x00000000 LCD Clock Divider Register
LHTIME1 0x0C W 0x00000000 LCD Horizontal Timing Register 1
LHTIME2 0x10 W 0x00000000 LCD Horizontal Timing Register 2
LVTIME1 0x14 W 0x00000000 LCD Vertical Timing Register 1
LVTIME3 0x1C W 0x00000000 LCD Vertical Timing Register 3
LLUTR 0x24 W 0x00000000 LCD Lookup Register for Red
LLUTG 0x28 W 0x00000000 LCD Lookup Register for Green
LLUTB 0x2C W 0x00000000 LCD Lookup Register for Blue
LDP7L 0x30 W 0x4d2b3401 LCD Modulo 7 Dithering Pattern (low)
LDP7H 0x34 W 0x0000003f LCD Modulo 7 Dithering Pattern (high)
LDP5 0x38 W 0x1d0b0610 LCD Modulo 5 Dithering Pattern Register
LDP4 0x3C W 0x00000768 LCD Modulo 4 Dithering Pattern Register
LDP3 0x40 W 0x00000034 LCD 3-bit Dithering Pattern Register
LCP1 0x44 W 0x000000ff LCD Clipping Register1
LK1 0x4C W 0x00000000 LCD Keying Register 1
LK2 0x50 W 0x00000000 LCD Keying Register 2
LKM1 0x54 W 0x00000000 LCD Keying Mask Register 1
LDS 0x5C W 0x00000000 LCD Display Size Register
LSTATUS 0x60 R/clr 0x00000000 LCD Status Register
LIM 0x64 W 0x0000001f LCD Interrupt Register.
LI0C 0x68 W 0x00000000 LCD Image 0 Control Register
LI0P 0x6C W 0x00000000 LCD Image 0 Position Register
LI0S 0x70 W 0x00000000 LCD Image 0 Size Register
LI0BA0 0x74 W 0x00000000 LCD Image 0 Base Address 0 Register.
LI0CA 0x78 W 0x00000000 LCD Image 0 Current Address Register.
LI0BA1 0x7C W 0x00000000 LCD Image 0 Base Address 1 Register
LI0BA2 0x80 W 0x00000000 LCD Image 0 Base Address 2 Register
LI0O 0x84 W 0x00000000 LCD Image 0 Offset Register
LI0SR 0x88 W 0x00000000 LCD Image 0 scale ratio
LI1C 0x8C W 0x00000000 LCD Image 1 Control Register
LI1P 0x90 W 0x00000000 LCD Image 1 Position Register
LI1CA 0x9C W 0x00000000 LCD Image 1 Current Address Register.
N/A 0xA0 - 0x00000000 -
N/A 0xA4 - 0x00000000 -
LI1O 0xA8 W 0x00000000 LCD Image 1 Offset Register
LI1SR 0xAC W 0x00000000 LCD Image 1 Scale ratio-
16
LI2C 0xB0 W 0x00000000 LCD Image 2 Control Register

LI2P 0xB4 W 0x00000000 LCD Image 2 Position Register
LI2S 0xB8 W 0x00000000 LCD Image 2 Size Register
LI2BA0 0xBC W 0x00000000 LCD Image 2 Base Address 0 Register.
LI2CA 0xC0 W 0x00000000 LCD Image 2 Current Address Register.
N/A 0xC4 - 0x00000000 -
N/A 0xC8 - 0x00000000 -
LI2O 0xCC W 0x00000000 LCD Image 2 Offset Register
LI2SR 0xD0 W 0x00000000 LCD Image 2 Scale ratio
DLCTRL 0xD4 W 0x00000000 Dual LCD Control Register
N/A 0xD8 - 0x00000000 -
DLCSA0 0xDC W 0x00000000 Dual LCD Configuration Start Address 0
DLCSA1 0xE0 W 0x00000000 Dual LCD Configuration Start Address 1
Y2RP0 0xE4 W 0x00000029 YCbCr to RGB conversion parameter 0
Y2RP1 0xE8 W 0x98D00464 YCbCr to RGB conversion parameter 1
LCDLUT 0xC00 W - LCD Lookup Table.
Table 1-29 LCDSI Register map(0x9000D000)

LCDSI CTRL0 0x400 R/W 0x00000000 Control register for LCDSI
LCDSI CTRL1 0x800 R/W 0xA0229011 Control register for nCS0 when RS=0
(for core access path using BUS clock)
LCDSI CTRL4 0x80C R/W 0xA0229011 Control register for nCS1 when RS=1
1
LCDSI CS0RS0 0x810 R/W - If this register is read or written, reading or writing
operations are generated on nCS0 while RS = 0.
(for lcd access path using LCD clock)
17
CPU
Multimedia Application Processor CPU
2 CPU
2.1 Overview
The TCC82xx has adopted the ARM946E-S (r1p1) core for controlling system and
processing various kinds of digital signals. The ARM946E-S is a Harvard architecture
cached processor with separate 16Kbyte data and 16Kbytes instruction caches, each with
8-word of line length.
A protection unit allows eight regions of memory to be defined, each with individual
cache and write buffer configurations and access permissions. The cache system is
software configurable to provide highest average of performance or to meet the needs of
real-time systems.
The followings are key features of the TCC82xx CPU core.
y CPU ARM946E-S
y Cache 16KB for Data / 16KB for Instruction
y TCM 4KB dual port data TCM
Functional Description
TBD (Please refer to ARM946 documentation)
1
General Purpose I/O Port
Multimedia Application Processor GPIO PORT
3 GPIO PORT
3.1 Overview
The TCC82xx has a lot of general purpose I/Os that can be programmed by setting
internal registers. All I/Os are set to input mode at reset. The block diagram of GPIO is
in the following figure.
G IO C O N 0
MUX
C o n tr o l o f o th e r b lo c k 1
C o n tro l o f te s t o r
2
o th e r b lo c k
A
P O u tp u t o f te s t o r
2
B o th e r b lo c k
G P IO p in
O u tp u t o f o th e r
MUX
1
b lo c k
B
U 0
W rite GDATA
S
1 G SEL, G TSEL
Read G D ATA
MUX
Figure 3.1 GPIO Block Diagram
The I/O mode can be set by the state of GIOCON register.

If a bit of GIOCON register is 1, the corresponding GPIO pin has come to output mode,
and if 0, which is the default state of GIOCON register, the corresponding GPIO pin is set
to input mode.
If GPIO pin is set to input mode, GPIO pin’s state can be fed to CPU by reading GDATA
register and when output mode, GPIO pin’s state can be controlled by the state of the
corresponding bit of GDATA register.
If GDATA register is read when the mode is output mode, the value that CPU gets is the
one that CPU has written before.
In TCC82xx, there are various kinds of peripherals that generate its own control signals.
These peripherals can occupy the dedicated GPIO pins. This option is controlled by the
state of the GSEL register.
If a bit of these GSEL is 1, the corresponding GPIO pin is entered to other function mode,
so used by other peripherals not by GPIO block. The direction control method of GPIO
pins in the other function mode is determined case by case. One of them follows the
normal direction control method using GIOCON register, the other method uses a its own
direction control signals.
3-1
3.2 Register Description

Table 3.1 GPIO Register Map (Base Address = 0x80003000)
GDATA_A 0x00 R/W 0x00000000 GPIO_A Data Register
GIOCON_A 0x04 R/W 0x00000000 GPIO_A Direction Control Register
GSEL_A 0x08 R/W 0x00000000 GPIO_A Function Select Register
GDATA_B 0x10 R/W 0x00000000 GPIO_B Data Register
GIOCON_B 0x14 R/W 0x00000000 GPIO_B Direction Control Register
GSEL_B 0x18 R/W 0x000003FE GPIO_B Function Select Register
GDATA_C 0x20 R/W 0x00000000 GPIO_C Data Register
GIOCON_C 0x24 R/W 0x00000000 GPIO_C Direction Control Register
GSEL_C 0x28 R/W 0x00000000 GPIO_C Function Select Register
GDATA_E 0x40 R/W 0x00000000 GPIO_E Data Register
GIOCON_E 0x44 R/W 0x00000000 GPIO_E Direction Control Register
GSEL_E 0x48 R/W 0x00000000 GPIO_E Function Select Register
GDATA_F 0x50 R/W 0x00000000 GPIO_F Data Register
GIOCON_F 0x54 R/W 0x00000000 GPIO_F Direction Control Register
GSEL_F 0x58 R/W 0x00000000 GPIO_F Function Select Register
GDATA_XA 0x70 R/W 0x00000000 GPIO_XA Data Register
GIOCON_XA 0x74 R/W 0x00000000 GPIO_XA Direction Control Register
GSEL_XA 0x78 R/W 0xEFFF_FFFF GPIO_XA Function Select Register
GDATA_XD 0x80 R/W 0x00000000 GPIO_XD Data Register
GIOCON_XD 0x84 R/W 0x00000000 GPIO_XD Direction Control Register
GSEL_XD 0x88 R/W 0x00000000 GPIO_XD Function Select Register
GPIOB_PE 0xB8 R/W 0x00000000 GPIO_B pull Enable Register
GPIOB_PS 0xBC R/W 0x00000000 GPIO_B pull Select Register
GPIOC_PE 0xC0 R/W 0x00000000 GPIO_C pull Enable Register
GPIOC_PS 0xC4 R/W 0x00000000 GPIO_C pull Select Register
GPIOE_PE 0xD0 R/W 0x00000000 GPIO_E pull Enable Register
GPIOE_PS 0xD0 R/W 0x00000000 GPIO_E pull Select Register
GPIOF_PE 0xD0 R/W 0x00000000 GPIO_F pull Enable Register
GPIOF_PS 0xD0 R/W 0x00000000 GPIO_F pull Select Register
GPIOG_PE 0xE0 R/W 0x00000000 GPIO_G pull Enable Register
GPIOG_PS 0xE4 R/W 0x00000000 GPIO_G pull Select Register
XA_PE 0xE8 R/W 0x00000000 XA pull Enable Register
XA_PS 0xEC R/W 0x00000000 XA pull Select Register
XD_PE 0xF0 R/W 0x00000000 XD pull Enable Register
XD_PS 0xFC R/W 0x00000000 XD pull Select Register
* GPIO_A does not have pull-up nor pull-down
3-2
GPIO_A Data Register (GDATA_A) 0x80003000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved Data for GPIO_A[27:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data for GPIO_A[15:0] pin
If a certain GPIO_A pin is set to output mode and act as GPIO, the corresponding bit of
this register controls the status of GPIO_A pin; Low or High. If it is set to input mode and
act as GPIO, the corresponding bit represents the status of GPIO_A pin; Low or High.
GPIO_A Direction Control Register (GIOCON_A) 0x80003004
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved Direction control for GPIO_A[27:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Direction control for GPIO_A[15:0] pin
If a bit is set to 1, the corresponding GPIO_A pin is set to output mode. If set to 0, the
corresponding GPIO_A pin is set to input mode.
GPIO_A Function Select Register (GSEL_A) 0x80003008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved HDD NFC8 NFC16 EHI8 EHI16
If a bit is set to 1, the corresponding GPIO_A pin is used by the other dedicated
peripherals. The dedicated peripherals for these GPIO_A pins are External Host Interface,
Hard Disk Drive controller and Nand Flash Memory Controller.
HDD [4] 16bit HDD Function Select

GPIO_A[25] : IO READY signal of HDD Controller
GPIO_A[24:22] : DA[2:0] signal of HDD Controller
GPIO_A[21] : nDIOR signal of HDD Controller
1 GPIO_A[20] : nDIOW signal of HDD Controller
GPIO_A[19] : CSN1 signal of HDD Controller
GPIO_A[18] : CSN0 signal of HDD Controller
GPIO_A[15:0] : Data bus[15:0] signal of HDD Controller
NFC8 [3] 8bit NFC Function Select
3-3
GPIO_A[25] : READY1 signal of NAND Flash Controller

GPIO_A[23] : ALE signal of NAND Flash Controller
GPIO_A[22] : CLE signal of NAND Flash Controller
1 GPIO_A[21] : OEN signal of NAND Flash Controller
GPIO_A[20] : WEN signal of NAND Flash Controller
GPIO_A[19] : CSN1 signal of NAND Flash Controller
GPIO_A[7:0] : Data bus[7:0] signal of NAND Flash Controller

GPIO_A[23] : ALE signal of NAND Flash Controller
GPIO_A[22] : CLE signal of NAND Flash Controller
1 GPIO_A[21] : OEN signal of NAND Flash Controller
GPIO_A[20] : WEN signal of NAND Flash Controller
GPIO_A[15:0] : Data bus[15:0] signal of NAND Flash Controller
EHI8 [1] 8bit EHI Function Select

GPIO_A[22] : EHI_OEN signal of EHI
GPIO_A[21] : EHI_WEN signal of EHI
GPIO_A[20] : EHI_CSN signal of EHI
1
GPIO_A[19] : EHI_XA signal of EHI
GPIO_A[18] : EHI_INT signal of EHI
GPIO_A[7:0] : HPXD[7:0] signal of EHI
EHI16 [0] 16bit EHI Function Select

GPIO_A[22] : EHI_OEN signal of EHI
GPIO_A[21] : EHI_WEN signal of EHI
GPIO_A[20] : EHI_CSN signal of EHI
1
GPIO_A[19] : EHI_XA signal of EHI
GPIO_A[18] : EHI_INT signal of EHI
GPIO_A[15:0] : EHI_XD[15:0] signal of EHI
3-4
GPIO_B Data Register (GDATA_B) 0x80003010

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data for GPIO_B[15:0] pin
If a certain GPIO_B pin is set to output mode and act as GPIO, the corresponding bit of
this register controls the status of GPIO_B pin; Low or High. If it is set to input mode and
act as GPIO, the corresponding bit represents the status of GPIO_B pin; Low or High.
GPIO_B Direction Control Register (GIOCON_B) 0x80003014

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Direction control for GPIO_B[15:0] pin
If a bit is set to 1, the corresponding GPIO_B pin is set to output mode. If set to 0,
GPIO_B pin is set to input mode.
GPIO_B Function Select Register (GSEL_B) 0x80003018

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved NDWEN IDECSN
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
N3-SPI N0-SPI N3-UT1 N1-UT1 N2-UT0 N0-UT0 N2-EI3 N2-EI2 N2-EI1 N2-EI0 N1-EI3 N1-EI2 N1-EI1 N1-EI0 reserved reserved
If a bit is set to 1, the corresponding GPIO_B pin is used by the other dedicated
peripherals. The dedicated peripherals for these GPIO_B pins are External Interrupt
Interface, UART0, UART1 and SPI(GSIO).
ND WEN [17] ND WEN Function Select

GPIO_B[7] : NAND Flash Write Enable signal which is controlled by
1
External Memory Controller.
IDE CSN [16] IDE CSN Function Select

GPIO_B[6] : IDE Chips Select signal which is controlled by External
1
Memory Controller.
N3-SPI [15] Nibble3 SPI Function Select

GPIO_B[15] : SDO signal of SPI block
GPIO_B[14] : FRM signal of SPI block
1
GPIO_B[13] : SCK signal of SPI block
GPIO_B[12] : SDI signal of SPI block
3-5
GPIO_B[3] : SDO signal of SPI block

GPIO_B[2] : FRM signal of SPI block
1
GPIO_B[1] : SCK signal of SPI block
GPIO_B[0] : SDI signal of SPI block
N3-UT1 [13] Nibble2 UART1 Function Select

GPIO_B[15] : RTS signal of UART1 block
GPIO_B[14] : CTS signal of UART1 block
1
GPIO_B[13] : TXD signal of UART1 block
GPIO_B[12] : RXD signal of UART1 block

1

1

1
N2-EI3 [9] Nibble2 EINT3 Function Select

1 GPIO_B[11] : EINT3 signal of External Interrupt Interface





3-6


3-7
GPIO_C Data Register (GDATA_C) 0x80003020

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 Data for GPIO_C[23:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data for GPIO_C[15:0] pin
If a certain GPIO_C pin is set to output mode and act as GPIO, the corresponding bit of
this register controls the status of GPIO_C pin; Low or High. If it is set to input mode and
act as GPIO, the corresponding bit represents the status of GPIO_C pin; Low or High.
GPIO_C Direction Control Register (GIOCON_C) 0x80003024

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 Direction control for GPIO_C[23:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Direction control for GPIO_C[15:0] pin
If a bit is set to 1, the corresponding GPIO pin is set to output mode. If set to 0, GPIO_C
pin is set to input mode.
GPIO_C Function Select Register (GSEL_C) 0x80003028

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved SD1 SD4 SD8 reserved HDD NFC8 NFC16 reserved reserved
If a bit is set to 1, the corresponding GPIO_C pin is used by the other dedicated
peripherals. The dedicated peripherals for these GPIO_C pins are Nand Flash Memory
Controller, Hard Disk Drive controller and Nand Flash Memory Controller and SD/MMC.
SD1 [8] 1bit SD/MMC Function Select

GPIO_C[5] : SD CMD signal of SD/MMC
1 GPIO_C[4] : SD CLK signal of SD/MMC
GPIO_C[0] : SD DATA[0] signal of SD/MMC

1 GPIO_C[4] : SD CLK signal of SD/MMC
GPIO_C[3:0] : SD DATA[3:0] signal of SD/MMC

1
GPIO_C[4] : SD CLK signal of SD/MMC
HDD [4] 16bit HDD Function Select
3-8
GPIO_C[23] : IO READY signal of HDD Controller

GPIO_C[22:20] : DA[2:0] signal of HDD Controller
GPIO_C[19] : nDIOR signal of HDD Controller
1 GPIO_C[18] : nDIOW signal of HDD Controller
GPIO_C[17] : CSN1 signal of HDD Controller
GPIO_C[16] : CSN0 signal of HDD Controller
GPIO_C[15:0] : Data bus[15:0] signal of HDD Controller

GPIO_C[23] : READY1 signal of NAND Flash Controller
GPIO_C[21] : ALE signal of NAND Flash Controller
GPIO_C[20] : CLE signal of NAND Flash Controller
1 GPIO_C[19] : OEN signal of NAND Flash Controller
GPIO_C[18] : WEN signal of NAND Flash Controller
GPIO_C[17] : CSN1 signal of NAND Flash Controller
GPIO_C[7:0] : Data bus[7:0] signal of NAND Flash Controller

GPIO_C[21] : ALE signal of NAND Flash Controller
GPIO_C[20] : CLE signal of NAND Flash Controller
1 GPIO_C[19] : OEN signal of NAND Flash Controller
GPIO_C[18] : WEN signal of NAND Flash Controller
GPIO_C[15:0] : Data bus[15:0] signal of NAND Flash Controller
3-9
GPIO_E Data Register (GDATA_E) 0x80003040

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Data for GPIO_E[7:0] pins
GPIO_E Direction Control Register (GIOCON_E) 0x80003044

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Direction control for GPIO_E[7:0] pin
If a bit is set to 1, the corresponding GPIO_E pin is set to output mode. If set to 0, GPIO_E pin is set to input
mode.
GPIO_E Function Select Register (GSEL_E) 0x80003048

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved I2C DAI
If a bit is set to 1, the corresponding GPIO_E pin is used by the other dedicated
peripherals. The dedicated peripherals for these GPIO_E pins are I2C and DAI controller.
I2C [1] I2C Function Select

GPIO_E[6] : SCL signal of I2C block
1
GPIO_E[5] : SDA signal of I2C block
DAI [0] DAI Function Select

GPIO_E[4] pin is working as DAO signal of DAI block
GPIO_E[3] pin is working as DAI signal of DAI block
1 GPIO_E[2] pin is working as MCLK signal of DAI block
GPIO_E[1] pin is working as LRCK signal of DAI block
GPIO_E[0] pin is working as BCLK signal of DAI block
3-10
GPIO_F Data Register (GDATA_F) 0x80003050

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data for GPIO_F[15:0] pin
If a certain GPIO_F pin is set to output mode and act as GPIO, the corresponding bit of
this register controls the status of GPIO_F pin; Low or High. If it is set to input mode and
act as GPIO, the corresponding bit represents the status of GPIO_F pin; Low or High.
GPIO_F Direction Control Register (GIOCON_F) 0x80003054

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Direction control for GPIO_F[15:0] pin
If a bit is set to 1, the corresponding GPIO_F pin is set to output mode. If set to 0,
GPIO_F pin is set to input mode.
GPIO_F Function Select Register (GSEL_F) 0x80003058

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved NDWEN IDECSN
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
N3-SPI N0-SPI N3-UT1 N1-UT1 N2-UT0 N0-UT0 N2-EI3 N2-EI2 N2-EI1 N2-EI0 N1-EI3 N1-EI2 N1-EI1 N1-EI0 I2C CIF
If a bit is set to 1, the corresponding GPIO_F pin is used by the other dedicated
peripherals. The dedicated peripherals for these GPIO_F pins are External Interrupt
Interface, UART0, UART1 and SPI(GSIO), I2C and Camera Interface Controller.
ND WEN [17] ND WEN Function Select

GPIO_F[7] : NAND Flash Write Enable signal which is controlled by
1
External Memory Controller.
IDE CSN [16] IDE CSN Function Select

GPIO_F[6] : IDE Chips Select signal which is controlled by External
1
Memory Controller.

GPIO_F[15] : SDO signal of SPI block
GPIO_F[14] : FRM signal of SPI block
1
GPIO_F[13] : SCK signal of SPI block
GPIO_F[12] : SDI signal of SPI block
3-11
GPIO_F[3] : SDO signal of SPI block

GPIO_F[2] : FRM signal of SPI block
1
GPIO_F[1] : SCK signal of SPI block
GPIO_F[0] : SDI signal of SPI block

GPIO_F[15] : RTS signal of UART1 block
GPIO_F[14] : CTS signal of UART1 block
1
GPIO_F[13] : TXD signal of UART1 block
GPIO_F[12] : RXD signal of UART1 block

1

1

1

1 GPIO_F[11] : EINT3 signal of External Interrupt Interface





3-12


I2C [1] I2C Function Select

GPIO_F[15] : SCL signal of I2C block
1
GPIO_F[14] : SDA signal of I2C block
CIF [0] Camera Interface Function Select

GPIO_F[12] : Power Down signal for Camera Module
GPIO_F[11] : Horizonal Synch signal for Camera Module
GPIO_F[10] : Vertical Synch signal for Camera Module
1
GPIO_F[9] : clock input signal for Carmera Module
GPIO_F[8] : clock output signal for Camera Module
GPIO_F[7:0] : Data bus for Camera Module Interface
3-13
GPIO_G Data Register (GDATA_G) 0x80003060

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 Data for GPIO_G[23:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data for GPIO_G[15:0] pin
If a certain GPIO_G pin is set to output mode and act as GPIO, the corresponding bit of
this register controls the status of GPIO_G pin; Low or High. If it is set to input mode and
act as GPIO, the corresponding bit represents the status of GPIO_G pin; Low or High.
GPIO_G Direction Control Register (GIOCON_G) 0x80003064

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 Direction control for GPIO_G[23:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Direction control for GPIO_G[15:0] pin
If a bit is set to 1, the corresponding GPIO pin is set to output mode. If set to 0, GPIO_G
pin is set to input mode.
GPIO_G Function Select Register (GSEL_G) 0x80003068

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved LCI8 LCI16 LCI18 LMI8 LMI16 LMI18
If a bit is set to 1, the corresponding GPIO_G pin is used by the other dedicated
peripherals. The dedicated peripherals for these GPIO_G pins are LCD Controller.
LCI8 [5] 8bit LCD CCIR Interface Function Select

GPIO_G[21] : Pixel Clock signal signal for LCD controller
GPIO_G[20] : Pixel Data Valid singnal for LCD controller
1 GPIO_G[19] : Horizontal Synch signal1 for LCD Controller
GPIO_G[18] : Vertical Synch signal for LCD Controleer
GPIO_G[7:0] : Data Bus For LCD Controller

3-14

LMI8 [2] 8bit LCD Memory Interface Function Select

GPIO_G[22] : Address Select signal for LCD controller
GPIO_G[21] : LCD Write Enable signal for LCD controller
GPIO_G[20] : LCD Output Enable signal for LCD controller
1
GPIO_G[19] : Chip Enable signal1 for LCD Controller

1

1
3-15
GPIO_XA Data Register (GDATA_XA) 0x80003070

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Data for GPIO_XA[31:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data for GPIO_XA[15:0] pin
If a certain GPIO_XA pin is set to output mode and act as GPIO, the corresponding bit of
this register controls the status of GPIO_XA pin; Low or High. If it is set to input mode
and act as GPIO, the corresponding bit represents the status of GPIO_XA pin; Low or
High.
GPIO_XA Direction Control Register (GIOCON_XA) 0x80003074

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Direction for GPIO_XA[31:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Diection for GPIO_XA[15:0] pin
If a bit is set to 1, the corresponding GPIO_XA pin is set to output mode. If set to 0, the
corresponding GPIO_XA pin is set to input mode.
GPIO_XA Function Select Register (GSEL_XA) 0x80003078

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XA[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XA[15:0]
If a bit is clear to 0, the corresponding GPIO_XA pin act as GPIO. The dedicated
peripherals for these GPIO_XA pins are External Memory Controller.
XA[31] [31] External Chip Select2 Function Select

1 nCS2 for External Memory Controller


XA[28] [28] SDRAM Clock Enable Function Select

1 SDR_CKE for External Memory Controller
XA[27] [27] SDRAM Clock Function Select

1 SDR_CLK for External Memory Controller
XA[26] [26] SDRAM nCS Function Select

1 SDR_nCS for External Memory Controller
3-16
XA[25] [25] nWE Function Select

1 nWE for External Memory Controller
XA[24] [24] nOE Function Select

1 nOE for External Memory Controller
XA[23:0] [23:0] XA Function Select

Each bit set to
XA[23:0] for External Memory Controller
1
3-17
GPIO_XD Data Register (GDATA_XD) 0x80003080

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Data for GPIO_XD[31:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Data for GPIO_XD[15:0] pin
If a certain GPIO_XD pin is set to output mode and act as GPIO, the corresponding bit of
this register controls the status of GPIO_XD pin; Low or High. If it is set to input mode
and act as GPIO, the corresponding bit represents the status of GPIO_XD pin; Low or
High.
GPIO_XD Direction Control Register (GIOCON_XD) 0x80003084

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Diection for GPIO_XD[31:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Diection for GPIO_XD[15:0] pin
If a bit is set to 1, the corresponding GPIO_XD pin is set to output mode. If set to 0, the
corresponding GPIO_XD pin is set to input mode.
GPIO_XD Function Select Register (GSEL_XD) 0x80003088

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XD[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XD[15:0]
If a bit is clear to 0, the corresponding GPIO_XD pin act as GPIO. The dedicated
peripherals for these GPIO_XD pins are External Memory Controller.
3-18
GPIO_B Pull Enable Register (GPIOB_PE) 0x800030B8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pull up/ pull down Enable for GPIO_B[15:0] pin
If a bit is set to 1, the corresponding GPIO_B pin is enabled pull-up or pull_down . If set
to 0, the corresponding GPIO_B pin is disabled pull-up and pull_down
GPIO_B Pull Select Register (GPIOB_PS) 0x800030BC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pull up/ pull down Selection for GPIO_B[15:0] pin
If a bit is set to 1 and the corresponding of GPIOB_PE is set to 1, the corresponding

GPIO_B pin is enabled pull-up. If set to 0 and the corresponding of GPIOB_PE, the
corresponding GPIO_B pin is enabled pull-down.
GPIO_C Enable Register (GPIOC_PE) 0x800030C0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 Pull up/ pull down Enable for GPIO_C[23:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pull up/ pull down Enable for GPIO_C[15:0] pin
If a bit is set to 1, the corresponding GPIO_C pin is enabled pull-up or pull_down . If set
to 0, the corresponding GPIO_C pin is disabled pull-up and pull_down
GPIO_C Pull Select Register (GPIOC_PS) 0x800030C4
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 Pull up/ pull down Selection for GPIO_C[23:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pull up/ pull down Selection for GPIO_C[15:0] pin
If a bit is set to 1 and the corresponding of GPIOC_PE is set to 1, the corresponding

GPIO_C pin is enabled pull-up. If set to 0 and the corresponding of GPIOC_PE, the
corresponding GPIO_C pin is enabled pull-down.
3-19
GPIO_E Pull Enable Register (GPIOE_PE) 0x800030D0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Pull up/ pull down Enable for GPIO_E[15:0] pin
If a bit is set to 1, the corresponding GPIO_E pin is enabled pull-up or pull_down . If set
to 0, the corresponding GPIO_E pin is disabled pull-up and pull_down
GPIO_E Pull Select Register (GPIOE_PS) 0x800030D4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Pull up/ pull down Selection for GPIO_E[15:0] pin
If a bit is set to 1 and the corresponding of GPIOE_PE is set to 1, the corresponding

GPIO_E pin is enabled pull-up. If set to 0 and the corresponding of GPIOE_PE, the
corresponding GPIO_E pin is enabled pull-down.
GPIO_F Pull Enable Register (GPIOF_PE) 0x800030D8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pull up/ pull down Enable for GPIO_F[15:0] pin
If a bit is set to 1, the corresponding GPIO_F pin is enabled pull-up or pull_down . If set
to 0, the corresponding GPIO_F pin is disabled pull-up and pull_down
GPIO_F Pull Select Register (GPIOF_PS) 0x800030DC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pull up/ pull down Selection for GPIO_F[15:0] pin
If a bit is set to 1 and the corresponding of GPIOF_PE is set to 1, the corresponding

GPIO_F pin is enabled pull-up. If set to 0 and the corresponding of GPIOF_PE, the
corresponding GPIO_F pin is enabled pull-down.
3-20
GPIO_G Pull Enable Register (GPIOG_PE) 0x800030E0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 Pull up/ pull down Enable for GPIO_G[23:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pull up/ pull down Enable for GPIO_G[15:0] pin
If a bit is set to 1, the corresponding GPIO_G pin is enabled pull-up or pull_down . If set
to 0, the corresponding GPIO_G pin is disabled pull-up and pull_down
GPIO_G Pull Select Register (GPIOG_PS) 0x800030EC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 Pull up/ pull down Selection for GPIO_G[23:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pull up/ pull down Selection for GPIO_G[15:0] pin
If a bit is set to 1 and the corresponding of GPIOG_PE is set to 1, the corresponding

GPIO_G pin is enabled pull-up. If set to 0 and the corresponding of GPIOG_PE, the
corresponding GPIO_G pin is enabled pull-down.
3-21
XA pull Enable Register (XA_PE) 0x800030E8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Pull up/ pull down Enable for XA[31:24] pin Pull up/ pull down Enable for XA[23:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pull up/ pull down Enable for XA[15:0] pin
If a bit is set to 1, the corresponding XA pin is enabled pull-up or pull_down . If set to 0,

the corresponding XA pin is disabled pull-up and pull_down.
XA_PE[31] [31] nCS2 Pull up/ pull down control enable

1 pull up or pull down controlled


XA_PE[28] [28] SDR_CKE Pullup /pull down control enable

1 SDR
XA_PE[27] [27] SDR_CLK Pull up/ pull down control enable

XA_PE[26] [26] SDR_nCS Pull up/ pull down control enable

XA_PE[25] [25] nWE Pull up/ pull down control enable

XA_PE[24] [24] nOE Pull up/ pull down control enable

XA_PE[23:0] [23:0] XA Pull up/ pull down control enable

Each bit set to
pull up or pull down controlled
1
XA Pull Select Register (XA_PS) 0x800030EC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Pull up/ pull down Selection XA[31:24] pin Pull up/ pull down Selection XA[23:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pull up/ pull down Selection for XA[15:0] pin
If a bit is set to 1 and the corresponding of XA_PE is set to 1, the corresponding XA pin is
enabled pull-up. If set to 0 and the corresponding of XA_PE, the corresponding XA pin is
enabled pull-down.
3-22
XD Pull Enable Register (XD_PE) 0x800030F0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Pull up/ pull down Enable for XD [31:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pull up/ pull down Enable for XD[15:0] pin
If a bit is set to 1, the corresponding XD pin is enabled pull-up or pull_down . If set to 0,

the corresponding XD pin is disabled pull-up and pull_down
XD Pull Select Register (XD_PS) 0x800030F4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Pull up/ pull down Selection XD[31:16] pin
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Pull up/ pull down Selection for XD[15:0] pin
If a bit is set to 1 and the corresponding of XA_PE is set to 1, the corresponding XA pin is
enabled pull-up. If set to 0 and the corresponding of XA_PE, the corresponding XA pin is
enabled pull-down.
3-23
Brief of Fuction Selection.

-The Follwing table is brief of fuction selection.
- Don’t set twice to the same functional port. For example,
UART0(UT0) port is existed in GPIO_B(N0-UT0, N3-UT0) and GPIO_F(N0-UT0, N2-UT0) but one bit
should be set among 4 selection bits. If more than one bits are set, UART0 is not selected.
Port Name GSEL_A

GPIO_A[0] EHI_XD[0] ND_XD[0] HDD_XD[0]
GPIO_A[3] EHI_XD[3] EHI16 ND_XD[3] NFC16 HDD_XD[3]
GPIO_A[4] EHI_XD[4] EHI8 ND_XD[4] NFC8 HDD_XD[4]
HDD
EHI16 NFC16
GPIO_A[16]
GPIO_A[17]
GPIO_A[18] EHI_INT ND_CS[0] HDD_nCS[0]
GPIO_A[19] EHI_XA ND_CS[1] HDD_nCS[1]
EHI16
GPIO_A[20] EHI_CSN ND_WEN HDD_nDIOW
EHI8
GPIO_A[21] EHI_WEN ND_OEN NFC8 HDD_nDIOR
HDD
GPIO_A[22] EHI_OEN ND_CLE HDD_DA[0]
GPIO_A[23] ND_ALE HDD_DA[1]
GPIO_A[24] ND_READY0 HDD_DA[2]
GPIO_A[25] ND_READY1 HDD_IORDY
GPIO_A[26]
GPIO_A[27]
3-24
Port Name GSEL_B

GPIO_B[0] UART0_RXD SPI_SDI
GPIO_B[1] UART0_TXD SPI_SCK
N0-UT0 N0-SPI
GPIO_B[2] UART0_CTS SPI_FRM
GPIO_B[3] UART0_RTS SPI_SDO
GPIO_B[4] UART1_RXD EINT[0] N1-EI0
GPIO_B[5] UART1_TXD EINT[1] N1-EI1
N1-UT1
GPIO_B[6] UART1_CTS EINT[2] N1-EI2 IDE CSN
GPIO_B[7] UART1_RTS EINT[3] N1-EI3 ND WEN
GPIO_B[8] UART0_RXD EINT[0] N2-EI0
GPIO_B[9] UART0_TXD EINT[1] N2-EI1
N2-UT0
GPIO_B[10] UART0_CTS EINT[2] N2-EI2
GPIO_B[11] UART0_RTS EINT[3] N2-EI3
GPIO_B[12] UART1_RXD SPI_SDI
GPIO_B[13] UART1_TXD SPI_SCK
N3-UT1 N3-SPI
GPIO_B[14] UART1_CTS SPI_FRM
GPIO_B[15] UART1_RTS SPI_SDO
Port Name GSEL_C

GPIO_C[0] ND_XD[0] HDD_XD[0] SD_XD[0] SD8 SD4 SD1
GPIO_C[1] ND_XD[1] HDD_XD[1] SD_XD[1]
GPIO_C[2] ND_XD[2] HDD_XD[2] SD_XD[2] SD8 SD4
GPIO_C[3] ND_XD[3] NFC16 HDD_XD[3] SD_XD[3]
GPIO_C[4] ND_XD[4] NFC8 HDD_XD[4] SD_CLK SD8 SD4 SD1
GPIO_C[5] ND_XD[5] HDD_XD[5] SD_CMD
GPIO_C[6] ND_XD[6] HDD_XD[6]
NFC16 HDD
GPIO_C[16] ND_CS[0] HDD_nCS[0] SD_XD[4]
GPIO_C[17] ND_CS[1] HDD_nCS[1] SD_XD[5]
SD8
GPIO_C[18] ND_WEN HDD_nDIOW SD_XD[6]
NFC16
GPIO_C[19] ND_OEN HDD_nDIOR SD_XD[7]
NFC8
GPIO_C[20] ND_CLE HDD_DA[0]
GPIO_C[21] ND_ALE HDD_DA[1]
GPIO_C[22] ND_READY0 HDD_DA[2]
GPIO_C[23] ND_READY1 HDD_IORDY
3-25
Port Name GSEL_E

GPIO_E[0] DAI_BCLK
GPIO_E[1] DAI_LRCK
GPIO_E[2] DAI_MCLK DAI
GPIO_E[3] DAI_SDI
GPIO_E[4] DAI_SDO
GPIO_E[5] I2C_SDA
I2C
GPIO_E[6] I2C_SCL
GPIO_E[7]
Port Name GSEL_F

GPIO_F[0] CIF_D[0] UART0_RXD SPI_SDI
GPIO_F[1] CIF_D[1] UART0_TXD SPI_SCK
N0-UT0
GPIO_F[2] CIF_D[2] UART0_CTS SPI_FRM
GPIO_F[3] CIF_D[3] UART0_RTS SPI_SDO
GPIO_F[4] CIF_D[4] UART1_RXD EINT[0]
GPIO_F[5] CIF_D[5] UART1_TXD EINT[1]
N1-UT1
GPIO_F[6] CIF_D[6] CIF UART1_CTS EINT[2] IDE CSN
GPIO_F[7] CIF_D[7] UART1_RTS EINT[3] ND WEN
GPIO_F[8] CIF_MCLK UART0_RXD EINT[0]
GPIO_F[9] CIF_PCLK UART0_TXD N2- EINT[1]
GPIO_F[10] CIF_VS UART0_CTS UT0 EINT[2]
GPIO_F[11] CIF_HS UART0_RTS EINT[3]
GPIO_F[12] CIF_PWDN UART1_RXD SPI_SDI
GPIO_F[13] UART1_TXD N3- SPI_SCK
GPIO_F[14] I2C_SDA UART1_CTS UT1 SPI_FRM
I2C
GPIO_F[15] I2C_SCL UART1_RTS SPI_SDO
3-26
Port Name GSEL_G

GPIO_G[0] LCD_XD[0] LCD_XD[0]
LMI18 LCI18
LMI16 LCI16
LMI8 LCI8
GPIO_G[11] LCD_XD[11] LMI18 LCD_XD[11] LCI18
GPIO_G[12] LCD_XD[12] LMI16 LCD_XD[12] LCI16
LMI18 LCI18
GPIO_G[18] LCD_CSN[0] LCD_VS
LCI18
GPIO_G[19] LCD_CSN[1] LMI18 LCD_HS
LCI16
GPIO_G[20] LCD_OEN LMI16 LCD_ACBIAS
LCI8
GPIO_G[21] LCD_WEN LMI8 LCD_CLK
GPIO_G[22] LCD_XA
GPIO_G[23]
3-27
Booting Procedure
Multimedia Application Processor BOOTING PROCEDURE
4 BOOTING PROCEDURE
4.1 Overview
In the TCC82xx, there is an internal boot ROM for system initialization process. It
contains the fundamental routines for system initialization or boot procedure through
various device or interface such as NOR flash, USB only, NAND flash, EHI and I2C.
There are 5 modes for booting procedure. Figure 4.1 illustrates the timing of reset
sequence at power-up. During this process, the configuration value including boot mode
is selected by the state of {BMSEL, GPIO_A[27], GPIO_A[26], GPIO_B[11],
GPIO_B[9], GPIO_B[7], GPIO_B[5], GPIO_B[3]} at nRESET going to high. The 8bit
configuration value (CFG[7:0]) determine the key system factors as Table 4.1, and
Table 4.2 represents the detailed boot mode of the TCC82xx.
Table 4.1 Configuration Value
GPIO_B[11]
GPIO_A[27]
GPIO_A[26]
GPIO_B[9]
GPIO_B[7]
GPIO_B[5]
GPIO_B[3]
BMSEL
Description
CFG[7:0] [7] [6] [5] [4] [3] [2] [1] [0]
NOR 1 0 0 0/1 X X X X
EHI x86 1 0 1 X X 0 X X
EHI 68000 1 0 1 X X 1 X X
NFC 16bit (GPIO-C) 1 1 0 X 0 X X X
USB I/F 1 1 1 X X X X X
NOR 0 X X 0/1 X 0 0 0
NFC 8bit (GPIO-A) 0 X X X 1 0 0 1
EHI x86 0 X X X 0 0 1 0
EHI 68000 0 X X X 1 0 1 0
I2C 0 X X X X 0 1 1
USB I/F 0 X X X X 1 X X
4-1
Figure 4.1 Reset Sequence
Table 4.2 Booting Mode of the TCC82xx

BOOT Description
F/W Download from USB I/F
In this mode, user can download any program to any memory.
USB In case of failure in other boot processing (except external boot), it also starts this
boot procedure automatically. Refer to USB Boot section for detailed
information.
Boot from NAND Flash attached at the GPIO_A[15:0] or GPIO_C[15:0]
In this mode, the F/W code is read from NAND flash attached at the
NAND
GPIO_A[15:0] or GPIO_C[15:0] ports. The detailed information of supported
NAND type and configuration is described in NFC NAND Boot section.
Boot from Serial EEPROM attached at the GPIO_F[15:14]
In this mode, the F/W code is read from serial EEPROM attached at the
I2C GPIO_B[15:14] ports. It uses standard I2C interface using GPIO_B15 as I2C
clock and GPIO_B14 as I2C data. The detailed information about this process is
described in I2C Boot section.
F/W Download from EHI I/F
In this mode, user can download any program to any memory through EHI
EHI
interface. It can support both of x86 interface and 68000 interface. The detailed
procedure is described in EHI Boot section.
Normal Boot from NOR Flash
NOR The TCC82xx executes code at the beginning of NOR flash which is attached at
nCS3 (XA[32]) pin. This is most commonly used mode.
4-2
4.2 Normal Boot from NOR Flash
GPIO_B[11]
GPIO_A[27]
GPIO_A[26]
GPIO_B[9]
GPIO_B[7]
GPIO_B[5]
GPIO_B[3]
BMSEL
Description
CFG[7:0] [7] [6] [5] [4] [3] [2] [1] [0]

NOR 1 0 0 0/1 X X X X
NOR 0 X X 0/1 X 0 0 0
It supports an external boot ROM.

When normal boot mode, the sequence begins from external ROM that is attached to
nCS3.
The bus width of external boot ROM can be determined by GPIO_B[11]/CFG[4] which
is acquired in reset sequence.
If CFG[4] == 0, the bus width is 16bit, if CFG[4] == 1, it is 8bit.
4.3 USB Boot
GPIO_B[11]
GPIO_A[27]
GPIO_A[26]
GPIO_B[9]
GPIO_B[7]
GPIO_B[5]
GPIO_B[3]
BMSEL
Description
CFG[7:0] [7] [6] [5] [4] [3] [2] [1] [0]
USB I/F 1 1 1 X X X X X
USB I/F 0 X X X X 1 X X
This mode is mainly for firmware upgrade mode. In this mode, user can download a
program into the user defined area. If the destination is SDRAM, user also send the
configuration register value (SDCFG) for SDRAM.
When the failure occurs in some other boot modes, it may progress this boot sequence
also.
The procedure of this mode is as follows.
i) The TCC82xx makes internal SRAM area starts from zero, and copies USB interrupt
service routine to internal SRAM area.
ii) It waits until USB connection is established.
iii) Once it is connected, host transfers first the parameter for USB loader routine
including destination address, user defined parameter and the amount of data to be
transferred (with a unit of packet). If user wants to download into SDRAM, the
SDCFG value must be transferred as user defined parameter.
iv) The TCC82xx starts communicating between a host PC with fixed amount of data
which is called as packet. The packet size of TCC82xx is 512 bytes.
v) At every successful reception of packet, it copies them where the destination address
pointed, and after all amount of data has been copied, it starts program where the start
address pointed.
4-3
Normally, the program downloaded is for writing user system firmware to non-volatile
memory like NOR or NAND flash.
The following figure illustrates the sequence of USB boot mode described above.
Mode Setting
Set PLL for USB operation
Set internal SRAM starts from zero
Copy USB service routine to SRAM
Initialize USB (Device enabled)
Connection No
Established ?
Yes
Receive the parameter for USB loader
Receive a packet
Copy the packet to destination block
All amount of No
Data ?
Yes
Jump to Destination Address
Figure 4.2 USB boot procedure
4-4
4.4 NFC NAND Boot
GPIO_B[11]
GPIO_A[27]
GPIO_A[26]
GPIO_B[9]
GPIO_B[7]
GPIO_B[5]
GPIO_B[3]
BMSEL
Description
CFG[7:0] [7] [6] [5] [4] [3] [2] [1] [0]

In this mode, the F/W code is read from NAND flash attached at the GPIO_A[15] or
GPIO_C[15:0] ports. NAND chip enable is controlled by GPIO_A[19:18] or
GPIO_C[17:16]. To make use of this mode, the predefined structure such as Master Block
and Master Cluster should be fused in the NAND flash. The detailed construction of these
structure is represented in Figure 4.4.
The supportable configuration of NAND flash is as follows.
Case1) one NAND flash of 8bit bus-width.

Case2) one NAND flash of 16bit bus-width
Case3) two NAND flashes of 8 or 16bit bus-width with separate chip enable signals.
Case4) two NAND flashes of 8bit bus-width with same chip enable signals.
In case of Case3, the F/W can be located in one of two NAND flashes.
In case of Case4, the CFG[4] should be 0 to regard as 16bit single NAND flash. So, the
two NAND flashes can share the 16bit data-bus by using upper and lower 8 bit separately.
The boot sequence of this mode is as follows. If there exists any problem hard to recover
during this sequence, it goes to USB boot mode automatically. It assumes the contents is
stored as little endian format.
i) Check if device ID exist in the device ID table. (Refer to Table 4.3)

Determine the configuration of NAND flashes. (Case1 ~ Case4)
Setup the parameter for NFC block (pages per block, number of address cycles, etc.)
according to device ID.
ii) Read the last 1 word (4 bytes) in the spare area of 0 page of 0 block.
It contains the block address of Master Block in upper 3 bytes, and number of Master
Cluster in lower 1 byte. If the MSB of master block address (CS1 bit) is 1, it means
the master block exist in the second NAND flash (that is attached at GPIO_A19 or
GPIO_C17).
31 30 8 7 0
CS1 Block address of Master Block. Number of Master Cluster
iii) Load and Construct the golden image of Master Cluster from the Master Block to
internal SRAM. The structure of Master Block and Master Cluster is represented in
Figure 4.4.
4-5
iv) The 1st word of golden Master Cluster determines the next procedure as follows.
In case of 0x54C34396 (‘T’, C3, ‘C’, 96), TCC82xx regard the Master Cluster as the
Master Code, and finishes booting procedure by jumping to the address of 2nd word
in golden Master Cluster.
In case of 0x54C34996 (‘T’, C3, ‘I’, 96), TCC82xx starts loading according to the
contents of golden Master Cluster.
v) After finishing download of F/W, TCC82xx progress C2 (Dual CRC Checking)

process on the loaded image. The C2 process is described at the Dual CRC
Checking section.
vi) After C2 process has finished, and it is OK, TCC82xx finishes booting procedure by
jumping to the destination address which is contained in golden Master Cluster.
In loading from NAND flash, TCC82xx uses MLC-ECC regardless of NAND type, so
loading is accomplished by unit of 512+16 bytes. The MLC-ECC can correct up to 4
symbol errors, so the F/W code can be stored with high robustness.
Table 4.3 Supported NAND flash types

Size Size of Page Pages / Number Device ID
(bytes) (bytes) Block of Page x8 / x8 / x16 / x16
8M 512 16 16K 39 / E6 / 49 / 59
16M 512 16 32K 33 / 73 / 43 / 53
32M 512 32 64K 35 / 75 / 45 / 55
64M 512 32 128K 36 / 76 / 46 / 56
128M 512 32 256K 78 / 79 / 72 / 74
256M 512 32 512K 71
512M 512 32 1024K DC
128M 2048 64 64K A1 / F1 / B1 / C1
256M 2048 64 128K AA / DA / BA / CA
512M 2048 64 256K AC / DC / BC / CC
1G 2048 64 512K A3 / D3 / B3 / C3
2G 2048 64 1024K A5 / D5 / B5 / C5
4-6
NAND Device ID reading
No Device ID is
OK ?
Yes
Get the address of Master Block &
The number of Master Cluster
ECC Failed
Construct Master Cluster at internal SRAM
No CRC of Master
USB Boot Mode
Cluster is OK ?
Yes
No 1st Word ==
0x54C34396 ?
Yes
1st word == No
Jump to 2nd word of Master Cluster
0x54C34996 ?
Yes
Load Master Image according to Master Cluster
Do C2 Process on the loaded Master Image
No
C2 is OK ? USB Boot Mode
Yes
Jump to Start of Loaded Image
Figure 4.3 NAND boot procedure
4-7
0 page / 0 block
Data Area Spare 0 : use 1st NAND device
1 : use 2nd NAND device
Last 1 word
C MBA MC
1st Copy of Master Cluster

2nd Copy of Master Cluster
3rd Copy of Master Cluster
...
MCth Copy of Master Cluster
Construct Golden Master Cluster

1) 1 Master Cluster has 2Kbytes and consists of 1 or 4 pages. (Including case of Case4)
2) From the MC number of Master Cluster, construct Golden Master Cluster that is error
free by ECC correction.
3) Error Correction occurs every sector (512+16 bytes) unit.
7 6 5 4 2 1 0
1st Sector (512 bytes) 16 bytes x BS x ECC[1:0]
... 15 BS : Block Status 8
4th Sector (512 bytes) 16 bytes ECC[9:2]
Code Type Index Type

3 0 3 0
0x54C34396 0x54C34996
Destination Destination address of Master Image.
User Param If Destination is SDRAM, this value means SDCFG.
Last Block Offset address of (BIDX[n] + 2).
BIDX[0] PADR Block & Page address of 1st part of image.
Up to 2040 bytes of
code can be BIDX[2] BIDX[1] Block address of 2nd part of image.
executed.
... ...
Reserved BIDX[n] Block address of last part of image.
...
Reserved
CRC CRC
Figure 4.4 Basic Structure and Boot Flow of NAND Boot
4.5 I2C Boot

GPIO_B[11]
GPIO_A[27]
GPIO_A[26]
GPIO_B[9]
GPIO_B[7]
GPIO_B[5]
GPIO_B[3]
BMSEL
Description
CFG[7:0] [7] [6] [5] [4] [3] [2] [1] [0]
I2C 0 X X X X 0 1 1
4-8
In this mode, the F/W code is read from serial EEPROM attached at the GPIO_F[15:14]
ports. It uses standard I2C interface using GPIO_B15 as I2C clock and GPIO_B14 as I2C
data.
The procedure checks if there exist EEPROM first. If there exist an EEPROM, TCC82xx
do the following procedure. If certain problem can not be solved has occurred, it goes to
USB boot mode automatically.
i) Read init line from EEPROM. The init line consists of the following information.
Name Size Description
Validity & Security Information.
Header 8
Should be matched with pre-defined rule.
Destination 4 Destination address of image
User Parameter 4 If destination address is SDRAM, this must be SDCFG.
Image Size 4 Size of image with byte unit.
ii) Check if the header information is correct.

iii) Load code from EEPROM into Destination address.
iv) After all amount of codes are loaded, do the C2 (Dual CRC Checking) process on the
loaded image. The C2 process is described at the Dual CRC Checking section.
v) After C2 process has finished, and it is OK, TCC82xxfinishes booting procedure by
jumping to the destination address.
Check If serial EEPROM is attached
No
Attached ?
Yes
Read Init Line (1st 5 words)
No
Header is OK ?
Yes
Load image into Destination Address
Do C2 Process on the loaded image
No
C2 is OK ?
Yes
Jump to the Destination Address USB Boot Mode
Figure 4.5 I2C boot procedure
4-9
4.6 EHI Boot
GPIO_B[11]
GPIO_A[27]
GPIO_A[26]
GPIO_B[9]
GPIO_B[7]
GPIO_B[5]
GPIO_B[3]
BMSEL
Description
CFG[7:0] [7] [6] [5] [4] [3] [2] [1] [0]
EHI x86 1 0 1 X X 0 X X
EHI 68000 1 0 1 X X 1 X X
EHI x86 0 X X X 0 0 1 0
EHI 68000 0 X X X 1 0 1 0
In this mode, the TCC82xx enables EHI I/F module, and waits until specific value is
received from HOST. While TCC82xx waiting this value, the HOST can control all of
memory space accessible by TCC82xx through EHI I/F. The EHI I/F can be manipulate
either of x86 or 68000 type interfacing. The interfacing type is determined by
CFG[2](BMSEL==1) or CFG[3](BMSEL==0). If CFG[2]==0(BMSEL==1) or
CFG[3]==0(BMSEL==0), it uses x86 type, and if CFG[2]==1(BMSEL==1) or
CFG[3]==1(BMSEL==0), it uses 68000 type. The bus-width of EHI I/F is predefined as
16bit width
.
The detailed procedure is as follows.
i) Enable EHI I/F. (Interfacing Type, Bus-width is set.)

ii) Set ST field of EHST register to 1.
iii) Waits until ST field of EHST register is cleared to 0.
iv) HPD contains the destination address. Read HPD register, and jump to the destination
address.
In this mode, TCC82xx doesn't execute any automatical processing such as SDRAM
initialization or CRC checking. So, the HOST should take part in all kind of process for
reliable downloading.
4-10
TCC82xx Processing External HOST Processing
Enable EHI I/F (Interfacing Type, Bus-width) Read EHST.ST register
Set EHST.ST to 0x55 EHST.ST == No

0x55 ?
Read EHST.ST register Yes

Download TCC82xx F/W Code
Yes EHST.ST ==
0x55 ? Set HSD Register to Destination Address
No
Read HSD Register. It is Destination Address.
Jump to the Destination Address
Figure 4.6 EHI boot procedure
4.7 Dual CRC Checking
The TCC82xx can check the CRC for the downloaded image according to the dedicated
algorithm. This is described as follows.
i) Calculate CRC on the downloaded image up to 64Kbytes. In calculation, the word at

the offset of 0x10 and 0x14 is skipped, because the good CRC code is contained at
the offset of 0x10, and the word at the offset of 0x14 means the address of user-
defined CRC routine.
ii) After the first CRC calculation has been done, and it is same as the value at the offset
address of 0x10, TCC82xx check if the address of user-defined CRC routine is not 0.
Or, TCC77x goes to pre-defined boot mode (USB or UART boot) automatically.
iii) If there exist user-defined CRC routine, call that routine.
The user-defined CRC routine checks its own CRC code and return with Equal
condition if it is OK or return Not Equal condition if it fails.
iv) If there are failure on the user-defined CRC checking, TCC82xx goes to pre-defined
boot mode (USB or UART boot) automatically.
The following code shows same CRC generation algorithm used in the first CRC
checking routine.
word calc_crc (word *base, word length, word *crctable)

{ // contents of crctable is acquired by gen_crc () function
word crcout = 0;
word cnt, i, code, tmp;
length >>= 2; // convert into word unit.

for (cnt = 0; cnt < length; cnt ++) {
if (cnt == 0x04 or cnt == 0x05) // skip offset of 0x10 and 0x14
continue;
code = base[cnt];
for (i = 0; i < 4; i ++) {
tmp = code ^ crcout;
crcout = (crcout >> 8) ^ crctable[tmp & 0xFF];
code = code >> 8;
}
4-11
}
return crcout;
}
void gen_crc (word *crctable)

{ // Polynomial = x32 + x31 + x16 + x15 + x4 + x3 + x + 1
word crc, cnt, i;
for (cnt = 0; cnt < 0x100; cnt ++) {

crc = cnt;
for (i = 0; i < 8; i ++) {
if (crc & 1) crc = (crc >> 1) ^ 0xD8018001;
else crc = (crc >> 1);
}
crctable[cnt] = crc;
}
}
4-12
JTAG Debug Interface
Multimedia Application Processor JTAG DEBUG INTERFACE
5 JTAG DEBUG INTERFACE
The TCC82xx has the ARM946ES core as main controller, and JTAG interface for
developing the application programs. It can be connected with OPENice32 of AIJI
System or Multi-ICE of ARM or other third party’s in-circuit emulator supporting for
ARM946ES core.
With the use of in-circuit emulator, users can easily develop the program for their own
system. It provides hardware breakpoints, internal register monitoring, memory dump, etc.
Refer to user’s manual of in-circuit emulator for more detail functions of it.
Figure 5.1 shows the application circuit for JTAG interface. Care must be taken not to
combine system reset with JTAG reset signal.
20 19 VDDIO
18 17 10K
nSRST 10K 10K 10K
16 15
14 13 TDO
TDO
12 11 RTCK
RTCK
TCK
10 9 TCK
TMS
8 7 TMS
TDI
6 5 TDI
4 3 nTRST
2 1 TCC82xx
nTRST
RESET
CIRCUIT
nRESET
Figure 5.1 JTAG Interface Circuit Diagram
5-1
Electrical Data
Multimedia Application Processor ELECTRICAL DATA
6 ELECTRICAL DATA
6.1 Absolute Maximum Ratings
Table 6.1 Absolute Maximum Ratings

Parameter Symbol Rating Unit
DC Supply Voltage for 1.8 ~ 3.3 V I/O VDDIO 4.8 V
DC Supply Voltage for 5.0V tolerant I/O VDDIOt 6.5 V
DC Supply Voltage for 1.2V VDDI12 1,8 V
DC Supply Voltage for 3.3V VDDI33 4.8 V
DC Input Current IIN +/- 20 mA
o
Storage Temperature TSTG -65 ~ 150 C
6.2 Recommended Operating Conditions
Table 6.2 Recommended Operating Conditions

Parameter Symbol MIN TYP MAX Unit
DC Supply Voltage for 1.8 ~ 3.3V I/O VDDIO 1.65 3.6 V
DC Supply Voltage for Internal Digital Logic VDDI 1.1 1.3 V
DC Supply Voltage for Analog Part 3.3V VDDA33 3.135 3.465 V
DC Supply Voltage for Analog Part 1.2V VDDA12 1.14 1.26 V
Digital Input Voltage for 1.8 ~ 3.3V I/O VIN VDDIO + 0.3 V
Digital Input Voltage for 5V tolerant I/O VINT 5.5 V
o
Operating Temperature TOPER 0 70 C
Notes:
1. Absolute maximum rating specifies the values beyond which the device may be damaged permanently.
Exposure to ABSOLUTE MAXIMUM RATING conditions for extended periods may affect reliability.
Each condition value is applied with the other values kept within the following operating conditions and
function operation under any of these conditions is not implied.
2. All voltages are measured with respect to VSS unless otherwise specified.
6-1
Multimedia Application Processor ELECTRICAL DATA
6.3 Electrical Characteristics
Table 6.3 DC Electrical Characteristics for I/O

Parameter Symbol Test Conditions MIN TYP MAX Unit
High Level Input Voltage VIH CMOS 0.7VDD V
Low Level Input Voltage VIL CMOS 0.25VDD V
Schmitt Trigger, Positive-going Threshold VT+ CMOS 0.7VDD V
Schmitt Trigger, Negative-going Threshold VT- CMOS 0.25VDD V
High Level Input Current -10 10 μA
IIH VIN = VDDIO
High Level Input Current (pull-down) 5 72 μA
Low Level Input Current -10 10 μA
IIL VIN = VSS
Low Level Input Current (pull-up) -72 -5 μA
4mA Buffer VDD - 0.2 V
High Level Output Voltage VOH
8mA Buffer VDD - 0.2 V
4mA Buffer 0.2 V
Low Level Output Voltage VOL
2mA Buffer 0.2 V
Tri-state Output Leakage Current IOZ VOUT = VSS or VDDIO -10 10 μA
Ta = 25 o C, VDDIO = 1.65 ~ 3.6V
Not all parameters are tested. Guaranteed by design characterization.
6-2
Package Dimensions
Multimedia Application Processor PACKAGE DIMENSIONS
7 PACKAGE DIMENSIONS
7.1 Package Dimension of TCC8200
Figure 7.1 TCC8200 Package Dimension (256-FPBGA-1313)
7-1
TCC82xx
Part 2. Interface
Chapter 1. Memory
Chapter 2. DAI
Chapter 3. UART
Chapter 4. SPIMS
Chapter 5. I2C
Chapter 6. ECC
Chapter 7. USB
Chapter 8. NAND
Chapter 9. SD(MMC)
Chapter 10. EHI
Chapter 11. IDE
Rev. 0.20
Apr. 24 2006
Revision History

Memory Controller
Multimedia Application Processor MEMORY CONTROLLER
1 MEMORY CONTROLLER
1.1 Overview
TCC82xx has a memory controller for various kind of memory for digital media en-decoding
system. It can manipulate SDRAM, Flash (NAND, NOR type), ROM, SRAM type memories,
and also support the IDE interface for HDD. It has configurable data bus width through the GPIO
pin or each configuration register. The data bus width can be configured for each chip select
separately
The memory controller provide the power saving function for SDRAM (self refresh).
The following figure represents the block diagram of memory control unit.
SDRAM
Refresh
SDCFG State
Controller
Machine
SDRAM
Signal
AHB
Generator
Memory
Remap
Signal Mixer Control
Flag
Signals
ExtMEM
Signal
Generator
ExtMEM
CSCFGn State
Machine
Figure 1.1 Memory Controller Block Diagram
The registers for memory controller block have the base address of 0xF0000000.
1-1
Table 1.1 Memory Controller Register Map (Base Address = 0xF0000000)

SDCFG 0x00 R/W 0x62E97010 SDRAM Configuration Register
SDFSM 0x04 R - SDRAM FSM Status Register
MCFG 0x08 R/W 0xZZZZ_02 Miscellaneous Configuration Register
TST 0x0C W 0x0000 Test mode register (must be remained zero)
CSCFG0 0x10 R/W 0x6D0AC809 Configuration Register for External ChipSelect0 (nCS0 pin)
CSCFG1 0x14 R/W 0x254AD01A Configuration Register for External Chip Select 1 (nCS1 pin)
CSCFG2 0x18 R/W 0x218AD03A Configuration Register for External Chip Select 2 (nCS2 pin)
CSCFG3 0x1C R/W 0x29CAD01A Configuration Register for External Chip Select 3 (nCS3 pin)
CLKCFG 0x20 R/W 0xXXXXXX00 Memory Controller Clock Count Register
SDCMD 0x24 W - SDRAM Command Register
Table 1.2 NAND flash Register Map (Base Address = N * 0x10000000)

NDCMD 0x00 R/W - Command Cycle Register
NDLADR 0x04 W - Linear Address Cycle Register
NDRADR 0x08 W - Row Address Cycle Register
NDSADR 0x0C W - Single Address Cycle Register
NDDATA 0x1x R/W - Data Access Cycle Register
*) N represents BASE field of configuration register (CSCFGn ) for each chip select.
1-2
1.2 SDRAM Controller
SDRAM controller can control from 16Mbit up to 256Mbit SDRAM. In TCC82xx system, the
SDRAM can contain almost parts for system operation. (Program, data, buffer, etc can be located
in SDRAM).
The SDRAM parameter such as size, refresh period, RAS to CAS delay, refresh to idle delay can
be programmed by internal register.
The registers for SDRAM controller are as follows.

Refer to SDRAM cycle diagram in Figure 1.2
SDRAM Configuration Register (SDCFG) 0xF0000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CL *R CW[1:0] SDBASE[3:0] RC[2:0] RCD[2:0] *R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
*R RP[2:0] RW[1:0] Refresh[5:0] AM APD PPD SR
*) The reset value means the following configuration.
CAS Latency = 2 cycles, CAS Width = 9bit, RAS Width = 12bit, SDBASE = 0x20000000
tRC = 3 cycles, tRCD = 3 cycles, tRD = 2 cycles, tRP = 8 cycles, Refresh = (32) cycles
*) R = Reserved.
The SDRAM is disabled at first, to enable SDRAM controller, you must set SDEN flag of MCFG register
first, and then set this register appropriately. At the beginning of using SDRAM, SDRAM must be refreshed
several times for reliable operation, and writing to SDCFG register can do this because this writing
automatically generates the SDRAM refresh cycle once at a time.
CL [31] CAS Latency (tCL)

0 CAS latency is 2 cycle
1 CAS latency is 3 cycle
CW[1:0] [29:28] CAS Width

0, 1 8 bit is used for CAS address
2 9 bit is used for CAS address
3 10 bit is used for CAS address
*) 64Mbit : CAS = 8 bit, RAS = 12 bit
128Mbit : CAS = 9 bit, RAS = 12 bit
SDBASE[3:0] [27:24] SDRAM Base Address

Indicates the MSB 4bit of SDRAM area. That is SDRAM base =
N
0xN0000000
RC[2:0] [23:21] Delay of Refresh to Idle (tRC)

n n number of HCLK cycle is used to meet the refresh to idle delay time
RCD[2:0] [20:18] Delay of RAS to CAS (tRCD)

n (n+1) number of HCLK cycle is used to meet the RAS to CAS delay time
RP[2:0] [14:12]
n (n+1) number of HCLK cycle is used to meet the precharge to refresh time
1-3
RW[1:0] [11:10] RAS Width

{x,1} 11bit is used for RAS address bus
{0,0} 12bit is used for RAS address bus
{1,0} 13bit is used for RAS address bus
*) 64Mbit : CAS = 8 bit, RAS = 12 bit
Refresh[5:0] [9:4] Refresh Cycle

Every (n * 32) number of HCLK cycle has passed, the SDRAM refresh
n request is generated. If on going cycle has finished, the refresh cycle starts.
Real refresh period depends on the period of HCLK.
AM [3] Address Matching Configuration Bit

0 BA-RAS-CAS
1 RAS-BA-CAS
APD [2] Reserved

0 Reserved for ChipTest. Must be written as “0”
PPD [1] Precharge Power-Down Mode

0 Disable precharge power-down mode
1 Enable precharge power-down mode
When sdram in precharge-idle state, CKE signal would be zero for power-
down. In this case, the redundant 1 cycle is needed to enter the active state.
SR [0] Self-Refresh Mode

0 Exit from the self-refresh mode
1 Enter the self-refresh mode
SDRAM FSM Status Register (SDFSM) 0xF0000004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 SDFSM[10:0]
This register is read only and represents current status of finite state machine in the SDRAM
controller. This can be used for test purpose only.
1-4
SDRAM Write Cycle (Non-sequential)
SDCLK
SDnCS
nRAS tDO
nCAS tRCD
XA RAS CAS0 CAS1
nWE
DQ DQ0 DQ1
DQM DQM0 DQM1
RAS WR WR Stop
Cmd Cmd Cmd Cmd
SDRAM Read Cycle (Row Actived)
SDCLK
SDnCS
nRAS
nCAS
nWE tCL
DQ DQ0 DQ2 DQ3
tCL
DQM
RD Stop
Cmd Cmd
SDRAM Precharge / Refresh Cycle
SDCLK
SDnCS
nRAS
nCAS tRP
nWE tRC
tRD
DQ Valid
PreC RFR SDRAM controller

Cmd Cmd goes to IDLE state
Figure 1.2 SDRAM Cycle Diagram
1-5
1.3 Miscellaneous Configuration
In this register, there is various special flag for TCC82xx system.
One of them is for supporting boot PROM. In initialization, the lower address space
(0x00000000 ~ 0x0FFFFFFF) is mapped to internal or external boot ROM but after initialization,
a kind of RAM must be mapped to these space as the system program including interrupt vector
table is located in this area. To satisfy this requirement, TCC82xx provide RM flag.
BM flag is used to select the boot procedure between the 7 kinds of them. Refer to chapter of
boot mode for details.
Miscellaneous Configuration Register (MCFG) 0xF0000008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 0 CSSTATE[5:0] 0 0 SDSTATE[5:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 XDM ERF 1 0 BM[2:0] SDW ENCK ECKE SDEN SDS *SBZ GPO RM
*) SBZ = Should Be Zero.
CSSTATE Type [29:24] CSx State

n Current State of Finite State Machine in Extrnal CSn
R
Momory Controller
SDSTATE Type [21:16] SDRAM State

n Current State of Finite State Machine in Extrnal SDRAM
R
Momory Controller
XDM [14] Data-Bus Output Mode

0 In idle state, the data bus would be in input-mode. (Default)
1 In idle state, the data bus would be in output mode.
ERF [13] Enable External Refresh Clock

0 Refresh cycles occurred by REFRESH COUNTER
1 Refresh cycles occurred by external refresh clock(PCLKCFG0)
SDW [7] SDRAM High-Frequency Wait

0 No additive wait cycle
1 Additive wait cycle
ENCK [6] SDRAM Gateing Clock Enable

0 SDRAM Clock Gating Disable
1 SDRAM Clock Gating Enable
ECKE [5] CKE Output Enable

0/1 ‘1’ for enabling the CKE output
1-6
SDEN [4] Master of Internal Memory Select

0 SDRAM controller is disabled
1 SDRAM controller is enabled
SDS [3] SD_CLK output select

0 SDRAM Clock is out from SD_CLK pin
1 GPO bit is out from SD_CLK pin
GPO [1] SD_CLK output

0/1 When SDS bit is high, this bit is out through SD_CLK pin
RM [0] Remap Flag

The area 0 (0x00000000 ~ 0x0FFFFFFF) space is mapped to internal /
0
external boot ROM
1 The area 0 space is released from boot ROM
In initialization, RM flag direct that the lower address space is mapped to internal or external boot
ROM. The boot program in internal or external ROM set RM flag high after going to address
space that is not in lower address space(0x00000000~0x0FFFFFFF). After RM flag is set to 1,
the lower address space is released from internal or external boot ROM, so the lower address
space can be mapped to other memories including SDRAM or internal SRAM by changing the
base address of that memories. The RM flag can be restored to 0 by user request, but because the
lower address space is remapped to boot ROM again, care must be taken not to illegally change
the RM flag.
1-7
1.4 External Memory Controller
External memory controller can control external memories such as NAND or NOR type flash
memory and ROM, SRAM type memory. These memories are selected by nCS3 ~ nCS0 pins.
The cycle parameter for accessing external memory can be configured by internal registers. In
case of NAND flash, additional parameters for address, command and data cycles can be
provided.
External Chip Select n Configuration Register (CSCFGn) 0xF0000010 + (n * 4)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OD WD BW[1:0] MTYPE[1:0] CSBASE[3:0] Reserved AMSK PSIZE[1:0] CADR[2]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CADR[1:0] STP[2:0] PW[7:0] HLD[2:0]
*) The reset value of each CSCFGn register means the following configuration for each chip select.
Chip Select 0 : 16bit, SRAM, Base = 0x40000000, tSTP=1, tPW=2, tHLD=1
Chip Select 1 : 16bit, IDE, Base = 0x50000000, tSTP=2, tPW=4, tHLD=2
Chip Select 2 : 16bit, NAND, Base = 0x60000000, AMSK=1, PSIZE=1, cLADR=3, tSTP=2, tPW=8, tHLD=2
Chip Select 3 : 16bit, NOR, Base = 0x70000000, tSTP=2, tPW=4, tHLD=2
OD [31] Delayed ‘OE’ Signal

0 Normal STP and HLD timing would be applied.
When STP and HLD are zero, 1 cycle would be added for delayed by
1
half-pulse for OE signal
WD [30] Delayed ‘WE’ Signal

0 Normal STP and HLD timing would be applied.
When STP and HLD are zero, 1 cycle would be added for delayed by
1
half-pulse for WE signal
BW[1:0] [29:28] Bus Width Select

0 Bus width = 16 bit
1 Bus width = 8 bit
3 Bus width = 8 bit
MTYPE[1:0] [27:26] Type of External Memory

0 NAND type
1 IDE type
SMEM_0 type (Ex : ROM, NOR flash)
2
Byte write control signal (DQM) is not needed.
SMEM_1 type (Ex : SRAM)
3
Byte write control signal (DQM) is needed.
CSBASE[3:0] [25:22] Chip Select n Base Address

M Indicates the MSB 4bit of nCS[n] area.
The base address of nCS[n] is set to M * 0x10000000.
1-8
AMSK [19] Address Mask Bit

0 Upper half of data bus is masked to zero.
*) In case of 16bit width NAND flash, the upper half byte must be held low, during address cycles. This bit
must be set to zero. But if the system uses multiple NAND flashes by sharing a chip select but separating each
data to 16 bit data bus of TCC82xx, the AMSK must be set to 1, so the address can be fed to each NAND
flashes.
PSIZE[1:0] [18:17] Page size of NAND Flash

The size of one page for NAND type flash.
psize It represents byte per page calculated by the following equation.
1 Page = 256 * 2psize
*) Refer to Table 1.3 about the relationship between the address generation and each page size configuration.
CADR[2:0] [16:14] Number of Address Cycles

The number of address command cycle for NAND type flash.
N
(N+1) cycle is used for generating address cycle command.
*) Refer to sub-register of NAND type memory for more information of PSIZE and CADR field.
STP[2:0] [13:11] Number of Cycle for Setup Time (tSH)

N N cycle is issued between the falling edge of nCS[n] and nOE / nWE.
PW[7:0] [10:3] Number of Cycle for Pulse Width

(tPW)
(N+1) cycle is issued between the falling and rising edge of nOE /
N ( = 0~31 )
nWE.
HLD[2:0] [2:0] Number of Cycle for Hold Time (tHLD)

N N cycle is issued between the rising edge of nOE / nWE and nCS[n].
1-9
The following figure displays the element cycle diagram for external memories.
SMEM_0 Type Cycle (Bus width >= Data width, URDY=0)
nCS
XA ADDR0 ADDR1
tPW
nOE
tSH tHLD tSH tHLD
tPW
nWE tH
DQ DQR DQW
SMEM_0 Type Cycle (Bus width < Data width, URDY=1, RDY=0)
tPW + tWait = tSH + tWait =

tPW 1 + tPW 2 + tWait tSH1 + tSH2 + tWait
nCS
XA ADDR0 ADDR1
tPW 1 tPW 2 tPW
nOE
tSH tHLD tSH1 tSH2 tHLD
tWait tWait
READY
tH
DQ DQRL DQRH
SMEM_1 Type Cycle (Bus width >= Data width, URDY=0)
nCS
XA ADDR0 ADDR1
tPW
nOE
tSH tHLD tSH tHLD
tPW
nWE tH
DQM1
DQM0
DQ[15:8] DQ1
DQ[7:0] DQ0
Figure 1.3 Basic Timing Diagram for External Memories
In case of IDE type memories, there are two chip-enable signals for it. In TCC82xx, each enable
signal can be controlled by offset address space. ‘nCS0’ reflects that the offset address range of 0
~ 0x1F is accessed, ‘nCS1’ reflects that 0x20 ~ 0x3F is accessed. For larger address than 0x3F, if
bit5 of address value means which enable signal is activated. (0 to ‘nCS0’, 1 to ‘nCS1’)
1-10
Memory Controller Clock Count Register (CLKCFG) 0xF0000020

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 SDCLKCNT[7:0]
SDCLKCNT Masked Period of SDCLK

N This determines the period of SDCLK masked.
If 0, the HCLK is out directly with same frequency.
SDRAM Command Register (SDCMD) 0xF0000024

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved A10
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
nCS nRAS nCAS nWE BA[1:0] A[9:0]
When this register is written, corresponding SDRAM signal is output to the SDRAM.
This is a write only register and read data is undefined. Any value written to this
register must be a valid SDRAM command (MRS or EMRS, etc). But, if you
changed the CAS latency in external SDRAM with this command, you should change
the CAS latency with corresponding cycles in this controller.
1-11
1.5 Sub-registers of NAND type memory
In case of NAND flash type memories, there are several sub-registers for generating command,
address, and data cycles.
Followings are these sub-registers. (M is base field of CSCFGn register)
Except the data register (NDDATA), the sub-register has implicit size of 16bit, so the bus-width
of CSCFGx register does not affect the cycle of command and address registers. It only affects
the cycle of data register.
Command Cycle Register (NDCMD) 0x10000000 * M

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDCMD3[7:0] NDCMD2[7:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDCMD1[7:0] NDCMD0[7:0]
*) If bus width of NAND flash is more than 8bit, the NDCMD1 ~ 3 may be used as command register,
otherwise only NDCMD0 is used as command register. The following values are an example commands for
NAND flash of SAMSUNG. Refer to corresponding datasheet of NAND flash chip for more detailed list of
command s.
0x00/0x01 : Page Read Command

0x80 : Page Program Command
0x60 : Block Erase Command
0x70 : Status Read Command (generated by reading from 0xM0000700 address)
Linear Address Cycle Register (NDLADR) 0x10000000 * M + 0x04

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDLADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDLADR[15:0]
*) By writing to this register, memory controller generates linear address cycle for NAND flash.
Row Address Cycle Register (NDRADR) 0x10000000 * M + 0x08

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDRADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDRADR[15:0]
*) By writing to this register, memory controller generates row address cycle for NAND flash.
Table 1.3 represents the relation between each cycle and address generation.
User must set this information appropriately to PSIZE and CADR field of CSCFGn register
ahead of accessing NAND data.
1-12
Table 1.3 Page size of NAND Flash

Address Generation
# of Cycle
PSIZE = 0 PSIZE = 1 PSIZE = 2 PSIZE = 3
st
1 ADR[7:0] ADR[7:0] ADR[7:0] ADR[7:0]
nd
2 ADR[15:8] ADR[16:9] ADR[10:8] ADR[11:8]
3rd ADR[23:16] ADR[24:17] ADR[18:11] ADR[19:12]
4th ADR[31:24] ADR[31:25] ADR[26:19] ADR[27:20]
th
5 - - ADR[31:27] ADR[31:28]
*) ADR means address value that is written to NDLADR or NDRADR register. The shaded cycles represent row
address cycles. That is, NAND address cycles start from there when NDRADR register is accessed.
Single Address Cycle Register (NDSADR) 0x10000000 * M + 0x0C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved NDSADR[7:0]
*) When CPU writes to this register, one cycle of address cycle is generated.
Data Register (NDDATA) 0x10000000 * M + 0x10

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NDDATA3[7:0] NDDATA2[7:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NDDATA1[7:0] NDDATA0[7:0]
*) NDDATA3~1 may be used as the value of data register, otherwise only NDDATA0 is used as
data register. It is dependant on the bus-width of CSCFGn register of NAND flash.
1-13
1.6 Internal Memory
In TCC82xx, there is 64Kbytes of SRAM for general purposes and 8Kbytes of ROM for system
initialization. SRAM area is dedicated to area 3 (0x30000000 ~ 0x3FFFFFFF), and also accessed
by area 0 (0x00000000 ~ 0x0FFFFFFF) when there are no devices assigned to area 0. ROM area
is dedicated to area E (0xE0000000 ~ 0xEFFFFFFF), and also accessed by area 0 (0x00000000
~ 0x0FFFFFFF) when RM flag of MCFG register is cleared to 0.
In case of internal ROM, access cycle can be extended by inserting 1 wait cycle. This wait cycle
is determined by writing any value to ROM area.
When writing to address of which the bit 2 is 1 (such as 0xE0000004, 0xE000000C,

0xE0000014, …) , the wait cycle is to be inserted from the next ROM access cycle. On the other
hand writing to address of which the bit 2 is 0 (such as 0xE0000000, 0xE0000008, 0xE0000010,
…), the wait cycle is to be removed from the next ROM access cycle.
1-14
1.7 DTCM
TCC82xx supports the 4k-bytes DTCM(Tightly-Coupled Data Memory). The DTCM is located
at address 0xA0000000 in the memory map. When out of reset, the behavior of DTCM is
controlled by the state of CP15 control register. You can enable the DTCM by setting bit 16 of
the CP15 control register.
The procedure for initializing the DTCM is as follows:
1. Set the DTCM base address 0xA0000000.

2. Set the DTCM enable bit .
A suggested assembler code sequence for this procedure is:
MRC p15, 0, r0, c9, c1, 0

ORR r0, r0, #0xA0000000
MCR p15, 0, r0, c9, c1, 0 ; base address setting
MRC p15, 0, r0, c1, c0, 0
ORR r0, r0, #0x00010000
MCR p15, 0, r0, c1, c0, 0 ; DTCM enable
1-15
DAI (Digital Audio Interface)
Multimedia Application Processor DAI
2 DAI
The block diagram of DAI is shown in Figure 2.1.
The TCC82xx provides digital audio interface that complies with IIS (Inter-IC Sound). The
DAI has five input/output pins for IIS interface; MCLK, BCLK, LRCK, DAI, DAO. All DAI
input/output pins are multiplexed with GPIO pins; GPIO_B<16:20>.
The MCLK is the system clock pin that is used for CODEC system clock. In master mode, the
MCLK can be generated from clock generator in which that is known as a DCLK, or fed from
the outside of chip in slave mode. The DAI can process 256fs, 384fs and 512fs as a system clock.
256fs means that the system clock has 256 times of sampling frequency (fs).
The BCLK is the serial bit clock for IIS data exchange. The DAI can generate 64fs, 48fs and
32fs by dividing a system clock. The polarity of BCLK can be programmed. That is, the serial
bit can be stable either rising edge of BCLK or falling edge of BCLK.
The LRCK is the frame clock for the stereo audio channel Left and Right. The frequency of
LRCK is known as the “fs” – sampling frequency. Generally, for audio application – such as
MP3 player , CD player, the fs can be set to 8kHz, 16kHz, 11.05kHz, 24kHz, 32kHz, 44.1kHz
and 48kHz. For supporting the wide range of sampling frequency in audio application, the
DCO function is very useful to generate a system clock. Refer the chapter of clock generator for
detail information.
All three clocks (MCLK, BCLK, LRCK) are selectable as master or slave.
The DAI, DAO are the serial data input output pins respectively.
The DAI has two 8-word input/output buffers. It has a banked buffer structure so that one side of
buffer is receiving/transmitting data while the other side of that can be read/written through the
DADI_XX/DADO_XX registers. The maximum data word size is 24 bit. Data is justified to
MSB of 32bits and zeros are padded to LSB.
There are 2 types of interrupt from IIS; transmit done interrupt, receive done interrupt. The
transmit-done interrupt is generated when the 8 words are transferred successfully in the output
buffer. At this interrupt, user should fill another 8 more words into the other part of the output
buffer in the interrupt service routine (ISR). In this ISR routine, 8 consecutive stores of word
data to the DADO registers are needed. The receive-done interrupt is generated when the 8 words
are received successfully in the input buffer. At this interrupt, user should read 8 received words
from the input buffer using 8 consecutive load instructions from the DADI registers.
2-1
Table 2.1 DAI Register Map (Base Address = 0x80000000)

DAMR 0x40 R/W 0x00000000 Digital Audio Mode Register
DAVC 0x44 R/W 0x0000 Digital Audio Volume Control Register
2-2
Digital Audio Mode Register (DAMR) 0x80000040

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
*R(Reserved) RXE RXS<1:0> TXS<1:0> *R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN TE RE MD SM BM FM *R BD<1:0> FD<1:0> BP *R MM LB
RXE [22] DAI RX Data Sign Extension

0 Disable (zero extension)
1 Enable (sign bit extension)
RXS[1:0] [21:20] DAI RX Shift

00 Bit-pack MSB and 24bit mode.
01 Bit-pack MSB and 16bit mode.
10 Bit-pack LSB and 24bit mode.
y RXE is the receive data sign extension bit as bit-pack LSB mode.
y If RXS[1:0] is 0, this function is equal to Telechips’ previous Digital Media Processors
(TCC72x, TCC76x series) and RXS[1:0] is 1, LSB 8bit of received data is masked. In case
of use LSB Bit-pack mode, user must set RXE register to 1.
TXS[1:0] [19:18] DAI TX Shift

0x Bit-pack MSB mode.
y If TXS[1:0] is 0, this function is equal to Telechips’ previous Digital Media Processors
(TCC72x, TCC76x series)
EN [15] DAI Master Enable

0 Disable DAI module
1 Enable DAI module
TE [14] DAI Transmitter Enable

0 Disable DAI transmitter
1 Enable DAI transmitter
RE [13] DAI Receiver Enable

0 Disable DAI receiver
1 Enable DAI receiver
MD [12] DAI Bus Mode

0 Set DAI bus as IIS bus mode
1 Set DAI bus as MSB justified mode
2-3
SM [11] DAI System Clock Master Select

0 Set that DAI system clock is come from external pin
1 Set that DAI system clock is generated by the clock generator block
y The DAI system clock in clock generator is known as DCLK. It’s frequency can be
determined by setting DCLKmode register.
BM [10] DAI Bit Clock Master Select

0 Set that DAI bit clock is come from external pin
1 Set that DAI bit clock is generated by dividing DAI system clock
FM [9] DAI Frame Clock Master Select

0 Set that DAI frame clock is come from external pin
1 Set that DAI frame clock is generated by dividing DAI bit clock
BD[1:0] [7:6] DAI Bit Clock Divider select

00 Select Div 4 ( 256fs->64fs )
01 Select Div 6 ( 384fs->64fs )
10 Select Div 8 ( 512fs->64fs, 384fs->48fs , 256fs->32fs)
11 Select Div16 ( 512fs->32fs )
FD[1:0] [5:4] DAI Frame Clock Divider select

00 Select Div 32 ( 32fs->fs )
y The combination of BD & FD determines that the ratio between main system clock and the
sampling frequency. The multiplication between the division factor of BD and FD must be
equal to this ratio.
BP [3] DAI Bit Clock Polarity

0 Set that data is captured at positive edge of bit clock
1 Set that data is captured at negative edge of bit clock
MM [1] DAI Monitor Mode

0 Disable DAI monitor mode
1 Enable DAI monitor mode. Transmitter should be enabled. (TE = 1)
LB [0] DAI Loop-back Mode

0 Disable DAI Loop back mode
1 Enable DAI Loop back mode
2-4
Digital Audio Volume Control Register (DAVC) 0x80000044

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved VC<4:0>
The volume of audio output can be manipulated by this register. It has –6dB unit so the output
volume can be set from 0 dB to –96 dB as the following table.
VC[4:0] [4:0] DAI Volume control

00000 0dB
00001 -6dB
00010 -12dB
00011 -18dB
00100 -24dB
00101 -30dB
00110 -36dB
00111 -42dB
01000 -48dB
01001 -54dB
01010 -60dB
01011 -66dB
01100 -72dB
01101 -78dB
01110 -84dB
01111 -90dB
10000 -96dB
2-5
Input Buffer
DADI_L0 LEFT0
DADI_R0 RIGHT0
S2P
DADI_L3 LEFT3 IIS_SDI
DADI_R3 RIGHT3 DAVC
LEFT4
RIGHT4
Input Buffer LB
Pointer MM
LEFT7
RIGHT7
IIS_SDO
Output Buffer
DADO_L0 LEFT0
DADO_R0 RIGHT0
DADO_L3 LEFT3
DADO_R3 RIGHT3
LEFT4
RIGHT4 P2S
Output Buffer
Pointer LEFT7
RIGHT7
DCO IIS_MCLK
SM
DIVIDER IIS_BCLK
BM
DIVIDER IIS_LRCK
FM
Figure 2.1 DAI Block Diagram
2-6
Left
LRCK Right
16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 16
BCLK
L M L M
DAI/O S S S S
B B B B
MD=0 (IIS mode), BP=0, BCLK = 32fs
Left
LRCK Right
32 31 30 29 28 27 10 9 8 7 6 5 4 3 2 1 32
BCLK
M L M
DAI/O S S S
B B B
MD=1(MSB justified mode), BP=0, BCLK=64fs
Left
LRCK Right
24 23 22 21 20 21 9 8 7 6 5 4 3 2 1
BCLK
M L M
DAI/O S S S
B B B
MD=1(MSB justified mode), BP=1, BCLK=48fs
Figure 2.2 DAI Bus Timing Diagram
2-7
UART
Multimedia Application Processor UART
3 UART
3.1 Overview
The TCC82xx has 2 UART modules (UART0, UART1) that can be used in programming
the system software, IrDA interfacing or high speed serial communication.
The UART has a automatic flow control for fast interface. In the UART, there are two
DMA requests (Rx/Tx DMA request) for each transmit and receiving data. It can be
operate with DMA without software burden. The block diagram of UART is in the Figure
3.1.
LSR
RTS
nRTS
Control
CR
Receiver Receiver RZ code

RXD
FIFO Shift Demod
DL
Transmit Transmit RZ code
TXD
FIFO Shift Modulator
Interrupt
IR IREQ
Generator
CTS
nCTS
Control
Figure 3.1 UART Block Diagram
3-1
Table 3.1 UART0 / UART1 Register Map

RBR 0x00 R Unknown Reciver Buffer Register(DLAB = 0)
THR 0x00 W 0x00 Transmitter Holding Register (DLAB=0)
DLL 0x00 R/W 0x00 Divisor Latch (LSB) (DLAB=1)
IER 0x04 R/W 0x00 Interrupt Enable Register (DLAB=0)
DLM 0x04 R/W 0x00 Divisor Latch (MSB) (DLAB=1)
IIR 0x08 R Unknown Interrupt Ident. Register (DLAB=0)
FCR 0x08 W 0xC0 FIFO Control Register (DLAB=1)
LCR 0x0C R/W 0x03 Line Control Register
MCR 0x10 R/W 0x40 MODEM Control Register
LSR 0x14 R Unknown Line Status Register
MSR 0x18 R Unknown MODEM Status Register
SCR 0x1C R/W 0x00 Scratch Register
AFT 0x20 R/W 0x00 AFC Trigger Level Register
UCR 0x24 R/W 0x00 UART Control Register
SRBR 0x40 R Unknown Rx Buffer Register
STHR 0x44 W 0x00 Transmitter Holding Register
SDLL 0x48 R/W 0x00 Divisor Latch (LSB)
SDLM 0x4C R/W 0x00 Divisor Latch (MSB)
SIER 0x50 R/W 0x00 Interrupt Enable Register
IRCFG 0x80 R/W 0x00 IRDA Configuration Register
3-2
Table 3.2 Summary of Register Ⅱ
0x00 0x04 0x08 0x0C 0x10 0x14
Dlab=0 Dlab=0 Dlab=0
B Rx Tx Interupt
Interrupt FiFo
i Buffer Holding Enable
Identity Control Line Modem Line
t Register Register Register
Register Register Control Control Status
(read (write Register Register Register
DLAB=1 DLAB=1
only) only
Divisor Divisor
Latch Latch
(LSB) (MSB)
THR IER
RBR IIR FCR LCR MCR LSR
/DLL /DLM
Enable
Interrupt FiFo Data
0 Bit0 Bit0 Rx Reserved
Pending Enable Word Ready
Data
Length
Enable Rx Request
Overrun
1 Bit1 Bit1 Tx FiFo To
Error
Holding Reset Send
Enable Tx
Interput Stop Parity
2 Bit2 Bit2 Rx FiFo Reserved
ID Bits Error
Line Reset
Enable DMA
Parity Framing
3 Bit3 Bit3 Modem Rx/Tx Reserved
Enable Error
Status Eanble
Tx Even Loop Break

4 Bit4 Bit4 0 0
Fifo Parity Back Interrupt
Trigger
Auto Tx
Level Stick
5 Bit5 Bit5 0 0 Flow Holding
(TXT) Parity
Control Register
RTS
FiFo Rx Break Tx
6 Bit6 Bit6 0 Start
Enabled Fifo Control Empty
Condition
Trigger
Divisor
FiFo Level
7 Bit7 Bit7 0 Latch 0 Error in Rx FiFo
Enabled (RXT)
Access
3-3
0x18 0x1C 0x20 0x24 0x40 0x44 0x48 0x4C 0x50 0x80
B
i AFC Tx
Modem UART Divisor Divisor Interupt IrDA
t Scratch Trigger Rx Buffer Holding
Status Control Latch Latch Enable Conf.
Register Level Register Register
Register Register (LSB) (MSB) Register Register
Register
MSR SCR AFT UCR SRBR STHR SDLL SDLM SIER IRCFG
Delta Tx Enable IrDA

0 Clear to Bit0 DMA Bit0 Bit0 Bit0 Bit0 Rx Tx
Send Enable Data Enable
Rx Enable IrDA
nRTS
1 Reserved Bit1 DMA Bit1 Bit1 Bit1 Bit1 Tx Rx
Deassert
Enable Holding Enable
Trigger
Tx Enable IrDA
Level
2 Reserved Bit2 Word Bit2 Bit2 Bit2 Bit2 Rx TXD
(DTL)
Access Line Polarity
Rx Enable IrDA
3 Reserved Bit3 Word Bit3 Bit3 Bit3 Bit3 Modem RXD
Access Status Polarity
Clear
4 To Bit4 Bit4 Bit4 Bit4 Bit4 0 0
Send
nRTS
5 Reserved Bit5 Bit5 Bit5 Bit5 Bit5 0 0
Assert
Trigger
Level
(ATL)
3-4
UART Receiver Buffer Register (RBR) 0x8000n000(DLAB=0) (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Received Data[7:0] (Read Only)
The RBR is a actually 16byte FiFo, a received data from external device is stored in the
RBR and CPU(or DMA) can read this register by Rx interrupt(or Rx DMA Request).
UART Transmitter Holding Register (THR) 0x8000n000(DLAB=0) (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Transmitting Data[7:0] (Write Only)
The THR is a actually 16byte FiFo . To transmitt data to external device, CPU(or DMA)
should write data to the THR.
UART Divisor Latch Register (DLL) 0x8000n000(DLAB=1) (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Divisor Latch LSB[7:0]
UART Divisor Latch Register (DLM) 0x8000n004(DLAB=1) (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Divisor Latch MSB
This is for generation of the desired baud rate clock. This register is set to 0 at reset,
UART is disabled until this register is set by non-zero value. The value can be calculated
as follows.
{DLM, DLL} = fUART / (16 * desired baud rate)
The UART clock is generated by clock generator block. It is recommended that the
frequency of UART clock is set to 3.6864MHz, so the desired baud rate can be
acquired by writing a value to DLL register as follows.
{DLM, DLL} = 230400 / (desired baud rate)
3-5
UART Interrupt Register (IER) 0x8000n004(DLAB=0) (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 EMSI ELSI ETXI ERXI
EMSI Type [3] Modem Status Interrupt Enable Bit

0 R/W Disable Modem status interrupt
1 R/W Enable Modem status interrupt
ELSI Type [2] Rx Line Status Interrupt Enable Bit

0 R/W Disable receiver line status interrupt
1 R/W Enable receiver line status interrupt
ETXI Type [1] Tx Holding register Empty Interrupt

Enable Bit
0 R/W Disable transmitter holding register empty intrrupt
1 R/W Enable transmitter holding register empty intrrupt
ERXI Type [0] Rx Data Available Interrupt Enable Bit

0 R/W Disable received data available interrupt
1 R/W Enable received data available interrupt
3-6
UART Interrupt Ident. Register (IIR) 0x8000n008 (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 IID[2:0] IPF
IID[2:0] Type [3:1] Interrupt ID

011 R Receiver line status
010 R Receved data available
110 R Character timeout indication
001 R Transmitter holding register empty
000 R MODEM status
IID[2:0] Type [3:1] Interrupt Source

011 R Overrun/parity error/framing error/break error
010 R Receiver data available or trigger level reached
110 R No characters have been removed from or input to the RX
FIFO during the last 4 char. Times and there is at least 1
char in it during this time.
001 R Transmitter holding register empty
000 R Clear to send data set ready or ring indicator or data carrier
detect
IID[2:0] Type [3:1] Interrupt Reset

011 R Reading the line status register
010 R Reading the receiver buffer register or the FIFO drops
below the trigger level
110 R Reading the receiver buffer register
001 R Reading the IIR register(if source of interrupt) or writing
into the transmitter holding register
000 R Reading the MODEM status register
IPF Type [0] Interrupt Flag

0 R Interrupt pending
1 R Interrupt has not generated
3-7
UART FIFO Control Register(FCR) 0x8000n008 (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 RXT[1:0] TXT[1:0] DRTE TXFR RXFR FE
RXT[1:0] Type [7:6] RX FIFO Trigger Level

00 W 1 Byte
01 W 4 Bytes
10 W 8 Bytes
11 W 14 Bytes
TXT[1:0] Type [5:4] TX FIFO Trigger Level

00 W Possible to Write 16 Byte (Empty)
01 W Possible to Write 8 Bytes
These bits are used to configure the writable amount at FIFO when the Tx interrupt or
DMA Tx request is generated.
DRTE Type [3] DMA Rx/Tx Enable

0 W DMA transfer is depend on RxDE or TxDE bits
1 W Enable both Rx & Tx DMA transfer (Regardless of RxDE
or TxDE status)
TXFR Type [2] TX FIFO Reset

1 W Reset TX FIFO counter and FIFO data
RXFR Type [1] RX FIFO Reset

1 W Reset RX FIFO counter and FIFO data
FE Type [0] FIFO Enable

1 W Enable TX and RX FIFOs.
3-8
UART Line Control Register(LCR) 0x8000n00C (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 DLAB SB SP EPS PEN STB WLS[1:0]
DLAB Type [7] Divisor Latch Access

1 R/W Access the divisor latches of the baud generator
0 R/W Access the receiver buff, the transmitter holding register, or
the interrupt enable register.
SB Type [6] Set Break

1 R/W The serial output is forced to the spacing(logic 0) state
0 R/W Disable the break
SP Type [5] Stick Parity

1 R/W When bits 3, 4 and 5 are logic 1 the parity bits is transmitted
and checked as a logic 0. If bits 3 and 5 are 1 and bit 4 is a
logic 0 then the parity bit is transmitted and checked as a
logic 1
0 R/W Disble stick parity
EPS Type [4] Even Parity Select

1 R/W Generate or check even parity
0 R/W Generate or check odd parity
PEN Type [3] Parity Enable

1 R/W A parity bit is generated(TX) or checked(RX)
STB Type [2] Number of Stop Bits

1 R/W One stop bit is generated in the transmitted data
0 R/W When 5-bit word length is selected, one and a half stop bits
are generated. When either a 6-, 7-, or 8-bit word length is
selected, two stop bits are generated.
WLS[1:0] Type [1:0] Word Length Select

00 R/W 5 bits
01 R/W 6 bits
11 R/W 7 bits
11 R/W 8 bits
3-9
UART Modem Control Register(MCR) 0x8000n010 (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 RS AFE LOOP 0 0 RTS 0
RS Type [6] RTS Deassert Condition Control Bit

0 R/W nRTS is de-asserted at the Rx Stop Condition
1 R/W nRTS is de-asserted at the Rx Start Condition (Reset value)
AFE Type [5] H/W Auto-Flow Control Enable Bit

0 R/W Disable Automatic Flow Control
1 R/W Enable Automatic Flow Control
LOOP Type [4] Loop Back

0 R/W Disable the local loop back feature
1 R/W Enable the local loop back feature
RTS Type [1] Request to Send(RTS)

0 R/W Set the nRTS line to high state
1 R/W Reset the nRTS line to low state
Table 3.3 UART1 Flow Control Configuration

AFE RTS Flow Control Configuration
1 1 Both nCTS and nRTS automatic flow control is activated
1 0 Only nCTS automatic flow control is activated
0 X Both nCTS and nRTS automatic flow control is de-activated
(Same as TCC77x series, only supprt for S/W Flow Control)
3-10
UART Line Status Register(LSR) 0x8000n014 (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 ERF TEMT THRE BI FE PE OE DR
ERF Type [7] Divisor Latch Access

1 R In the FIFO mode this bit is set when there is at least one
parity error, framing error or break indication in the FIFO
0 R In the 16450 mode
TEMT Type [6] Transmitter Empty

1 R Transmitter holding register and the transmitter shift register
are both empty
THRE Type [5] Transmitter Holding Register Empty

1 R UART is ready to accept a new char for transmission
BI Type [4] Break Interrupt

1 R The received data input is held in the spacing(logic 0) state
for longer than a full word transmission time
FE Type [3] Framing Error

1 R The received character did not have a valid stop bit
PE Type [2] Parity Error

1 The received data character does not have the correct even
or odd parity
OE Type [1] Overrun Error

1 R The receiver buffer register was not read by the CPU before
the next character was transferred into the receiver buffer
register.
DR Type [0] Data Ready

1 R The receiver data ready
3-11
UART Modem Status Register(MSR) 0x8000n018 (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 0 CTS 0 0 0 DCTS
CTS Type [4] Clear to Send

R Complement of the Clear to Send input port (nCTS)
DCTS Type [0] Delta Clear to Send

R The change of the Clear to Send input port (nCTS) indicator.
UART Scratch Register (SCR) 0x8000n01C (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Scratch Data[7:0]
This 8-bit Read/Write Register does not contol the UART in anyway. It is
inteded as a scratchpad register to be used by the programmer to hold
data temporarily.
UART AFC Trigger Level Register (AFT) 0x8000n020 (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 ATL[3:0] DTL[3:0]
ATL Type [3:0] nRTS Assert Trigger Level

N R/W nRTS assert trigger level
DTL Type [3:0] nRTS Deassert Trigger Level

N R/W nRTS de-assert trigger level
3-12
UART Control Register(UCR) 0x8000n024 (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 RWA TWA RxDE TxDE
RWA Type [3] Rx Word Access

0 R/W Rx FIFO access to byte
1 R/W Rx FIFO access to word (4 bytes)
TWA Type [2] Tx Word Access

0 R/W Tx FIFO access to byte
1 R/W Tx FIFO access to word (4 bytes)
RxDE Type [1] Rx DMA Enable

0 R/W Rx DMA disable
1 R/W Rx DMA enable
TxDE Type [0] Tx DMA Enable

0 R/W Tx DMA disable
1 R/W Tx DMA enable
3-13
UART Receiver Buffer Register (SRBR) 0x8000n040 (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Received Data (Read Only)
UART Transmitter Holding Register (STHR) 0x8000n044 (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Transmitting Data (Write Only)
UART Divisor Latch Register (SDLL) 0x8000n048 (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Divisor Latch LSB
UART Divisor Latch Register (SDLM) 0x8000n04C (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Divisor Latch MSB
UART Interrupt Register (SIER) 0x8000n050 (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 EMSI ELSI ETXI ERXI
SRBR, STHR, SDLL, SDLM, SIER registers are copy of the RBR, THR,
DLL, DLM, IER registers. These registers can be accessed without concern
of DLAB state.
IRDA Configuration Register (IRCFG) 0x8000n080 (n=6/5)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 RXP TXP RXE TXE
In IrDA Mode, each zero bit of TXD has a pulse width of 3/16 of a bit time.
RXP Type [3] RXD polarity

1 R/W Invert polarity of IrDA-RXD signal
TXP Type [2] TXD polarity
3-14
1 R/W Invert polarity of IrDA-TXD signal
RXE Type [1] Rx Enable

1 R/W Enable IrDA-Rx
TXE Type [0] TX Enable

1 R/W Enable IrDA-Tx
3-15
The following decriptions are the example of Rx/Tx operation with DMA and the H/W Auto Flow
Control scheme is applied. The nRTS/nCTS lantency should be considered and User should change
the register setting value to achive high-speed transferring data.
A. Example of Rx Operation with DMA and AFC(H/W)

UART Register Set Value
FE (FCR[0]) : FiFo Enable Bit = 1
AFE (MCR[4]): Auto Flow Control Enable Bit = 1
RxDE(UCR[1]: Rx DMA Enable bit = 1
DTL (AFT[3:0]) : nRTS Deassert Trigger Level = 12
ATL (AFT[7:4]) : nRTS Assert Trigger Level = 11
RXT (FCR[7:6]) : Rx Available FiFo Trigger Level = 8
DMA Register Set Value

TYPE(CHCTRL[9:8]) : H/W transfer with level sensitive = 2'b11
SYNC(CHCTRL[13]) : Syncronize External Request = 1
BSIZE(CHCTRL[7:6] : 8Read / 8Write = 2'b11 (depend on RXT)
10~ 17~
RXD line (byte) 1 2 3~7 8 9 16 20 21 22 23 24 STOP START 25
15 19
<*D>
nRTS
<*D>
<*E>
DMA Rx REQ
<*B>
<*C>
DMA reads Rx Data from
<*A> <*A> <*F>
Rx FiFo (each 8bytes)
Valid Data Level in

1 2 3~7 8 1 2~7 8 9~11 12 13 14 15 16 8 0 1
Rx FiFo
Figure 3.2 Example of Rx Operation with DMA and AFC(H/W)
<*A> : DMA Rx Request is asserted by RXT
<*B> : DMA detects Rx Request but DMA can't transfer data ( Other master higer than DMA occupies the bus )
<*C> : nRTS is reached by DTL
<*D> : The nRTS latency is delay. The nRTS latency should be considered. if not, overrun error will occur
<*E> : nRTS is asserted by ATL

<*F> : DMA Rx Request is Deasserted By RxT
B. Example of Tx Operation with DMA and AFC(H/W)

UART Register Set Value
3-16
FE (FCR[0]) : FiFo Enable Bit = 1

TxDE(UCR[0] : Tx DMA Enable bit = 1
TXT (FCR[5:4]) : Tx FiFo Trigger Level = 8
DMA Register Set Value

TYPE(CHCTRL[9:8]) : H/W transfer with level sensitive = 2'b11
SYNC(CHCTRL[13]) : Syncronize External Request = 1
BSIZE(CHCTRL[7:6] : 8Read / 8Write = 2'b11 (depend on TXT)
Figure 3.3 Example of Tx Operation with DMA and AFC(H/W)
<*A> : DMA Tx Request is asserted by TXT
<*B> : DMA Tx Request is deasserted by TXT
<*C> : nCTS asserted by External UART, Internal UART wait until nCTS is deasserted.
<*D> : nCTS de-asserted by External UART, Internal UART restart data transfering.
3-17
SPIMS (Serial Peripheral Interface
Master/Slave)
Multimedia Application Processor SPI MASTER/SLAVE
4 SPI MASTER/SLAVE
4.1 Overview
The previous SPI of our products functions as slave only and has only two
frame format of four ones which is compatible with Motorola SPI. Our GSIO
also supports only two frame format of Motorola SPI four ones aand has no
FIFO.
Therfore we added following features to supplement our SPI master/slave.
1) Supports four frame format of Motorola SPI. It is differentiated by SCK

Polarity and Phase shift. Refer to Figure 4.1 and Figure 4.2
Figure 4.1 frame format when CPH = 1
Figure 4.2 frame format when CPH = 0
2) Master and Slave cant be switched by user and occupy FIFOs

indivisually.
3) Up to 256 bytes, data can be transferred continuously. Previous SPI

separated data into 4 bytes and should disable /SS after transfering 4 byte-
data.
4-1
Figure 4.3 SPI Block Diagram
Table 4.1 GSIO/SPIS Register Map (Base Address = 0x90003000)

SDO 0x00 R/W 0x0000 SPI Output Data Register
SDI 0x04 R 0x0000 SPI Input Data Register
SBCR 0x08 R/W 0x0000 SPI Base Clock Register
SCR 0x0C R/W 0x0000 SPI Control Register
SPCTRL 0x10 R/W 0x0000 SPI Interrupt Control Register
SPSTS 0x14 R 0x0000 SPI Interrupt Status Register
4-2
SPI Output Data Register (SDO) 0x90003000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDO[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDO[15:0]
SPI Input Data Register (SDI) 0x90003004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SDI[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SDI[15:0]
SPI Base Clock Register (SBCR) 0x90003008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved DIV[6:0]
Base clock = SPI clock / (DIV + 1)
4-3
SPI Control Register (SCR) 0x9000300C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN M/S CPL CPH M/L TOE EDN CON FRM_LEN
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved FX FP CRF CTF FRM1 FRM2
EN [31] SPI Enable

1 Enable SPI
0 Disalbe SPI
M/S [30] Select Master/Slave

1 SPI works as Master
0 SPI works as Slave
CPL [29] SCK Polarity

1 Starts transfer a half SCK later after /SS is low
0 Starts transfer as soon as /SS is low
CPH [28] SCK Phase

1 Starts transfer a half SCK later after /SS is low
0 Starts transfer as soon as /SS is low
MLB [27] MSB/LSB

1 Send MSB firstly
0 Send LSB firstly
TOE [26] TDO Enable

1 TDO is enabled or disabled depending on asserting or
disasserting of /SS.
0 TDO is always disabled.
END [25] Select Endian

1 Big Endian transfer mode
0 Little Endian transfer mode
* Endian you selected is applied to Rx/Tx at the same
CON [24] Continuous Transfer Mode

1 Run in the continuous transfer mode
0 Run in the single transfer mode
* If you want to run SPI under continuous mode, you should make CPH to
be ‘1’ and FRM_LENGTH[2] to be ‘1’.
FRM_LENGTH [23:16] Frame Length

0 ~ 255 Length of one frame to transfer (1 ~ 256 bytes)
FX [13] Frame Signal Extension
4-4
1 Extends head and tail of FRM signal by one cycle of SCK

0 Don’t extend FRM signal
* FX should be ‘0’ when CPH=0.
FP [12] Frame Pulse Polarity

1 FRM has high active pulse
0 FRM has low active pulse
CRF [11] Clear Rx FIFO

1 Empties Rx FIFO
0 Don’t empty Rx FIFO
CTF [10] Clear Tx FIFO

1 Empties Tx FIFO
0 Don’t empty Tx FIFO
FRM1 [9:5] Frame Pulse Start Position

N Frame pulse starts after n base clock has generated
FRM2 [4:0] Frame Pulse End Position

N Frame pulse ends after n base clock has generated
4-5
SPI Interrupt Control Register (SPCTRL) 0x90003010

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RxCnt RCFulEnREmpEnRFulEnROREnRUREn TxCnt TCEmpEnTEmpEnTFulEnTOREnTUREn
RxCnt [15:13] Rx FIFO Threshold Level

1~8 Sets threshold level of Rx FIFO to notify how many data it
is filled with.
RCFulEn [12] Rx FIFO Count Full Interrupt Enable

1/0 Enables / Disables Rx FIFO count full interrupt
REmpEn [11] Rx FIFO Empty Interrupt Enable

1/0 Enables / Disables Rx FIFO empty interrupt
RFulEn [10] Rx FIFO Full Interrupt Enable

1/0 Enables / Disables Rx FIFO full interrupt
ROREn [9] Rx FIFO Overrun Error Interrupt Enable

1/0 Enables / Disables Rx FIFO overrun error interrupt
RUREn [8] Rx FIFO Underrun Error Interrupt Enable

1/0 Enables / Disables Rx FIFO underrun error interrupt
TxCnt [7:5] Tx FIFO Threshold Level

1~8 Sets threshold level of Tx FIFO to notify how much room is
available.
TCEmpEn [4] Tx FIFO Count Empty Interrupt Enable

1/0 Enables / Disables Tx FIFO count empty interrupt
TEmpEn [3] Tx FIFO Empty Interrupt Enable

0/1 Tx FIFO overrun error status flag (read only)
TFulEn [2] Tx FIFO Full Interrupt Enable

1/0 Enables / Disables Tx FIFO full interrupt
TOREn [1] Tx FIFO Overrun Error Interrupt Enable

1/0 Enables / Disables Tx FIFO overrun error interrupt
TUREn [0] Tx FIFO Underrun Error Interrupt Enable

1/0 Enables / Disables Tx FIFO underrun error interrupt
4-6
SPI Interrupt Status Register (SPSTS) 0x90003014

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved RCFul REmp RFul ROR RUR Reserved TCEmp TEmp TFul TOR TUR
* After you read this status register, it will be cleared
RCFul [12] Rx FIFO Count Full

1/0 Rx FIFO count full status flag (read only)
REmp [11] Rx FIFO Empty

1/0 Rx FIFO empty status flag (read only)
RFul [10] Rx FIFO Full

1/0 Rx FIFO full status flag (read only)
ROR [9] Rx FIFO Overrun Error

1/0 Rx FIFO overrun error status flag (read only)
RUR [8] Rx FIFO Underrun Error

1/0 Rx FIFO underrun error status flag (read only)
TCEmp [4] Tx FIFO Count Empty

1/0 Tx FIFO count empty status flag (read only)
Temp [3] Tx FIFO Empty

0/1 Tx FIFO empty status flag (read only)
TFul [2] Tx FIFO Full

1/0 Tx FIFO full status flag (read only)
TOR [1] Tx FIFO Overrun Error

1/0 Tx FIFO overrun error status flag (read only)
TUR [0] Tx FIFO Underrun Error

1/0 Rx FIFO underrun error status flag (read only)
4-7
I2C Controller
Multimedia Application Processor I2C CONTROLLER
5 I2C CONTROLLER
5.1 Functional Description
I2CCLK from Clock Controller
Prescale
Register Clock
Generator
Command
Register
Byte SCL
Command
Controller
Bit
APB
Status Command
Register Controller
SDA
Transmit
Register
DataI/O
Shift
Register
Receive
Register
Figure 5.1 I2C Block Diagram
5.2 Related Blocks
After the signals are enabled, I2CCLK (the main clock of I2C) must be enabled and configured to the proper
frequency. Refer to section “CLOCK GENERATOR” for I2CCLK (EX2CLK) related descriptions.
For internal synchronization, the APB clock frequency must be faster than the I2CCLK frequency.
fI2CLK ≤ fHCLK / 4.0
5-1
Table 5.1 I2C Register Map (Base Address = 0x80008000)

PRES 0x00 R/W 0xFFFF Clock Prescale register
CTRL 0x04 R/W 0x0000 Control Register
TXR 0x08 W 0x0000 Transmit Register
CMD 0x0C W 0x0000 Command Register
RXR 0x10 R 0x0000 Receive Register
SR 0x14 R 0x0000 Status Register
5-2
Prescale Register (PRES) 0x80008000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Clock Prescale data[15:0]
This register is used to prescale the SCL clock line. Change the value of the prescale register
only when ‘EN’ bit is cleared.
CLK Input frequency / (Prescale*5) = Desired SCL frequency
Control Register (CTRL) 0x80008004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 EN IEN MOD Reserved
EN [7] I2C Core enable bit

0 Disabled
1 Enabled
IEN [6] I2C Core interrupt enable bit

0 Disabled
1 Enabled
MOD [5] I2C Data Width

0 8bit Mode
1 16bit Mode
Transmit Register (TXR) 0x80008008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Transmit Data[15:0]
When CTRL[5] is set, in case of 16Bit Mode is selected, Transmit Data bit width become 16 bit. Default mode is
8bit mode.
5-3
Command Register (CMD) 0x8000800C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 STA STO RD WR ACK Reserved IACK
STO [7] Start Condition Generation

0 Disabled
1 Enabled
STO [6] Stop Condition Generation.

0 Disabled
1 Enabled
RD [5] Read From Slave

0 Disabled
1 Enabled
WR [4] Write to Slave

WR Write to Slave
0 Disabled
1 Enabled
ACK [3] Sent ACK

ACK Sent ACK
0 Enabled
1 Disabled
IACK [0] Interrupt Acknowledge

0 -
1 Clear a pending interrupt
Receive Register (RXR) 0x80008010

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Receive Data[15:0]
When CTRL[5] is set, in case of 16Bit Mode is selected, Transmit Data bit width become 16 bit. Default mode is
8bit mode.
5-4
Status Register (SR) 0x80008014

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 RxACK BUSY AL 0 0 0 TIP IF
RxACK [7] Received acknowledge from slave

1 No Acknowledge received
0 Acknowledge received
BUSY [6] I2C Bus Busy

0 ‘0’ after STOP signal detected
1 ‘1’ after START signal detected
AL [5] Arbitration lost

0 The core don’t lost arbitration
1 The core lost arbitration
Arbitration is lost when :
a STOP signal is detected, but non requested
the master drives SDA high, but SDA is low
TIP [1] Transfer in progress

0 Transfer Complete
1 Data Transfer
IF [0] Interrupt Flag

0 -
1 Interrupt is pending
5-5
ECC (Error Correction Code)
Multimedia Application Processor ECC (ERROR CORRECTION CODE)
6 ECC (Error Correction Code)
6.1 Functional Description
The ECC (Error Correction Code) is used to correct data error in storage device or various kind of
communicating system. The TCC82xx has simple ECC generation and Error Correction Module. By
enable ECC module, it consistently monitors internal bus activity and calculate ECC whenever there is
read or write cycle from/to a predefined memory area. The area can be determined by special register
so this module can be used ECC calculation itself not only for specific storage device such as NAND
flash.
The following figure represents block diagram including internal bus connection for ECC module.
DATA
HTRANS
HWRITE
Error DATA
SLC ECC CORE
HADDR
Error ADDR - ERROR DETECTION
HWDATA
- ERROR CORRECTION
Error NUM
HRDATA
HREADY
HRESP ECC CONTROLLER
PSELecc
PENABLE ENCODE/
DECODE
PWRITE
DATA
ECC
PADDR
CONTROLLER
CONTROL
Error DATA
MLC ECC4 CORE
SIGNAL
PWDATA - ERROR DETECTION
PRDATA
Error ADDR - ERROR CORRECTION
Error NUM
PREADY APB I/F
FIFO CONTROL SIGNAL
INTERRUPT
To Interrup REQUEST FIFO
Controller
(16x32)
To DMA
DMA
REQUEST ECC
Figure 6.1 ECC Block Diagram
6-1

Table 6.1 ECC Register Map (Base Address = 0x80009000)
ECC_CTRL 0x00 R/W 0x00000000 ECC Control Register

ECC_BASE 0x04 R/W 0x00000000 Base Address for ECC Calculation
ECC_MASK 0x08 R/W 0x00000000 Address mask for ECC area.
ECC_CLR 0x0C W - Clear ECC output register
SLC_ECC0 0x10 R 0x00000000 1st Block ECC output for SLC NAND
SLC_ECC1 0x14 R 0x00000000 2nd Block ECC output for SLC NAND
SLC_ECC2 0x18 R 0x00000000 3rd Block ECC output for SLC NAND

CORR_START 0x4C W - MLC ECC4 Correction Start Register

ERRADDR3 0x5C R 0x00000000 MLC ECC4 Error Address Register3
ERRDATA3 0x6C R 0x00000000 MLC ECC4 Error Data Register3
ERR_NUM 0x70 R 0x00000004 MLC ECC4 Error Number Register
6-2
ECC Control Register (ECC_CTRL) 0x80009000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 DEN ENC FLG IEN 0 MN ECC_WCNT[9:4]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC_WCNT[3:0] 0 HOLD M4EN ZERO SBZ SLC_BCNT[2:0] SEN
DEN [28] ECC DMA Request Enable

0 ECC DMA Request Disable
1 ECC DMA Request Enable
*)For ECC DMA Request Enable, DMA Transfer Type must be Single Transfer with Level Sensitive
Detection.
When this register is writing ‘1’, data transfer is started. That is, DMA transfer is started.
You must set EN flag of DMA_CHCTRL register first, and then writing ‘1’ to DEN of ECC_CTRL
ENC [27] MLC ECC ENCODE/DECODE Selection

0 Decoding Calculation for MLC ECC3/4
1 Encoding Calculation for MLC ECC3/4
*)For MLC ECC3/4, this bit field must be setted according as data transfer is encoding because ECC
geneation algorithm is the difference between encode and decode.
FLG [26] MLC ECC Flag

1 Read ECC evaluation is Finished. (for MLC ECC3/4)
1 Write Flag bit Clear. (for MLC ECC3)
1 Write Interrupt Request and Flag Clear. (for MLC ECC4)
*)If MLC ECC3/4 evaluation operation is finished, ecc flag bit is setted. After checking these flags, user can
clear FLG bit of ECC_CTRL register by writing “1”.
IEN [25] MLC ECC4 evaluation Interrupt Enable

0 MLC ECC4 Evlauation Interrupt Disable
1 MLC ECC4 Evaluation Interrupt Enable
*)It is possible only to detect data erro in case of MLC ECC3, but to detect and correct data error in case of MLC ECC4.
If ECC source data byte size is 512 byte, it take 512 clock cycle to MLC ECC4 data correction, therefore MLC ECC4
evaluation interrupt is only existed. After MLC ECC4 evaluation interrupt, ERR_NUM register can be used to
detect data error, and it is able to correct data error by ERRADDRx/ERRDATAx.
If IEN bit of ECC_CTRL register is set and MLC ecc4 evaluation operation is finished, ECC interrupt is
really generated and user can clear interrupt request register by writing “1” into FLG field.
MN [22] Manual Correction Start Enable

0 Manual Correction Start Disable
1 Manual Correction Start Enable
WCNT[9:0] [21:12] ECC Count

For SLC, Word Data Count.
N(0~527, 0~512)
For MLC ECC3/4, Byte Data Count
HD [7] ECC Hold

1 Hold Enabled. ECC output register is not changed.
6-3
M4EN [6] MLC ECC4 Enable

0 MLC ECC4 Disable
1 MLC ECC4 Enable
ZERO [5] ECC Zero

Means that ECC output register (SLC & MLC_ECC0R &
1
MLC_ECC1R & MLC_ECC2R for MLC) contains 0.
SBZ [4] Should be Zero

0 Should Be Zero.
SLC_CNT[2:0] [3:1] SLC ECC Block Count

Means that N numbers of ECC block (256 bytes) are calculated.
This is useful to determine how many ECC output registers are valid.
N (0 ~ 7)
That is, N number of ECC output register counting from SLC_ECC0 are
valid.
SEN [0] SLC ECC Enable

1 Enable ECC for SLC
0 Disable ECC of SLC
6-4
ECC Base Address Register (ECC_BASE) 0x80009004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ECC_BASE[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC_BASE[15:2] 0
ECC Address Mask Register (ECC_MASK) 0x80009008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 ECC_MASK[27:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ECC_MASK[15:2] 0
*)The ECC is calculated whenever the specified region of memory is accessed. The region for ECC
calculating is determined by ECC_BASE & ECC_MASK register. The real base address is
determined by following formula.
Real base address = ECC_BASE(0x80009004) & ~(ECC_MASK[27:2] << 2)
(The real base address is assumed to be word aligned, so the least 2 bits are always 0.)
The size of region is also determined by ECC_MASK register. If ECC_MASK register have N
concatenated 0 from LSB, the region size is set to 2N bytes.
ECC Clear Register (ECC_CLR) 0x8000900C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Don’t care
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Don’t care
*)Whenever this register is written by any value, all ECC output registers are cleared to 0.
6-5
ECC Output Register for SLC (SLC_ECCn) 0x80009010 + n*4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 SLC_ECCn_0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SLC_ECCn_1 SLC_ECCn_2
*)These registers contain ECC output for SLC. It calculates ECC of SSFDC standard, and can
contain up to 8 blocks of data.
For each output register, there are a total of 22 bits of parity data (6 bits for column parity and 16
bits for line parity) as follows:
P1, P1’, P2, P2’, P4, P4’, P8, P8’, P16, P16’, ……, P1024, P1024’
The parity data that have been generated are stored as follows.
Bit7 Bit6 Bit5 Bit4 Bit3 Bit2 Bit1 Bit0

SLC_ECC0_0 P64 P64’ P32 P32’ P16 P16’ P8 P8’
SLC_ECC0_1 P1024 P1024’ P512 P512’ P256 P256’ P128 P128’
SLC_ECC0_2 P4 P4’ P2 P2’ P1 P1’ 1 1
*)To correct error for SLC ECC, writing original ECC data that read from nand flash to
SLC_ECCx register.
6-6
ECC Evaluation Register for MLC (MLC_ECC0W) 0x80009030

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 MLC_ECC[23:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MLC_ECC[15:00]

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MLC_ECC[47:32]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MLC_ECC[31:16]

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MLC_ECC[79:64]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MLC_ECC[63:48]
To evaluate ECC for MLC, write acquired ECC to these registers for MLC ECC
Decoding Calculation. The order of writing should be LSB first and then MSB.
For MLC ECC, write acquired ECC to MLC_ECC0W, MLC_ECC1W, MLC_ECC2W.

After writing to MLC_ECC2W for MLC ECC, ECC module starts evaluation.
After finishing evaluation, user can determine whether ECC error occurred or not by
checking Zero flag of ECC_CTRL register or checking MLC_ECC0R & MLC_ECC1R
registers.
If ECC Error occurred, User Can Correct Error by writing any value to CORR_START
and Reading ERRDATA/ERRADDR register.
6-7
ECC Output Register for MLC (MLC_ECC0R) 0x80009040

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 MLC_ECC[23:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MLC_ECC[15:0]

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MLC_ECC[47:32]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MLC_ECC[31:16]

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
MLC_ECC[79:64]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MLC_ECC[63:48]
MLC ECC4 Error Correction Register (CORR_START) 0x8000900C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Don’t care
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Don’t care
Whenever this register is written by any value, MLC ECC4 Correction Module is started.
6-8
MLC ECC4 Error Address Register (ERRADDR0) 0x80009050

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 ERRADDR0[13:0]
For SLC ECC, Error Byte Address = ERRADDR0[13:3], Error Bit Address[2:0].
For MLC ECC4, Error Address = Byte Data Size – ERRADDR[9:0] – 1 + 8
MLC ECC4 Error Address Register (ERRADDRn, n=1,2,3) 0x80009050 + (n*4)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 ERRADDRn[9:0]
Error Address = Byte Data Size – ERRADDR[9:0] – 1 + 8.
MLC ECC4 Error Data Register (ERRDATAn, n=0,1,2,3) 0x80009060 + (n*4)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 ERRDATAn[9:0]
Correction Data = Error Data[9:0] ^ ERRDATA.
MLC ECC4 Error Number Register (ERRNUM) 0x80009070

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 ERRNUM[2:0]
ERRNUM ECC4 Error Number

[3:0] SLC ECC MLC ECC4
000 Correctable Error 1 Error Occurred
001 Reserved 2 Error Occurred
100 No Error No Error
111 Correction Impossible Correction Impossible
6-9
[ECC_BADDR]
[ECC_MASK]
- Address region of the calculated ECC source data setting
SLC ECC ENABLE
Data Transfer
SLC ECC DISABLE
- For Transfer data size < 256x(n),

SLC_ECCx READ
: SLC_ECC0 ~ SLC_ECCn is useful.
n Time Repeat
CALCULATED ECC
DATA WRITE
[ECC_CLR]
- SLC ECC Clear
SLC ECC
ENCODING
COMPLETE
A) SLC ECC Encoding Flow Chart
EXTERNAL NAND DATA[15:0] ND_DATA ND_DATA ... ND_DATA ND_DATA ECC ECC
Must be setting Data transfer by DMA/ARM Must be clear SLC ECC RESULT
SEN bit field SEN bit field that read from SLC_ECCx.
AHB BUS xxxxxxxx DATA DATA ... DATA DATA xxxxxxxx SLC_ECC0 SLC_ECCx SLC_ECCn xxxxxxxxxxxxxxxxxxxxxxxx
ECC STATE ST_IDLE ST_SLC_ECC_ENCODE ST_IDLE

Cn READ
C0 READ
Cx READ
SLC_ECC EN
SLC_EC
SLC_EC
SLC_EC
SLC ECC DATA[31:0] xxxxxxxxx DATA DATA DATA DATA DATA xxxxx xxxxxxxx xxxxxxx
ECC Calculation Source DATA
SLC ECC RESULT191:0] xxxxxxxxxxxxxxxxx Calculated ECC Result[191:0]
B) SLC ECC Encoding Timing Diagram
Figure 6.2 Example of SLC ECC Encoding
6-10
[ECC_BADDR]
[ECC_MASK]
SLC ECC ENABLE
Data Transfer
SLC ECC DISABLE
ORIGINAL ECC READ

FORM MEMORY
- For Transfer data size < 256x(n),

SLC_ECCx WRITE
: SLC_ECC0 ~ SLC_ECCn is useful.
n Time Repeat
- ERR_NUM READ
ERROR : 000 = Correctable Error(1 Bit Error)
DETECTION : 100 = No Error
: 111 = Correction Impossible
FOR ERR_NUM = 000. - ERR_ADDR1 READ

ERROR : ERR_ADDR1[13:3] = Byte Address
CORRECTION : ERR_ADDR1[03:0] = Bit Address
[ECC_CLR]
- SLC ECC Clear
SLC ECC
DECODING
COMPLETE
A) SLC ECC Decoding Flow Chart
EXTERNAL NAND DATA[15:0] ND_DATA ND_DATA ... ND_DATA ND_DATA SLC_ECCx SLC_ECCx
Must be setting Data transfer by DMA/ARM Must be clear Original SLC_ECC[191:0]

SEN bit field M4EN bit field that read from memory.
AHB BUS xxxxxxxx DATA DATA ... DATA DATA xxxxxxxx SLC_ECC0 xxx SLC_ECCx xxx SLC_ECCn xxx xxxxxxxxxxxxxxxxxxxxxxxx
ECC STATE ST_IDLE ST_SLC_ECC_ENCODE ST_SLC_ECC_EVA ST_IDLE
MLC_ECC3 EN
MLC ECC DATA[9:0] xxxxxxxxx DATA DATA DATA DATA DATA
ECC Calculation Source DATA
MLC ECC4 RESULT[79:0] xxxxxxxxxxxxxxxxx Calculated ECC Result[191:0]
ERRNUM ERRNUM ERRNUM

ERR_NUM[2:0] xxxxxxxxxxxxxxxxx
Of SLC_ECC0 Of SLC_ECCx Of SLC_ECCn
ERRADDRx[13:0] ERRADDRx[13:0] ERRADDRx[13:0]

ERRADDR0[13:0] xxxxxxxxxxxxxxxxx
Of SLC_ECC0 Of SLC_ECCx Of SLC_ECCn
B) SLC ECC Decoding Timing Diagram
Figure 6.3 Example of SLC ECC Decoding
6-11
AD
AD
AD
CR0 RE
CR1 RE
CR2 RE
MLC_EC
MLC_EC
MLC_EC
Figure 6.4 Example of MLC ECC4 Encoding
6-12
[ECC_BADDR]
[ECC_MASK]
[ECC_CTRL]
- DECODE setting
MLC ECC4 ENABLE
- EN Flag of [DMA_CHCTRL] setting

=> DEN of [ECC_CTRL] setting
Data Transfer
ORIGINAL ECC READ - For Transfer data size =< 512 Byte ,
FORM MEMORY : x = {0,1,2}.
3 Time Repeat
MLC_ECCWx WRITE
MLC ECC4 DISABLE

[ECC_CTRL]
- DEN Disable setting
- ERR_NUM READ
ERROR
DETECTION
: 000 = 1 Error Occurred.(ERRADDR1/ERRDATA1)
: 001 = 2 Error Occurred.(ERRADDR1~2/ERRDATA1~2)
Error Occurred. : 100 = No Error
: 111 = Correction Imposible.
ERROR
CORRECTION
- ERROR ADDRESS : Byte Size of Transfer Data ERRADDRx 1+8
No Error. - CORRECT DATA : Error Data in Error Address ^ ERRDATAx
[ECC_CLR]
- MLC ECC3 Clear
MLC ECC4
DECODING
COMPLETE
A) MLC ECC4 Decoding Flow Chart
EXTERNAL NAND DATA[15:0] ND_DATA ND_DATA ... ND_DATA ND_DATA ECC ECC
Must be setting Data transfer by DMA/ARM Original MLC_ECCR[79:0] Must be clear

M4EN/ENC bit field that read from memory. M4EN bit field
AHB BUS xxxxxxxx DATA DATA ... DATA DATA xxxxxxxx ECC[23:0] ECC[47:16] ECC[79:48] xxxxxxxxxxxxxxxxxxxxxxxx
ECC STATE ST_IDLE ST_MLC_ECC4_DECODE ST_MLC_ECC4_EVA ST_IDLE
MLC_ECC3 EN
MLC ECC DATA[9:0] xxxxxxxxx DATA DATA DATA DATA DATA xxxxxxxx xxxxxxxx xxxxxxxx xxxx DATA ... DATA xxxxxxxxxxxxxx
ECC Calculation Source DATA Original ECC Result[59:0]

512 Byte Data Size
ECC Evaluation Start
ORIGINAL ECC RESULT[79:0] xxxxxxxxxxxxxxxxx ECC[23:0] ECC[47:0] ECC[79:0]
MLC ECC4 RESULT[79:0] xxxxxxxxxxxxxxxxx Calculated ECC Result[79:0]
ERR_NUM[2:0] xxxxxxxxxxxxxxxxx ERR_NUM
ERRADDRx[9:0] xxxxxxxxxxxxxxxxx ERRADDRx
ERRDARA[9:0] xxxxxxxxxxxxxxxxx ERRDATAx
B) MLC ECC4 Decoding Timing Diagram
Figure 6.5 Example of MLC ECC4 Decoding
6-13
USB Controller
Multimedia Application Processor USB CONTROLLER
7 USB CONTROLLER
7.1 Overview
The TCC82xx USB Controller consists of 3 kind of blocks such as USB 2.0 D LINK,
USB 2 PHY and USB Interface
The USB Interface connects a USB Device Controller to a USB system
USB 2.0 DEVICE
DP
UTMI Signal
DM From LINK To PHY
ATEST
REXT
USB 2 PHY USB 2.0 LINK
RKELVIN
XI
UTMI Signal
XO From PHY To LINK
MCU Interface :
- MCU CLK,
- MCU ADDR
PHY Control signal
- MCU CSN
(Oscillator and PLL
- MCU WRN
External signals)
- MCU RDN
- MCU WDATA
- MCU RDATA
USB IF
AHB Bus
Figure 7.1 USB 2.0 Device Block Diagram
7-1
7.2 USB Physical Layer (USB PHY)
The USB PHY consists of two basic block components: the common block and the
transceiver block. The common block contains design components that can be reused in
multiple transceivers, such as the phase-locked loop and the bias circuitry. The transceiver
block contains the bulk of the USB PHY circuitry.
USB PHY port has three distinct external interfaces:

USB Data Plus (D+) and Data Minus (D-) lines: these lines are USB1.1 and 2.0
specification-compliant. The USB PHY supports high-speed 480-Mbps transfers, as
well as USB2.2 full-speed and low-speed transfers through the USB
USB 2.0 Transceiver Macrocell Interface (UTMI): the USB PHY supports the
following modes through the UTMI
The UTMI contains a receive port, a transmit port and associated control lines to interface
with a USB Host Controller or Device Controller.
The following are feature of The TCC82xx USB PHY:

z Integrated 45-ohm termination, 1.5k-ohm pull-up and 15k-ohm pull-down
resistors.
z Support 480Mbps (HS), 12Mbps (FS), FS only, and FS-Serial and 1.5Mbps LS-
Serial data transmission rates.
z Dual (HS/FS) mode device support.
z Data and clock recovery from serial data on the USB connector.
z SYNC/End-of-Packet (EOP) generation and checking.
z Bit stuffing and unstuffing, and bit-stuffing error detection.
z Non Return to Zero Invert encoding and decoding
z Bit serialization and deserialization
z Logic to support suspend, resume and remote wake operations
Common Block Transceiver Block
Analog Block Digital Block

BIAS
HS/FS/LS
Reciever
U
T
OSC
NRZI M
HS/FS/LS Encoder I
Transmitter &
Decoder
PLL
DM/DP
Single-Ended USB1.1
Receiver Transceiver Serial
I/F
Figure 7.2 USB 2 PHY Block Diagram
7-2
7.3 Register Description for USB PHY
USB PHY Configuration Register(USB_CFG) 0x8000D0C4

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MC Reserved. SIDDQ *SBZ *SBZ Reserved.
*) SBZ = Should Be Zero..
MC Type [15] MCU Cycle Selection Bit

1 MCU Interface is 3 Cycle
R/W
0 MCU Interface is 2 Cycle
SIDDQ Type [9] MCU Cycle Selection Bit

1 Power Down the analog block
R/W
0 Does not Power Down the analog block
Note. the recommend USB configuration register value is as follows

USB 2.0 Device Mode = 0x0008 or 0x8008
7-3
7.4 USB2.0 Device Controller
The TCC82xx USB2.0 Device supports a fully compliant to USB 2.0 specification, high-
speed (480 Mbps) functions and suspend/resume signaling. The USB function
controller has an endpoint EP0 for control , two in/output endpoints EP1/EP2 for bulk
data transaction and an EP3 for interrupt data transaction. The endpoint EP0 has a single
64 byte FIFO; Max packet size is 64 bytes. The endpoint EP1 has a dual 2048 bytes
FIFO; Max packet size is 1024 bytes. The EP2 has a dual 1024 bytes FIFO; Max packet
size is 512 bytes. And the EP3 has a dual 128 bytes FIFO; Max packet size is 64 bytes,
respectively.
Interrupt (Status) and Interrupt Enable registers are broken down into 2 banks: Endpoint
Interrupts, USB Interrupts. The MAXP, ENDPOINT INTERRUPT and ENDPOINT
INTERRUPT ENABLE registers are used regardless of the direction of the endpoint.
The associated CSR registers correspond to the direction of endpoint.
SIE UPH
MCU_DATAIN[15:0]
UTM DATA[15:0]
Token
Decoder
RX Interface EP Machine
RX Control
Line State[1:0] MCU_RDN
MCU_WDN
Timeout
Checker
ORC RESET & RAM

Sus Con
Endpoint FIFO
I/F
MCU_DATAOUT[15:0]
TX Interface
MCU/DMA
TX I/F
USB_REG
Control
DACK
DREQ
CSN
ADDR
Figure 7.3 USB Controller Block Diagram
7-4
7.5 Register Description for USB Device Controller
Table 7.1 USB Register Map (Base Address = 0x8000D000)
Non-Indexed Registers Indexed Registers
Name Abbr. Address Name Abbr. Address
Endpoints Status
Index Register IR 0x00 ESR 0x2C
Register
Endpoint Interrupt Endpoint Control
EIR 0x04 ECR 0x30
Register Register
Endpoint Interrupt Byte Read Count
EIER 0x08 BRCR 0x34
Register Register
Function Address Byte Write Count
FAR 0x0C BWCR 0x38
Register Register
Endpoint Direction Max Packet
EDR 0x14 MPR 0x3C
Register Register
System Status DMA Control
SSR 0x1C DCR 0x40
Register Register
System Control DMA Transfer

SCR 0x20 DTCR 0x44
Register Counter Register
EP0 Status
EP0SR 0x24 DMA FIFO Counter Register DFCR 0x48
Register
EP0 Control DMA Total Transfer

EP0CR 0x28 DTTCR1 0x4C
Register Counter1 Register
DMA Total Transfer

EP0 Buffer Register EP0BUF 0x60 DTTCR2 0x50
Counter2 Register
EP1 Buffer Register EP1BUF 0x64 DMA MCU Address Register 1/2 DMAR1/2 0xA0/A4
EP2 Buffer Register EP2BUF 0x68 DMA Transfer Status Register DTSR 0xC0
EP3 Buffer Register EP3BUF 0x6C
7-5
Index Register(IR) 0X8000D000

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved IDX[1:0]
IDX[1:0] Endpoint
n Endpoint
The index register is used for indexing a specific endpoint. In most

cases setting the index register value should precede any other
operation.
Endpoint Interrupt Flag Register(EIR) 0x8000D004

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved EP3 EP2 EP1 EP0
Operating in MCU mode the endpoint interrupt register lets the MCU knows what
endpoint generates the interrupt. Clearing the bits can be accomplished by writing ‘1’ to
the bit position where the interrupt is detected.
EP3 Type [3] EP3 Interrupt Flag

R Indicates that the USB EP2 interrupt has been generated
1
W Clear the EP2 interrupt flag.

1

1

1
7-6
Endpoint Interrupt Enable Register(EIER) 0x8000D008

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved EP3 EP2 EP1 EP0
EP0 Type [3] EP3 Interrupt Control

1 Enable EP3 interrupt
R/W
0 Disable EP3 interrupt

R/W

R/W

R/W
Function Address Register(FAR) 0x8000D00C

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved FA[6:0]
This register reports a unique USB device address transferred from USB host through
“set_address” command
7-7
Endpoint Direction Register(EDR) 0x8000D014

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved EP3D EP2D EP1D EP0D
EP0 Type [3] Endpoint 3 Direction Selection

1 TX Endpoint
R/W
0 Rx Endpoint

1 TX Endpoint
R/W
0 Rx Endpoint

1 TX Endpoint
R/W
0 Rx Endpoint

1 TX Endpoint
R/W
0 Rx Endpoint
7-8
System Status Register(SSR) 0x8000D01C

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BAERR TMERR BSERR TCERRDCERREOERR VBOFF VBON TBM DP DM HSP SDE HFRM HFSUSP HFRES
This register reports operational status of the core, especially about error status and power
saving mode status. Except the line status. Every status bits in the System status Register
could be an interrupt sources. When the register is read after an interrupt due to certain
system status changes MCU should write back 1 to the corresponding bits to clear it.
BAERR Type [15] Byte Align Error

1 If error interrupt enable bit of SCR register is set to 1,
R/W
0 BAERR is set to 1 when byte alignment error is detected
TMERR Type [14] Timeout Error

R/W
0 TMERR is set to 1 when timeout error is detected
BSERR Type [13] Bit Stuff Error

R/W
0 BSERR is set to 1 when bit stuff error is detected
TCERR Type [12] Token CRC Error

1
If error interrupt enable bit of SCR register is set to
R/W 1,TCERR is set to 1 when CRC error in token packet is
0
detected
DCERR Type [11] Data CRC Error

1
If error interrupt enable bit of SCR register is set to
R/W 1,DCERR is set to 1 when CRC error in data packet is
0
detected
EOERR Type [10] EB OVERRUN Error

1
If error interrupt enable bit of SCR register is set to 1,
R/W EOERR is set to 1 when EB overrun error in transceiver is
0
detected
VBOFF Type [09] VBUS OFF

1 If vbus off interrupt enable bit of SCR register is set to 1,
R/W
0 VBUSOFF is set to 1 when VBUS is low
VBON Type [08] VBUS ON

1 If vbus off interrupt enable bit of SCR register is set to 1,
R/W
0 VBUSOFF is set to 1 when VBUS is high
7-9
TBM Type [7] Toggle Bit Mismatch

1 If error interrupt enable bit of SCR register is set to 1, TBM
R
0 is set to 1 when Toggle mismatch is detected
DP Type [6] DP Data Line State

1
R DP informs the status of D+ line
0
DM Type [5] DM Data Line State

1
R DP informs the status of D- line
0
HSP Type [4] Host Speed

1 High speed
R/W
0 Full speed
SDE Type [3] Speed Detection End

1 SDE is set by the core when the HS Detect Handshake
R/W
0 process is ended.
HFRM Type [2] Host Forced Resume

1 HFRM is set by the core in suspend state when Host sends
R/W
0 resume signaling.
HFSUSP Type [1] Host Forced Suspend

1 HFSUSP is set by the core when the SUSPEND signaling
R/W
0 from host is detected.
HFRES Type [0] Host Forced Reset

1 HFRES is set by the core when the RESET signaling from
R/W
0 host is detected.
7-10
System Control Register(SCR) 0x8000D020

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTZIEN DIEN VBOFE VBOE RWDE EIE BIS SPDEN RRDE IPS MFRM HSSPE HRESE
DTZIEN Type [14] DMA Total Counter Zero Int. Enable

1 Enable
R/W
0 Disable
DIEN Type [12] DUAL Interrupt Enable

1 Enable
R/W
0 Disable
VBOFE Type [11] VBUS OFF Enable

1 Enable
R/W
0 Disable
VBOE Type [10] VBUS ON Enable

1 Enable
R/W
0 Disable
RWDE Type [9] Reverse Write Data Enable

1 High byte data is first sent to Host
R/W
0 Low byte data is first sent to Host
EIE Type [8] Error Interrupt Enable

1
R/W This bit must be set to 1 to enable error interrupt
0
BIS Type [7] BUS Interface Select

1 The MCU bus width is selected by BIS. When set to 0, bus
R/W
0 width is 8bit, when set to 1, bus width is set to 16bit.
SPDEN Type [6] Speed Detect End Interrupt Enable

1
R/W When set to 1, Speed detection interrupt is generated
0
RRFE Type [5] Reverse Read Data Enable

1 First received byte is loaded in High byte field.
R/W
0 First received byte is loaded in Low byte field.
IPS Type [4] Interrupt Polarity Select

1 The signal polarity of the interrupt from the core is changed
through IPS. When set to 0, the interrupt is considered to be
R/W
0 active in low state. When set to 1, the interrupt is
considered to be active in high
7-11
MFRM Type [2] Resume by MCU

1
If this bit is set, the suspended core generates a resume
R/W signal. This bit is set when MCU write 1. this bit is cleared
0
when MCU write 0.
HSSPE Type [1] Suspend Enable

1 Enable
R/W
0 Disable
HRESE Type [0] Reset Enable

1 Enable
R/W
0 Disable
7-12
EP0 Status Register(EP0SR) 0x8000D024

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved LWO SHT TST RSR
This register stores status information of the Endpoint 0. This status information is set
automatically by the core when corresponding conditions are met. After reading the bits,
MCU should write 1 to clear them.
LWO Type [6] Last Word Odd

1
LWO informs that the last word of a packet in FIFO has
R/W an invalid upper byte. The bit is cleared automatically
0
after the MCU reads it from the FIFO.
SHT Type [4] Stall Handshake Transmitted

1
SHT informs that STALL handshake due to stall condition
R/W is sent to Host. This bit is an interrupt source. This bit is
0
cleared when MCU write 1.
TST Type [1] TX successfully transmitted

1
TST is set by core after core sends TX data to Host and
R/W receives ACK successfully. TST is one of the interrupt
0
sources.
RSR Type [0] Rx successfully received

1
RSR is set by core after core receives error free packet
R/W from Host and sent ACK back to Host successfully. RSR is
0
one of the interrupt sources.
7-13
EP0 Control Register(EP0CR) 0x8000D028

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved ESS TZLS
EP0 control register is used for the control of endpoint 0. Controls such as enabling ep0
related interrupts and toggle controls can be handled by EP0 control register.
EES Type [1] Endpoint Stall Set

1 ESS is set by MCU when it intends to send STALL hand
shake to Host.
R/W
0 This bit is cleared when the MCU writes 0 on it
ESS is needed to be set 0 after MCU writes 1 on it.
TZLS Type [0] TX Zero Length Set

1
TZLS is set by MCU when it intends to send TX zero
R/W length data to Host. This bit is cleared when the MCU write
0
0 on it.
Endpoint0 Buffer Register(EP0BUF) 0x8000D060

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EP0 BUF[15:0]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EP1 BUF[15:0]

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EP2 BUF[15:0]
Endpoint3 Buffer Register(EP3BUF) 0x8000D06C

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EP3 BUF[15:0]
The buffer register is used to hold data for TX/RX transfer.
7-14
Endpoint Status Register (ESR) 0x8000D02C

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FUDR FOVF FPID OSD DTCZ SPT DOM FFS FSC LWO PSIF[1:0] TPS RPS
The endpoint status register reports current status of an endpoint(except EP0) to the MCU.
FUDR Type [15] FIFO Underflow

1
FUDR is only used for ISO mode. FUDR is set when FIFO
R/W is empty and Host sends IN token.
0
This bit is cleared when the MCU writes 1.
FOVF Type [14] FIFO Overflow

1
FOVF is only used for ISO mode FOVF is set when FIFO
R/W is full and Host sends OUT data. This bit is cleared when
0
the MCU write 1.
FPID Type [11] First OUT Packet Interrupt Disable

1
First out packet interrupt disable in out DMA operation.
R/W First received OUT packet generates interrupt if this bit is
0
disabled and DEN in DMA control register is enabled
OSD Type [10] OUT Start DMA

1 OSD is set when First OUT packet is received after
R/W
0 Registers related DMA operation is set.
DTCZ Type [9] DMA Total Count Zero

1 DTCA is set when DMA total counter reach to 0
R/W
0 This bit is cleared when the MCU writes 1 on it
SPT Type [8]

1
R/W
0
DOM Type [7] Dual Operation Mode

1
DOM is set when the max packet size of corresponding
R endpoint is equal to a half FIFO size.
0
Endpoint 0 does not support dual mode
7-15
FFS Type [6] FIFO Flushed

1
FFS informs that FIFO is flushed. This bit is an interrupt
R/W source. This bit is cleared when the MCU clears FLUSH
0
bit in Endpoint Control Register.
FSC Type [5] Functional Stall Condition

1
FSC informs that STALL handshake due to functional stall
condition is sent to Host. This bit is set when endpoint stall
R/W
0 set bit is set by the MCU. This bit is cleared when the
MCU writes 1 on it
LWO Type [4] Last Word Odd

1
LWO informs that the lower byte of last word is only valid.
R This bit is automatically cleared after the MCU reads
0
packet data received Host.
PSIF[1:0] Type [3:2] Packet Status In FIFO
00 : No packet in FIFO.
01 : One packet in FIFO.
R/W
10 : Two packet in FIFO.
11 : Invalid value.
TPS Type [1] TX Packet Success

1
TPS is used for Single or Dual transfer mode
TPS is activated when one packet data in FIFO was
R/W Successfully transferred to Host and received ACK from
0
Host. This bit should be cleared by writing 1 on it after
being read by MCU.
RPS Type [0] Rx Packet Success

1
RPS is used for Single or Dual transfer mode
RPS is activated when FIFO has a packet data to receive.
R/W RPS is automatically cleared when MCU reads all packet
0
form FIFO MCU can identify the packet size through
BYTE READ COUNT REGISTER
7-16
Endpoint Control Register (ECR) 0x8000D030

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve INHLDOUTHD TNPMF[1:0] IME DUEN FLUSH TTE TTS[1:0] CDP ESS TZLS
The endpoint control register is useful for controlling an endpoint both in normal
operation and test case. Putting an endpoint in specific operation mode can be
accomplished through the endpoint control register.
INHLD Type [12] IN Packet HOLD

The USB sends NAK handshake to Host regardless of IN
1
FIFO status.
R/W
The USB can send IN data to Host according to IN FIFO
0
status(normal operation)
OUTHD Type [11] OUT Packet HOLD
1 The USB does not accept OUT data from Host

R/W
The USB can accept OUT data from Host according to
0
OUT FIFO status(normal operation)
TNPMF[1:0] Type [10:9] Transaction Number / Micro Frame

TNPMF is useful for ISO transfer.
00 : Invalid value.
R/W 01 : 1 transaction per micro frame
10 : 2 transaction per micro frame
11 : 3 transaction per micro frame
IME Type [8] ISO Mode Endpoint
1 ISO mode
R/W
0 Bulk(interrupt) mode
DUEN Type [7] Dual FIFO mode Enable

1 Dual Enable
R/W
0 Dual disable(Single mode)
FLUSH Type [6] FIFO Flush

1 FIFO is flushed when this bit is set to 1. The bit is
R/W
0 automatically cleared after MCU write 1.
7-17
TTE Type [5] TX Toggle Enable
1 The MCU can force TX data toggle bit with TTE. The bit
is useful for test. The TX data toggle bit changes
R/W
automatically in normal operation.
0 0 : disable / 1: enable
TTS[1:0] Type [4:3] TX Toggle Select

TTS is used for test. This is valid when TX Toggle
Enable(TTE) is set
00 : DATA PID 0.
R/W
01 : DATA PID 1.
10 : DATA PID 2.(Only in ISO mode)
11 : DATA PID 3.(Only in ISO mode)
CDP Type [2] Clear Data PID

In RX Mode
When this bit is set to 1, data toggle bit in core to be
compared with the data PID of received packet is reset to 0.
this bit is automatically cleared after MCU writes 1.
R/W
In TX Mode
TX data PID to be transmitted to host is reset to 0 when
this bit is set to 1. this bit is automatically cleared after
MCU write 1.
ESS Type [1] Endpoint Stall Set

1 ESS is set by the MCU when the MCU intend to send
R/W
0 STALL handshake to Host.
TZLS Type [0] TX Zero Length Set
1 This bit is used for Test. TZLS is set by the MCU when the
R/W MCU intend to send zero length TX data to Host this bit is
0 cleared when the MCU write 0 in it.
7-18
Byte Read Count Register (BRCR) 0x8000D034

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved RDCNT[9:0]
FIFO READ Count[9:0] RDCNT is read only The BRCD inform the amount of received
data from host.
RDCNT informs the amount of data in word(16bit) unit. Through the LWO bit of EP0SP,
the MCU can determine valid byte in last data word.
In 8 bit Interface, RDCNT keeps the byte size of received data.
Byte Write Count Register (BWCR) 0x8000D038
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved WRTCNT[9:0]
The byte write count register keeps the byte count value of a TX packet from MCU. The
counter value will be used to determine the end of TX packet.
Through BWCR, the MCU must load the byte counts of a TX data packet to the core. The
core uses this count value to determine the end of packet. The count value to this register
must be less than MAXP.
MAX Packet Register (MPR) 0x8000D03C

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved MAXP[10:0]
The max packet size of each endpoint is determined by programming the MAX packet
Register.
Max Packet[10:0]
The max packet size of each endpoint is determined by MAX packet register. The range
of max packet is from 0 to 2048 byte
Note. This USB2.0 device has 4 FIFO memory. and each size of EP0,EP1,EP2 and
EP3 are 64byte,1024byte,2048byte,128byte.
7-19
DMA Control Register(DCR) 0x8000D040

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve ARDRD FMDE 0 TDR RDR DEN
ARDRD Type [5] Auto Rx DMA Run set disable

1 Enable
R/W
0 Disable
This bit is cleared when DMA operation is ended.
FMDE Type [4] Fly Mode DMA Enable

1 Fly mode Enable
R/W
0 Fly mode Disable
This bit is used to run Fly mode DMA operation.
TDR Type [2] TX DMA Run

1 DMA run
R/W
0 DMA stop
This bit is used to set start DMA operation for TX Endpoint(out endpoint)
RDR Type [1] Rx DMA Run

1 DMA run
R/W
0 DMA stop
This bit is used to start DMA operation for Rx Endpoint (OUT endpoint)
This bit is automatically set when USB receives OUT packet data and DEN bit is
set to 1 and ARDRD bit is set to 0
To operation DMA after OUT packet data received, MCU must set RDR to 1.
DEN Type [0] DMA Mode Enable

1 Interrupt Operation mode
R/W
0 DMA Operation mode
7-20
DMA Transfer Counter Register (DTCR) 0x8000D044

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTCR[15:0]
This 16bit counter keeps the DMA transfer unit. If the value of counter is set to 16’0002,
there will be two byte(one word) transfer per each DMA request. To operate single mode
DMA transfer, DTCR is needed to be set 16’h0002.
DMA FIFO Counter Register (DFCR) 0x8000D048

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTCR[15:0]
This register has the byte number of data per DMA operation. The max packet size is
loaded in this register. In case of OUT Endpoint, the size value of received packet will be
loaded in this register automatically when Rx_DMA_run is enabled.
In case of IN Endpoint, the MCU should set max packet value.
DMA Total Transfer Counter Register1,2 (DTTCR1,2) 0x8000D04C/50

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DTCR[15:0]
This register should have total byte size of be transferred using DMA
DMA Total Transfer Counter1 : Low half word value.
DMA Total Transfer Counter2 : High half word value.
The max value is up to 2^32
DMA MCU Address Register1/2 (DMAR1,2) 0x8000D0A0/A4

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMAR[15:0]
This register indicates source or destination address in MCU
DMA MCU Address Register 1 : Low half word address value.
DMA MCU Address Register 2 : High half word address value.
When USB device is transfer mode(IN mode), this address indicates source address.
When device is receiving mode(OUT mode), this address means destination address.
* USB DMA can’t access external memory. So this address register must be set by
internal SRAM or DTCM address.
DMA Transfer Status Register (DTSR) 0x8000D0C0

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserve TD2 TD1 TD0
This register reports the result of EP1,2,3 transfer. If transfer is complete each bit is
set to 1
*Note. During USB DMA is operated, USB MCU access is prohibited at the same
time
7-21
7.6 DMA Operation Flow Chart
DMA Register Set DMA Register Set
USB Core reiceive OUT data form USB Core reiceive IN Token form Host
Host ctroller and generates DREQ to controller and sends IN data to Host.
DMA Controller USB core generates DREQ to DMA
Controller
DMA Controller reads data from OUT DMA Controller writes data to IN fifo in
fifo In usb core usb core
Total Transfer Count is Zero ? Total Transfer Count is Zero ?
DMA Operation is ended and interrupt DMA Operation is ended and interrupt
mode is On mode is On
(a) OUT DMA Operation Flow (b) IN DMA Operation Flow
7-22
NFC (Nand Flach Controller)
Multimedia Application Processor NFC
8 NFC
8.1 Function Description
PSELnfc ND_nCS0/1
PENABLE ND_nWE
Memory Control
Signal
PWRITE ND_nOE
APB BUS
PADDR ND_CLE
MEMORY NAND
CONTROLLER ND_ALE FLASH
PWDATA
ND_IO[15:00]
PRDATA
ND_READY0/1
APB I/F
PREADY
FIFO
READ/WRITE
SIGNAL
INTERRUPT
REQUEST
FIFO
To Interrup
Controller
DMA
(16x32)
To DMA
REQUEST
NFC
Figure 8.1 Nand Flash Controller Block Diagram
8-1
Table 8.1 Nand Flash Controller Register Map (Base Address = 0x90000000)
NFC_CMD 0x00 W - Nand Flash Command Register
NFC_LADDR 0x04 W - Nand Flash Linear Address Register
NFC_BADDR 0x08 W - Nand Flash Block Address Register
NFC_SADDR 0x0C W - Nand Flash Signal Address Register
NFC_WDATA 0x1x R/W 0x00000000 Nand Flash Word Data Register
NFC_LDATA 0x2x/3x R/W UnKnown Nand Flash Linear Data Register
NFC_SDATA 0x40 R/W 0x00000000 Nand Flash Single Data Register
NFC_CTRL 0x50 R/W 0x00f00111 Nand Flash Control Register
NFC_PSTART 0x54 W - Nand Flash Program Start Register
NFC_RSTART 0x58 W - Nand Flash Read Start Register
NFC_DSIZE 0x5C R/W 0x0000ffff Nand Flash Data Size Register
NFC_IREQ 0x60 R/W 0x00000000 Nand Flash Interrupt Request Register
NFC_RST 0x64 W - Nand Flash Controller Reset Register
8-2
Command Register (NFC_CMD) 0x90000000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMD1 CMD0
*)For 16bit bus width of NAND flash, the NFC_CMD1 may be used as command register,
For 8bit bus width of NAND flash, , the NFC_CMD1 must be Zero.
The following values are an example commands for NAND flash of SAMSUNG. Refer to corresponding datasheet of
NAND flash chip for more detailed list of commands.
(For 16bit bus width) (for 8bit parallel configuration, 16bit bus width)
0x0000 0x0000 : Page Read Command
0x0080 0x8080 : Page Program Command
0x0060 0x6060 : Block Erase Command
0x0070 0x7070 : Status Read Command
Linear Address Register (NFC_LADDR) 0x90000004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LADDR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LADDR[15:0]
*)By writing to this register, memory controller generates linear address shown in Table 8.2.
Block Address Register (NFC_BADDR) 0x90000008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BADDR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BADDR[15:0]
*)By writing to this register, memory controller generates Block address shown in Table 8.2.
Single Address Cycle Register (NFC_SADDR) 0x9000000C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SADDR1 SADDR0
*)When CPU writes to this register, one cycle of address cycle is generated.
For 16bit bus width of NAND flash, the NFC_SADDR1 may be used as single address register.
For 8bit bus width of NAND flash, , the NFC_SADDR1 must be Zero.
(For 16bit bus width) (for 8bit parallel configuration, 16bit bus width)
0x0012 0x1212 : for 0x12 Single Address
8-3
Table 8.2 Page size of NAND Flash

# of Cycle Address Generation
(CADDR) PSIZE = 0 PSIZE = 1 PSIZE = 2 PSIZE = 3
st
1 ADDR[7:0] ADDR[7:0] ADDR[7:0] ADDR[7:0]
nd
2 ADDR[16:9] ADDR[16:9] ADDR[10:8] ADDR[11:8]
3rd ADDR[24:17] ADDR[24:17] ADDR[18:11] ADDR[19:12]
4th ADDR[31:25] ADDR[31:25] ADDR[26:19] ADDR[27:20]
th
5 - - ADDR[31:27] ADDR[31:28]
*)The Table 8.2 represents the relation between each cycle and address generation.
User must set this information appropriately to PSIZE and CADDR field of NFC_CTRL register
ahead of accessing NAND data.
ADDR means address value that is written to NFC_LADDR or NFC_BADDR register. The shaded
cycles represent Block address cycles. That is, NAND address cycles start from there when
NFC_BADDR register is accessed.
ND_nCS0/1 ND_nCS0/1
ND_CLE ND_CLE
ND_ALE ND_ALE
ND_nWE ND_nWE
ND_nOE ND_nOE
ND_IO[15:00] 0x00FF ND_IO[15:00] 0x0012
ND_READY0/1 ND_READY0/1
For Writing 0x00000012 in NFC_SADDR Register

For Writing 0x00FF in NFC_CMD Register 2) SINGLE ADDRESS
1) COMMAND
ND_nCS0/1 ND_nCS0/1
ND_CLE ND_CLE
ND_ALE ND_ALE
ND_nWE ND_nWE
ND_nOE ND_nOE
ND_IO[15:00] 0x0000 0x002b 0x001a ND_IO[15:00] 0x002b 0x001a
ND_READY0/1 ND_READY0/1
For Writing 0x0012345600 in NFC_LADDR Register For Writing 0x0012345600 in NFC_BADDR Register
- CADDR = 2 (3 Cycle) - CADDR = 2 (3 Cycle)
- PSIZE = 512 Byte - PSIZE = 512 Byte
3) LINEAR ADDRESS 3) BLOCK ADDRESS
Figure 8.2 Example of Address/Command Writing Opertion.
8-4
Word Data Register (NFC_WDATA) 0x9000001x

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NFC_WDATA[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NFC_WDATA[15:0]
*)This register is used for single word data transfer by CPU.
This Register is useful in reading and writing Nand Flash data of spare area.
Linear Data Register(NFC_LDATA) 0x9000002x/3x

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
NFC_LDATA[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NFC_LDATA[15:00]
*)This register is used for burst data transfer by DMA/CPU.
To start burst data transfer, User must write any value to NFC_PSTART or NFC_RSTART
Single Data Register (NFC_SDATA) 0x90000040

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NFC_SDATA1 NFC_SDATA0
*)This register is used for reading and writing one 8bit or 16bit data according to NAND Flash Bus Size.
For 16bit bus width of NAND flash, the NFC_SDATA0/1 may be used as single data register,
otherwise only NFC_SDATA0 is used as single data register.
This Register is useful in reading Nand ID/Status data.
8-5
Nand Flash Control Register(NFC_CTRL) 0x90000050

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEN IEN IEN DEN FS BW AR CEN CFG[1:0] STA RDY BSIZE PSIZE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 CADDR STP PW HLD
RDY_IEN [31] Nand Flash Ready Interrupt

0 Nand Flash Ready Interrupt Disable
1 Nand Flash Ready Interrupt Enable
PROG_IEN [30] Nand Flash Program Interrupt

0 Nand Flash Program Interrupt Disable
1 Nand Flash Program Interrupt Enable
READ_IEN [29] Nand Flash Read Interrupt

0 Nand Flash Read Interrupt Disable
1 Nand Flash Read Interrupt Enable
DEN [28] Nand Flash DMA Request

0 Nand Flash DMA Request Disable
1 Nand Flash DMA Request Enable

*)Transfer type of CHCTRL register in DMA must be single transfer with level-sensitive detection.
FS [27] Nand Flash FIFO Status

0 FIFO status is Busy to write and read in FIFO
1 FIFO status is Ready to write and read in FIFO

*)For burst data transfer by ARM, user must check that this bit is high, ahead of access NFC_LADATA.
BW [26] Nand Flash Bus Width Select

0 Bus width = 8 bit
AR [25] Auto Read Start Selection

0 Auto Read Start Disable
1 Auto Read Start Enable
CEN [24] NAND Flash Controller CS Selection

0 Nand Flash CS is Low
1 Nand Flash CS is generated by Controller
*)When CEN is low, nCSx is ~CS0/1.
*)When CEN is low, nCSx is chip select signal of nand flash controller.
8-6
CFG [23:22] NAND Flash CS Configuration

11 NAND Flash nCS0/1 is not active
10 NAND Flash nCS0 is active
01 NAND Flash nCS1 is active
00 NAND Flash nCS0 is active in parallel
STA [21] NAND Flash Controller State Flag

0 Nand Flash Controller is Busy
1 Nand Flash Controller is Ready
*)If STA is low(busy), do not used NFC_CMD/NFC_xADDR/NFC_xDATA.
RDY [20] Nand Flash Ready Flag

0 External Nand Flash is Busy
1 External Nand Flash is Ready
BSIZE [19:18] Burst Size of Nand Controller

00 1Read/Write
01 2Read/Write
10 4Read/Write
11 8Read/Write
*)This register value must be same BURST SIZE of CHCTRL in DMA.
PSIZE [17:16] Page Size of Nand Flash

00 1 Page = 256 Half-Word
01 1 Page = 512 Byte
10 1 Page = 1024 Half-Word
11 1 Page = 2048 Byte
CADDR [14:12] Number of Address Cycles

The number of address command cycle for NAND type flash.
N
(N+1) cycle is used for generating address cycle command.
STP [11:08] Number of Cycle for Setup Time(tSH)

STP is issued between the falling edge of nCSx and nOE / nWE.
N ( = 0~15 )
N cycle is generated.
PW [07:04] Number of Cycle for Pulse Width (tPW)

PW is issued during low state of nOE / nWE.
N ( = 0~15 )
HLD [03:00] Number of Cycle for Hold Time (tHLD)

HLD is issued between the rising edge of nOE / nWE and nCSx.
N ( = 0~15 )
8-7
The following figure displays the element cycle diagram for external memories.
Figure 8.3 Timing Diagram of Read/Write Enanle Signal.
Program Start Register(NFC_PSTART) 0x90000054

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Don’t care
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Don’t care
*)When this register is written by any value, data transfer is started. That is, Programming operation to nand flash is
started.
For Butsr data transfer by DMA/ARM, you must set EN flag of DMA_CHCTRL register first, and then writing any value to
NFC_PSTART ahead of accessing NFC_LADATA.
Read Start Register(NFC_RSTART) 0x90000058

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Don’t care
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Don’t care
*)When this register is written by any value, data transfer is started. That is, Reading operation to nand flash is started.
For Burst data transfer by DMA/ARM, you must set EN flag of DMA_CHCTRL register first, and then writing any value to
NFC_RSTART ahead of accessing NFC_LADATA.
Data Size Register(NFC_DSIZE) 0x9000005C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
NFC_DSIZE[15:0]
NFC_DSIZE Nand Flash Data Size

N N is transferred byte data size
*)For Samsung 258 Half-word/512 Byte small block, N is 512(byte).
For Samsung 1024 Half-Word/2048 Byte big block, N is 2048(byte).
8-8
Nand Flash Request Register(NFC_IREQ) 0x90000060

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved NFC_FLAG[2:0] Rvd NFC_IREQ[2:0]
FLAG[2] [6] Nand Flash Ready Flag

1 Read The Rising edge of Ready Signal is occurred.
1 Write Ready Flag Clear
*)When this register is cleared, ready interrupt request also is cleared.
FLAG[1] [5] Nand Flash Program Flag

1 Read Program data transfer is finished.
1 Write Program Flag Clear
*)When this register is cleared, program interrupt request also is cleared.
FLAG[0] [4] Nand Flash Read Flag

1 Read Read data transfer is finished.
1 Write Read Flag Clear
*)When this register is cleared, read interrupt request also is cleared.
IRQ[2] [2] Nand Flash Ready Interrupt Request

1 Read Ready Interrupt is occurred.
1 Write Ready Interrupt Request Clear
*)When this register is cleared, ready flag also is cleared.
IRQ[1] [1] Nand Flash Program Interrupt Request

1 Read Program Interrupt is finished.
1 Write Program Interrupt Request Clear
*)When this register is cleared, program flag also is cleared.
IRQ[0] [0] Nand Flash Read Interrupt Request

1 Read Read Interrupt is finished.
1 Write Read Interrupt Request Clear
*)When this register is cleared, read flag also is cleared.
Controller Reset Register(NFC_RST) 0x90000064

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Don’t care
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Don’t care
*)When this register is written by any value, Controller and Register is reset.
8-9
Figure 8.4 Example of Page Program.
8-10
NFC_CMD(00h) Write
[NFC_CTRL]
- BW/CEN/CFG/PSIZE/CADDR/STP/PW/HLD Setting.
[NFC_CTRL]
NFC_LADDR Write - BSIZE Setting.
- Read Interrupt Enable Setting.
- DMA Request Enable Setting.
[NFC_DSIZE]
- Transfer Data Size Setting.
[DMA Setting]
NFC_RSTART Write
Data Transfer
A) NAND FLASH Page Read Flow Chart
ST_IDLE ST_CMD ST_IDLE ST_ADDR ST_IDLE ST_READ ST_IDLE
ND_CLE
ND_ALE
ND_WEN
ND_OEN
N Times
ND_I/O[15:0] x0000 A[7:0] A[16:9] A[24:17] DATA DATA DATA
ND_READY
t(R)
Ready Interrupt Read Interrupt

Occured Occured
B) NAND FLASH Page Read Timing Diagram
Figure 8.5 Example of Page Read.
8-11
SD / MMC Controller
Multimedia Application Processor SD/MMC CONTROLLER
9 SD/MMC CONTROLLER
SD/MMC controller is designed to support SD specification Ver.1.01, SDIO specification

Ver1.10, CE-ATA and MMC specification Ver.3.0. By using DMA and internal FIFO(8x32bits)
data transfer rate is up to maximum speed, SD/MMC card supports. Moreover because this block
has internal clock controller, it is possible to adjust operating frequency for power saving or other
operating conditions just from setting special register.
SD/MMC
Controller
PSELSD
SDIClk CLOCK SDCLK
CONTROLLER
PWRITE
SDICMD
APB BUS
PENABLE SDIARGU SDCMD

CMD PATH
SDIRSPCMD
PADDR
CONTROLLER
SDIRSPARGUs
PWDATA
SD/MMC
APB I/F
PRDATA CARD
TRANSFER
SDIWDATA FIFO ENABLE
SDIO
SDIRDATA (8x32 bits) CARD
FIFODATA
SDIDCTRL
SDIDTIMER
DATA PATH SDDATA
CONTROLLER
SDIFLAG SDIIENABLE
STATUS
INTERRUPTS
DMA INTERRUPT I/F

INTERRUPT
Figure 9.1 SD/MMC Controller Block Diagram
9-1
The overall registers are shown in Table 9.1.
Table 9.1 SD/MMC Controller Register Map (Base Address = 0x90001000)

SDICLK 0x04 R/W 0x3000 Clock control register
SDIARGU 0x08 R/W 0x0 Command argument register
SDICMD 0x0C R/W 0x20000 Command index and type register
SDIRSPCMD 0x10 R Response index register
SDIRSPARGU2 0x1C R Response argument register
SDIDTIMER 0x24 R/W 0x40FFFF Wait cycles for data transfer
SDIDCTRL2 0x28 R/W 0x0 Data path control register
SDIDCTRL 0x2C R/W 0xFF1490 Data path control register
SDISTATUS 0x30 R Status register
SDIIFLAG 0x34 R/W 0x0 Interrupt flag register
SDIWDATA 0x38 R/W 0x0 Transmit data register
SDIRDATA 0x3C R Receive data register
SDIIENABLE 0x40 R/W 0x0 Interrupt enable register
9-2
Clock Control Register(SDICLK) 0x90001004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 BP EN CLKDIV
Clock controller generates SDI_CLK (internal operating clock of SD/MMC controller), which is
gated clock of SDCLK. By setting EN field and BP field of SDICLK register to ‘0’, SD/MMC
controller can be halted for saving power.
BP Type CLK BYPASS

0
R/W
1 SDI_CLK equals PCLK
EN Type CLK ENABLE
0 SDI_CLK hold to low if BP is set to ‘0’
R/W
1 SDI_CLK operates
CLKDIV Type CLK DIVIDE FACTOR
N R/W *Fsd = Fsource/2(N+1)
Fsource : frequency of SDCLK
Fsd : frequency of SDI_CLK
SDOCLK that is fed to SD/MMC card is inverted from SDI_CLK. Therefore when SDI_CLK
holds to low, SDOCLK shall hold to high.
Command Argument Register(SDIARGU) 0x90001008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CMDARGUMENT [31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CMDARGUMENT[15:00]
A SD/MMC command always starts with a start bit (always 0), followed by the bit indicating the
direction of transmission (host = 1). The next 6 bits indicate the index of the command that is
equal to CMDINDEX field of SDICMD register, this value being interpreted as a binary coded
number (between 0 and 63). Some commands need an argument (e.g. an address) that is equal to
CMDARGUMENT field of SDIARGU, which is coded by 32bits. A value denoted by ‘x’ in the
table below indicates this variable is dependent on the command. All commands are protected by
a CRC. Every command codeword is terminated by the end bit (always 1). This SD/MMC
controller automatically attaches the start bit, the direction of transmission bit, CRC (7bits) and
the end bit except command index and argument field. So user set just the command index to
SDICMD register and command argument to SDIARGU register.
Bit position 47 46 [45:40] [39:8] [7:1] 0

Width (bits) 1 1 6 32 7 1
Value ‘0’ ‘1’ x x x ‘1’
Description start bit transmission command argument CRC7 end bit
bit index
9-3
Command Index Register(SDICMD) 0x9000100C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 RWT[6:4]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RWT[3:0] EN CD RT WR CMDINDEX
EN field of SDICMD register is automatically reset to zero after three cycles from Command
transfer start.
RWT Type Command Response Wait Time

Maximum cycles to the start bit of response from
N R/W
command end bit
EN Type Transmit Command
When this field is set to ‘1’, SD/MMC controller
transmits the command to SD/MMC card. And the it
1 R/W
is automatically reset to ‘0’ after three cycles from
transmission start.
CD Type Command With Data
0 Command without data transfer
R/W
1 Command with data transfer (e.g. CMD17, CMD25)
RT Type Response Type
N R/W * Response type
WR Type Wait Response
0 Command without response
R/W
1 Command with response
CMDINDEX Type Command Index
n R/W Command index
* Response Type
RspType1 1 normal command with response of 48bit width

RspType1b 2 command with optional busy signal
RspType2 3 CID, CSD register
RspType3 4 OCR register
RspType4 5 CMD5 for SDIO
RspType5 6 CMD52, CMD53 for SDIO
RspType6 7 Published RCA response
9-4
Response Index Register(SDIRSPCMD) 0x90001010

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 RSPINDEX
All response from SD/MMC card are sent via the command line CMD. The response
transmission always starts with the left bit of the bit string corresponding to the response
codeword. The code length depends on the response type. A response always starts with a start
bit (always 0), followed by the bit indicating the direction of transmission (card = 0). A value
denoted by ‘x’ in the below indicates a variable entry. All responses except for the type RspType3
are protected by a CRC. Every response codeword is terminated by the end bit (always 1)
Bit position 47 46 [45:40] [39:8] [7:1] 0

Width (bits) 1 1 6 32 7 1
Value ‘0’ ‘0’ x x x ‘1’
Description start bit transmission response card status CRC7 end bit
bit index
A response index must be same with transmitted command index except RspType2 and
RspType3. So user may check whether the controller receives the correct response by the
response index.
Response Argument Register(SDIRSPARGUn) 0x90001014+4n

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RSPARGUn[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RSPARGUn[15:00]
When response is short types (RspType1, RspType1b, RspType3, RspType4, RspType5 and
RspType6), SDIRSPARGU0 is only used for card status[39:8]. In the other case,
SDIRSPARGUn registers are used as below.
LongRspArgu[127:96] SDIRSPARGU0
9-5
Data Timer Register(SDIDTIMER) 0x90001024

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Ncc DWT[23:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DWT[15:00]
Ncc Type Response & Command Interval

Interval cycles from the response end bit to the command
N R/W
start bit
DWT[26:0] Type Data Wait Time
Maximum cycles for *data timeout error when controller
reads data from SD/MMC card. DWT[26:24] is set to
N R/W SDIDTCRL register. DWT means only when WTD is set to
‘0’. If WTD is set to ‘1’, controller waits data permanently
regardless of DWT.
*data timeout maximum : 2.6 sec when SDI_CLK is 50Mhz
9-6
Data Control Register2(SDIDCTRL2) 0x90001028

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 BCNT ST MB DD MODE
The fields in SDIDCTRL2 register are used to define data transfer type (e.g. direction, stop
command). BCNT field and ST field of SDIDCTRL2 are specially used for SDIO or CE-ATA
devices. Those fields don’t’ have meaning when the controller operates in the SD/MMC mode.
BCNT Type Byte Count

N R/W Byte size per block for SDIO(or CE-ATA) data transfer
ST Type Stop Transfer

1 Stop command for SDIO(or CE-ATA) multi block transfer
R/W
0 Non stop command
BM Type Multi Block Transfer

1 Block transfer
R/W
0 Byte transfer
DD Type Data Direction

1 Write data to card
R/W
0 Read data from card
MODE Type SDIO Data Transfer Mode
1 Data transfer in SDIO(or CE-ATA) mode
R/W
0 Data transfer in SD/MMC mode or
*It is important that MODE field is set to ‘0’ for command without data transfer. In other words,
If user want to transmit commands in SDIO (or CE-ATA) without data transfer, then MODE
field has ‘0’ value before transmitting command.
9-7
Data Control Register(SDIDCTRL) 0x9000102C
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 WTD DWT[26:24] BE MBN
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MBN FSR FCNT BS WB 0 DEN
FCNT field of SDIDCTRL register is used for data transfer request signal to CPU or DMA.
During a user writes data to device, FIFO_load_request signal (FLR field in SDISTATUS
register) is set to ‘1’ if the number of entries in FIFO is less than FCNT value. But in the case that
a user read data from device, FIFO_fetch_request signal (FFR field in SDISTATIS register) is set
to ‘1’ if the number of entries in FIFO is more than FCNT values. Normally FCNT value ‘4’ is
recommended for 4-read 4write DMA operation.
WTD Type Wait Time Disable

0 Controller waits data for DTW cycles
R/W
1 Controller waits data forever
DWT [26:24] Type Data Wait Time
N R/W The most significant 3 bits of DWT
BE Type Big Endian

0 Data transfer in little endian mode
R/W
1 Data transfer in big endian mode
MBN Type Multi Block Number

N R/W The number of Blocks for multi block transfer
FSR Type FIFO Synchronous nRESET

0 Internal FIFO synchronous negative reset
R/W
1 Internal FIFO operates normally
FCNT Type FIFO CNT

N R/W FIFO counts for data transfer request
BS Type Block Size

N R/W Block size(byte) = 2^n
WB Type Wide Bus
0 : 1bit mode
N R/W 1: 4bit mode
2: 8bit mode(MMC_EX)
DEN Type DMA Enable
0 Data transfer by using CPU
R/W
1 Data transfer by using DMA
9-8
Status Register(SDISTATUS) 0x90001030

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 SI MBE SBE FD DPR CPR RFU TFO FFR FLR FCF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FF FE RA TA 0 RDCP TDCP 0 RCP FWE 0 DTO CTO RDCF TDCF CCF
SDISTATUS register indicates that the controller operates in what kind of state. A user must
control appropriately the controller depending on each status field in SDISTATUS. For example,
before transmitting a command, it is confirmed that the controller is ready to transmit the
command by watching CPR field. Also some fields notify that errors like CRC failure are
occurred. See section 1.3 for detail description.
SI Type SDIO Interrupt

1 R Assigned number of multi-block data transfer completed
MBE Type Multi-block Transfer End

1 R Assigned number of multi-block data transfer completed
SBE Type Single Block Transfer End

1 R Single block transfer end
FD Type FIFO Direction
0 Read data from device
R
1 Write data to device
DPR Type Data Path Ready

1 R Data path control block is ready
CPR Type Command Path Ready

1 R Command path control block is ready
RFU Type Receive FIFO Under-run

1 R It is issued when FIFO is read despite of empty flag
TFO Type Transmit FIFO Over-run
1 R It is issued when FIFO is written to despite of full flag
FFR Type FIFO Fetch Request

1 It issued When the number of entries in FIFO is more than or equal
R
to FCNT value with FD field ‘0’
FLR Type FIFO Load Request
1 It is issued When the number of entries in FIFO is less than FCNT
R
value with FD field ‘1’
FCF Type FIFO CNT Full
1 It is issued When the number of entries is FIFO is more than or
R
equal to FCNT values regardless of FD field
FF Type FIFO Full
1 R It is issued When FIFO is full
FE Type FIFO Empty
1 R It is issued When FIFO is empty
9-9
RA Type Data Receive In Progress

1 R Data path control block is receiving data from device
TA Type Data Transmit In Progress
1 R Data path control block is writing data to device
RDCP Type Data Block Received (CRC PASS)

1 R CRC check of received block is passed
TDCP Type Data Block Sent (CRC PASS)

1 R CRC check of transmitted block is passed
RCP Type Response Received

1 R Response is received
FWE Type Flash Write Error

1 R It is issued when CRC token from device means flash write error
DTO Type Data Time Out
1 R Data doesn’t come until DWT cycles
CTO Type RESPONSE TIME OUT
1 R Response doesn’t come until Ncc cycles
RDCF Type Data Block Receive(CRC FAIL)
1 R CRC check of received data is failed
TDCF Type Data Block Sent(CRC FAIL)
1 R CRC check of transmitted data is failed
RCF Type Response Received(CRC FAIL)
1 R CRC check of response is failed
9-10
Interrupt Register(SDIIFLAG) 0x90001034

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 SDIOI DRI CRI FWEI SBEI DTI RTI RDCFI TDCFI RCFI
SDIOI Type SDIO Interrupt

1 R SDIO interrupt
1 W SDIO interrupt clear
DRI Type Data Path Ready Interrupt
1 R Data transfer end interrupt
1 W Data transfer end interrupt clear
CRI Type Command Path Ready Interrupt

1 R Command transfer end interrupt
1 W Command transfer end interrupt clear
FWEI Type Flash Write Error Interrupt

1 R Transmitted data flash write error interrupt
1 W Transmitted data flash write error interrupt clear
DTI Type Data Time-Out Interrupt

1 R Received data time-out interrupt
1 W Received data time-out interrupt clear
RTI Type Response Time-Out Interrupt
1 R Response time-out interrupt
1 W Response time-out interrupt clear

RDCFI Type Receive Data CRC Fail Interrupt
1 R Received data CRC check fail interrupt
1 W Received data CRC check fail interrupt clear
TDCFI Type Transmit Data CRC Fail Interrupt

1 R Transmitted data CRC check fail interrupt
1 W Transmitted data CRC check fail interrupt clear
RCFI Type Response CRC Fail Interrupt
1 R Response CRC check fail interrupt
1 W Response CRC check fail interrupt clear
9-11
Write Data Register(SDIWDATA) 0x90001038

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[15:0]
In order to transfer data to a device, a user may write data (32bit width) to FIFO through
SDIWDATA register by CPU or DMA. DATA[31:00] on SDIWDATA are re-written FIFO as
two types on endian in according to BE field in SDIDCTRL register as below. The controller
transmits first the most significant bit of data in FIFO.
BE = ‘0’ (little endian mode)

FIFO[n][31:24] = DATA[07:00]
FIFO[n][23:16] = DATA[15:08]
FIFO[n][15:08] = DATA[23:15]
FIFO[n][07:00] = DATA[31:24]
BE = ‘1’ (big endian mode)
FIFO[n][31:00] = DATA[31:00]
FIFO[n][31:00] is nth entry of FIFO, and DATA[31:00] is data on SDIWDATA.
Read Data Register(SDIRDATA) 0x9000103C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DATA[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DATA[15:0]
As like writing data to a device, a user may use read data through SDIRDATA. The relation
between DATA[31:00] on SDIRDATA register and data in FIFO is as below
BE = ‘0’ (little endian mode)

DATA[31:24] = FIFO[n][07:00]
DATA[23:16] = FIFO[n][15:08]
DATA[15:08] = FIFO[n][23:16]
DATA[07:00] = FIFO[n][31:24]
BE = ‘1’ (big endian mode)
DATA[31:00] = FIFO[n][31:00]
9-12
Interrupt Enable Register(SDIIENABLE) 0x90001040

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRI CRI FWEI SBEI DTI RTI RDCFI TDCFI CCFI
SDIOI[08] Type SDIO Interrupt Enable

0 SDIO interrupt disable
R/W
1 SDIO interrupt enable
DRI[08] Type Data Path Ready Interrupt Enable
0 Data transfer end interrupt disable
R/W
1 Data transfer end interrupt enable
CRI[07] Type Command Path Ready Interrupt Enable

0 Command transfer end interrupt disable
R/W
1 Command transfer end interrupt enable
FWEI[06] Type Flash Write Error Interrupt Enable

0 Transmitted data flash write error interrupt disable
R/W
1 Transmitted data flash write error interrupt enable
DTI [04] Type Data Time-Out Error Interrupt Enable

0 Received data time-out interrupt disable
R/W
1 Received data time-out interrupt enable
RTI[03] Type Response Time-Out Error Interrupt Enable
0 Response time-out interrupt disable
R/W
1 Response time-out interrupt enable
RDCFI [02] Type Receive Data CRC Fail Interrupt Enable
0 Receive data CRC check fail interrupt disable
R/W
1 Receive data CRC check fail interrupt enable
TDCFI [01] Type Transmit Data CRC Fail Interrupt Enable

0 Transmit data CRC check fail interrupt disable
R/W
1 Transmit data CRC check fail interrupt enable
RCFI [00] Type Response CRC Fail Interrupt Enable
0 Response CRC check fail interrupt disable
R/W
1 Response CRC check fail interrupt enable
9-13
EHI (External Host Interface)
Multimedia Application Processor EHI
10 EHI
10.1 Overview
External host interface (EHI) allows external host device to be connected to
system bus of TCC82xx. External host device can be directly connected to
68/80-series interfaces and access the memory area of TCC82xx. For
software based data transfer, EHI can generate internal interrupt of TCC82xx,
and TCC82xx can also send interrupt request to the external host controller.
And this block can be used for external host boot.
The features of EHI are the followings.
z 68/80 series interface with 8/16bits data can be supported.

z Burst transfer is supported and address can be incremented
automatically.
z External host device can generate an internal interrupt of TCC82xx.
z Interrupt request can be sent to the external host by programming
specific bits in EHI control register.
z External host booting mode is supported.
z Semaphore is supported for improving data transfer efficiency.
Table 10.1 EHI pin configuration

PIN Name I/O Function
HPCSn I Chip select signal
HPXA I Address signal. It is used for switching between normal

access and EHIND/EHST register access.
Normal access(HPXA = 0) : EHI register indicated by

EHIND register is accessed.
EHIND/EHST access(HPXA = 1) : Writing to EHIND

register and reading from EHST register.
HPWEN I 68-interface: Enable signal
80-interface: Write strobe signal
HPOEN I 68-interface: Data reading or writing select signal
80-interface: Read strobe signal
HPXD[15:0] B Data bus
HPINT O External host interrupt request signal / Ready signal
10-1
HPCSn
HPWEN
AHB
AHB 68/80 HPOEN

Interface FIFO Interface
16x32
HPXA
HPXD[15:0]
Control Registers
HPINT
To interrupt controller
Figure 10.1 EHI Block Diagram
10-2
10.2 Registers
Table 10.2 EHIF register map (Base Address = 0x90008000)
Offset Int. Ext. Reset Description
Name *
EHST 0x00 R/W R/W 0x00000000 Status register

EHIINT 0x04 R/W R/W 0x00000000 Internal interrupt control register
EHEINT 0x08 R/W R/W 0x00000000 External interrupt control register
EHA 0x0C R R/W 0x00000000 Address register
EHAM 0x10 R/W R 0x00000000 Address masking register
EHD 0x14 R/W R/W 0x00000000 Data register
EHSEM 0x18 R/W R/W 0x00000000 Semaphore register
EHCFG 0x1C R/W R/W 0x00000000 Configuration registers
EHIND 0x20 R W 0x00000000 Index register
EHRWCS 0x24 R R/W 0x00000000 Read/Write Control/Status register
*
If an external host device accesses to an EHI register, the offset value that corresponds to it must be written to
EHIND register.
10-3
Status Register (EHST) 0x90008000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDY ST[6:0]
Notice that EHST register can be read when HPXA is high.
RDY [7] Ready (Read Only)

It represents that an external host device can access to
TCC82xx. If EHCFG.RDYE is equal to 1, it can be output
0 or 1
through HPINT pin. In this case, HPINT is RDY ⊕ **
EHCFG.RDYP.
ST [6:0] Status[6:0]
0-127 It is only updated by software.
Internal Interrupt Control Register (EHIINT) 0x90008004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IIRQ_ST[6:0] IIRQ
IIRQ_ST [6:0] Internal Interrupt Status
0 – 127 This specifies IIRQ interrupt source.
IIRQ [0] Internal Interrupt Request

External host interrupt in TCC82xx is generated. This bit
1
must be cleared manually.
**
It means EXCLUSIVE OR operation.
10-4
External Interrupt Control Register (EHEINT) 0x90008008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EIRQ_ST[6:0] EIRQ
EIRQ_ST[6:0] [7:1] External Interrupt Status

This specifies EIRQ interrupt source. An external host
0 – 127
device can detect interrupt source via EIRQ_ST.
EIRQ [0] External Interrupt Request

If HPINT is connected to external interrupt input of
1 external host, TCC82xx can send interrupt request to the
external host.
Address Register (EHA) 0x9000800C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EHA[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EHA[15:2] 0
EHA[31:0] [31:0] Address

It maps to TCC82xx memory space directly. If
TCC82xx EHRWCS.AI = 1 and EHRWCS.RW = 01 or 10, it
address space increments automatically during data transfer. It can be
masked by EHAM register.
Address Masking Register (EHAM) 0x90008010

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EHAM[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EHAM[15:2] 0
EHAM [31:0] Address Masking

When an external host device accesses to TCC82xx
system bus, internal address of TCC82xx is EHA[31:2] &
~EHAM[31:2].
10-5
Data Register (EHD) 0x90008014

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EHD[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EHD[15:0]
EHD[31:0] [31:0] Data register

While EHRWCS.RW = 01 or 10, an external host device
accesses TCC82xx address space using EHA register. In
DATA this case, it is used for writing or reading data.
If ERWCS.RW = 00, it can be used for status register
which is programmed only by software.
Semaphore Register (EHSEM) 0x90008018

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST[5:0] FLG[1:0]
ST[5:0] [7:2] Status

According to FLG, reading/writing operation can be
0-63
issued. Refer to FLG[1:0].
FLG [1:0] Semaphore Flag

If EHSEM is read and then FLG is 00, this means
EHSEM is not occupied by any master.
If external host device reads EHSEM and read value is
00 00, then FLG is 01. If TCC82xx reads EHSEM and read
value is 00 then FLG is 10. If TCC82xx and external host
read EHSEM simultaneously, return value for external
host is 00 and it for TCC82xx is 01.
Reading/Writing: External host device
01
Reading only: TCC82xx
Reading/Writing: TCC82xx
10
Reading only: External host device
11 N/A
10-6
Configuration Register (EHCFG) 0x9000801C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDYP RDYE BW MD
RDYP [4] Ready Polarity

If RDYE = 1, EHST.RDY ⊕ EHCFG.RDYP is output
0 or 1
through HPINT. So it is only valid when RDYE = 1.
RDYE [3] Enable Ready

0 HPINT is used for the interrupt request signal.
1 HPINT is used for EHST.RDY ⊕ EHCFG.RDYP signal.
BW [2] Bus Width

0 8-bit interface
1 16-bit interface
MD [0] Mode
0 80-interface
1 68-interface
Index Register (EHIND) 0x90008020

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EHIND[7:0]
EHIND[7:0] [7:0] Index register

It selects internal register for external host device. It can
be written by external host device while HPXA is high. It
0x00 – 0x24
is only written by an external host device. Refer to Table
10.2 for value corresponding to each register.
10-7
Read/Write Control/Status Register (EHRWCS) 0x90008024

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
AI LOCK RW[1:0] BSIZE[3:0]
Notice that EHRWCS is only written by an external host device.
AI [7] Address auto-increment

1 Address is auto-incremented if RW = 01 or 10.
LOCK [6] Bus Lock

Once an external host device is a master of TCC82xx
system bus, bus-handover cannot be occurred until this
1
bit is cleared to 0. Notice that this bit must be cleared
manually.
When an external host device accesses to TCC82xx
0 system bus, a master of TCC82xx which has higher
priority can be a bus master.
RW[1:0] [5:4] Reading/Writing operation

00 Access to EHI control registers
Writing to TCC82xx system bus. When BSIZE = 0(single
01
transfer), it is cleared automatically.
Reading from TCC82xx system bus. When BSIZE = 0, it
10
is cleared automatically.
11 N/A
BSIZE[3:0] [3:0] Burst size

It specifies how many words will be transferred. N means
that N+1 words will be transferred . For continuous burst
N transfer, EHST.RDY needs to be checked every burst
size transfer. Notice that it should be programmed before
EHRWCS.RW is set to 10 or 11.
10-8
10.3 Interface Signals

10.3.1 External interface
In case of 80-interface, HPWEN and HPOEN pulse width must be 2 HCLK
cycles at least. And 4 HCLK cycles are required between reading/writing
operations. In case of 68-interface, HPWEN(E) pulse width must be 2 HCLK
cycles at least.
Figure 10.2 Timing Diagram of interface signals
10.4 Operation
10.4.1 Booting From External Host
In case of external host booting mode, bootstrap codes in the internal ROM
recognize EHI configuration through TCC82xx GPIO ports and initialize
EHCFG register and EHST register. An external host device reads EHST
register from TCC82xx and determines whether TCC82xx is ready for data
transfer. Refer to about TCC82xx booting modes.
10.4.2 Access to registers

An external host device can access EHI registers. If it intends to write data to
EHIND, it must drive HPXA pin to high. When HPXA is high, an external host
device reads from EHST register. To write to or read from an EHI register
except EHIND and EHST registers, EHIND register must be set to its offset
value and HPXA must be low. When an external host device intents to write
to EHST register, it must also use EHIND register. Figure 21.4 and Figure
21.5 show that an external host device writes from and reads to EHI registers.
The following shows how to write data (=0x12345678) to EHAM register.
1. Write EHAM[15:0] offset value(=0x10) while HPXA = 1. EHIND register

indicates EHAM[15:0] register.
2. Write 0x5678 for EHAM[15:0] while HPXA=0.
10-9
3. Write EHAM[31:16] offset value(=0x12) while HPXA = 1. EHIND register

indicates EHAM[31:16] register.
4. Write 0x1234 for EHAM[31:16] while HPXA = 0.
Figure 10.3 Example of writing / reading operation from an external host device
(80 interface, 16bits)
Figure 10.4 Example of writing /reading operation from an external host device
(68 interface, 8bits)
10-10
10.4.3 Access to TCC82xx system bus

An external host device that is connected to TCC82xx via EHI can access
TCC82xx system bus. Figure 10.5 shows how to program an external host
device for access to TCC82xx system bus. For continuous transfer, it needs
to check EHST.RDY in the end of burst transfer. The size of burst transfer is
specified by EHRWCS.BSIZE. Notice that EHRWCS.BSIZE should be
programmed before EHRWCS.RW is set.
writing to the TCC87xx reading from the TCC87xx
EHA = start address EHA = start address
EHRWCS_BURST = N-1 EHRWCS_BURST = N-1
EHRWCS.WR = 1 EHRWCS_RD = 1
EHRWCS.AI = 1 EHRWCS_AI = 1
EHIND <= EHD offset EHIND <= EHD offset
External host writes N words

EHST_RDY = 1
No
Yes
EHST_RDY = 1 External host reads N words

No
Yes
Completed ? Completed ?
No No
Yes
EHRWCS = 0 EHRWCS = 0
End Of Transfer End Of Transfer
(a) writing operation (b) reading operation
Figure 10.5 Access to TCC82xx system bus
10-11
Figure 10.6 Example of writing to TCC82xx system bus(86 interface, 8bits)
Figure 10.7 Example of reading from TCC82xx system bus (68 interface, 8bits)
10-12
IDE Controller
Multimedia Application Processor IDE
11 IDE
11.1 Overview
IDE controller support to PIO mode0,1,2,3,4.
The simple block diagram of IDE Controller is as followings.
Figure 11.1 IDE Controller Block Diagram
11-1
Maximum Speed
The Speed of a IDE Interface is shown in Table 11.1
Table 11.1 Speed of Data Transfer (Byte per Second)

MODE SPEED
PIO MODE 0 3.3 MBps
PIO MODE 1 5.22 MBps
Table 11.2 IDE Controller Register Map (Base Address = 0x90009000)

CS0n 0x00~ 0x1F R/W - PIO CS0n Access Register
CS1n 0x20 ~0x3F R/W - PIO CS1n Access Register
PIOCTRL 0x00 R/W 0x00600000 PIO Mode Control Register
.
11-2
PIO CS0n Access Register (CS0n) 0x90009000~0x9000902F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DD0[15:0]
DD0 PIO Data for CS0n

DD0 16bit access data for CS0n
DD 0 is access data to read or to be written for CS0n in PIO MODE.
For example,
To write 0x1234(data value) at pio address 0x6 using CSn0, CPU or DMA target address(HADDR[6:0])
must be 0x18 and DD0 must be 0x1234, that is HADDR[4:2] equals DA[2:0] and DD0 equals DD[15:0]. To
read data of pio address 0x7, CPU or DMA target address(HADDR[6:0]) must be 0x1C. that is HADDR[4:2]
is DA[4:2] and DD0 is read data in PIO MODE.
PIO CS1n Access Register (CS1n) 0x90009020 ~ 0x9000903F

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DD1[15:0]
DD1 PIO Data for CS0n

DD1 16bit access data for CS1n
DD 1 is access data to read or to be written for CS1n in PIO MODE.
To write 0x1234(data value) at pio address 0x6 using CSn1, CPU or DMA target address(HADDR[6:0])
must be (0x18 + 0x20 )and DD1 must be 0x1234, that is HADDR[4:2] equals DA[2:0] and DD1 equals
DD[15:0]. To read data of pio address 0x7, CPU or DMA target address(HADDR[6:0]) must be (0x1C +
0x20). that is HADDR[4:2] is DA[4:2] and DD1 is read data.a in PIO mode.
PIO Mode Control Register (PIOCTRL) 0x90009040

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SYNC[1:0] STP[4]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STP[3:0] PW[5:0] HLD[5:0] RDY
SYNC[1:0] [22:21] Sync Bit Register for IORDY/DDMARDYn

00 Bypass
01 1 SYNC
10 2 SYNC
These bits are need to synchronize from HDD clock domain to AHB clock domain for IORDY (and
DDMARDYn) signal. The default value is 2 synch.
STP[3:0] [16:13] Number Of Cycle for Setup Time

STP (STP value + 1 ) AHB cycles are issued
These bits define the time requirement from the active CSn to the active DIORn (or DIOWn) in PIO MODE.
For further details, See Figure 11.2.
11-3
PW[5:0] [12:7] Number Of Cycle for Pulse Width

PW (PW value + 1 ) AHB cycles are issued
These bits define the time requirement for active duration of the DIORn ( or DIOWn ) .
For further details, See Figure 11.2.
HLD[5:0] [6:1] Number Of Cycle for HOLD Time

HLD (HLD value + 1 ) AHB cycles are issued
These bits define the time requirement from the negation of the DIORn (or DIOWn) to the negation of the
CSn.
For further details, SeeFigure 11.2.
IORDY [0] IORDY Enable

0 PW cycles is irrelative of IORDY
1 PW cycles are extended by IORDY
When this bit is set, PW Cycles are extended by IORDY.
For further details, See Figure 11.2
Example 1)STP = 1, PW = 5, HLD = 3, IORDY = 0
AHB clock
CS0n/CS1n
DIORn/DIOWn
2 cycles 6 cycles 4 cycles
Write
DD[15:0]
Read
DD[15:0]
Example 2)STP = 1, PW = 4, HLD = 2, IORDY = 1
CS0n/CS1n
DIORn/DIOWn
2 cycles ( (A+B)5cycles + IORDY ) cycles 3 cycles
IORDY
(A) (B)
Write
DD[15:0]
Read
DD[15:0]
Figure 11.2 PIO Interface Timing Diagrams
11-4
TCC82xx
Part 3. System
Chapter 1. Interrupt
Chapter 2. Timer
Chapter 3. Clock
Chapter 4. RTC
Chapter 5. DMA
Chapter 6. ADC
Rev. 0.20
Apr. 24 2006
Revision History

PIC (Program Interrupt Controller)
Multimedia Application Processor PIC
1 PIC
1.1 Overview
The following figure represents the block diagram of interrupt controller. Interrupt
controller can manage up to 32 interrupt sources. In the TCC82xx, there are four external
interrupt sources that can be detected various kind of method, that is a rising edge / falling
edge / level high / level low can be detected from external interrupt sources. External
interrupt sources can be fed reliably into interrupt controller with dedicated noise filters.
There are two types of interrupt in ARM946ES; IRQ type, FIQ type.
Interrupt controller can select these two types for each interrupt sources separately.
internal interrupt sources

pi_INTIN<31:4>
external interrupt sources
pi_EXTIN<3:0>
Clock Edge/Level
PCLK Noise Filter
Generator Selector
ICFG
IREQ
IRQ Flag
APB
CREQ
MREQ
IEN nIRQ
nIRQ/nFIQ
to ARM946E-S
Generator
IRQSEL nFIQ
Figure 1.1 Program Interrupt Controller Block Diagram
1-1
Table 1.1 Interrupt Controller Register Map (Base Address = 0x80001000)

IEN 0x00 R/W 0x00000000 Interrupt Enable Register
CREQ 0x04 W - Clear Interrupt Request Register
IREQ 0x08 R 0x00000000 Interrupt Request Flag Register
IRQSEL 0x0C R/W 0x00000000 IRQ / FIQ Select Register
ICFG 0x10 R/W 0x00000000 External Interrupt Configuration Register
MREQ 0x14 R 0x00000000 Masked Interrupt Request Flag Register
TSTREQ 0x18 R/W 0x00000000 Test Mode Register (must be remained zero)
IRQ 0x20 R - IRQ Raw Status (IREQ & IRQSEL)
FIQ 0x24 R - FIQ Raw Status (~IREQ & IRQSEL)
MIRQ 0x28 R - Masked IRQ Status (IRQ & IEN)
MFIQ 0x2C R - Masked FIQ Status (FIQ & IEN)
TMODE 0x30 W 0x000007C0 Trigger Mode (0: edge, 1:level)
SYNC 0x34 W 0x00000000 Synchronizer Control
WKUP 0x38 W 0x00000000 Wakeup Control
SDDCFG 0x3C R/W 0x00000000 SD Detect Configuration Register
Caution)
Some peripherals have their own request flags as well as the flag in interrupt controller, so in the
interrupt service routine, user should clear their own request flags in the peripherals ahead of clearing
the flag in the interrupt controller.
The following pseudo code illustrates the sequence of processing the timer interrupt flags.
if (MREQ & TimerREQ) { // If timer interrupt flag is set
if (TIREQ & Timer0) {
process_timer0(); // Process Timer0 interrupt
TIREQ = Timer0; // Clear the flag of Timer0
}
}
}
}
}
}
CREQ = TimerREQ; // Clear the flag of Timer
}
1-2
Interrupt Enable Register (IEN) 0x80001000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
- MSCL UT1 SPI_R ECC G2D JPEG SAD EHI - SD ND RTC_A RTC_P I2C ADC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCD TC32 DMA CIF SD3 uDMA SPI_T USD UT0 TC I2S_T I2S_R E3 E2 E1 E0
MEN [31] Master Enable

0 All interrupts are disabled.
1 Any interrupt enabled by corresponding bit[30:0] can be generated to CPU
*) Master Enable functionality is not effective if RDYIRQEN bit of Miscellaneous
Configuration Register is set as “1”.
Interrupt Request Control

Bit Field
1 = Interrupt enabled, 0 = Interrupt disabled
MSCL [30] Memory-to-Memory scaler
UT1 [29] UART1 interrupt control
SPI_R [28] SPI Rx interrupt control
ECC [27] ECC interrupt control
G2D[26] Graphic 2D interrupt control
JPEG [25] JPEG codec interrupt control
SAD [24] SAD calculator interrupt control
EHI [23] External Host Interface interrupt control
[22] Not Used
SD [21] Sequre Digital / MMC Controller interrupt control
ND [20] NAND Flash Controller interrupt control
RTC_A [19] Real Time Clock alarm interrupt control
RTC_P [17] Real Time Clock power-down wake up interrupt control
ADC [16] ADC interrupt control
LCD [15] LCD controller interrupt control
TC32 [14] 32-bit Timer interrupt control
DMA [13] General DMA interrupt control
CIF [12] CIF interrupt control
SD3 [11] Sequre Digital / MMC Detect interrupt control
uDMA [10] USB DMA interrupt control
SPI_T [9] SPI Tx interrupt control
USD [8] USB device interrupt control
UT0 [7] UART0 interrupt control
TC [6] Timer/Counter interrupt control
I2S_T [5] I2S TX interrupt control
I2S_R [4] I2S RX interrupt control
E3 [3] External interrupt request 3 control
1-3
Clear Interrupt Request Register (CREQ) 0x80001004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
By writing “1” to each field, the interrupt request flag of corresponding interrupt is cleared. Writing to “0”
doesn’t mean anything and the corresponding flag remains its previous state.
Interrupt Request Register (IREQ) 0x80001008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
If each field is “1”, it means that the corresponding interrupt has been requested. If each peripheral has its own
request flags, it means at least one of those flags has been set.
IRQ Interrupt Select Register (IRQSEL) 0x8000100C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
If each field is “1”, it means that the corresponding interrupt is considered as IRQ interrupt, if each field is ‘0’ it
means that its interrupt is considered as FIQ interrupt. Refer to chapter 3 for more information about IRQ / FIQ
interrupts.
External Interrupt Configuration Register (ICFG) 0x80001010

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FE3 DTYPE3 FT3 FE2 DTYPE2 FT2 FE1 DTYPE1 FT1 FE0 DTYPE0 FT0
FE3~FE0 Filter Enable

0 Noise filter is enabled (in case of DTYPEn != 3)
1 Noise filter is disabled (in case of DTYPEn != 3)
If DTYPEn == 3, noise filter is always enabled, and this field sets which level generates the
interrupt. If it is set to 1, level high triggers interrupt, and if it is set to 0, level low triggers interrupt.
DTYPE3~0 Detection Type

0 Falling edge triggered external interrupt
1 Rising edge triggered external interrupt
2 Both edge triggered external interrupt
Level high / low triggered external interrupt
3 FEn field determines which level triggers the interrupt. If FEn == 1, level
high triggers the interrupt and FEn == 0, level low triggers the interrupt.
FT3~FT0 Filter Type

X Reserved
Following is the summary of all above fields.
1-4
Table 1.2 Summary of External Interrupt Configuration

FEn, DTYPEn Triggering Noise Filter
000 Set falling edge triggered Filter Enabled
001 Set rising edge triggered Filter Enabled
010 Set both edge triggered Filter Enabled
011 Set low level triggered Filter Enabled
100 Set falling edge triggered Filter disabled
101 Set rising edge triggered Filter disabled
110 Set both edge triggered Filter disabled
111 Set high level triggered Filter Enabled
Masked Interrupt Request Register (MREQ) 0x80001014

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Same meaning as IREQ except that it represents only that of the enabled interrupts. Only the flags of enabled
interrupts can be checked by this register. It is recommended that use MREQ register instead of IREQ in the
interrupt handler routine.
Test Mode Register (TSTREQ) 0x80001018

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
This register can be used to generate an interrupt by writing 1 at the corresponding bit of the internal interrupt
source. This register is for testing purpose only. It must be remained zero during normal operation.
IRQ Raw Status Register (IRQ) 0x80001020

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
This register reflects IREQ bits selected when the corresponding IRQSEL bit is low (IREQ & IRQSEL)
FIQ Raw Status Register (FIQ) 0x80001024

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
This register reflects IREQ bits selected when corresponding IRQSEL bit is high (~IREQ & IRQSEL).
Masked IRQ Raw Status Register (MIRQ) 0x80001028

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MIRQ = IRQ & IEN
1-5
Masked FIQ Raw Status Register (MFIQ) 0x8000102C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MFIQ = FIQ & IEN
Trigger Mode Register (TMODE) 0x80001030

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
This register selects trigger mode (0: edge, 1:level) for each internal interrupt source.
Synchronization Control Register (SYNC) 0x80001034

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
By default, all internal interrupt source lines are synchronized to HCLK. This register disables synchronization
registers (0: sync enabled, 1:sync disabled). Do not disable synchronization if an interrupt source is asynchronous to
HCLK
Wakeup Control Register (WKUP) 0x80001038

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
By default, all interrupt source lines are used for system wakeup events in power saving mode. (0: enabled, 1:
disabled). Appropriate bits must be enabled before the system enters power saving mode (clock stop mode).
Otherwise, system cannot wakeup.
1-6
SD Detect Configuration Register (SDDCFG) 0x8000103C

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- SDFE SDDTYPE SDFT
SDFE SD Filter Enable

0 Noise filter is enabled (in case of SDDTYPE != 3)
1 Noise filter is disabled (in case of SDDTYPE != 3)
If SDDTYPE == 3, noise filter is always enabled, and this field sets which level generates the
interrupt. If it is set to 1, level high triggers interrupt, and if it is set to 0, level low triggers interrupt.
SDDTYPE SD Detection Type

0 Falling edge triggered external interrupt
1 Rising edge triggered external interrupt
2 Both edge triggered external interrupt
Level high / low triggered external interrupt
3 SDFE field determines which level triggers the interrupt. If SDFE == 1, level
high triggers the interrupt and SDFE == 0, level low triggers the interrupt.
SDFT SD Filter Type

X Reserved
Following is the summary of all above fields.
Table 1.3 Summary of External Interrupt Configuration

SDFE, SDDTYPE Triggering Noise Filter
000 Set falling edge triggered Filter Enabled
001 Set rising edge triggered Filter Enabled
010 Set both edge triggered Filter Enabled
011 Set low level triggered Filter Enabled
100 Set falling edge triggered Filter disabled
101 Set rising edge triggered Filter disabled
110 Set both edge triggered Filter disabled
111 Set high level triggered Filter Enabled
1-7
Timer & Counter
Multimedia Application Processor TIMER / COUNTER
2 TIMER / COUNTER
2.1 Overview
The TCC82xx has four 16bit and two 20bit timer/counters. Each timer counter has three
registers for basic operation modes. Refer to register description table for details. When
operating in counter modes, External interrupt pin is used as counting clock for that
counter.
The main clock frequency of timer counter can be configured by setting TCLK frequency.
(Refer to Clock generator block) With the 12bit internal basic counter, the timer counter
can generate various intervals from microseconds to seconds unit.
The following figure represents the block diagram of timer/counter.
external clock source through the

noise filter of interrupt controller
pi_EXTCK<3:0>
Basic Clock
TCLK Counter
Counter Selector
TCFG
APB
TCNT
Compare
TREF
(=) TREQ
Compare
TMREF
(=)
Tgl TCO
Figure 2.1 Timer Counter Block Diagram
The following table explains the registers of each timer counter. The address of each timer
counter is 16bytes aligned. The base address of timer counter is 0x80002000.
The number n represents for each timer/counter. In case of timer/counter 4, 5 (that is n = 4

or 5) the TREF, TCNT register has 20bit resolution. It can be used for generating long
time of event.
2-1
Table 2.1 Timer/Counter Register Map (Base Address = 0x80002000)

TIREQ 0x60 R/W 0x0000 Timer/Counter n Interrupt Request Register
TWDCFG 0x70 R/W 0x0000 Watchdog Timer Configuration Register
TWDCLR 0x74 W - Watchdog Timer Clear Register
TC32EN 0x80 R/W 0x00007FFF 32-bit Counter Enable / Pre-scale Value
TC32LDV 0x84 R/W 0x00000000 32-bit Counter Load Value
TC32CMP0 0x88 R/W 0x00000000 32-bit Counter Match Value 0
TC32CMP1 0x8C R/W 0x00000000 32-bit Counter Match Value 1
TC32PCNT 0x90 R/W - 32-bit Counter Current Value (pre-scale counter)
TC32MCNT 0x94 R/W - 32-bit Counter Current Value (main counter)
TC32IRQ 0x98 R/W 0x0000---- 32-bit Counter Interrupt Control
2-2
Timer/Counter n Configuration Register (TCFGn) 0x80002000 + (0x10 * n)

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 CC POL TCKSEL[2:0] IEN PWM CON EN
CC [8] Clear Count

0 TCNTn is not cleared.
1 TCNTn is cleared to zero.
POL [7] TCK Polarity

0 TCNTn is incremented at rising edge of the selected counting clock
1 TCNTn is incremented at falling edge of the selected counting
clock
TCKSEL[2:0] [6:4] TCK Select

TCK is internally generated from divider circuit. It is driven by
k=0~4 TCLK, and this value determines the division factor of this circuit.
Division factor is 2(k+1).
TCK is internally generated from divider circuit. It is driven by
k = 5, 6 TCLK, and this value determines the division factor of this circuit.
Division factor is 22k
TCK is the external pin shared by external interrupt signal. In
TCC82xx, there are 4 external pins for this purpose, so this
k=7
configuration is valid only for timer/counter 3 ~ 0. (not for
timer/counter 5, 4)
IEN [3] Interrupt Enable

1 Enable Timer/Counter interrupt
0 Disable Timer/Counter interrupt
PWM [2] PWM Mode Enable

Enable PWM mode
Timer/Counter output is changed at every time the TCNTn is equal to
1 TREFn and TMREFn value. It can be used to generate PWM
waveform, by changing TMREFn while fixing TREFn. (where, TREFn
> TMREFn)
Disable PWM mode
Timer/Counter output can be changed only when the TCNTn is equal
0
to TREFn.
It can be used to generate a rectangular pulse of variable frequency.
The output of 3 Timer/Counters can be monitored through GPIO_A[10:12] or

GPIO_B[8:10] ports. The other Timer/Counters cannot be monitored through GPIOs, but
these can be used internally. Refer to GPIO chapter for more information.
CON [1] Continue Counting

0 When the TCNTn is reached to TREFn, TCNTn restarts counting
from 0 at the next pulse of selected clock source.
1 The TCNTn continues counting from the TREFn.
EN [0] Timer/Counter Enable

1 Timer counter is enabled.
2-3
Following figure illustrates the basic behavior of timer / counter.
CONT = 1 , IEN = 1 , PWM = 0 , TCKSEL = 0 , TREF = 3
TCLK
TCK
TCNT 0 1 2 3 4 5 6
TEQU
TCO TCO TCO is inverted
nTREQ
CONT = 0 , IEN = 1 , PWM = 1 , TCKSEL = 0 , TREF = 3 , TMREF = 1
TCLK
TCK
TCNT 0 1 2 3 0 1 2
TMEQU
TEQU
TCO
nTREQ
Figure 2.2 Timing diagram of timer/counter
Timer/Counter n Counting Register (TCNTn) 0x80002004 + (0x10 * n)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 TCNTn[19:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TCNTn[15:0]
TCNTn is increased by 1 at every pulse of selected clock source. TCNTn can be set to
any value by writing to this register. In case of timer 4 and timer 5, it has 20 bits,
otherwise it has 16 bits.
Timer/Counter n Counting Reference Register (TREFn) 0x80002008 + (0x10 * n)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 TREFn[19:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TREFn[15:0]
When TCNTn is reached at TREFn and the CON flag of TCFGn register is set to 1, the
TCNTn is cleared to 0 at the next pulse of selected clock source. According to the TCFGn
settings, various kinds of operations may be done. In case of timer 4 and timer 5, it has 20
bit, otherwise it has 16 bit.
2-4
Timer/Counter n Middle Reference Register (TMREFn) 0x8000200C + (0x10 * n)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 TMREFn[19:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TMREFn[15:0]
When TCNTn is reached at TMREFn and the PWM flag of TCFGn register is set to 1,
the timer output of TCOn is cleared to 0 at the negative edge of that pulse of selected
clock source. The TCOn is set to 1 when the TCNTn is reached at TREFn. (refer Figure
2.1). So you can generate PWM signal by modifying TMREFn between 0 ~ (TREFn-1).
In case of timer 4 and timer 5, it has 20 bit, otherwise it has 16 bit.
Timer/Counter Interrupt Request Register (TIREQ) 0x80002060

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 TWF TF5 TF4 TF3 TF2 TF1 TF0 0 TWI TI5 TI4 TI3 TI2 TI1 TI0
TWF [14] Watchdog Timer Flag

1 Watchdog timer has reached to its reference value.
TFn [13:8] Timer/Counter n Flag

1 Timer/counter n has reached to its reference value.
TWI Type [6] Watchdog Timer Interrupt

Request Flag
1 Read Watchdog timer has generated its interrupt.
1 Write Watchdog timer interrupt is cleared.
TIn Type [6] Timer/Counter n Interrupt

Request Flag
1 Read Timer/counter n has generated its interrupt.
1 Write Timer/counter n interrupt flag is cleared.
If a timer n has reached its reference value, the TFn is set. (bit n represents for Timer n). If
its interrupt request is enabled by set bit 3 of TCFGn register, then the TIn is set. If the TC
bit of IEN register is set, the timer interrupt is really generated and this TIREQ register
can be used to determine which timer has requested the interrupt. After checking these
flags, user can clear these TFn and TIn field by writing “1” to corresponding TFn or TIn
bit field.
2-5
Watchdog Timer Configuration Register (TWDCFG) 0x80002070

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 TCKSEL[2:0] IEN 0 ISEL EN
Watchdog timer is used for the system not to be stuck by generating a reset pulse
automatically when the watchdog timer counter overflows to zero. It has 8bit counter
and when this counter overflows from 0xFF to 0x00, the reset or interrupt is
generated.
The programmer must clear the watchdog counter before it overflows by writing any
value to TWDCLR register. The duration can be chosen by selecting TCKSEL field
appropriately.
TCKSEL[2:0] [6:4] TCK Select

k=0~3 Undefined. Should not be used.
TCK is internally generated from divider circuit. It is driven by TCLK,
k=4 and this value determines the division factor of this circuit. Division
factor is 25.
TCK is internally generated from divider circuit. It is driven by TCLK,
k = 5, 6 and this value determines the division factor of this circuit. Division
factor is 22k
k=7 Undefined. Should not be used.

Watchdog Timer Interrupt is enabled.
1
This field is valid only if RST field is set to 0.
ISEL [1] Interrupt Select

Watchdog timer generates the reset signal when it reaches to the
0 reference value, the reset signal is applied to every component in the
chip.
Watchdog timer does not generate reset signal although it reaches to the
1
reference value, and it continue counting from 0.
EN [0] Watchdog Timer Enable

Watchdog timer is enabled. If the watchdog timer is disabled, its
1 counter goes to 0xE0, so when it is first enabled, user must clear the
counter by writing to TWDCLR register.
Watchdog Timer Clear Register (TWDCLR) 0x80002074

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
any value
The watchdog timer counter can be cleared to 0 by writing any value to this register.
If it is not cleared before it overflows, the watchdog timer generate reset signal to the
entire component of chip.
2-6
As illustrated in the figure 6.3, TC32 consists of a pre-scale counter, main counter
and two comparators. The pre-scale counter is a simple 24-bit up-counter which
always counts from zero to PRESCALE value programmed in TC32EN register.
The 32-bit main counter is incremented only when the prescale counter reaches
PRESCALE value. The clock input of TC32 module can be either XTIN (default) or
XIN. Refer to Clock Generator description (XTTC32 bit of PWDCTL register).
ZCLK from Clock Controller

(XTIN or XIN)
TC32EN Pre-scale
Counter
APB
Main
TC32LDV Counter
Compare
TC32CMP0
(=)
IRQ IRQ to
Compare Sync. Interrupt
TC32CMP1 Controller
(=)
TC32IRQ
Figure 2.3 32-bit Counter Block Diagram
Possible counter modes are described in the table below.
Table 2.2 TC32 Count Mode

TC32EN Register Bits Main Counter Operation
Mode
LOADZERO LDM1 LDM0 Start Count Value End Count Value
0 0 0 0 LOADVAL 0xFFFFFFFF
1 0 0 1 LOADVAL CMP0 (if LOADVAL < CMP0)
2 0 1 0 LOADVAL CMP1 (if LOADVAL < CMP1)
3 0 1 1 LOADVAL CMP0 (if LOADVAL < CMP0 ≤ CMP1) or
CMP1 (if LOADVAL < CMP1 ≤ CMP0)
4 1 0 0 0 LOADVAL – 1
5 1 0 1 0 CMP0 (if LOADVAL > CMP0)
6 1 1 0 0 CMP1 (if LOADVAL > CMP1)
7 1 1 1 0 CMP0 (if LOADVAL > CMP1 ≥ CMP0) or
CMP1 (if LOADVAL > CMP0 ≥ CMP1)
Refer to register descriptions below for CMP0, CMP1 and LOADVAL.
Mode0 can be used as 1Hz counter mode, if PRESCALE = 0x007FFF, STOPMODE = 0,
ZCLK = XTIN(32.768kHz)
2-7
TC32 Enable / Pre-scale Value Register (TC32EN) 0x80002080

Bit Name Default R/W Description
31:30 Reserved 0 R
29 LDM1 0 R/W Re-load counter when the counter value matched with CMP1.
LOADZERO bit below selects the couter load(start) value.
28 LDM0 0 R/W Re-load counter when the counter value matched with CMP0
LOADZERO bit below selects the couter load(start) value.
27 Reserved 0 R
26 STOPMODE 0 R/W 0 = Free Running Mode, 1 = Stop Mode.
25 LOADZERO 0 R/W By default, counter starts from LOADVAL. When this bit is enabled
(1), the counter is forced to count from “0” to “LOADVAL – 1”.
24 ENABLE 0 R/W Counter Enable
23:0 PRESCALE 0x007FFF R/W Pre-scale counter load value. The pre-scale counter always runs
from “0” up to PRESCALE. The default value is for 1Hz counter
when ZCLK = XTIN (32.768kHz).
TC32 Load Value Register (TC32LDV) 0x80002084

31: 0 LOADVAL 0x00000000 R/W Counter Load Value.
The counter is restarted whenenver one of the TC32En and TC32LDV is written.
TC32 Match Value 0 Register (TC32CMP0) 0x80002088

31: 0 CMP0 0x00000000 R/W Counter Match Value
TC32 Match Value 1 Register (TC32CMP1) 0x8000208C

31: 0 CMP1 0x00000000 R/W Counter Match Value
TC32 Pre-scale Counter Current Value Register (TC32PCNT) 0x80002090

31:24 Reserved 0x00 R
23: 0 PCNT 0x000000 R Pre-scale counter current value. The AHB system clock must be
three times faster than the frequency of ZCLK to read valid value.
TC32 Main Counter Current Value Register (TC32MCNT) 0x80002094

31: 0 MCNT 0x00000000 R Main counter current value. When RSYNC is enabled, the AHB
system clock must be faster than the frequency calculated below.
(ZCLK frequency) / (PRESCALE + 1) * 3
2-8
TC32 Interrupt Control Register (TC32IRQ) 0x80002098

31 IRQCLR 0 R/W Interrupt Clear Control. When this bit is 0, interrupt status bits
(IRQRSTAT) are cleared by reading this register. When this bit is
set, IRQSTAT bits are cleared only if written with non-zero value.
30 RSYNC 0 R/W Synchronization control for Counter Current Value Registers
(TC32PCNT and TC32MCNT). 0 = Enable, 1 = Disable.
29:24 BITSEL 0x00 R/W Counter bit selection value for interrupt generation. Any one of the
counter bits {MCNT[31:0], PCNT[23:0]} selected by BITSEL is used
to generate an interrupt.
0x00 ~ 0x17 : PCNT[0] ~ PCNT[23]
0x18 ~ 0x38: MCNT[0] ~ MCNT[31]
23:21 Reserved 0 R/W
20 IRQEN[4] 0 R/W Enable Interrupt at the rising edge of a counter bit selected by
BITSEL.
19 IRQEN[3] 0 R/W Enable Interrupt at the end of pre-scale count
18 IRQEN[2] 0 R/W Enable Interrupt at the end of count
17 IRQEN[1] 0 R/W Enable Interrupt when the counter value matched with CMP1
16 IRQEN[0] 0 R/W Enable Interrupt when the counter value matched with CMP0
15:13 Reserved 0 R/W
12:8 IRQRSTAT 0x00 R/W Interrupt Raw Status. Refer to the description for IRQEN above.
7:5 Reserved 0 R/W
4:0 IRQMSTAT 0x00 R/W Masked Interrupt Status = IRQRSTAT & IRQEN
2-9
CKC (Clock Controller)
Multimedia Application Processor CKC
3 CKC
3.1 Overview
The block diagram of CKC is shown in Figure 3.1.
The CKC block have 4 primary clock sources from pll0, pll1, XIN and XTIN. Pll clock sources,
XIN and XTIN can generate divided clock. These 4 primary clock sources and 4 divided clock
sources can be used for generating the CPU clock, the bus clock, and each peripheral clocks.
The output clock of safe clock changer, which generates glitch-free clock from 8 independent
clock sources, can be used for making the main operating clocks (CPU clock and bus clock).
The peripheral clock generator makes the corresponding hardware clock using 4 primary clock
sources and 4 divided clock sources.
The TCC82xx has 2 operating modes, halt-mode and power-down mode. In the halt mode, the
CPU clock and bus clock are masked until the FIQ or IRQ interrupt. In power-down mode, all
the oscillator circuits are disabled and all the clocks in TCC82xx are masked until the pre-defined
external interrupt.
CLOCK SAFE
AHB Bus I/F CONTROLLER CLOCK HCLKGEN FBUS
REGISTER I/F CHANGER
FSYS
Reg.
Config. s CPUCLKGEN FCPU
PLL0
PLL0 Reg.
DIVIDER Config. s
PLL1
PLL1
DIVIDER PCLK
CKSRCs PCLKs
XIN GENERATORs
XIN
DIVIDER
XTIN BUS CLK S/W RESET SWRESETs
CONTROLLER
XTIN
DIVIDER
Figure 3.1 CKC Block Diagram
3-1
Table 3.1 CKC Register Map (Base Address = 0x80004000)

CLKCTRL 0x00 R/W 0x80000014 CPU & Bus Clock Control Register
CLKDIVC 0x0C R/W 0xE0E0E0E0 Divided Clock Configuration Register
MODECTR 0x10 R/W 0x00000000 Operating Mode Control Register
BCLKCTR 0x14 R/W 0x0FFFFFFF Bus Clock Enable Register
SWRESET 0x18 R/W 0xFFFFFFFF Software Reset Control Register
PCLKCFG0 0x1C R/W 0x40000000 SDRAM Refresh Clock Control Reigster
PCLKCFG1 0x20 R/W 0x40000000 I2C Clock Control Register
PCLKCFG2 0x24 R/W 0x40000000 SPI Clock Control Register
PCLKCFG3 0x28 R/W 0x40004000 UART1/UART0 Clock Control Register
PCLKCFG4 0x2C R/W 0x40004000 Timer T-Clock Control Register
PCLKCFG5 0x30 R/W 0x40004000 Timer X-Clock/Z-Clock Control Register
PCLKCFG6 0x34 R/W 0x40004000 DAI0/ADC Clock Control Register
PCLKCFG7 0x38 R/W 0x00080000 DAI1 Clock Control Register
PCLKCFG8 0x3C R/W 0x40004000 CIF Scaler Clock Control Register
PCLKCFG9 0x40 R/W 0x40000000 LCD Clock Control Register
3-2
BUS Clock Control Register (CLKCTRL) 0x80004000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
XE 0 CB 0 CCKDIV[3:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 BCKDIV[7:0] 0 CKSEL[2:0]
XE [31] XIN Oscillator Enable Bit

0 XIN Oscillator Disabled
1 XIN Oscillator Enabled
CB [29] CPU Clock(FCPU) Selection Bit

1 FCPU = FBUS
CCKDIV [19:16] CPU Clock(FCPU) Divider

N FCPU = FBUS + ((FSYS - FBUS) * (CCKDIV + 1)) / 16
BCKDIV [11:4] Bus Clock(FBUS) Divider

N FBUS = FSYS / (BCLKDIV + 1), N must be >= 1
CKSEL [2:0] System Clock(FSYS) Selection Bits

0 Direct output from PLL0
2 Divided output from PLL0
4 XIN from external main-oscillator ( shared by UTMI clock )
5 Divided output from XIN
6 XTIN from external sub-oscillator ( shared by RTC )
7 Divided output from XTIN
3-3
PLL0 Configuration Register (PLL0CFG) 0x80004004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PD 0 S[1:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M[7:0] 0 P[5:0]
PD [31] PLL Power Down Enable

0 PLL Enabled
1 PLL Disabled
S [17:16] Post Divisor

0~3 Post divisor ( s = S )
M [15:8] Main Divisor

1 ~ 248 Main Divisor ( m = M + 8 )
P [5:0] Pre Divisor

1 ~ 62 Pre Divisor ( p = P + 2 )
z Fvco = ( m * Fin ) / ( p ) : 100MHz ~ 300MHz

z Fout = Fvco / ( 2 ^ s ) : 50MHz ~ 300MHz
PLL1 Configuration Register (PLL1CFG) 0x80004008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
PD 0 S[1:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
M[7:0] 0 P[5:0]
PD [31] PLL Power Down Enable

0 PLL Enabled
1 PLL Disabled
S [17:16] Post Divisor

0~3 Post divisor ( s = S )
M [15:8] Main Divisor

1 ~ 248 Main Divisor ( m = M + 8 )
P [5:0] Pre Divisor

1 ~ 62 Pre Divisor ( p = P + 2 )
z Fvco = ( m * Fin ) / ( p ) : 100MHz ~ 300MHz

z Fout = Fvco / ( 2 ^ s ) : 50MHz ~ 300MHz
3-4
Divider Control Register (CLKDIVC) 0x8000400C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
P0E P0P 0 P0DIV[4:0] P1E P1P 0 P1DIV[4:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
XE XP 0 XDIV[4:0] XTE XTP 0 XTDIV[4:0]
P0E/P1E [31, 23] PLL 0/1 Divider Enable

0 PLL 0/1 Divider Disabled
1 PLL 0/1 Divider Enabled
P0P/P1P [30, 22] PLL 0/1 Post Divider Enable

0 Post Divider Disabled
1 Post Divider Enabled
P0DIV[4:0] [28:24] PLL 0 Divisor

P1DIV[4:0] [20:16] PLL 1 Divisor
0 ~ 31 Post Divisor
z Fp0div = Fpll0 / ((P0DIV+1) * 2^P0P)
z Fp1div = Fpll1 / ((P1DIV+1) * 2^P1P)
XE [15] XIN Divider Enable

0 XIN Divider Disabled
1 XIN Divider Enabled
XP [14] XIN Post Divider Enable

XDIV[4:0] [12:8] XTIN Divisor

0 ~ 31 Post Divisor
z Fxdiv = Fxin / ((XDIV+1) * 2^XP)
XE [7] XTIN Divider Enable

0 XTIN Divider Disabled
1 XTIN Divider Enabled
XTP [6] XTIN Post Divider Enable

XTDIV[4:0] [4:0] XTIN Divisor

0 ~ 31 Post Divisor
z Fxtdiv = Fxtin / ((XTDIV+1) * 2^XTP)
3-5
MODE Control Register (MODECTR) 0x80004010

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 PDCK PD 0 HALT
PDCK [9] Power Down Wakeup Clock Selection Bit

0 XTIN Selected
1 XIN Selected
PD [8] Power Down Mode

0 Stay in Normal Mode
1 Enter Power Down Mode
HALT [0] Halt Mode

0 Stay in Normal Mode
1 Enter Halt Mode
z The function of halt mode is same as waiting-for-interrupt described in ARM946ES

technical reference manual or user manual.
3-6
Bus Clock Mask Control Register (BCLKCTR) 0x80004014

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BCLKEN[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BCLKEN[15:00]
BCLKEN[31:00] Bus Clock Enable Bits

0 (for each bit) Disable the Bus Clock for Corresponding Controller
1 (for each bit) Enable the Bus Clock for Corresponding Controller
Corresponding Controller for For Each Bits

0 DAI Controller 1 Interrupt Controller
2 Timer 3 GPIO
4 USB2.0 Device 5 UART Controller Channel 0
6 7 I2C Controller
8 9 ECC Controller
10 ADC 11 SAD Calculator
12 3 Channel DMA Controller 13 LCD Controller
14 JPEG Codec 15 RTC
16 NAND Flash/LCD/HDD Controller 17 SD/MMC Controller
18 Graphic 2D 19 Host Interface Controller
20 IDE Controller 21 Camera Interface
22 USB Interface 23 UART Controller Channel 1
24 SPI Slave Interface Controller 25
26 27
28 29
30 31
3-7
Soft-Ware Reset Register (SWRESET) 0x80004018

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SWRESET [31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SWRESET[15:00]
SWRESET[31:00] Software Reset Control Register

0 (for each bit) Not Reset
1 (for each bit) Reset
These Bits are automatically cleared.
Corresponding Controller for For Each Bits

0 DAI Controller 1 Interrupt Controller
2 Timer 3 GPIO
4 USB2.0 Device 5 UART Controller Channel 0
6 7 I2C Controller
8 9 ECC Controller
10 ADC 11 SAD Calculator
12 3 Channel DMA Controller 13 LCD Controller
14 JPEG Codec 15 RTC
16 NAND Flash Controller 17 SD/MMC Controller
18 Graphic 2D 19 Host Interface Controller
20 HDD Controller 21 Camera Interface
22 USB Interface 23 UART Controller Channel 1
24 SPI Slave Interface Controller 25 Memory Scaler
26 Main Bus Components 27 External Memory Controller
28 Internal Memory Controller 29 DTCM Interface
30 31 ARM
3-8
Peri-Clock Configuration Register (PCLKCFGX) 0x8000401C ~ 0x80004040

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN1 SEL1[2:0] P1 DIV1[10:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN0 SEL0[2:0] P0 DIV0[10:0]
z EN1/SEL1/P1/DIV1 : Peripheral Clock 1 (PCLK1)

z EN0/SEL0/P0/DIV0 : Peripheral Clock 0 (PCLK0)
EN1/EN0 [31, 15] Clock Divider Enable Bit

0 Disabled
1 Enabled
SEL1[2:0] [30:28] Clock Source Selection Bits

SEL0[2:0] [14:12]
4 XIN from external main oscillator
6 XTIN from external sub oscillator
P1/ P0 [27, 11] Post Divider Enable Bit

0 Disabled
1 Enabled
DIV1[10:0] [26:16] Divisor

DIV0[10:0] [10:0]
0 ~ 2047 Fout = Fselected / ( ( DIV + 1 ) * 2 ^ P)
3-9
Peri-Clock Configuration Register (PCLKCFG0) 0x8000401C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN1 SEL1[2:0] P1 DIV1[10:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
z EN1/SEL1/P1/DIV1 : SDRAM Refresh Clock(REFCLK)
EN1 [31] Clock Divider Enable Bit

0 Disabled
1 Enabled

P1 [27] Post Divider Enable Bit

0 Disabled
1 Enabled
DIV1[10:0] [26:16] Divisor

3-10
Peri-Clock Configuration Register (PCLKCFG1) 0x80004020

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN1 SEL1[2:0] P1 DIV1[10:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
z EN1/SEL1/P1/DIV1 : I2C Controller Clock(ICLK)

0 Disabled
1 Enabled


0 Disabled
1 Enabled
DIV1[10:0] [26:16] Divisor

3-11

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN1 SEL1[2:0] P1 DIV1[10:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
z EN1/SEL1/P1/DIV1 : SPI Slave Interface Clock(SCLK)

0 Disabled
1 Enabled


0 Disabled
1 Enabled
DIV1[10:0] [26:16] Divisor

3-12

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN1 SEL1[2:0] P1 DIV1[10:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN0 SEL0[2:0] P0 DIV0[10:0]
z EN1/SEL1/P1/DIV1 : UART Controller Channel 1 Clock(UT1CLK)

z EN0/SEL0/P0/DIV0 : UART Controller Channel 0 Clock(UT0CLK)

0 Disabled
1 Enabled

SEL0[2:0] [14:12]

0 Disabled
1 Enabled
DIV1[10:0] [26:16] Divisor

DIV0[10:0] [10:0]
3-13

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN1 SEL1[2:0] P1 DIV1[10:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
z EN1/SEL1/P1/DIV1 : Timer T-Clock(TCLK)
EN1/EN0 [31] Clock Divider Enable Bit

0 Disabled
1 Enabled

P1/ P0 [27] Post Divider Enable Bit

0 Disabled
1 Enabled
DIV1[10:0] [26:16] Divisor

3-14

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN1 SEL1[2:0] P1 DIV1[10:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN0 SEL0[2:0] P0 DIV0[10:0]
z EN1/SEL1/P1/DIV1 : Timer Z-Clock(ZCLK)

z EN0/SEL0/P0/DIV0 : Timer X-Clock(XCLK)

0 Disabled
1 Enabled

SEL0[2:0] [14:12]

0 Disabled
1 Enabled
DIV1[10:0] [26:16] Divisor

DIV0[10:0] [10:0]
3-15

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN1 SEL1[2:0] P1 DIV1[10:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN0 SEL0[2:0] P0 DIV0[10:0]
z EN1/SEL1/P1/DIV1 : DAI Controller Clock(DCLK0)

z EN0/SEL0/P0/DIV0 : ADC Clock(ACLK)

0 Disabled
1 Enabled

SEL0[2:0] [14:12]

0 Disabled
1 Enabled
DIV1[10:0] [26:16] Divisor

DIV0[10:0] [10:0]
3-16

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 DSEL EN SEL[2:0] DVM
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CNT[15:0]
z DAI Controller Clock(DCLK1)
DSEL [21] DAI Clock Selection Bit

0 DAI Clock is DCLK0(PCLKCFG6)
1 DAI Clock is DCLK1(PCLKCFG7)
EN [20] DAI Clock 1 (DCLK1) Enable Bit

0 DAI Clock 1 Disable
1 DAI Clock 1 Enable
SEL[2:0] [19:17] Clock Source Selection Bits

DVM [16] DCO/Divider Mode Selelction Bits

0 DCO Mode
1 Divider Mode
CNT[15:0] [15:0] Divisor

0 ~ 65535 Fout = Fselected * (CNT + 1) / 2^16 : DCO Mode
Fout = Fselected / (CNT + 1) : Divider Mode
3-17

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN1 SEL1[2:0] P1 DIV1[10:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
EN0 SEL0[2:0] P0 DIV0[10:0]
z EN1/SEL1/P1/DIV1 : CIF Scaler Clock(CIFSCLK)

z EN0/SEL0/P0/DIV0 : CIF Master Clock(CIFMCLK)

0 Disabled
1 Enabled

SEL0[2:0] [14:12]

0 Disabled
1 Enabled
DIV1[10:0] [26:16] Divisor

DIV0[10:0] [10:0]
3-18

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
EN1 SEL1[2:0] P1 DIV1[10:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0
z EN1/SEL1/P1/DIV1 : LCD Clock Controller Clock(LCDCLK)
EN1/EN0 [31] Clock Divider Enable Bit

0 Disabled
1 Enabled

P1/ P0 [27] Post Divider Enable Bit

0 Disabled
1 Enabled
DIV1[10:0] [26:16] Divisor

3-19
3.3 Clock Change Operation
An example of the timing diagram for changing the clock is shown below – Figure 3.2
3 ~ 4 Cycles
CPUCLK
CKSEL 4 0 2
3 Cycles 3 Cycles
Change Event from ‘SLOW’ Clock to ‘FAST’ Clock Change Event from ‘FAST’ Clock to ‘SLOW’ Clock
Figure 3.2 Clock Change Timing Diagram
An example shows two changing sequences. The first sequence is for changing from slower to
faster frequency.
When the CPU write the ‘CKSEL’ register bits with specified value ( ‘0’ in this example ), the
glitch-free circuit in the CKC hardware first stops the current clock after 3 clock cycles. And then
in the 3 clock period, the clock multiplexor changes from the current clock to the next clock.
Finally, the wake-up circuits enables the clock output. The changing sequence from ‘faster’ to
‘slower’ clocks is same procedure.
3.3.1 Configuration of Peripheral Clocks
The Figure 3.3 shows the configuration procedure for peripheral clock.
The programmer should take care of some cautions in configuring the peripheral clock for
corresponding hardware. (ex, I2C, DAI, etc.)
The controller should be in reset state by setting the SWRESET bit before configuring the
hardware clock and configuring the corresponding ports. If you configure the clock and ports in
not-reset state, which is not-initialized state, the unexpected operations can occur.
The hardware starts operating by clearing the SWRESET bit after the configuration for the clock
and ports of corresponding controller.
If you want to close the hardware operation, you should make the controller into reset-state by
SWRESET bit and stop the clock and release the port.
If the controller is in reset-state (SWRESET=’1’), the program can’t access the control register for
corresponding hardware.
3-20
If set the SWRESET bit, the

Set SWRESET for Controller
controller goes to reset state.
Configure the Corresponding Ports If configures the ports in not-

reset state, the unexpected
operation would be occurred.
Enable the Bus Clock (HCLK)
Enable the Peripheral Clock (PCLK)

1. Disable PCK
2. Sets the divider value
3. Enable PCK
Reset SWRESET for Controller
The controller starts

operating at this time.
Figure 3.3 Peripheral Clock Configuration Procedure
3.3.2 Reference PMS Table for Target Frequency
The Table 3.2 lists the reference PMS value for corresponding target frequency.
TBD
Table 3.2 Reference PMS Table
3.3.3 Enter Halt Mode
The timing diagram of entering halt mode is shown below, Figure 3.4.
To enter the halt mode, all you do is writing the ‘1’ into ‘HALT’ bit.
If the program sets the ‘HALT’ bit, the halt mode controller stops the CPU clock after 3 clock
cycles. After then, the CPU can’t access the bus, TCM, and cache components any more. This
causes that the clocks to CPU would be stopped, the processor do not operate any more, and the
power consumption could be reduced.
But this mode is not recommended because all the correlated operations between cache and bus
components are not proven yet.
The ARM946ES core has the same function, the waiting-for-interrupt function described in
ARM946ES technical reference manual is to halt the processor core and wait until IRQ or FIQ
interrupt. In this mode, the internal clock does not propagate to reduce the power consumption.
3-21
3.3.4 Exit Halt Mode
The timing diagram of exit halt mode is shown below, Figure 3.4.
Entering the Halt Mode Exit the Halt Mode
CPUCLK
Interrupt
HALT Normal Mode Halt Mode
Service Routine
Normal Mode
3 Cycles
3 Cycles
Halt Event from CPU ( Program )
IRQ / FIQ
Wakeup Event by IRQ or FIQ
Figure 3.4 Timing Diagram to Enter and Exit Halt Mode
The only way to exit halt mode is that the IRQ or FIQ interrupt occur. In halt mode, the FIQ or
IRQ interrupt wakes up the halt-mode controller and enables the CPU clocks.
After enabling the CPU clock, the processor in halt mode goes to interrupt service routine and
goes to normal mode after the interrupt service routine. And you can re-enter the halt mode when
no jobs to process.
3.3.5 Enter Power-Down Mode
The timing diagram of entering power-down mode is shown below, Figure 3.5.
In the power-down mode, all the on-chip clocks are disabled including main oscillator (XIN). To
enter the power-down mode, all you do is set the ‘PWRDN’ bit by software.
The sequence for entering the power-down mode is as follows.
1. Changes the CPU clock with XIN or XTIN

2. Sets the selection bit for power-down clock, XIN or XTIN.
3. Sets the ‘PWRDN’ bit.
Once the ‘PWRDN’ bit is set, the CKC power-down controller disables the oscillator after 1.5 or
2.5 cycles. After some cycles, the main crystal does not oscillate any more until the external
interrupt.
In the power-down mode, the power consumption is lowest among the various powered-on
operating modes. But, the wake-up time is longest.
If you selected the XTIN with power-down mode clock, the XTIN oscillator is not disabled
because the XTIN oscillator is always turned-on.
3-22
3.3.6 Exit Power-Down Mode
The timing diagram of exit power-down mode is shown below, Figure 3.5.
Entering the Power-Down Mode Exit the Power-Down Mode
XIN
Interrupt
PWRDN Normal Mode PWRDN
Service Routine
Normal Mode
3 Cycles
Halt Event from CPU ( Program ) Clear by Software
XINEN
XIN Disabled XIN Re-Enabled
EINT
Wakeup Event by External Interrupt
Figure 3.5 Timing Diagram of Enter and Exit Power-Down Mode
The only way to exit the power down mode is external interrupt, which does not controlled by
oscillator (ex, key, host, etc).
The external interrupt wakes up the power-down controller in CKC and enables the main
oscillator(XIN). The clocks from main oscillator goes through the CKC blocks via on-chip clock-
noise filter, which consumes the long wake-up time, and the processor starts interrupt service.
3-23
RTC (Real Time Clock)
Multimedia Application Processor RTC
4 RTC
4.1 Overview
The Real Time Clock (RTC) unit can operate by the backup battery although
the system power turns off. The RTC transmits data to CPU as BCD (binary
coded decimal) values. The data includes second, minute, hour, date, day of
the week, month, and year. The RTC unit works with an external 32.768kHz
crystal and also can perform the alarm function. The block diagram is shown
in Figure 4.1.
Features
z Clock and calendar functions (BCD display): seconds, minutes, hours,
date, day of week, month, year
z Leap year generator
z Wake-up (PMWKUP) signal generation: support on the power down
mode (PWDN)
z Alarm interrupt (ALMINT) in normal operation mode
z Power Supply Voltage: System power supply(3.0V, 1.2V), Backup
battery (3.0V)
RTC
RTCEXTAL1
RTCXTAL1 Oscillator and Reset Register Leap Year Generator
Clock Divider
RTCOSC
SEC MIN HOUR DATE DAY MON YEAR
PWDN
PRI Control Register
Alarm Generator PMWKUP
& Control
ALMINT
RTC Internal Module Bus
APB Interface
AMBA APB(Advanced Peripheral Bus)
Figure 4.1 RTC Block Diagram
4-1
4.2.3 System Clock Frequency Control
The leap year generator calculates which the last date of each month is 28,29,30 or 31
that is based on data from BCDDAY, BCDMON, and BCDYEAR. This also
considers leap years in deciding the last date. A 16 bit counter can just represent four
BCD digits, so it can decide whether any year is a leap year or not.
4.2.4 System Power Operation
It is required to set bit 1 of the RTCCON register for interfacing between CPU and
RTC logic. An one second error can occur when the CPU reads or writes data into
BCD counters and this can cause the change of the higher time units. When the CPU
reads/writes data to/from the BCD counters, another time unit may be changed if
BCDSEC register is overflowed. To avoid this problem, the CPU should reset
BCDSEC register to 00h. The reading sequence of the BCD counters is BCDYEAR,
BCDMON, BCDDATE, BCDDAY, BCDHOUR, BCDMIN, and BCDSEC. It is
required to read it again from BCDYEAR to BCDSEC if BCDSEC is zero.
4.2.5 Backup Battery Operation
The RTC logic is driven by backup battery if the system power turns off. The
interfaces of the CPU and RTC logic are blocked and the battery only drives the
oscillation circuit and the BCD counters to minimize power dissipation.
4.2.6 Alam Function
The RTC generates alarm signal at specified time in the normal operation mode. In
normal operation mode, the alarm interrupt (ALMINT) is activated. The RTC alarm
register, RTCALM, determines the alarm enable and the condition of the alarm time
setting.
4.2.7 Round Reset Function
The round reset function can be performed by the RTC round reset register, RTCRST.
You can select the round boundary (30, 40, or 50 sec) of the second carry generation
and the second value is rounded to zero value in the round reset operation. For
example, when the current time is 23:37:47 and the round boundary is selected as 40
sec, the round reset operation changes the current time with 23:38:00.
4-2
4.3 RTC Operation
4.3.1 Boot-Up Sequence
Figure 4.2 shows how to initialize register of RTCINT block ( RTCALM, RTCIM,
RTCPEND ).
RTCCON reg. Reset
RTCWEN of RTCCON reg. <= 1'b1 RTC Block Write Enable Bit Setting
INTWREN of INTCON reg. <= 1'b1 RTCINT Block Write Enable Bit Setting
PWDN of RTCIM reg. <= 1'b0 Normal Operation Mode Setting
- RTCALM Initialization. RTCINT Block Initialization

- RTCIM Initialization.
- RTCPEND Initialization
INTWREN of INTCON reg. <= 1'b0 RTCINT Block Write Enable Bit Clear
RTCWEN of RTCCON reg. <= 1'b0 RTC Block Write Enable Bit Clear
Figure 4.2 Boot-Up Sequence
4.3.2 RTC Time Setting
Figure 4.3 shows how to set the time when clock is stopped. This works when the
entire calendar or clock is to be set.
STARTB of RTCCON reg. <= 1'b1

RTC BCD Counter Clock Stop.
CLKRST of RTCCON reg. <= 1'b1
RTC Divider Circuit Reset
CLKRST of RTCCON reg. <= 1'b0
Set BCDSEC, BCDMIN, BCDHOUR,

BCDDATE, BCDDAY, BCDMON and BCD Counter Setting
BCDYEAR
STARTB of RTCCON reg. <= 1'b0

RTC BCD Counter Clock Active
RTCWEN of RTCCON reg. <= 1'b0
Figure 4.3 The RTC Time Setting Sequence
4-3
4.3.3 RTC Alarm Time Setting
Figure 4.4 shows how to set Alarm Time.

Alarms can be generated using the seconds, minutes, hours, day of week, date, month,
year or any combination of these.
Set RTCALM, ALMSEC, ALMMIN,

Alarm Time Setting
ALMHOUR, ALMDATE, ALMDAY,
Alarm Enable Setting
ALMMON and ALMYEAR
Figure 4.4 RTC Alarm Time Setting Sequence
4.3.4 RTCPEND Clear

Figure 4.5 shows how to Clear RTC interrupt
There are two types of interrupt.
- Alarm Interrupt(ALMINT).
- Wake-Up Interrupt(WKUPINT).
RTCPEND reg. <= 1'b0 RTCPEND Register Clear
Figure 4.5 PEND Clear Sequence
4-4
4.3.5 RTC Operation
System Power On
Boot-Up Sequence *) Figure 16.2
RTC Time Setting Sequence *) Figure 16.3
Alarm Function Use ?
- Alarm Interrupt
- Wake-Up Interrupt
Normal Operation - PM Wake-Up in Power Off Mode
RTC Alarm Time Setting Sequence *) Figure 16.4
- INTMODE[1:0] of RTCIM reg. Setting INTMODE[1:0] of RTCIM reg. Setting :

- WKUPMODE of RTCIM reg. Setting Alarm Interrupt Mode Selection
- PWDN of RTCIM reg. Setting :
Wake – Up Mode Setting
RTCWEN of RTCCON reg. <= 1'b0 :

RTC Block Write Enable Bit Clear
- INTWREN of INTCON reg. <= 1'b0 :
RTCINT Block Write Enable Bit Clear
AIOUTEN of RTCCON reg. <= 1'b1 :

ALMINT Output Enable Bit Setting
- RTCWEN of RTCCON reg. <= 1'b0 :
RTC Block Write Enable Bit Clear
WKUPINT or
PMWKUP ?
PM Wake-Up use ! Wake-Up Interrupt use !

- WUOUTEN of RTCCON reg. <= 1'b1 :
System Power Off
WKUPINT Output Enable Bit Setting
: Power Down Mode
Wait Wake-Up Wait Interrupt
YES! Alarm Time NO! Alarm Time

= RTC Time = RTC Time
NO! YES!
*) Figure 16.5 RTCPEND Clear Sequence

YES! NO!
System Power On
Figure 4.6 RTC Operation Process Flow Chart.
4-5
4.3.6 Crystal Oscillator Circuit
Crystal oscillator circuit constants (recommended values) are shown in Table 4.1, and
the RTC crystal oscillator circuit in Figure 4.7.
Table 4.1 Recommended Oscillator Circuit Constants

fosc Cin Cout
32.768 kHz from 10 pF to 22 pF from 10 pF to 22 pF
User
Chip
RTCEXTAL1
Cin
Rf
Crystal 10 Mega Ohm
XT
Cout RTCXTAL1
Notes: 1. Select either the Cin or Cout side for frequency adjustment variable capacitor according to
requirements such as frequency range, degree of stability, etc.
2. Built-in registance value Rf(Typ value) = 10 Mega Ohm
3. Cin and Cout values include floating capacitance due to writing. Take care when using a
ground plane.
4. The crystal oscillation setting time depends on the mounted circuit constants, floating
capacitance, etc., and should be decided after consultation with the crystal resonator
manufacturer.
5. Place the crystal resonator and load capacitance Cin and Cout as close as possible to
the chip. (Correct oscillation may not be possible if there is externally included noise in
RTCEXTAL1 and RTCXTAL1 pins.)
6. Ensures that the crystal resonator connection pin (RTCEXTAL1, RTCXTAL1) wiring is
routed as far away as possible from other power lines (except GND) and signal lines.
Figure 4.7 Example of Crystal Oscillator Circuit Connection
4-6
4.4 Programmer’s model
4.4.3 Register memory map
Table 4.2 RTC Register Map (Base Address = 0x8000B000)

Register Address R/W Description Reset value
RTCCON 0x00 R/W RTC Control Register 0x00
INTCON 0x04 R/W RTC Interrupt Control Register -
RTCALM 0x08 R/W RTC Alarm Control Register -
ALMSEC 0x0C R/W Alarm Second Data Register -
ALMMIN 0x10 R/W Alarm Minute Data Register -
ALMHOUR 0x14 R/W Alarm Hour Data Register -
ALMDATE 0x18 R/W Alarm Date Data Register -
ALMDAY 0x1C R/W Alarm Day of Week Data Register -
ALMMON 0x20 R/W Alarm Month Data Register -
ALMYEAR 0x24 R/W Alarm Year Data Register -
BCDSEC 0x28 R/W BCD Second Register -
BCDMIN 0x2C R/W BCD Minute Register -
BCDHOUR 0x30 R/W BCD Hour Register -
BCDDATE 0x34 R/W BCD Date Register -
BCDDAY 0x38 R/W BCD Day of Week Register -
BCDMON 0x3C R/W BCD Month Register -
BCDYEAR 0x40 R/W BCD Year Register -
RTCIM 0x44 R/W RTC Interrupt Mode Register -
RTCPEND 0x48 R/W RTC Interrupt Pending Register -
4-7
4.4.4 Register Description

RTC Control Register (RTCCON) 0x8000B000
RTCCON register consists of 8-bits such as STARTB that controls to run the
normal counters, RTCWEN that controls the read/write enable of the BCD registers,
CLKSEL, CNTSEL, and CLKRST for BCD counters testing.
RTCWEN bit controls all interfaces between the CPU and the RTC, so it should be
set to '1' in an initialization routine to enable data transfer after a system reset. Instead
of working BCD with 1Hz, CLKSEL bit enables the operation of BCD counters with
an external clock which is applied through the pin EXTAL1 to the test BCD counters.
CNTSEL bit converts the dependent
operation of BCD counters into independent counters for the test. CLKRST resets the
frequency divided logic in the RTC.
OSCEN bit controls the path from input of Crystal to the output of divider logic. If
this bit is high, the output of divider is 1 Hz clock. To purpose of testing that
oscillator circuit and divider block, this bit is implemented.
INTWREN bit controls the path from the RTCIF Block to the RTCINT Block.
Table 4.3 RTC Control Register (RTCCON)

RTCCON Bit Description Initial State
STARTB [0] RTC start bit 0
0: RUN 1: Halt
RTCWEN [1] RTC write enable bit 0
0: Disable 1: Enable
CLKSEL [2] BCD counter test clock set bit 0
0: EXTAL1 divided clock (1 Hz)
1: Reserved (EXTAL1: 32.768 kHz)
CNTSEL [3] BCD count test type set bit 0
0: Merge BCD counters
1: Reserved (Separate BCD counters)
CLKRST [4] RTC clock count set bit 0
0: No reset 1: reset
OSCEN [5] Oscillator and Divider circuit test enable bit 0
AIOUTEN [6] Alarm Interrupt Output Enable 0
WUOUTEN [7] Wake Up Output Enable 0
4-8
RTC Interrupt Control Register (INTCON) 0x8000B004

Table 4.4 RTC Interrupt Control Register (INTCON)
INTCON Bit Description Initial State
INTWREN [0]
Interrupt Block Write Enable bit Undef.
STATUS [2:1] User Define Status Register Undef.
*)To Write INTCON register, you must be set RTCWEN ( RTCCON[1] ).
RTC Alarm Control Register (RTCALM) 0x8000B008

RTCALM register determines the alarm enable and the condition of the alarm time
setting. Note that RTCALM register generates the alarm signal through ALMINT in
normal operation mode.
Alarms can be generated using the seconds, minutes, hours, day of week, date, month,
year or any combination of these. Set the ALMEN bit (bit 7) in the register on which
the alarm is placed to "1", and then set the alarm time. Clear the ALMEN bit in the
register on which the alarm is placed to "0".
Table 4.5 RTC Alarm Control Register (RTCALM)

RTCALM Bit Description Initial State
SECEN [0] Second alarm enable bit Undef.
0 : Disable 1 : Enable
MINEN [1] Minute alarm enable bit Undef.
HOUREN [2] Hour alarm enable bit Undef.
DATEEN [3] Date alarm enable bit Undef.
DAYEN [4] Day of week alarm enable bit Undef.
ALMEN [5] Alarm global enable bit Undef.
0: Disable 1 : Enable
*)To Write RTCALM register, you must be set RTCWEN ( RTCCON[1] ) and
INTWREN ( INTCON[0] )
To Read RTCALM register, you must be set INTWREN ( INTCON[0] ).
Alarm Second Data Register (ALMSEC) 0x8000B00C

Table 4.6 Alarm Second Data Register (ALMSEC)
ALMSEC Bit Description Initial State
SECDATA [6:0]
BCD value for alarm second bits Undef.
[3:0] bit is from 0 to 9
*)To Write ALMSEC register, you must be set RTCWEN ( RTCCON[1] ) and
To Read ALMSEC register, you must be set INTWREN ( INTCON[0] ).
4-9
Alarm Minute Data Register (ALMMIN) 0x8000B010

Table 4.7 Alarm Minute Data Register (ALMMIN)
ALMMIN Bit Description Initial State
MINDATA [6:0] BCD value for alarm second bits Undef.
*)To Write ALMMIN register, you must be set RTCWEN ( RTCCON[1] ) and
To Read ALMMIN register, you must be set INTWREN ( INTCON[0] ).
Alarm Hour Data Register (ALMHOUR) 0x8000B014

Table 4.8 Alarm Hour Data Register (ALMHOUR)
ALMHOUR Bit Description Initial State
HOURDATA [5:0] BCD value for alarm hour bits Undef.
*)To Write ALMHOUR register, you must be set RTCWEN ( RTCCON[1] ) and
To Read ALMHOUR register, you must be set INTWREN ( INTCON[0] ).
Alarm Date Data Register (ALMDATE) 0x8000B018

Table 4.9 Alarm Date Data Register (ALMDATE)
ALMDATE Bit Description Initial State
DATEDATA [5:0] BCD value for alarm date, from 0 to 28, Undef.
29, 30, 31 (decimal: 01 ~ 31)
*)To Write ALMDATE register, you must be set RTCWEN ( RTCCON[1] ) and
To Read ALMDATE register, you must be set INTWREN ( INTCON[0] ).
4-10
Alarm Day of Week Data Register (ALMDAY) 0x8000B01C

Table 4.10 Alarm Day of Week Data Register (ALMDAY)
ALMDAY Bit Description Initial State
DAYDATA [2:0]BCD value for alarm day bits Undef.
000: Sunday
001: Monday
010: Tuesday
011: Wednesday
100: Thursday
101: Friday
110: Saturday
*)To Write ALMDAY register, you must be set RTCWEN ( RTCCON[1] ) and
To Read ALMDAY register, you must be set INTWREN ( INTCON[0] ).
Alarm Month Data Register (ALMMON) 0x8000B020

Table 4.11 Alarm Month Data Register (ALMMON)
ALMMON Bit Description Initial State
MONDATA [4:0]BCD value for alarm month bits Undef.
[4] bit is from 0 to 1
*)To Write ALMMON register, you must be set RTCWEN ( RTCCON[1] ) and
To Read ALMMON register, you must be set INTWREN ( INTCON[0] ).
Alarm Year Data Register (ALMYEAR) 0x8000B024

Table 4.12 Alarm Year Data Register (ALMYEAR)
ALMYEAR Bit Description Initial State
YEARDATA [15:0]BCD value for alarm year bits Undef.
*)To Write ALMYEAR register, you must be set RTCWEN ( RTCCON[1] ) and
To Read ALMYEAR register, you must be set INTWREN ( INTCON[0] ).
4-11
BCD Second Data Register (BCDSEC) 0x8000B028

Table 4.13 BCD Second Data Register (BCDSEC)
BCDSEC Bit Description Initial State
SECDATA [6:0] BCD value for second bits Undef.
*)To Write BCDSEC register, you must be set STARTB ( RTCCON[0] ) and
RTCWEN ( RTCCON[1] ).
To Read BCDSEC register, you must be set INTWREN ( INTCON[0] ).
BCD Minute Data Register (BCDMIN) 0x8000B02C

Table 4.14 BCD Minute Data Register (BCDMIN)
BCDMIN Bit Description Initial State
MINDATA [6:0] BCD value for minute bits Undef.
*)To Write BCDMIN register, you must be set STARTB ( RTCCON[0] ) and
To Read BCDMIN register, you must be set INTWREN ( INTCON[0] ).
BCD Hour Data Register (BCDHOUR) 0x8000B030

Table 4.15 BCD Hour Data Register (BCDHOUR)
BCDHOUR Bit Description Initial State
HOURDATA [5:0] BCD value for hour bits Undef.
*)To Write BCDHOUR register, you must be set STARTB ( RTCCON[0] ) and
To Read BCDHOUR register, you must be set INTWREN ( INTCON[0] ).
BCD Date Data Register (BCDDATE) 0x8000B034

Table 4.16 BCD Date Data Register (BCDDATE)
BCDDATE Bit Description Initial State
DATEDATA [5:0] BCD value for date bits(decimal : 01 ~ 31) Undef.
*)To Write BCDDATE register, you must be set STARTB ( RTCCON[0] ) and
To Read BCDDATE register, you must be set INTWREN ( INTCON[0] ).
4-12
BCD Day of Week Data Register (BCDDAY) 0x8000B038

Table 4.17 BCD Day of Week Data Register (BCDDAY)
BCDDAY Bit Description Initial State
DATEDAY [2:0] BCD value for date bits Undef.
000 : Sunday
001 : Monday
010 : Tuesday
011 : Wednesday
100 : Thursday
101 : Friday
110 : Saturday
*)To Write BCDDAY register, you must be set STARTB ( RTCCON[0] ) and
To Read BCDDAY register, you must be set INTWREN ( INTCON[0] ).
BCD Month Data Register (BCDMON) 0x8000B03C

Table 4.18 BCD Month Data Register (BCDMON)
BCDMON Bit Description Initial State
MONDATA [4:0] BCD value for month bits Undef.
[4] bit is from 0 to 1
*)To Write BCDMON register, you must be set STARTB ( RTCCON[0] ) and
To Read BCDMON register, you must be set INTWREN ( INTCON[0] ).
BCD Year Data Register (BCDYEAR) 0x8000B040

Table 4.19 BCD Year Data Register (BCDYEAR)
BCDYEAR Bit Description Initial State
YEARDATA [15:0]BCD value for year bits Undef.
*)To Write BCDYEAR register, you must be set STARTB ( RTCCON[0] ) and
To Read BCDYEAR register, you must be set INTWREN ( INTCON[0] ).
4-13
RTC Interrupt Mode Register (RTCIM) 0x8000B044

When the INTMODE bit of RTCIM register is high, and the clock and alarm times
match, "1" is set in the PEND bit of RTCPEND register. The detection of alarm can
be checked with reading the PEND bit.
Table 4.20 RTC Interrupt Mode Register (RTCIM)

RTCIM Bit Description Initial State
INTMODE [1:0]
Interrupt mode selection bit Undef.
x0: Disable alarm interrupt mode.
x1: Enable alarm interrupt mode.
01: Supports on the edge alarm interrupt.
11: Supports on the level alarm interrupt.
WKUPMODE [2] Wakeup mode selection bit Undef.
0: PMWKUP active low
1: PMWKUP active high
PWDN [3] Operation mode selection bit Undef.
0: Normal Operation Mode
1: Power Down Mode
*)To Write RTCIM register, you must be set RTCWEN ( RTCCON[1] ) and
To Read RTCIM register, you must be set INTWREN ( INTCON[0] ).
To generate the alarm interrupt, you must be set INTMODE ( RTCIM[0] = 1 ),
PWDN ( RTCIM [3] = 0 ) and RTCALM register shoud be set properly.
To generate PMWKUP signal, PWDN regiser should be set to normal operation
mode.
RTC Interrupt Pending Register (RTCPEND) 0x8000B048

Table 4.21 RTC Interrupt Pending Register (RTCPEND)
RTCPEND Bit Description Initial State
PEND [0] Interrupt pending enable bit 0
0 : PEND bit is cleared.
1 : PEND bit is pending.
*)To Clear RTCPEND register, you must be set RTCWEN ( RTCCON[1] ) and
To Read RTCPEND register, you must be set INTWREN ( INTCON[0] ).
4-14
DMA Controller
Multimedia Application Processor DMA CONTROLLER
5 DMA CONTROLLER
5.1 Overview
TCC82xx has 3-channel general DMA(gDMA, This DMA is called Centeral DMA sometimes)
controller for data transfer and 1 channel DMA for USB Device (usbDMA). gDMA can be used
to perform high-speed transfers between external memory, on-chip memory, memory-mapped
external devices, and on-chip peripheral module. It’s possible to select channel priority levels with
fixed priority or round-robin priority.
usbDMA is used to perform high-speed transfers between USB device and any other memory
mapped device.
When usbDMA is not used for USB Device, it can be used gDMA .
The block diagram of gDMA and usb DMA controller is in the following figure.
CHANNEL
R e g is te rs EREQ
E x te rn a l 16
R equest
A H B I/F S e le c to r
C o n tro l
s ig n a l
G e n e ra to r
IR Q
S o u rc e / In te rru p t
D e s tin a to n G e n e ra to r
A A d d re s s
H G e n e ra to r
B
B
U D a ta B u ffe r
S C H AN N EL0 ( 8 x 3 2 F ifo )
C H A N N E L1
C H A N N E L2
CHANNEL MUX
C H A N N E L A R B IT E R
Figure 5.1 gDMA Controller Block Diagram
18-1
CHANNEL
R e g is te rs EREQ
E x te rn a l 16
R equest
A H B I/F S e le c to r
C o n tro l
A s ig n a l
H G e n e ra to r
B
IR Q
S o u rc e / In te rru p t
B D e s tin a to n G e n e ra to r
U A d d re s s
S G e n e ra to r
D a ta B u ffe r
( 8 x 3 2 F ifo )
C H A N N E L0
Figure 5.2 usbDMA Controller Block Diagram
18-2
Table 5.1 General DMA Controller Register Map (Base Address = 0x8000E000)
C
H
A
N
N
C
H
A
N
N
C
SPARAM2 0x64/0x68 R/W 0x00000000 Parameter of Source Block
H
A
N
DPARAM2 0x74/0x78 R/W 0x00000000 Parameter of Destination Block
N
Table 5. usbDMA Controller Register Map (Base Address = 0x8000D800)

C SPARAM0 0x04 R/W 0x00000000 Parameter of Source Block
H C_SADR0 0x0C R 0x00000000 Current Address of Source Block
A ST_DADR0 0x10 R/W 0x00000000 Start Address of Destination Block
N DPARAM0 0x14 R/W 0x00000000 Parameter of Destination Block
N C_DADR0 0x1C R 0x00000000 Current Address of Destination Block
E HCOUNT0 0x20 R/W 0x00000000 Initial and Current Hop count
L CHCTRL0 0x24 R/W 0x00000000 Channel Control Register
0 RPTCTRL0 0x28 R/W 0x00000000 Repeate Control Register
18-3
Start Source Address Register (ST_SADR)0x8000nnnn(nnnn=E000/E030/E060/D800)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST_SADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST_SADR[15:0]
This register contains the start address of source memory block for DMA transfer. The transfer
begins reading data from this address.
Start Destination Address Register (ST_DADR)0x8000nnnn(nnnn=E010/E040/E070/D810)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ST_DADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST_DADR[15:0]
This register contains the start address of destination memory block for DMA transfer.
Source Block Parameter Register (SPARAM)0x8000nnnn(nnnn=E004/E304/E064/D804)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SMASK[23:8]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SMASK[7:0] SINC[7:0]
SMASK[23:0] [31:8] Source Address Mask Register

0 non-masked
Masked so that source address bit doesn’t be changed during DMA
1
transfer
Each bit field controls the dedicated bit of source address field. That is, if SMASK[23] is set to 1,
the 28th bit of source address is masked, and if SMASK[22] is set to 1, the 27th bit of source
address is masked, and so on. If a bit is masked, a corresponding bit of address bus is not changed
during DMA transfer. This function can be used to generate circular buffer address.
SINC[7:0] [7:0] Source Address Increment Register

Source address is added by amount of sinc at every write cycles. sinc is
sinc represented as 2’s complement, so if SINC[7] is 1, the source address is
decremented.
The addresses of DMA transfer have 32bit wide, but the upper 4bit of them are not affected
during DMA transfer. If the source or destination address reaches its maximum address space like
0x7FFFFFFF or 0x2FFFFFFF, the next transfer is starting from 0x70000000 or 0x20000000 not
from 0x80000000 or 0x30000000.
Destination Block Parameter Register (DPARAM)0x8000nnnn(nnn=E014/E044/E074/D814)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMASK[23:8]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DMASK[7:0] DINC[7:0]
DMASK[28:0] [31:8] Destination Address Mask Register

0 non-masked
Masked so that destination address bit doesn’t be changed during DMA
1
transfer
Each bit field controls the corresponding bit of source address field. That is, if DMASK[23] is set
to 1, the 28th bit of source address is masked, and if DMASK[22] is set to 1, the 27th bit of
18-4
source address is masked, and so on. If a bit is masked, a corresponding bit of address bus is not
changed during DMA transfer. This function can be used to generate circular buffer address.
DINC[7:0] [7:0] Destination Address Increment Register

Destination address is added by amount of dinc at every write cycles.
dinc dinc is represented as 2’s complement, so if DINC[7] is 1, the
destination address is decremented.
The addresses of DMA transfer have 32bit wide, but the upper 4bit of them are not affected
during DMA transfer. If the source or destination address reaches its maximum address space like
0x7FFFFFFF or 0x2FFFFFFF, the next transfer is starting from 0x70000000 or 0x20000000 not
from 0x80000000 or 0x30000000.
18-5
Current Source Address Register (C_SADR)0x8000nnnn(nnnn=E00C/E03C/E06C/D80C)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C_SADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C_SADR[15:0]
This register contains the current source address of DMA transfer. It represents that the current
transfer read data from this address. This is read only register.
Current Destination Address Register (C_DADR)0x8000nnnn(nnnn=E01C/E04C/E07C/D81C)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C_DADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
C_DADR[15:0]
This register contains current destination address of DMA transfer. It represents that the current
transfer write data to this address. This is read only register.
HOP Count Register (HCOUNT) 0x8000nnnn(nnn=E020/E050/E080/D820)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
C_HCOUNT[15:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ST_HCOUNT[15:0]
C_HCNT[15:0] Type [31:16] Current Hop Count

cn R Represent cn number of Hop transfer remains
ST_HCNT[15:0] Type [15:0] Start Hop Count

sn R/W DMA transfers data by amount of sn Hop transfers
At the beginning of transfer, the C_HCNT is updated by ST_HCNT register. At the end of every
hop transfer, this is decremented by 1 until it reaches to zero. When this reaches to zero, the DMA
finishes its transfer and may or may not generate its interrupt according to IEN flag of CHCTRL
register.
18-6
Channel Control Register (CHCTRL) 0x8000nnnn(nnn=E024/E054/E084/D824)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DMASEL[15:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CONT DTM SYN HRD LOCK BST TYPE BSIZE WSIZE FLG IEN REP EN
DMASEL[15:0] [31:16] Select Source of DMA Request

Each bit field selects corresponding signal as a source for DMA
non-zero request. If multiple bits of this field are set, all the corresponding signal
can generate DMA request for this channel.
DMASEL[15] Timer
DMASEL[14] UART1 Transmite
DMASEL[13] UART1 Receive
DMASEL[12] LCD controller
DMASEL[11] SD Card
DMASEL[10] ECC controller
DMASEL[09] SPI controller
DMASEL[08] NAND flash controller
DMASEL[07] UART0
DMASEL[06] GSIO
DMASEL[05] I2S Transmite
DMASEL[04] I2S Receive
DMASEL[03] External Interrupt 3
CONT [15] Issue Continuous Transfer

0 DMA transfer begins from ST_SADR / ST_DADR address
DMA transfer begins from C_SADR / C_DADR address
1 It must be used after the former transfer has been executed, so that
C_SADR and C_DADR contain a meaningful value.
DTM [14] Differential Transfer Mode

0 Differential Transfer Mode Disable
Differential Transfer Mode Enable
for WSIZE = 10 and BSIZE = 11:
- 32 bit-to- 16bit transfer
1 - 4 Read(Word Unit) / 8 Write(Half-Word Unit)
for WSIZE = 11 and BSIZE = 11 :
- 16 bit-to- 32bit transfer.
- 8 Read(Half-Word Unit) / 4 Write(Word Unit)
SYNC [13] Hardware Request Synchronization

0 Do not Synchronize Hardware Request.
1 Synchronize Hardware Request.
HRD [12] Hardware Request Direction

0 ACK/EOT signals are issued when DMA-Read Operation.
1 ACK/EOT signals are issued When DMA-Write Operation.
18-7
LOCK [11] Issue Locked Transfer

1 DMA transfer executed with lock transfer
Lock field controls the LOCK signal (refer to AHB specification). When the LOCK is set to 1,
the DMA transfer doesn’t be bothered by other AHB masters like LCD controller, ARM etc. This
field is only meaningful in case of non-burst type transfers.
BST [10] BURST Transfer

0 DMA transfer executed with arbitration.
1 DMA transfer executed with no arbitration. ( burst operation )
Arbitration means that at the end of every HOP transfer, the AHB bus is released from DMA
channel so other master can occupy the bus when that master has requested the bus.
Burst means that once the DMA request occurs, all of transfers are executed without further
DMA requests.
TYPE[1:0] [9:8] Transfer Type

00 SINGLE transfer with edge-triggered detection
11 SINGLE transfer with level-sensitive detection
01 HW transfer
10 SW transfer
In SINGLE Type, After one Hop data transferring DMA checks External DMA Request
(DREQ ) and then if its bit is active , DMA transfers next hop data . DREQ is detected level-
sensitive or edge-triggered by SINGLE transfer TYPE.
The 1 Hop of transfer means 1 burst of read followed by 1 burst of write. 1 burst means 1, 2 or 4
consecutive read or write cycles defined by BSIZE field of CHCTRL register. The Figure 5.2
illustrates the relation among the above transfers.
DMA Transfer
1 Hop of Transfer 1 Hop of Transfer
1 Burst of Read 1 Burst of Write 1 Burst of Read 1 Burst of Write
R R R R W W W W R R R R W W W W
* R : Read cycle for 8,16 or 32bit data

* W : Write cycle for 8,16 or 32bit data
* Arbitration Mode
Figure 5.3 Relation between Hop and Burst Transfers (If burst size is 4.)
Hardware type transfer means that the DMA transfer triggered by external or internal hardware
blocks selected by DMASEL field in CHCTRL register. This field has same mapping with
interrupt enable flag of interrupt controller, so the DMA transfer can be occurred as like as
interrupt is generated.
Software type transfer means that the DMA transfer triggered by EN bit of CHCTRL Register .
When this is set to 1, transfer request signal is generated internally and then the transfer begins
immediately.
Hardware demand type transfer (HW_DEMAND) means that once the DMA request occurs,
DMA checks request signal each hope transfer, and if request signal is set, DMA transfer one
hope’s data. After transferring all hope’s data, DMA operation will be finished.
Figure 5.3 is the example of various types of transfer.
18-8
EREQ
Transefer IDLE 1HOP WAIT 1HOP WAIT 1HOP WAIT
< SINGLE TRANSFER with edge-triggered >
EREQ
Transefer IDLE 1HOP WAIT 1HOP WAIT 1HOP WAIT 1HOP WAIT
< SINGLE TRANSFER with Level Sensitive >
Transefer IDLE 1HOP WAIT 1HOP WAIT 1HOP WAIT 1HOP WAIT 1HOP
< S(H)W TRANSFER with ARBitration >
Transefer IDLE 1HOP 1HOP 1HOP 1HOP 1HOP 1HOP 1HOP
< S(H)W TRANSFER with Burst >
Figure 5.4 The Example Of Various Types of Transfer.
BSIZE[1:0] [7:6] Burst Size

0 1 Burst transfer consists of 1 read or write cycle.
1 1 Burst transfer consists of 2 read or write cycles
WSIZE[1:0] [5:4] Word Size

0 Each cycle read or write 8bit data
1 Each cycle read or write 16bit data
2, 3 Each cycle read or write 32bit data
FLAG Type [3] DMA Done Flag

1 R Represents that all hop of transfers are fulfilled.
1 W Clears FLAG to 0
It does not automatically cleared by another transfer starts, so before starting any other DMA
transfer, user must clear this flag to 0 for checking DMA status correctly.

At the same time the FLAG goes to 1, DMA interrupt request
1
is generated.
To generate IRQ or FIQ interrupt, the DMA flag of IEN register in the interrupt controller must
be set to 1 ahead.
REP [1] Repeat Mode Control

After all of hop transfer has executed, the DMA channel is
0
disabled
The DMA channel remains enabled. When another DMA request has
occurred, the DMA channel start transfer data again with the same
1
manner (type, address, increment, mask) as the latest transfer of that
channel.
18-9
EN [0] DMA Channel Enable

DMA channel is terminated and disabled.
It does not affect the HCOUNT register, so if the current hop counter is
0 not zero when channel is disabled, it is possible that the transfer illegally
starts right after channel is re-enabled. Make sure that HCOUNT is zero
not to continue transfer after channel is re-enabled.
DMA channel is enabled. If software type transfer is selected,
this bit generates DMA request directly, or if hardware type
1
transfer is used, the selected interrupt request flag generate
DMA request.
Repeat Control Register (RPTCTRL) 0x8000nnnn(nnn=E028/E058/E088/D828)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DRI EOT 0 RPTCNT[23:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RPTCNT[15:0]
DRI [31] Disable Repeat Interrupt

DMA Interrupt is occurred when the end of each Repeated DMA
0
operation.
DMA Interrupt occur is occurred when the last DMA Repeated DMA
1
operation
This bit is meaningful when Repeat Mode is enabled.
EOT [30] EOT

EOT signal is occurred when the end of each Repeated DMA operation
0
in HW(including Single) transfer Mode.
EOT Signal is occurred when the last Repeated DMA operation in
1
HW(including Single) transfer Mode.
This bit is meaningful when Repeat Mode is enabled.
RPTCNT[23:0] [23:0] Repeat Count

0 DMA transfer data endlessly.
None zero DMA transfer the number of ( N + 1 ) * HCOUNT data
This bit is meaningful when Repeat Mode is enabled. When this bit is cleared in repeat mode,
DMA will run endlessly. To exit endless repeat mode , clear EN bit of DMACTRL or disable
Repeat Mode. It’s possible to circular transfer using repeat count.
18-10
Channel Configuration Register(CHCONFIG) 0x80000E2C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 IS2 IS1 IS0 0 MIS2 MIS1 MIS0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 SWP2 SWP1 SWP0 0 PRI[2:0] 0 FIX
IS2 [22] Channel 2 Alternate interrupt status

0 No interrupt in channel 2
1 Channel2 Interrupt is occurred
Without regard to Interrupt enable bit(IEN) of channel2, this bit indicates the channel1 interrupt
status.
This bit is automatically cleared when FLAG bit of channel2 is cleared. This bit is read only.

Except for channel difference, This bit is the same as IS2 bit.

Except for channel difference, This bit is the same as IS2 bit.
MIS2 [18] Channel2 Masked Interrupt Status

0 Masked interrupt is not occurred in channel 2
1 Channel2 Masked Interrupt is occurred
This bit is set when channel2 interrupt occurs and interrupt enable bit (IEN) of channel2 is set.

Except for channel difference, This bit is the same as MIS2 bit.

Except for channel difference, This bit is the same as MIS1 bit.
SWP2 [10] Channel2 SWAP Enable bit

0 Do not Swap Channel2 Data.
1 Swap Channel2 Data.
When this bit is set, data to be written to destination address will be swapped.
For example, the 32bit source data which consists of 4bytes {D3,D2,D1,D0} will be stored
{D0,D1,D2,D3} in destination address. The 16bit source data which consists of 2bytes {D1,D0}
will be stored {D0,D1} in destination address.

Except for channel difference, the function controlled by this bit is the same as its SWP2 bit.
18-11

Except for channel difference, the function controlled by this bit is the same as its SWP2 bit.
PRI[2:0] [5:4] Channel Priority

000 CH0 > CH1 > CH2
001 CH0 > CH2 > CH1
010 CH1 > CH0 > CH2
011 CH1 > CH2 > CH0
100 CH2 > CH1 > CH0
101 CH2 > CH0 > CH1
PRI bits is meaningful when fix[0] bit is enabled.
FIX [0] Fixed Priority Operation

0 Round-Robin (Cyclic) Mode.
1 Fixed Priority Mode.
In round-robin mode, Each channel is enabled one by one every one hop transferring.
In Fixed mode, according to PRI bit, the highest channel is serviced first and lower priority
channel is serviced after higher priority channel operation is finished. See Figure 5.4 for more
information.
CH1 CH0
IDLE 1HOP 1HOP CH1 END 1HOP CH0 END IDLE
< 2CHANNEL TRANSFER with Fixed Priority (channel 1 higher priority) >
CH0 CH1 CH0 CH1 CH0
IDLE 1HOP WAIT 1HOP WAIT 1HOP WAIT 1HOP WAIT 1HOP
< 2CHANNEL TRANSFER with Round Robin Priority >
Figure 5.5 Enabled 2Channel Transfer.
Channel Configuration Register(CHCONFIG) 0x8000D82C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 IS0 MIS0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 PD[1:0] 0 SWP0 0 0

Without regard to Interrupt enable bit(IEN) of channel0, this bit indicates the channel1 interrupt
status.

This bit is set when usbDMA interrupt occurs and interrupt enable bit (IEN) of channel0 is set.
18-12
PD[1:0] [13:12] Port Direction

0 Memory (mapped device) to to memory (mapped device)
1 Data transfer form Memory (mapped device) to usb device
2 Data transfer form usb device to Memory (mapped device)
3 Reserved

When this bit is set, data to be written to destination address will be swapped.
For example, the 32bit source data which consists of 4bytes {D3,D2,D1,D0} will be stored
{D0,D1,D2,D3} in destination address. The 16bit source data which consists of 2bytes {D1,D0}
will be stored {D0,D1} in destination address.
18-13
ADC
Multimedia Application Processor ADC
6 ADC
6.1 Overview
The TCC82xx has 2 channel general purpose low-power ADC for battery level detection, key detection, remote
control interface, touch screen interface, etc. It is a CMOS type 10bit A/D converter with 2-channel analog input
multiplexer.
• Resolution : 10-bit
• Maximum Conversion Rate : 500KSPS
• Main Clock : 2.5MHz (Max.)
• Standby Mode
• Input Range : 0.0V ~ VDDA_ADC
IRQ to Interrupt
Controller
ADCDATA/ Read Data DO[9:0]

ADCSTATUS Buffer (x4) EOC
STC
Timing STBY ADC AIN[1:0]
ADCCFG
APB
Control CLK Core
ADCCON/ Command SEL[2:0]

ADCCONA Buffer (x4)
Figure 6.1 ADC Controller Block Diagram
Except for the APB interface, the ADC controller module runs with ADCLK from the Clock Generator module. The
clock input is always divided before sent to the ADC core. The PCLKCFG6 register of Clock Generator and
CLKDIV bits of ADCCFG register must be programmed to get desired frequency. The maximum frequency of CLK
signal in Figure 6.1 must not exceed 2.5MHz.
When one of the ADCCON or ADCCONA register is written with a channel number (SEL[2:0]), the SEL value
is posted to the Command Buffer. The ADC Core starts conversion cycle as long as the Comand Buffer is not
empty. After the conversion cycle is completed, the result is written in Read Data Buffer. The data can be
read from either ADCDATA or ADCSTATUS register. Up to four different SEL values can be posted to the
Command Buffer. When the buffer is full, data written to ADCCON/ADCCONA registers are ignored.
Various operating options can be set by using ADCCFG register.
6-1
6.2 ADC Controller Register Description.
Table 6.1 ADC Controller Register Map (Base Address = 0x8000A000)

ADCCON 0x00 R/W 0x00000018 ADC Control Register
ADCDATA 0x04 R Unknown ADC Data Register
ADCCONA 0x80 R/W 0x00000018 ADC Control Register A
ADCSTATUS 0x84 R/W Unknown ADC Status Register
ADCCFG 0x88 R/W 0x00002400 ADC Configuration Register
6-2
ADC Control Register (ADCCON) 0x8000A000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
*R 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 STB R ASEL[2:0]
*) R = Reseved..
STB Type [4] ADC Standby Select

1 ADC goes to standby mode
R/W
0 ADC starts operating
ASEL[2:0] [2:0] ADC Input Select

n ADINn pin is selected as ADC input signal
ADC Data Register (ADCDATA) 0x8000A004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 ADATA[9:0] FLG
ADATA[9:0] [10:1] ADC Data

adc ADC data = adc
*) All the AD input levels must be within the operable range that is from 0 V to
VDDADC(the main power level of ADC). Do not exceed the limit.
FLG [0] ADC Status Flag

1 Indicate that A/D conversion has finished, data is stable.
0 A/D conversion is on processing, data is unstable
6-3
ADC Control Register A (ADCCONA) 0x8000A080

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
*R 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 STB R ASEL[2:0]
*) This register has the same functionality as that of ADCCON register.
Only the register address is different.
R = Reseved..
ADC Status Register (ADCSTATUS) 0x8000A084

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 WBVCNT[2:0] 0 RBVCNT[2:0] 0 RSELV[2:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 RBDATA[9:0]
Bit Name R/W Reset Description

31 Reserved R 0
30:28 WBVCNT R 0 Command Write Buffer Valid entry count. Up to 4 entries
with different ASEL values can be posted to command buffer.
27 Reserved R 0
26:24 RBVCNT R 0 Read Data Buffer Valid entry count. Up to 4 entries.
23:19 Reserved R 0
18:16 RSEL R X Input channel number for current read data. Valid only if RBCNT
is not zero.
15:10 Reserved R 0
9:0 RBDATA R X Read Buffer Data.
ADC Configuration Register (ADCCFG) 0x8000A088

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLKDIV DLYSTC NEOC 0 FIFOTH IRQE R8 APD SM
Bit Name R/W Reset Description

15:12 CLKDIV R/W 0x2 Clock Divisor Value. ADCLK is divided by ((CLKDIV + 1) * 2).
11:8 DLYSTC R/W 0x4 Delay from SEL to STC (Start of Conversion) in ADC core CLK
count. Whenever SEL value changes, delay is inserted.
7 NEOC R/W 0 For test purpose only. Must be written as “0”
6 Reserved R/W 0
5:4 FIFOTH R/W 0 FIFO Threshold for interrupt assertion. Interrupt will be asserted
only if FIFOTH < (# of Valid Entry).
3 IRQE R/W 0 Interrupt Enable.
2 R8 R/W 0 When this bit is “1”, two LSBs are truncated. (shift right). Only
“ADCSTAUS” register is affected by this bit.
1 APD R/W 0 Auto Power Down Enable. This bit is effective only if SM bit
(described below) is “1”. After conversion cycle is done, the ADC
core is forced to power down mode.
0 SM R/W 0 Single Mode Enable. When disabled (0), ADC conversion cycle
is repeated forever with the input selected by ASEL bits. When
enabled (1), only one cycle is executed.
6-4
TCC82xx
Part 4. Video
Chapter 1. Sensor interface
Chapter 2. LCD controller
Chapter 3. SAD calculator
Chapter 4. Graphic 2D
Chapter 5. JPEG codec
Chapter 6. Scaler
Rev. 0.20
Apr. 24 2006
TCC82xx Preliminary Specification
Multimedia Application Processor PART 4. VIDEO
Revision History

ii
CIF
Multimedia Application Processor CIF
1 Camera Interface
1.1 Overview
The block diagram of Camera Interface (CIF) is shown inFigure 1.1.
The TCC82XX provides camera interface. The features of CIF are
- CCIR 601/656, 4:2:2,YCbCr(YUV)

- 555RGB, 565RGB (16/8 bits bus)
- Convert YUV422 to YUV420 mode
- Skip frame mode
- Packing he image data to 32 bit format
- The overlay, alpha blending
- The image effect mode (only 8 bit input mode)
- The image scaler (ratio : original * 256/target)
- Max. Image : 1600 * 1200 8fps.
- Storing the data using the burst mode (supporting 1, 2, 4, 8 burst)
- 64 depths, 32 bits FIFO * 4 (3 channel fifos and 1 overlay image fifo)
The features of image scaler in CIF are
- Scaling ratio
Upscale : 1 : 4
Downscale : 64 : 1
Each step size is 256 step
- Input image : 1600 x 1200 x 8fps
- Output image 1600 x 1200 x 8fps
- Supporting windowing
The programs can change the following parameters
- The input format of image (Max. : 1600 x 1200)

- Image sizing and windowing (include overlay image)
- Control the transparency of overlay image
- The packing method of the image data
- Variable scaling ratio
- Variable image effect mode
Sepia
Gray
Negative
Embossing
Sketch
Color filter
Inversion Y value….
- CAUTION
If you operate the effect mode, format register of camera (ICPCR1 reg.) is
set 16bit yuv mode. Because architecture of effect block is that input
format is 8 bit YUV(RGB565/555) and output format of effect mode is
only 16 bit YUV mode. Input image format is RGB mode, ‘en’ field of
CR2Y register set ‘1’, then CIF_FMT of figure 1.1 is operated and output
format of CIF_FMT is 8bit YUV mode. Input format is 16bit
mode(RGB/YUV), you can’t use the effect mode.
Preliminary 1-1
Sencor_CLK
Register
PXCLK CIF_CLKCTRL
Bank
SCLK SCLK
CKC_CTRL Register
MCLK
PXCLK
CIF_PACK CIF_Macro CIF_DMA
PACK/UNPAC 32 32
HS HS FIFO_Y DMA_Y
CIF_ONOFF CIF_FMT CIF_SKIP K
CIF_ 32 32
VS VS Windowing FIFO_U DMA_U
Scaler CAP
AHB_BUS
Format_
Sync_pol. Skip_frame CTRL
DATA DATA conv 32 32
Scaling FIFO_V DMA_V
8/16
32 32
Overlay FIFO_OL DMA_OL
Macro_status VS
VS
Status
Figure 1.1 CIF Block Diagram
The image data have several formats. The input data is packed the 32 bit data bus and
stored in the memory. The packing sequence is shown in Figure 1.2. The packing
method is composed 2 methods that are separated and non-separated from each
channel. If channel data isn’t separated, the sequence of channels is shown in Table 1.1.
This sequence is applied to overlay images..
The CIF have the interrupt signal that is shown a t the storing 1 frame image
pixel clock
HS
Y[7:0] Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
UV[7:0] U0 V0 U2 V2 U4 V4 U6 V6 U8 V8
MSB LSB MSB LSB

Y3 Y2 Y1 Y0 V0 Y1 U0 Y0
U6 U4 U2 U0 V2 Y3 U2 Y2
V6 V4 V2 V0 V4 Y5 U4 Y4
31 0 31 0
Packing at non-separating each
Packing at separating each channel
channel
Figure 1.2 Packing Method
Table 1.1 Packing at non-separating mode
1-2 Preliminary
Stored Image Order (bypass & overlay image)

V0-Y1-U0-Y0 (422YUV)
R1-G1-B1-R0-G0-B0 (565RGB)
0-R1-G1-B1-0-R0-G0-B0 (555RGB)
0-R-G-B / 0-U-Y-V (444 RGB/YUV)
Y1-U1(V0)-Y0-U0(V0) ( 4:2:0 YUV)
y Bayer RGB mode is stored the memory from LSB as the data input sequence.
y The sequence of data is stored from LSB to MSB.
Preliminary 1-3
1.2 Camera Register Descriptions
Table 1.2 CIF Register Map (Base Address = 0x90004000)

ICPCR1 0x00 W/R 0x00000000 Input Image Color/Pattern Configuration
Register 1
656FCR1 0x04 W/R 0x06ff0000 CCIR656 Format Configuration Register 1
656FCR2 0x08 W/R 0x010b CCIR656 Format Configuration Register 2
IIS 0x0C W/R 0x00000000 Input Image Size
FIFOSTATE 0x34 R 0x00000000 FIFO Status Register
CIRQ 0x38 W/R 0x00000000 Interrupt & Status register
OCTRL1 0x3C W/R 0x37000000 Overlay Control 1
OIS 0x4C W/R 0x00000000 Overlay Image Size
COBA 0x58 W/R 0x00000000 Overlay Base Address
CDS 0x5C W/R 0x00000000 Camera Down Scaler
CESA 0x64 W/R 0x00000000 Point Encoding Start Address
CR2Y 0x6C W/R 0x00000000 RGB2YUV Format converter Configuration
CCYA 0x70 R - Current Y Address
CCYU 0x74 R - Current U Address
CCYV 0x78 R - Current V Address
CCLC 0x7C R Current Line count
1-4 Preliminary
Input Image Color/Pattern Configuration Register 1 (ICPCR1) 0x90004000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ON PWD 0 BPS 0 POL SKPF M420
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BP BBS C656 CP PF<1:0> RGBM<1:0> RGBBM<1:0> CS<1:0> 0 BO HSP VSP
ON [31] On/Off on CIF

0 Can’t operate CIF.
1 Operating CIF.
PWD [30] Power down mode in camera

0 Disable
1 Power down mode.
This power down mode is connected the PWDN of camera sensor.
BPS [23] Bypass Scaler

0 Non
1 Bypass
POL [21] PXCLK Polarity

0 Positive edge
1 Negative edge.
SKPF Skip frame

[20:18]
0 Not-skip
1~7 # frame(s) skip.
M420 [15] Format Conv.

00 Not-Convert
10 Converted in odd line skip.
11 Converted in even line skip.
BP [15] Bypass (Non-Separate)

0 Not Bypass (separate)
1 Bypass (non-separate)
BBS [14] Bypass Bus Select

0 When bypass 16 bits mode, MSB 8 bits are stored in first.
1 When bypass 16 bits mode, LSB 8 bits are stored in first.
C656 [13] Convert 656 format

0 Disable
1 Enable
CP [12] Color Pattern
Preliminary 1-5
0 YCbCr(YUV/RGB) color pattern

1 RGB(555,565,bayer) color pattern
PF [11:10] Pattern Format

00 4:4:4 format
01 4:2:2 format
10 4:2:0 format or RGB(555,565,bayer) mode
RGBM [9:8] RGB Mode

00 Bayer RGB mode
01 RGB555 mode
10 RGB565 mode
This mode is operated at RGB mode.
RGBBM [7:6] RGB Bit Mode

00 16 bit mode (4:2:0 YCbCr/YUV. RGB555/565, 4:2:2/4:4:4 format)
01 8 bit disable sync (Non sync-port)
10 8 bit mode (Bayer/555/565RGB), 8 bit enable sync (sync-port)
Color Sequence
CS [5:4]
555RGB 565RGB 4:4:4/4:2:2:/4:2:0 Bayer RGB CCIR656
00 RGB(MG) RGB R/Cb/U first BG->GR YCbYCr
01 RGB(LG) RGB R/Cb/U first GR->BG YCrYCb
10 BGR(MG) BGR B/Cr/V first RG->GB CbYCrY
11 BGR(LG) BGR B/Cr/V first GB->RG CrYCbY
MG/LG of 555RGB item means MSB/LSB 1bit garbage.
The sequence of Bayer RGB means that odd line is BGBGBG… and even line is
GRGRGR…. at 00.
Default value is 00.
BO [2] Bus Order

0 Don’t switch the MSB/LSB 8bit bus.
1 Switch the MSB/LSB 8bit bus.
When 8 bits mode, the 8 bits data bus is connected to MSB 8bit in default.
This bit must be set to ‘1’ in TCC75x.
HSP [1] Horizontal Sync Polarity

0 Active low
1 Active high (default)
VSP [0] Vertical Sync Polarity

0 Active low (default)
1 Active high
1-6 Preliminary
CCIR656 Format Configuration Register 1 (656FCR1) 0x90004004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved PSL<1:0> 0 FPV<7:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SPV<7:0> TPV<7:0>
This register and next register (656FCR1 and 656FCR2) define the configuration of
CCIR656. The figure 1.3 shows that the control signals of this format.
Start of digital line Start of digital active line
HS CCIR601 H signal
EAV SAV
F 0 0 X 8 1 8 1 F 0 0 X C C C
… Y Y Y Y
F 0 0 Y 0 0 0 0 F 0 0 Y B R B
8-bit data
D7
D6 D5 D4 D3 D2 D1 D0
(MSB)
1 1 1 1 1 1 1 1
preamble 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
status 1 F V H P3 P2 P1 P0
•Status word define

•F=‘0’ for field 1, ‘1’ for field 2 (interlace mode. If progressive, this value is ‘0’)
•V=‘1’ during vertical blanking
•H=‘0’ at SAV, ‘1’ at EAV
•Protection bits
•P3=V xor H
•P2=F xor H
•P1=F xor V
•P0=F xor V xor H
Figure 1.3 CCIR-656 Format Diagram
PSL [26:25] Preamble and Status Location

00 The status word is located the first byte of EAV & SAV
01 The status word is located the second byte of EAV & SAV
10 The status word is located the third byte of EAV & SAV
11 The status word is located the forth byte of EAV & SAV
If RGB bit mode is 8 bit disable mode, we must find the location of preamble and status
for getting sync information. The total size of preamble and status is composed 4 bytes
that preamble is 3 bytes and status is 1 byte. This register used to find the location of
status word.
FIELD Description
Preliminary 1-7
First preamble value

FPV [23:16]
Define the first preamble value. Default value is 0x00.
Second preamble value
SPV [15:8]
Define the second preamble value. Default value is 0x00.
Third preamble value
TPV [7:0]
Define the third preamble value. Default value is 0x00.
1-8 Preliminary
CCIR656 Format Configuration Register 2 (656FCR2) 0x90004008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved HB<3:0> 0 VB<3:0>
FIELD Description
Horizontal blank
HB [8:5] In status word, location of ‘H’ and H value at blanking. The MSB 3 bit means
the location of ‘H’, the other bit means value at blanking. Default value is 0x09.
Vertical blank
VB [3:0] In status word, location of ‘V’ and V value at blanking. The MSB 3 bit means
the location of ‘V’, the other bit means value at blanking. Default value is 0x0B
Input Image Size (IIS) 0x9000400C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSIZE <15:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VSIZE <15:0>
FIELD Description
HSIZE [31:16] Horizontal size of input image
VSIZE [15:0] Vertical size of input image
Input Image Windowing1 (IIW1) 0x90004010

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HW1<15:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HW2<15:0>
Input Image Windowing2 (IIW2)

0x90004014
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VW1<15:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VW2 <15:0>
Preliminary 1-9
Input Image
VW1
HW1 HW2
Windowing Image
VW2
Figure 1.4 Input Image Windowing
All default value is 0x00.
CMOSIF DMA Configuration Register 1 (CDCR1) 0x90004018

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TM Lock BS <1:0>
BS [1:0] Preamble and Status Location

00 The DMA transfers the image data as 1 word to memory.
01 The DMA transfers the image data as 2 words to memory.
10 The DMA transfers the image data as 4 words to memory.
11 The DMA transfers the image data as 8 words to memory. (default)
Using the burst of AMBA system.
LOCK [2] Lock Transfer

0 Non-Lock (default)
1 Lock Transfer
TM [2] Transfer Method

0 Burst Transfer(default)
1 INC Transfer
1-10 Preliminary
CMOSIF DMA Configuration Register 2 (CDCR2) 0x9000401C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Input Image /Y(G) Channel Base Address<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Input Image / Y(G) Channel Base Address<15:0>
FIELD Description
CDCR2 [31:0] Input Image Base Address. / Y(G) channel base address

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
U(R) Channel Base Address<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U(R) Channel Base Address<15:0>
FIELD Description
CDCR3 [31:0] U(R) Channel Base Address.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
V(B) Channel Base Address<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD Description
CDCR4 [31:0] V(B) Channel Base Address

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Input Image /Y(G) Channel End Address<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Input Image / Y(G) Channel End Address<15:0>
FIELD Description
Input Image End Address. / Y(G) channel end address
CDCR5 [31:0]
This mode is operated, when rolling address Y is enable.
CMOSIF DMA Configuration Register 6 (CDCR6) 0x9000402C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
U(R) Channel End Address<31:16>
Preliminary 1-11
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U(R) Channel End Address<15:0>
FIELD Description
U(R) Channel End Address
CDCR6 [31:0]
This mode is operated, when rolling address U is enable.

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD Description
V(B) Channel End Address
CDCR7 [31:0]
This mode is operated, when rolling address U is enable.
FIFO States (FIFOSTATE) 0x90004034

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved CLR 0 REO REV REU REY
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 WEO WEV WEU WEY 0 EO EV EU EY 0 FO FV FU FY
CLR [21] Clear FIFO states

0 Not clear
1 Clear
REO [19] Overlay FIFO Read Error
0 The empty signal of overlay FIFO is Low, or empty is High and read enable
signal is Low.
1 The empty signal of input overlay FIFO and read enable signal are High.
REV [18] V(B) Channel FIFO Read Error
0 The empty signal of V(B) channel FIFO is Low, or empty is High and read
enable signal is Low.
1 The empty signal of input V(B) channel FIFO and read enable signal are High.
REU [17] U(R) Channel FIFO Read Error
0 The empty signal of U(R) channel FIFO is Low, or empty is High and read
1 The empty signal of input U(R) channel FIFO and read enable signal are High.
REO [16] Y(G) Channel FIFO Read Error
0 The empty signal of Y(G) channel FIFO is Low, or empty is High and read
1 The empty signal of input Y(G) channel FIFO and read enable signal are High.
WEO [13] Overlay FIFO Write Error
0 The full signal of overlay FIFO is Low, or full is High and write enable signal is
1-12 Preliminary
Low.
1 The full signal of overlay FIFO and write enable signal are High.
WEV [12] V(B) Channel FIFO Write Error
0 The full signal of V(B) channel FIFO is Low, or full is High and write enable
signal is Low.
1 The full signal of V(B) channel FIFO and write enable signal are High.
WEU [11] U(R) Channel FIFO Write Error
0 The full signal of U(R) channel FIFO is Low, or full is High and write enable
signal is Low.
1 The full signal of U(R) channel FIFO and write enable signal are High.
WEY [10] Y Channel FIFO Write Error
0 The full signal of Y channel FIFO is Low, or full is High and write enable signal
is Low.
1 The full signal of Y channel FIFO and write enable signal are High.
EO [8] Overlay FIFO Empty Signal
0 The state of overlay FIFO is non-empty.
1 The state of overlay FIFO is empty.
EV [7] V(B) Channel FIFO Empty Signal
0 The state of V(B) channel FIFO is non-empty.
1 The state of V(B) channel FIFO is empty.
EU [6] U(R) Channel FIFO Empty Signal
0 The state of U(R) channel FIFO is non-empty.
1 The state of U(R) channel FIFO is empty.
EY [5] Y Channel FIFO Empty Signal
0 The state of Y channel FIFO is non-empty.
1 The state of Y channel FIFO is empty.
FO [3] Overlay FIFO Full Signal
0 The state of overlay FIFO is non-full.
1 The state of overlay FIFO is full.
FV [2] V(B) Channel FIFO Full Signal
0 The state of V(B) channel FIFO is non-full.
1 The state of V(B) channel FIFO is full.
FU [1] U(R) Channel FIFO Full Signal
0 The state of U(R) channel FIFO is non-full.
1 The state of U(R) channel FIFO is full.
FY [0] Y Channel FIFO Full Signal
0 The state of Y channel FIFO is non-full.
1 The state of Y channel FIFO is full.
CMOSIF Interrupt Register (CIRQ) 0x90004038

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IEN URV ITY ICR 0 MVN MVP MVIT MSE MSF MEM MRLV MRLU MRLY MSCF MSOF
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 0 0 VSS 0 VN VP VIT SE SF ENS ROLV ROLU ROLY SCF SOF
Preliminary 1-13

0 Interrupt disable
1 Interrupt enable
URV [30] Update Register in VSYNC

0 Register is updated without VSYNC.
1 When VSYNC is posedge, register is updated.
ITY [29] Interrupt Type.

0 Pulse type
1 Hold-up type when respond signal(ICR) is high.
ICR [28] Interrupt Clear

0
1 Interrupt Clear (using ITY is hold-up type)
MVN [26] Mask interrupt of VS negative edge

0 Don’t mask
1 Mask
MVP [25] Mask interrupt of VS positive edge

0 Don’t mask
1 Mask
MVIT [24] Mask interrupt of VCNT Interrupt

0 Don’t mask
1 Mask
MSE [23] Mask interrupt of Scaler Error

0 Don’t mask
1 Mask
MSF [22] Mask interrupt of Scaler finish

0 Don’t mask
1 Mask
MENS [21] Mask interrupt of Encoding start

0 Don’t mask
1 Mask
MRLV [20] Mask interrupt of Rolling V address.

0 Don’t mask
1 Mask
MRLU [19] Mask interrupt of Rolling U address.

0 Don’t mask
1-14 Preliminary
1 Mask
MRLY [18] Mask interrupt of Rolling Y address.

0 Don’t mask
1 Mask
MSCF [17] Mask interrupt of Capture frame.

0 Don’t mask
1 Mask
MSOF [16] Mask interrupt of Stored one frame.

0 Don’t’ mask
1 Mask.
VSS [12] Status of vertical sync.

0 Non- vertical sync blank area.
1 Vertical sync blank area.
VN [10] VS negative.
0 -
1 When VS is generated in negative edge.
VP [9] VS positive
0 -
1 When VS is generated in positive edge.
VIT [8] VCNT Interrupt.

0 -
1 When VCNT is generated...
SE [6] Scaler Error.

0 -
1 When Scale operation is not correct.
SF [6] Scaler Finish.

0 -
1 When Scale operation is finished..
ENS [5] Encoding start status.

0 -
1 When Y adddress is bigger than encoding start address, this bit is high.
ROLV [4] Rolling V address status.

0 -
1 If V address is move to start address, this bit is high
Preliminary 1-15
ROLU [3] Rolling U address status.

0 -
1 If U address is move to start address, this bit is high
ROLY [2] Rolling Y address status.

0 -
1 If Y address is move to start address, this bit is high
SCF [1] Stored captured frame.

0 -
1 If Captured frame is stored, this bit is high.
SOF [0] Stored One frame.

0 -
1 If One frame if stored, this bit is high.
Overlay Control 1 (OCTRL1) 0x9000403C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved OCNT<4:0> 0 OM
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved OE 0 XR1 XR0 0 AP1<1:0> AP0<1:0> 0 AEN 0 CEN
OM[16] Overlay Method

0 Full image overlay
1 Block image overlay
Full image overlay mode, overlay image size is equal to the input image size.
OE[12] Overlay Enable
0 Disable
1 Enable
XR1[10] XOR in AP1 is 3
0 XOR operation
1 100 %
When AP1 is 3 and CEN & AEN is 1, we select the 100% alpha value or XOR
operation.
XR0 [9] XOR in AP0 is 3
0 XOR operation
1 100 %
When AP0 is 3 and CEN & AEN is 1, we select the 100% alpha value or XOR
operation
AP1 [7:6] Alpha Value in alpha is 1
0 25 %
1 50 %
2 75 %
3 100 % or XOR operation (for XR value)
AP0 [5:4] Alpha Value in alpha is 0
1-16 Preliminary
0 25 %
1 50 %
2 75 %
3 100 % or XOR operation
When 565RGB and AEN, alpha value is depend on AP0 value.
AEN[2] Alpha Enable

0 Disable
1 Enable
CEN[2] Chroma key Enable
0 Disable
1 Enable
OCNT[29:24] Overlay Count (FIFO)
n
Overlay Control 2 (OCTRL2) 0x90004040

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved CONV RGB MD
CONV[3] Color Converter Enable

0 Disable
1 Enable
RGB[2] RGB Mode

0 565RGB
1 555RGB
2 444RGB
3 332RGB
MD[0] Color Mode

0 YUV color
1 RGB color
Overlay Control 2 – key value(OCTRL2) 0x90004044

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved KEYR<7:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KEY<7:0> KEYB<7:0>
KEYR[23:16] Chroma-key value R(U)

n Chrome-key value in R(U) channel
Preliminary 1-17
Default value is 0x00
KEYG[15:8] Chroma-key value G(Y)

n Chrome-key value in G(Y) channel.
KEYB[7:0] Chroma-key value B(V)

n Chrome-key value in B(V) channel.
Overlay Control 3 – mask key value(OCTRL3) 0x90004048

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved MKEYR<7:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MKEY<7:0> MKEYB<7:0>
MKEYR[23:16] Mask Chroma-key value R(U)

N Chrome-key value in R(U) channel
MKEYG[15:8] Mask Chroma-key value G(Y)

N Chrome-key value in G(Y) channel.
MKEYB[7:0] Mask Chroma-key value B(V)

n Chrome-key value in B(V) channel.
Overlay Image Size (OIS) 0x9000404C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OHSIZE<15:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVSIZE<15:0>
FIELD Description
OHSIZE Horizontal size of overlay image
[31:16] Default value is 0x0280. (decimal is 640)
Vertical size of overlay image
OVSIZE [15:0]
Default value is 0x01E0 (decimal is 480)
Overlay Image Windowing 1 (OIW1) 0x90004050

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OHW1<15:0>
1-18 Preliminary
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OHW2<15:0>
Overlay Image Windowing 2 (OIW2) 0x90004054

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
OVW1<15:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OVW2 <15:0>
Input
Image
OVW1
OHW1 OHW2
Windowing
Image
OVW2
Figure 1.5 Overlay Image Windowing
All default value is 0x00.
CMOSIF Overlay Base Address (COBA) 0x90004058

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Overlay Image Base Address<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Overlay Image Base Address<15:0>
FIELD Description
Overlay Image Base Address.
COBA [31:0]
Default value is 0x20100000.
CMOSIF Down Scaler (CDS) 0x9000405C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved SFH<1:0> SFV<1:0> 0 SEN
SFH [5:4] Horizontal Scale Factor
Preliminary 1-19
0 1/1 down scale

1 1/2 down scale
2 1/4 down scale
3 1/8 down scale
SFV [3:2] Vertical Scale Factor

0 1/1 down scale
1 1/2 down scale
2 1/4 down scale
3 1/8 down scale
SEN Scale Enable

0 Disable
1 Enable
CMOSIF Capture mode_1 (CCM_1) 0x90004060

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ENCNUM ROLNUMV ROLNUMU ROLNUMY
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved CB EIT UES SKIPNUM RLV RLU RLY CAP
ENCNUM Encode INT number (using CAP mode)

[31:28]
0~15 Encode Interrupt number
ROLNUMV Rolling Number in V (using CAP mode)

[27:24]
0~15 Rolling number
ROLNUMU Rolling Number in U (using CAP mode)

[23:20]
0~15 Rolling number
ROLNUMY Rolling Number in Y (using CAP mode)

[19:16]
0~15 Rolling number
CB [10] Capture Busy

0 -
1 Capture busy..
EIT [9] Encoding INT count

0 Always 1 pulse
1 Counting encoding INT.
1-20 Preliminary
UES [8] Using Encoding Start Address

0 disable
1 Enable
SKIPNUM Skip frame number (using CAP mode)

[7:4]
0~15 Skip frame number
RLV[3] Rolling address V.

0 Disable
1 Enable
RLU[2] Rolling address U.

0 Disable
1 Enable
RLY[1] Rolling address Y.

0 Disable
1 Enable
CAP [0] Image Capture

0 Normal
1 Image Capture
CMOSIF CAPTURE MODE_2 (CCM_2) 0x90004064

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved VCNT VEN
FIELD Description (Using CAP mode)

Threshold line counter in interrupt.
VCNT[7:4]
1 : 16 line, 2: 32line, 3:48line….
VEN [0] VCNT folling enable (Using CAP mode)

0 Normal
1 Enable
CMOSIF Encoding Start Address (CESA) 0x90004068

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Encoding Start Address [31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Preliminary 1-21
Encoding Start Address [15:0]
FIELD Description
Using capture and encoding, this register desides the encoding start point.
CESA[31:0] Default value is 0x20100000.
This address is compare with Y address.
CMOSIF R2Y configuration(CR2Y) 0x9000406C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FMT EN
FMT [4:1] Input format

0 0 0 0 16bit 565RGB (RGB sequence)
0 0 0 1 16bit 565RGB (BGR sequence)
0 1 0 0 16bit 555RGB (RGB-garbage)
0 1 0 1 16bit 555RGB (BGR-garbage)
0 1 1 0 16bit 555RGB (garbage-RGB)
0 1 1 1 16bit 555RGB (garbage-BGR)
1 0 0 0 8bit 565RGB (RGB sequence)
1 0 0 1 8bit 565RGB (BGR sequence)
1 1 0 0 8bit 555RGB (RGB-garbage)
1 1 0 1 8bit 555RGB (BGR-garbage)
1 1 1 0 8bit 555RGB (garbage-RGB)
1 1 1 1 8bit 555RGB (garbage-BGR)
EN [0] R2Y enable

0 Disable
1 Enable
CMOSIF Current Y Address (CCYA) 0x90004070

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Current Y address [31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Current U address [15:0]
FIELD Description
CCYA[31:0] Current Y Address.
CMOSIF Current U Address (CCUA) 0x90004074

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1-22 Preliminary

15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FIELD Description
CCUA[31:0] Current U Address
CMOSIF Current V Address (CCVA) 0x90004078

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Current V address [31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Current V address [15:0]
FIELD Description
CCVA[31:0] Current V Address
CMOSIF Current Line Count (CCLC) 0x9000407C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Line count [15:0]
FIELD Description
LCNT[15:0] Current Line Count
Preliminary 1-23
4:4:4 format
CLK
HS
Y[7:0] Y0 Y1 Y2 Y3 Y4
CbCr[7:0] Cb0 Cr0 Cb1 Cr1 Cb2 Cr2 Cb3 Cr3 Cb4 Cr4
pixel clk * 2
* YCbCr, YUV, RGB [Y(G), Cb(U,R), Cr(V,B)]
4:2:2 16bits format (CCIR-601)

pixel clock
HS
Y[7:0] Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
CbCr[7:0] Cb0 Cr0 Cb2 Cr2 Cb4 Cr4 Cb6 Cr6 Cb8 Cr8
pixel clock
4:2:2 8bits format (CCIR-656)

pixel clock
HS
YCbCr[7:0] Cb0 Y0 Cr0 Y1 Cb2 Y2 Cr2 Y3 Cb4 Y5
pixel clock * 2
4:2:0 16bits format

pixel clock
HS
Y[7:0] Y0 Y1 Y2 Y3 Y4 Y5 Y6 Y7 Y8 Y9
CbCr[7:0] (odd) Cb0 Cb2 Cb4 Cb6 Cb8
16 bits
CbCr[7:0] (even) Cr0 Cr2 Cr4 Cr6 Cr8
pixel clock
* YCbCr, YUV, RGB [Y, Cb(U), Cr(V)]
Figure 1.6 YCbCr Timing Diagram
1-24 Preliminary
Figure 1.7 RGB Timing Diagram
Preliminary 1-25
1.3 Image Effect
The TCC82XX provides image effect in camera interface. The supporting effect modes
are YUV bias (YUV offset value), Inversion of Y value, strong C mode (x2 C value), Y
clipping, color filter, sketch mode, embossing (positive and negative), gray, and sepia.
The input format of effect mode is always 8 bit yuv format and output format is only
16bit mode. So, this is not supported in 16 bit mode. But this is supported RGB555,565
mode. If you want to use effect from 8bit 555RGB or 565RGB in 8 bit mode, camera
interface provides RGB to YUV format converter.
For Example, input mode is RGB565, CIF_FMT block of camera interface is converted
from RGB565 8 bit mode to YUV422 8bit mode, then through effect block, output data
of effect block if YUV422 16 bit mode.
Timing diagram is shown figure 1.8
Effect Block Input
i_vs
i_hs
pclk
i_data[7:0] Y0 U0 Y1 V0 Y2 U2 Y3 V2 Y4 U4 Y5 V4
Effect Block Output
i_vs
i_hs
o_data_en
mclk
o_data[15:8] Y0 Y1 Y2 Y3 Y4 Y5
o_data[7:0] U0 V0 U2 V2 U4 V4
Figure 1.8 Timing diagram of effect block
1-26 Preliminary
1.4 Effect Register Descriptions
Table 1.3 Effect Register Map (Base Address = 0x90004100)

EMR 0x00 W/R 0x00000000 Effect mode register
SEPIAUV 0x04 W/R 0x00000000 Sepia UV setting
CSR 0x08 W/R 0x00000000 Color selection register
HFIL_COEF 0x0C W/R 0x00000000 H-filter coefficent0
SKETCHTH 0x10 W/R 0x00000000 Sketch threshold register
CLAMPTH 0x14 W/R 0x00000000 Clamp threshold register
BIAS 0x18 W/R 0x00000000 BIAS register
ISIZE 0x1C W/R 0x00000000 Image size register
INPATH_CTRL 0x40 W/R 0x00000000 Inpath configuration
SRC_ADDRY 0x44 W/R 0x00000000 Source address in Y channel
SRC_ADDRU 0x48 W/R 0x00000000 Source address in U channel
SRC_ADDRV 0x4C W/R 0x00000000 Source address in V channel
SRC_SIZE 0x50 W/R 0x00000000 Source image size
SRC_OFFS 0x54 W/R 0x00000000 Source image offset
DST_SIZE 0x58 W/R 0x00000000 Destination image size
TAR_SCALE 0x5C W/R 0x00000000 Target scale
Preliminary 1-27
CMOSIF Effect Mode (CEM) 0x90004100

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
UVS VB UB YB YCS IVY STC YCL CS SKT EMM EMB NEGA GRAY SEPI NOR
UVS [15] UV Swap

0 u-v-u-v sequence
1 v-u-v-u sequence
VB [14] V Bias (V channel value offset)

0 Disable
1 Enable
UB [13] U Bias (U channel value offset)

0 Disable
1 Enable
YB [12] Y Bias (Y channel value offset)

0 Disable
1 Enable
YCS [11] YC Swap

0 u-y-v-y sequence
1 y-u-y-v sequence
IVY[10] Invert Y
0 Disable
1 Enable
STC[9] Strong C
0 Disable
1 Enable
YCL[8] Y Clamp (Y value clipping)

0 Disable
1 Enable
CS[7] C Select (Color filter)

0 Disable
1 Enable (color filter)
SKT[6] Sketch Enable
1-28 Preliminary
0 Disable
1 Enable
EMM[5] Emboss Mode

0 Positive emboss
1 Negative emboss
EMB[4] Emboss
0 Disable
1 Enable
NEGA[3] Nagative mode

0 Disable
1 Enable
GRAY[2] Gray mode

0 Disable
1 Enable
SEPI[1] Sepia mode

0 Disable
1 Enable
NOR[0] Normal mode

0 Effect mode
1 Normal mode
CMOSIF Sepia UV (CSUV) 0x90004104

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SEPIA_U SEPIA_V
FIELD Description
SEPIA_U[15:8] U chanel threshold value for sepia
SEPIA_V[7:0] V channel threshold value for sepia
CMOSIF Color Selection (CCS) 0x90004108

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
U start U end
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
V start V end
FIELD Description
Preliminary 1-29
U_Start[31:24] Color filter range start point of U channel

U_End[23:16] Color filter range end point of V channel
V_Start[15:8] Color filter range start point of U channel
V_End[7:0] Color filter range end point of V channel
CMOSIF H filter Coeff. (CHFC) 0x9000410C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 Coeff 0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Coeff 1 Coeff 2
FIELD Description
Coeff0[23:16] Horizontal filter coefficient0 for emboss or sketch.
Coeff1[15:8] Horizontal filter coefficient1 for emboss or sketch.
Coeff2[7:0] Horizontal filter coefficient2 for emboss or sketch
CMOSIF Sketch Threshold. (CST) 0x90004110

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Sketch Threshold
FIELD Description
Sketch[7:0] Sketch threshold
CMOSIF Clamp Threshold. (CCT) 0x90004114

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Clamp Threshold
FIELD Description
Clamp[7:0] Clamp threshold
CMOSIF Bias Register. (CBR) 0x90004118

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Y bias
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
U bias V bias
FIELD Description
Y_BIAS[23:16] Y value offset
1-30 Preliminary
U_BIAS[15:8] U value offset

V_BIAS[7:0] V value offset
CMOSIF Effect Image Size (CEIS) 0x9000411C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HSIZE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VSIZE
FIELD Description
HSIZE[26:16] Horizontal size of input image
VSIZE[10:0] Vertical size of input image
CMOSIF Inpath Control (CIC) 0x90004140

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
H2H_WAIT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
STB_CYCLE 0 INP_WAIT INPR FA INE INP
FIELD Description
H2H_WIAT Horizontal sync (hs) to hs wait cycle.
[31:16]
FIELD Description
STB_CYCLE CCIR strobe cycle.
[15:12]
Minimum. Value of STB_CYCLE is 4.
FIELD Description
INP_WAIT -
[6:4]
INPR[3] -
0 -
1 -
FA[2] Flush all

0 -
1 -
INE[1] Inpath Enable

0 Disable
1 Enable
INP[1] Inpath Mode
Preliminary 1-31
0 Camera mode
1 Memory mode
CMOSIF Inpath SRC_ADDR 1 (CISA1) 0x90004144

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRC_BASE SRC_BASE_Y
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRC_BASE_Y
FIELD Description
SRC_BASE Source base address (31 downto 28 bit assign in base address).
[31:28]
FIELD Description
SRC_BASE_Y Source base address in Y channel (27 downto 0 bit assign in base address).
[31:28]
CMOSIF Inpath SRC_ADDR 2 (CISA2) 0x90004148

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 SRC_TYPE SRC_BASE_U
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRC_BASE_U
INP[29:28] Source type

0 4:2:2 SEQ0
1 4:2:2 SEQ1
2 4:2:2 Separate
3 4:2:0 Separate
FIELD Description
SRC_BASE_U Source base address in U channel (27 downto 0 bit assign in base address).
[27:0]
CMOSIF Inpath SRC_ADDR 3 (CISA3) 0x9000414C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 SRC_BASE_V
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRC_BASE_V
FIELD Description
SRC_BASE_V Source base address in V channel (27 downto 0 bit assign in base address).
[27:0]
1-32 Preliminary
CMOSIF Inpath SRC_SIZE (CISS) 0x90004150

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 SRC_HSIZE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 SRC_VSIZE
FIELD Description
SRC_HSIZE Horizontal size in source image
[27:16]
SRC_VSIZE Vertical size in source image
[11:0]
CMOSIF Inpath SRC_Offset (CISO) 0x90004154

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 SRC_OFFSET_Y
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 SRC_OFFSET_C
FIELD Description
SRC_OFFSET_Y Source address offset in Y channel
[27:16]
SRC_OFFSET_C Source address offset in C channel
[11:0]
CMOSIF Inpath DST_SIZE_ (CIDS) 0x90004158

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 DST_HSIZE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 DST_VSIZE
FIELD Description
DST_HSIZE Horizontal size in destination image
[27:16]
DST_VSIZE Vertical size in destination image
[11:0]
CMOSIF Inpath SCALE_ (CIS) 0x9000415C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Preliminary 1-33
0 HSCALE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
VSCALE
FIELD Description
HSCALE Horizontal scale factor
[29:16]
VSCALE Vertical scale factor
[13:0]
HSCALE = SRC_HSIZE * 256 / DST_HSIZE.
VSCALE = SRC_VSIZE * 256 / DST_VSIZE
1-34 Preliminary
1.5 Image Scaler
The TCC82XX provides image scaler in camera interface. The supporting scaling ratio
is 1 : 4 (zoom up to 4 times) to 64 : 1 (zoom down to 64 times), scaling step is 256 step.
Maximum scaling image is 1600*1200*8 fps.
Preliminary 1-35
1.6 Scaler Register Descriptions
Table 1.4 Scaler Register Map (Base Address = 0x90004200)

SC_CTRL 0x00 W/R 0x00000000 Scaler configuration
SC_SCALE 0x04 W/R 0x00000000 Scale factor
SC_SRC_OFFSET 0x08 W/R 0x00000000 Image offset
SC_SRC_SIZE 0x0C W/R 0x00000000 Source image size
SC_DST_SIZE 0x10 W/R 0x00000000 Destination image size
1-36 Preliminary
CMOSIF Scaler CTRL (OSC) 0x90004200

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved EN
EN [0] Scaler Enable

0 Disable
1 Enable
CMOSIF Scaler SCALE Factor(OSSF) 0x90004204

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 HSCALE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 VSCALE
FIELD Description
HSCALE Horizontal scale factor
[29:16]
VSCALE Vertical scale factor
[13:0]
HSCALE = SRC_HSIZE * 256 / DST_HSIZE.
VSCALE = SRC_VSIZE * 256 / DST_VSIZE
CMOSIF Scaler SRC_Offset(OSSO) 0x90004208

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 H_OFFSET
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 V_OFFSET
FIELD Description
H_OFFSET Horizontal offset
[27:16]
VSCALE Vertical offset
[11:0]
CMOSIF Scaler SRC_Size(OSSS) 0x9000420C
Preliminary 1-37
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 H_SIZE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 V_SIZE
FIELD Description
H_SIZE Horizontal size in source image
[27:16]
V_SIZE Vertical size in source image
[11:0]
CMOSIF Scaler DST_Size(OSSS) 0x90004210

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 H_SIZE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 V_SIZE
FIELD Description
H_SIZE Horizontal size in destination image
[27:16]
V_SIZE Vertical size in destination image
[11:0]
1-38 Preliminary
LCD Controller
Multimedia Application Processor LCD INTERFACE
2 LCD Interface
2.1 Overview
The LCD controller (LCDC) is used to send out image data from the system memory
or scaler to LCD panels or an NTSC/PAL encoder by properly formatting the raw
image data stored in the memory. The LCDC provides all the necessary control signals
to interface directly to mono STN, color STN, TFT panels, and NTSC/PAL encoders.
The features of the LCDC are:
y supports dual Thin Film Transistor(TFT) color displays with 8-bit, 16-bit or
18-bit interface
y supports Super Twisted Nematic(STN) displays with 4 or 8-bit interface
y 1, 2 or 4 bits per pixel(bpp) displays for mono STN
y 8(332) /16 bpp color displays for color STN
y 16 bpp true-color non-palettized color displays for color TFT
y resolution programmable up to 1024 * 1024
y programmable timing for different display panels
y NTSC/PAL digital video encoder interface (CCIR601/656 interface)
y Supports color lookup table for 8bpp(332bbp, using FIFO2).
y Supports the overlay and alpha blending (2 overlay and 1 original image)
y Supports the image up/down scaling (x2, x3, x4, x8)
Register
Bank Timing
Controller
LDMAC1 Timing control
signals
LDMAC0
BUS
FIFO1 Gray Pixel Data

AHB
Formatter
FIFO_Y YCbCr scaler

Pixel
FIFO_U to Mixer Output FIFO
FIFO_V Serializer RGB
RGB
to
FIFO1
FIFO_Y YCbCr
FIFO2 Lookup
FIFO_Y Table
(256*24bit)
FIFO
controller
Figure 2.1 LCD controller Block Diagram
The following key parameters can be programmed:
y horizontal front and back porch

y horizontal synchronization pulse width
y number of panel clocks per line
y vertical front and back porch
y vertical synchronization pulse width
y vertical synchronization pulse delay for STN mode
y number of lines per panel
y signal polarity
y panel clock frequency
y AC panel bias
2-2 Preliminary
y bits-per-pixel
y display type, STN mono/color or TFT
y STN 4 or 8-bit interface mode
y NTSC/PAL, Interlace/Non-interlace mode
y Overlay/alpha blending mode
y Image up/down scale ratio
Image data stored in frame buffers are transferred to the LCDC’s input FIFO, on a
demand basis, using the AMBA AHB master interface.
The LCDC starts the DMA data transfer after it has been initialized and enabled. The
DMA automatically performs burst word(32-bit) transfers, filling the empty entries of
the input FIFO. The data in the FIFO are fetched one entry at a time, and each 32-bit
data is unpacked into appropriate pixel data formats(1, 2, 4, 8 or 16 bpp) according to
the pixel data format information.
The frame buffer is in an off-chip memory area used to supply enough encoded pixel
values to fill the entire screen one or more times. The pixel data buffer contains one
encoded pixel values for each of the pixels present on the screen. The number of pixel
data values depends on the size of the screen. Figure 2.2 shows the memory
organization within the frame buffer for each size pixel encoding.
LCDC generates interrupt every end of frame. DMA base address can be updated in
this ISR. It can be masked by interrupt controller.
2.2 STN-LCD
The LCDC generates VSYNC, HSYNC, PXCLK, ACBIAS, and PXDATA signals for
STN LCD driver.
Figure 2.2 shows 1bpp, 2bpp, 4bpp, 332bpp, 444bpp, and 16bpp of PXDATA memory
organization. BR of LI0C and LI1C register indicates whether pixel data in frame
memory is big-endian for 1bpp, 2bpp, or 4bpp mode. Figure 2.3 shows RGB
configuration for color STN LCD.
The timing diagram for STN mode is shown in Figure 2.4. VSYNC and HSYNC pulse
are controlled by the configurations of the LPC field of LHTIME and FLC field of
LVTIME1 and LVTIME2. Each field is related to the LCD size and display mode.
At the relations between VSYNC and HSYNC pulse, the VSYNC pulse must be
delayed 50 ns at the minimum in base HSYNC pulse.
In 1bpp, 2bpp, 4bpp:
LPC =(Horizontal display size / pixel data width) – 1
In 8pp and 16bpp (RGB):
LPC = {3 * Horizontal display size / (pixel data width) – 1}
Preliminary 2-3
Pixel data width is determined by PXDW of LCTRL register. In the case of STN LCD
mode, it must be 4 or 8-bit width.
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
1BPP p31 p30 p29 p28 p27 p26 p25 p24 p23 p22 p21 p20 p19 p18 p17 p16
2BPP p15 p14 p13 p12 p11 p10 p9 p8
4BPP p7 p6 p5 p4
8BPP p3 p2
16BPP p1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2BPP p7 p6 p5 p4 p3 p2 p1 p0
4BPP p3 p2 p1 p0
8BPP p1 p0
16BPP p0
a) BR=0
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
2BPP p12 p13 p14 p15 p8 p9 p10 p11
4BPP p6 p7 p4 p5
8BPP p3 p2
16BPP p1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
2BPP p4 p5 p6 p7 p0 p1 p2 p3
4BPP p2 p3 p0 p1
8BPP p1 p0
16BPP p0
b) BR=1
Figure 2.2 Pixel data organization
STN 7 6 5 4 3 2 1 0
8BPP R[1:0] G[2:0] B[2:0]
STN 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
16BPP X R[3:0] G[3:0] B[3:0]
Figure 2.3 Color STN Pixel Data
ACBIAS signal is used by the LCD driver to alternate the polarity of the row and
column voltage used to turn the pixel on and off. It is controlled by the ACDIV field of
LCLKDIV register:
facbias = fhsync / (2 * ACDIV)
2-4 Preliminary
PXCLK frequency is determined by the CLKDIV field of LCLKDIV register as follows.

The minimum value of CLKDIV is 3 in STN mode.
fPXCLK = fLCLK / (2 * CLKDIV) (1)
VSYNC frequency is related to the field of FPW, LSWC, LEWC, LPC, and FLC as well
as HCLK and PXCLK.
fVSYNC = fPXCLK / [{(LPW+1) + (LPC+1) + (LSWC+1) + (LEWC+1)}

x {(FLC + 1) + (FPW+1)}]
Therefore, if FR is the required refresh rate, fPXCLK_REQ, which is the required PXCLK, is
the flowing.
fPXCLK_REQ = FR x [ {(LPW+1) + (LPC+1) + (LSWC+1) + (LEWC+1)}

x {(FLC + 1) + (FPW+1)} ] (2)
The LCDC contains dithering pattern registers for STN LCD: a 48-bit modulo 7
dithering pattern register (LDP7L and LDP7H), a 32-bit modulo 5 dithering pattern
register (LDP5), a 16-bit modulo 4 dithering pattern register (LDP4), and a 16-bit
modulo 3(LDP3) dithering pattern register. These dithering pattern registers can
contain the programmable pre-dithered pattern values for each duty cycle ratio.
The LDP7H and LDP7L contain 5 pre-dithered patterns for 1/7, 3/7, 4/7, 5/7, and 6/7
duty cycle rate. Each field of LDP7H and LDP7L is 7-bit long. The LDP5 has 4 pre-
dithered pattern fields for 1/5, 2/5, 3/5, and 4/5 duty cycle rate. Each field of LDP5 is
5-bit long. The LDP4 has 3 pre-dithered pattern fields for 1/4, 1/2(=2/4), and 3/4 duty
cycle rate, and each field is 4-bit long. Likewise, the LDP3 has 2 fields for 1/3 and 2/3
duty cycle rate with 3-bit length.
Note that the pre-dithered data for 1 and 0 is not defined in the dithering pattern
register, because these values are implemented with VDD and VSS condition.
Preliminary 2-5
Figure 2.4 STN mode timing
EXAMPLE )
For a monochrome STN LCD, 4-bit interface panel, 4 pixels are captured by the panel
in every panel clock cycle. Figure 2.3 gives the major registers to be programmed for
supporting 4-bit interface STN LCD. LCLK and Refresh rate are examples only. And
LSWC, LEWC, LPW, and FPW are STN LCD panel dependent.
LCLK = 20 MHz, Refresh rate = 60 Hz

PXDW* = 0 (4bits), BPP* = 2 (4bpp) , DP* = 0 (one pixel data per one pixel cycle)
NI = 1, TV* = 0, TFT* = 0, STN* = 1
LSWC* = LEWC* = LPW* = FPW* = 1 (STN LCD dependent)
Width Height F**

LPC* FLC* DHSIZE* DVSIZE* CLKDIV* fPXCLK***
(pixel) (pixel) PXCLK_REQ
160 160 39 159 160 160 0.393 25 0.4

160 200 39 199 160 200 0.491 20 0.5
320 200 79 199 320 200 0.973 10 1
* ** ***
. ) control registers to be programmed. ) Refer to expression (2). ) Refer to expression (1).
Figure 2.5 Monochrome STN LCD(4bits, 1BPP) example
2-6 Preliminary
2.3 TFT-LCD
The LCDC supports 16bpp true-color non-palletized color displays for color TFT LCD.
It generates the control signals for LCD driver such as, VSYNC, HSYNC, PXCLK,
PXDEN(ACBIAS) and PXDATA. Figure 2.6 shows 16bpp of PXDATA memory
organization in TFT mode. The timing diagram of TFT mode is shown in Figure 2.8.
TFT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB565 R[4:0] G[5:0] B[4:0]
TFT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RGB555 I* R[4:0] G[4:0] B[4:0]
*) intensity bit
Figure 2.6 TFT LCD pixel data
The VSYNC and HSYNC frequency is controlled by the LPC and FLC field.
LPC = (Horizontal display size) – 1

FLC = (Vertical display size) – 1
And PXCLK frequency is determined by the CLKDIV value.
fPXCLK = fLCLK / (2 x CLKDIV) (3)
The frequency of VSYNC signal is the frame rate. So the frame rate can be calculated as
follows:
fVSYNC = fPXCLK / [ (FSWC + FPW + FLC +FEWC)

x {(LSWC+1) + (LPC+1) + (LEWC+1) + (LPW+1)}]
Therefore, if FR is the required refresh rate in TFT mode, fPXCLK_REQ, which is the
required PXCLK, is the flowing.
fPXCLK_REQ = FR x {(LPW+1) + (LPC+1) + (LSWC+1) + (LEWC+1)}

x {(FSWC+1) + (FPW+1) + (FLC+1) +(FEWC+1)} (4)
Example
For TFT LCD(RGB565), if LCLK = 80MHz and Refresh rate = 60Hz,
PXDW* = 0x4, YUV* = 0, BPP* = 0x4, DP* = 0, NI* = 1, TV* = 0, TFT* = 1, STN* = 0
LSWC* = LEWC* = LPW* = 3 (TFT LCD dependent)
FSWC* = FEWC* = FPW* = 1 (TFT LCD dependent)
Width Height F**
LPC* FLC* DHSIZE* DVSIZE* CLKDIV* fPXCLK***
(pixel) (pixel) PXCLK_REQ
176 220 175 219 176 220 2.55 15 2.67

240 320 239 319 240 320 4.93 8 5
640 480 639 479 640 480 19.01 2 20
.*) control registers to be programmed. **) Refer to expression (4). ***)
Refer to expression (3).
Figure 2.7 TFT LCD(RGB565) example
Preliminary 2-7
FPW FSWC FLC FEWC

VSYNC
HSYNC
PXDATA line 1 line 2 ...... line n-1 line n
ACBIAS
LPW LSWC LPC LSWC
HSYNC
PXCLK
PXDATA line 1
ACBIAS
Figure 2.8 TFT mode timing
2.4 NTSC/PAL Interface
The LCDC can generate the control signals for 8-bit or 16-bit NTSC/PAL encoder. The
supporting mode is CCIR601/656 interlace/non-interlace. The pixel color mapping of
NTSC/PAL mode is identical to that of 8-bit or 16-bit LCD interfacing.
For NTSC/PAL interface, TV field of LCTRL register must be set. Registers used in this
mode are similar to those in TFT mode except for LVTIME1 and LVTIME2 registers.;
LVTIME1 is for odd field and LVTIME2 is for Even field. And these registers value is
not based on HSYNC, but based on half of HSYNC. For example, if FPW of LVTIME1
is 3, pulse width of VSYNC on odd field is not 4 HSYNC cycles, but 2 HSYNC cycles.
And if FPW of LVTIME1 is 4, it is 2.5 HSYNC cycles.
It is two kind of method to make 27MHz pixel clock, one is to use PLL with DCO and
the other is to use XTin directly. By using the former method, user can save extra
crystal for NTSC/PAL interfacing and it can be more efficient in view of power
consumption.
Interlace/Non-interlace mode can be configured by NI field of LCTRL register. Figure

2.9 and Figure 2.10 each show the timing diagram of NTSC and PAL interlace mode. In
non-interlace mode, odd field sync signals are repeated instead.
The CCIR656 mode can be configured by 656 field of LCTRL register. This mode uses 8
bit output port of which data is composed image data, HSYNC and VSYNC
information. (Don’t us SYNC ports). The pixel clock must be 27 MHz. Figure 2.11 each
show timing diagram and format diagram of CCIR656 mode.
2-8 Preliminary
FEWC of LVTIME2 FPW of LVTIME1 FPW of LVTIME2

Odd Field ...... Even Field
VSYNC
1 2 3 4 5 6 7 8 ...... 265 266 267 268 268

HSYNC
FSWC
VSYNC ......
LPW LPC
......
HSYNC
......
PXCLK
......
ACBIAS
PXDATA line 0 line 1
LSWC LEWC
Figure 2.9 NTSC interlace mode timing
FEWC of LVTIME2 FPW of LVTIME1 Even Field

Odd Field
......
VSYNC
......
HSYNC
FSWC
VSYNC ......
LPW LPC
......
HSYNC
......
PXCLK
......
ACBIAS
PD line 0 line 1
LSWC LEWC
Figure 2.10 PAL interlace mode timing
Preliminary 2-9
Start of digital line Start of digital active line
HS CCIR601 HSYNC signal

EAV SAV
F 0 0 X 8 1 8 1 F 0 0 X C C C
… Y Y Y Y
F 0 0 Y 0 0 0 0 F 0 0 Y B R B
8-bit data
D7
D6 D5 D4 D3 D2 D1 D0
(MSB)
1 1 1 1 1 1 1 1
preamble 0 0 0 0 0 0 0 0
0 0 0 0 0 0 0 0
status 1 F V H P3 P2 P1 P0
•Status word define

•F=‘0’ for field 1, ‘1’ for field 2
•V=‘1’ during vertical blanking
•H=‘0’ at SAV, ‘1’ at EAV
•Protection bits
•P3=V xor H
•P2=F xor H
•P1=F xor V * HSYNC is active low mode
•P0=F xor V xor H
Figure 2.11 CCIR656 format diagram
2-10 Preliminary

Table 2.1 LCDC Register Map (Base Address = 0x9000D000)
LCTRL 0x00 W 0x00000000 LCD Control Register
LBC 0x04 W 0x00000000 LCD Background Color Register
LCLKDIV 0x08 W 0x00000000 LCD Clock Divider Register
LHTIME1 0x0C W 0x00000000 LCD Horizontal Timing Register 1
LHTIME2 0x10 W 0x00000000 LCD Horizontal Timing Register 2
LVTIME3 0x1C W 0x00000000 LCD Vertical Timing Register 3
LLUTR 0x24 W 0x00000000 LCD Lookup Register for Red
LLUTG 0x28 W 0x00000000 LCD Lookup Register for Green
LLUTB 0x2C W 0x00000000 LCD Lookup Register for Blue
LDP7L 0x30 W 0x4d2b3401 LCD Modulo 7 Dithering Pattern (low)
LDP7H 0x34 W 0x0000003f LCD Modulo 7 Dithering Pattern (high)
LDP5 0x38 W 0x1d0b0610 LCD Modulo 5 Dithering Pattern Register
LDP4 0x3C W 0x00000768 LCD Modulo 4 Dithering Pattern Register
LDP3 0x40 W 0x00000034 LCD 3-bit Dithering Pattern Register
LK1 0x4C W 0x00000000 LCD Keying Register 1
LK2 0x50 W 0x00000000 LCD Keying Register 2
LDS 0x5C W 0x00000000 LCD Display Size Register
LSTATUS 0x60 R/clr 0x00000000 LCD Status Register
LIM 0x64 W 0x0000001f LCD Interrupt Register.
LI0C 0x68 W 0x00000000 LCD Image 0 Control Register
LI0P 0x6C W 0x00000000 LCD Image 0 Position Register
LI0CA 0x78 W 0x00000000 LCD Image 0 Current Address Register.
LI0BA1 0x7C W 0x00000000 LCD Image 0 Base Address 1 Register
LI0BA2 0x80 W 0x00000000 LCD Image 0 Base Address 2 Register
LI0O 0x84 W 0x00000000 LCD Image 0 Offset Register
LI0SR 0x88 W 0x00000000 LCD Image 0 scale ratio
LI1C 0x8C W 0x00000000 LCD Image 1 Control Register
LI1P 0x90 W 0x00000000 LCD Image 1 Position Register
LI1CA 0x9C W 0x00000000 LCD Image 1 Current Address Register.
N/A 0xA0 - 0x00000000 -
N/A 0xA4 - 0x00000000 -
Preliminary 2-11
LI1O 0xA8 W 0x00000000 LCD Image 1 Offset Register

LI1SR 0xAC W 0x00000000 LCD Image 1 Scale ratio-
LI2C 0xB0 W 0x00000000 LCD Image 2 Control Register
LI2P 0xB4 W 0x00000000 LCD Image 2 Position Register
LI2S 0xB8 W 0x00000000 LCD Image 2 Size Register
LI2BA0 0xBC W 0x00000000 LCD Image 2 Base Address 0 Register.
LI2CA 0xC0 W 0x00000000 LCD Image 2 Current Address Register.
N/A 0xC4 - 0x00000000 -
N/A 0xC8 - 0x00000000 -
LI2O 0xCC W 0x00000000 LCD Image 2 Offset Register
LI2SR 0xD0 W 0x00000000 LCD Image 2 Scale ratio
DLCTRL 0xD4 W 0x00000000 Dual LCD Control Register
N/A 0xD8 - 0x00000000 -
DLCSA0 0xDC W 0x00000000 Dual LCD Configuration Start Address 0
DLCSA1 0xE0 W 0x00000000 Dual LCD Configuration Start Address 1
Y2RP0 0xE4 W 0x00000029 YCbCr to RGB conversion parameter 0
Y2RP1 0xE8 W 0x98D00464 YCbCr to RGB conversion parameter 1
LCDLUT 0xC00 W - LCD Lookup Table.
2-12 Preliminary
LCD Control Registers (LCTRL) 0x9000D000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Y2R2 AEN2 CEN2 Y2R1 AEN1 CEN1 Y2R0 656 BPP<3:0> PXDW<3:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ID IV IH IP CLEN R2Y DP NI TV TFT STN MSEL IEN2 IEN1 IEN0 LEN
Y2R2 [31] YUV to RGB Channel Converter Enable 2

0 Disable
1 Enable
AEN2 [30] Alpha Blend Enable 2

0 Disable
1 Enable
y This mode is operated at overlay mode.
CEN2 [29] Chroma Key Enable 2

0 Disable
1 Enable

0 Disable
1 Enable
AEN1 [27] Alpha Blend Enable 1

0 Disable
1 Enable
CEN1 [26] Chroma Key Enable 1

0 Disable
1 Enable
Preliminary 2-13

0 Disable
1 Enable
656 [24] CCIR 601 to 656 Enable

0 Disable
1 Enable
y This mode is operated at TV mode. Using this mode, NI, IH, and IV of LCTRL
field. Set 1,0 and 1. And LCP field set value.
BPP [23:20] Bit Per Pixel

0 1bbp
1 2bpp
2 4bpp
3 332bpp
4 444bpp
5 565bpp
6 555bpp
7 888bpp
y This mode is operated at STN-LCD mode.
PXDW [19:16] Pixel Data Width for Output

0 4 pxdw
1 8 pxdw
2 888 pxdw
3 565 pxdw
4 555 pxdw
5 18 pxdw
6 8 pxdw (UY)
7 8 pxdw (VY)
8 16 pxdw (YU)
9 16 pxdw (YV)
ID [15] Inverted ACBIAS

0 Normal
1 Inverted
2-14 Preliminary
IV [14] Inverted Vertical Sync

0 Normal
1 Inverted
IH [13] Inverted Horizontal Sync

0 Normal
1 Inverted
IP [12] Inverted Pixel Clock

0 Data is driven onto the LCD’s data pins on the rising edge of pixel clock pin
1 Data is driven onto the LCD’s data pin on the falling edge of pixel clock pin
CLEN[11] Clipping Enable

0 Disable
1 Enable
R2Y[10] RGB to YUV Channel Converter Enable

0 Disable
1 Enable
DP[9] Double Pixel Data

0 One pixel data per PXCLK cycle is output
1 One pixel data per 2 PXCLK cycle is output
NI[8] Non-interlace
0 Interlace mode
Odd field timing control : LVTME1, LVTME2
Even field timing control : LVTIME3, LVTIME4
1 Non-interlace mode (progressive mode)
TV[7] TFT[6] STN[5] Non-interlace

0 0 1 STN-LCD mode
0 1 0 TFT-LCD mode
1 0 0 TV mode
Preliminary 2-15
In this mode, all values of LVTIMEn registers are divided

by 2
y Other combinations of flags are undefined and should net be used..
MSEL[4] Master Select

0 FIFO filled through DMA master 0 (default)
1 FIFO filled through DMA master 1, (from scaler)
IEN2[3] Fetch Enable 2

0 Disable
1 Enable

0 Disable
1 Enable

0 Disable
1 Enable
LEN[0] LCD Controller Enable

0 Disable
1 Enable
LCD Background Color (LBC) 0x9000D004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 BG2<7:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BG1<7:0> BG0<7:0>
FIELD Description
BG2 [23:16] Background color 2 (Y/B)
BG1 [15:8] Background color 1. (U/G)
BG0 [7:0] Background color 0. (V/R)
2-16 Preliminary
LCD Clock Divider Register (LCLKDIV) 0x9000D008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CS 0 ACDIV<7:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LCLKDIV<7:0> PXCLKDIV<7:0>
FIELD Description
Clock source
CS [31] 0 : The clock source of LCLK is CKC (Clock Controller)
1 : The clock source of LCLK is HCLK (AHB bus clock)
AC bias clock divisor (STN only)
ACDIV [23:16]
The number of line clock cycle to count between each toggle of AC_BIAS pin
LCLK clocks divider (using CS is set to 1)
LCLKDIV
LCLK = HCLK / (LCLKDIV+1)
[7:0]
(if LCLKDIV = 0, LCLK = HCLK)
Pixel clock divider.
PXCLKDIV Note that programming CLKDIV less than 3 is illegal for STN LCD.
[7:0] PXCLK = LCLK / (2*PXCLKDIV)
(if PXCLKDIV = 0, PXCLK = LCLK)
LCD Horizontal Timing Register 1 (LHTIME1) 0x9000D00C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 LPW<7:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 LPC<10:0>
FIELD Description
LPW [23:16] Line pulse width
Line pulse count is the number of pixel clock cycles in each line minus 1 on the
screen.
LPC [10:0] TFT/NTSC(16bit)/PAL(16bit) : active horizontal pixel – 1
Color STN : (3 * Horizontal display size / pixel width)
Mono STN : (Horizontal display size / pixel width) - 1
Preliminary 2-17
LCD Horizontal Timing Register 2 (LHTIME2) 0x9000D010

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 LSWC<8:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 LEWC<8:0>
FIELD Description
Line start wait clock is the number of dummy pixel clock cycles minus 1 to
LSWC [24:16]
insert from the start of each horizontal line of pixels.
Line end wait clock is the number of dummy pixel clock cycles minus 1 to
LEWC [10:0]
insert before the end of each horizontal line of pixels
LCD Vertical Timing Register 1 (LVTIME1) 0x9000D014

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VDB 0 VDF FPW<5:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 FLC<10:0>
FIELD Description
Back porchVSYNC delay
Delay cycle is -10 to 10cycle delay by PXLCLK.
VDB[31:27]
When TV mode, VDB value is equal to VDF.
Ex) if VD=5, VSYNC delay is 5 cycle delay by HSYNC.
Front porch of VSYNC delay
VDF[26:23] Delay cycle is 0 to 10 cycle delay by PXLCLK.
Ex) if VD=5, VSYNC delay is 5 cycle delay by HSYNC.
TFT/TV : Frame pulse width is the pulse width of frame clock (VSYNC).
FPW [21:16]
STN : N/A
FLC [10:0] Frame line count is the number of lines in each frame on the screen.
y Refer to Figure 2.4.
2-18 Preliminary

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 FSWC<5:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 FEWC<10:0>
FIELD Description
TFT/TV : Frame start wait cycle is the number of lines to insert at the end of
each frame.
FSWC [24:16]
STN : FSWC is N/A. If FSWC[0] is set, VSYNC signal starts on negative falling
edge of HSYNC.
TFT/TV : Frame end wait cycle is the number of lines to insert at the beginning
FEWC [8:0] of each frame.
STN : extra dummy lines between the end and beginning of frame..
LCD Vertical Timing Register 3 (LVTIME3) 0x9000D01C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 FPW<5:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 FLC<10:0>
y If NI of LCTRL is 0, LVTIME3 and LVTIME4 is for even field. Otherwise, LVTIME3 and
LVTIME4 must be the same with LVTIME1 and LVTIME2..

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 FSWC<8:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 FEWC<8:0>
y If NI of LCTRL is 0, LVTIME3 and LVTIME4 is for even field. Otherwise, LVTIME3 and
LVTIME4 must be the same with LVTIME1 and LVTIME2.
LCD Lookup Register for RED (LLUTR) 0x9000D024

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LLUTR<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LLUTR<15:0>
y This register is used for supporting palletized color STN-LCD. It is divided into 8 nibbles. The
passive color mode uses a lookup table register, which allows any 8 red levels to be selected
out of the 16 possible red levels. The most significant 3-bit of 8-bit encoded pixel addresses 8
red palette locations. Note that LLUTR register is only used in STN-LCD mode.
Preliminary 2-19
LCD Lookup Register for GREEN (LLUTG) 0x9000D028

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
LLUTG<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LLUTG<15:0>
passive color mode uses a lookup table register, which allows any 8 green levels to be
selected out of the 16 possible green levels. The most significant 3-bit of 8-bit encoded pixel
addresses 8 green palette locations. Note that LLUTG register is only used in STN-LCD
mode.
LCD Lookup Register for BLUE (LLUTB) 0x9000D02C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LLUTB<15:0>
passive color mode uses a lookup table register, which allows any 4 blue levels to be selected
out of the 16 possible blue levels. The most significant 2-bit of 8-bit encoded pixel addresses 4
blue palette locations. Note that LLUTB register is only used in STN-LCD mode.
LCD Dithering Pattern Register (LDP7L) 0x9000D030

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 DP5_7<6:0> 0 DP4_7<6:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 DP3_7<6:0> 0 DP1_7<6:0>
LCD Dithering Pattern Register (LDP7H) 0x9000D034

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 DP6_7<6:0>
LCD Dithering Pattern Register (LDP5) 0x9000D038

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 DP4_5<5:0> 0 DP3_5<5:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 DP2_5<5:0> 0 DP1_5<5:0>
2-20 Preliminary
LCD Dithering Pattern Register (LDP4) 0x9000D03C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 DP3_4<4:0> DP2_4<4:0> DP1_4<4:0>
LCD Dithering Pattern Register (LDP3) 0x9000D040

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 DP2_3<3:0> DP1_3<3:0>
LCD Clipping Register 1 (LCP1) 0x9000D044

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CLP2L CLP2
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLP1L CLP1
FIELD Description
CLP2L[31:24] Clipping U/G below this value. (standard value is 0)
CLP2 [23:16] Clipping U/G upper this value. (standard value is 255)
CLP1L [15:8] Clipping Y/R below this value.. (standard value is 0)
CLP1 [7:0] Clipping Y/R upper this value. (standard value is 255)
LCD Clipping Register 2 (LCP2) 0x9000D048

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CLP3L CL3Y
FIELD Description
CLP3L [15:8] Clipping V/B below this value.. (standard value is 0)
CLP3 [7:0] Clipping V/B upper this value. (standard value is 255)
Preliminary 2-21
LCD Keying Register (LK1) 0x9000D04C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A10<1:0> KR1<7:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KG1<7:0> KB1<7:0>
LCD Keying Register (LK2) 0x9000D050

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A20<1:0> KR2<7:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
KG2<7:0> KB2<7:0>
LCD Keying Mask Register (LKM1) 0x9000D054

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A11<1:0> MKR1<7:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MKG1<7:0> MKB1<7:0>
LCD Keying Mask Register (LKM2) 0x9000D058

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
A21<1:0> MKR2<7:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MKG2<7:0> MKB2<7:0>
LCD Display Size Register (LDS) 0x9000D05C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
VSIZE<11:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
HSIZE<11:0>
FIELD Description
VSIZE [27:16] Horizontal size : number of active pixel in a line
HSIZE [11:0] Vertical size : number of active lines
2-22 Preliminary
LCD Status Register (LSTATUS) 0x9000D060

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ITY ICR 0 BY EF DD RU 0 0 FU
FIELD Description
Interrupt Type
ITY 0 : Pulse type
1 : hold-up type when respond signal (ICR) is high.
ICR Interrupt Clear (using ITY is level type)
Busy signal
BY When LCDC is operating, this bit is set to 1. If LEN is disable, BY will be 0 after
current frame has been displayed.
Even-field (read only)
EF [5] 0 : Odd field or frame
1 : Even field or frame
Disable Done (Read/Clear)
DD [4] If LEN is disabled, DD will be 1 after current frame has been displayed. As
MDD of LIM register is cleared, it can be LCD interrupt source.
Register update (Read/Clear)
RU [3] It indicates that all registers programmed are applied to current frame data. As
MRU of LIM register is cleared, it can be LCD interrupt source.
FIFO underrun (Read/Clear)
It indicates that FIFO underrun has been occurred. In this case, LCLK
FU [0]
frequency must be lower. As MFU of LIM register is cleared, it can be LCD
interrupt source.
LCD Interrupt Masking Register (LIM) 0x9000D064

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
MDD MRU 0 0 MFU
FIELD Description
MDD [4] Masking disable done interrupt.
MRU [3] Masking register update interrupt
MFU [0] Masking FIFO underrun interrupt.
Preliminary 2-23
LCD Image0 Control Register (LI0C) 0x9000D068

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OP BR YUV BPP
OP [13:12] Overay Priority

- 1st priority - 2nd priority – 3rd priority
0 Image 0 – image 1 – image 2
y OP field of LI0C reg. is equal to OP dield of LI1C and LI2C
BR [7] Bit Reverse

0 Little endian pixel data
1 Big endian pixel data
y It is only used when BPP is 1, 2, or 4 bpp
YUV[6] YUV[5] YUV[4] YUV

0 0 1 YUV 4:2:0
0 1 1 YUV 4:2:2
1 1 1 YUV 4:2:2 patch
y This value is valid only if the BPP[3:0] is 3.
y At the YUV422Patch mode, the sequence of channel is V0-Y1-U0-Y0 (MSB first)
BPP [3:0] Bit Per Pixel for Input

0 1bbp
1 2bpp
2 4bpp
3 332bpp or YUV
332bpp if the YUV[4] is 0.
YUV if the YUV[4] is 1.
4 444bpp
5 565bpp
6 555bpp
7 888bpp
2-24 Preliminary
LCD Image0 Position Register (LI0P) 0x9000D06C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IMG_Y<10:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMG_X<10:0>
FIELD Description
IMG_Y [26:16] Y position to display.
IMG_X [10:0] X position to display.
LCD Image0 Size Register (LI0S) 0x9000D070

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HEIGHT<11:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIDTH<11:0>
FIELD Description
HEIGHT Image0 height
[27:16]
WIDTH [10:0] Image0 width
LCD Image0 Base Address0 (LI0BA0) 0x9000D074

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I0_BASE0<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I0_BASE0<15:2> 0
FIELD Description
I0_BASE0 Image0 base address
[31:2] If a image0 is YUV data, it is Y base address.
Preliminary 2-25
LCD Image0 Current Address (LI0CA) 0x9000D078

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I0_CUR<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I0_CUR<15:0>
FIELD Description
I0_CUR [31:0] Image0 current address.
LCD Image0 Base Address1 (LI0BA1) 0x9000D07C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I0_BASE1<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I0_BASE1<15:2> 0
FIELD Description
Image0 base address
I0_BASE1
If a image0 is YUV data, it is U base address.
[31:2]
Otherwise, it is not used.
LCD Image0 Base Address2 (LI0BA2) 0x9000D080

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I0_BASE2<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I0_BASE2<15:2> 0
FIELD Description
Image0 base address
I0_BASE2
If a image0 is YUV data, it is V base address.
[31:2]
Otherwise, it is not used.
LCD Image0 Offset (LI0O) 0x9000D084

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I0_OFS1<26:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I0_OFS0<10:0>
2-26 Preliminary
FIELD Description
Image0 offset.
I0_OFS1[26:16]
Address offset in U or V channel of FIFO (FIFO1,2)
Image0 offset.
I0_OFS0 [10:0]
Address offset in Y channel of FIFO (FIFO0).
LCD Image0 Scale (LI0SCALE) 0x9000D088

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Y_SCALE X_SCALE
SCALE[3] [2] [1] [0] Description

0 0 0 0 Non-Scalable
0 0 0 1 Downscale by 2
1 0 0 1 Upscale by 2
Preliminary 2-27
LCD Image1 Control Register (LI1C) 0x9000D08C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BR YUV BPP
BR [7] Bit Reverse


1 1 1 YUV 4:2:2 patch
Other values are not allowed.

0 1bbp
1 2bpp
2 4bpp
3 332bpp or YUV
4 444bpp
5 565bpp
6 555bpp
7 888bpp
LCD Image 1 Position Register (LI1P) 0x9000D090

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IMG_Y<10:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IMG_X<10:0>
FIELD Description
2-28 Preliminary
LCD Image 1 Size Register (LI1S) 0x9000D094

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HEIGHT<11:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIDTH<11:0>
FIELD Description
HEIGHT Image1 height
[27:16]
WIDTH [10:0] Image1 width
LCD Image 1 Base Address0 (LI1BA0) 0x9000D098

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I1_BASE0<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I1_BASE0<15:2> 0
FIELD Description
I1_BASE0 Image 1 base address
[31:2] If a image 1 is YUV data, it is Y base address.
LCD Image 1 Current Address (LI1CA) 0x9000D09C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I1_CUR<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I1_CUR<15:0>
FIELD Description
I1_CUR [31:0] Image 1 current address.
Preliminary 2-29
LCD Image 1 Offset (LI1O) 0x9000D0A8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I1_OFS0<10:0>
FIELD Description
Image 1 offset.
I1_OFS0 [10:0]
LCD Image1 Scale (LI1SCALE) 0x9000D0AC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 Y_SCALE X_SCALE

2-30 Preliminary
LCD Image2 Control Register (LI2C) 0x9000D0B0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
LUT BR YUV BPP
LUT [9] Use Lookup Table

0 Not used
1 Use the Color Lookup Table
y It is only used when BPP is 332 bpp
y Refer to 14.7 LCD lookup table.
BR [7] Bit Reverse


1 1 1 YUV 4:2:2 patch
Other values are not allowed.

0 1bbp
1 2bpp
2 4bpp
3 332bpp or YUV
4 444bpp
5 565bpp
6 555bpp
7 888bpp
LCD Image 2 Position Register (LI2P) 0x9000D0B4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IMG_Y<10:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Preliminary 2-31
IMG_X<10:0>
FIELD Description
LCD Image 2 Size Register (LI2S) 0x9000D0B8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
HEIGHT<11:0>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WIDTH<11:0>
FIELD Description
HEIGHT Image 2 height
[27:16]
WIDTH [10:0] Image 2 width
LCD Image 2 Base Address0 (LI2BA0) 0x9000D0BC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2_BASE0<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2_BASE0<15:2> 0
FIELD Description
I2_BASE0 Image 2 base address
[31:2] If a image 2 is YUV data, it is Y base address.
2-32 Preliminary
LCD Image 2 Current Address (LI2CA) 0x9000D0C0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
I2_CUR<31:16>
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2_CUR<15:0>
FIELD Description
I2_CUR [31:0] Image 2 current address.
LCD Image 2 Offset (LI2O) 0x9000D0CC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
I2_OFS0<10:0>
FIELD Description
Image 2 offset.
I2_OFS0 [10:0]
LCD Image2 Scale (LI2SCALE) 0x9000D0D0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Y_SCALE X_SCALE

Preliminary 2-33
Dual LCD Control (DLCTRL) 0x9000D0D4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DRE DLE
DRE [4] Dual LCD Register Update Enable

0 Disable
1 Enable
DLE [0] Dual LCD Operation Enable

0 Disable
1 Enable
y -
Dual LCD Configuration Start Address 0 (DLCSA0) 0x9000D0DC

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLCSA0[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLCSA0[15:2]
FIELD Description
DLCSA0 [31:2] Configuration start address for LCD0.
Dual LCD Configuration Start Address 1 (DLCSA1) 0x9000D0E0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DLCSA1[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DLCSA1[15:2]
FIELD Description
DLCSA1 [31:2] Configuration start address for LCD1.
YCbCr to RGB Conversion Parameter 0 (Y2RP0) 0x9000D0E4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Y
FIELD Description
Y [7:0] Refer to Figure 2.12
2-34 Preliminary
YCbCr to RGB Conversion Parameter 1 (Y2RP1) 0x9000D0E8

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CR2 CR1
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CB2 RCr
FIELD Description
CR2 [31:24] Refer to Figure 2.12
CR1 [23:16] Refer to Figure 2.12
CB2 [15:8] Refer to Figure 2.12
CB1 [7:0] Refer to Figure 2.12
R = 1.164(Y-16) + 1.596(Cr-128)
= Y + Cr - 233 + 0.164*Y + 0.596*Cr
Figure 2.12 LCD system interface block diagram
Preliminary 2-35
2.6 LCD Lookup Table (0x9000DC00 ~ 0x9000DFFF)
The LCDC supports the 24(width)-by-255(depth) bits color lookup table and the table
is connected from FIFO2 (3rd image channel). The range of lookup data address is
from 0x9000Dc00 to 0x9000Dfff (255 depth) and one data is 24bit data that is composed
by blue, green, red channel in sequence. The other 8 bit is garbage and located MSB 8bit.
For using the color lookup table, the LCDC set image 3 enable cause the table is
connected 3rd image channel and BPP mode set BPP332, YUV mode set clear. And
lookup table is initialized before the operating. The data of BPP332 (8 bits) is used the
address of color lookup table.
32 bit width
LCD Color Lookup Table

Garbage Blue Green Red
0x00 (Reg. : 0xF0000C00) Address (8 bit) : input data of BPP332 mode

Data (24 bit) :Blue-Green-Red channel
255 word depth
Not Used
0xFF (Reg. : 0xF0000FFC)
Figure 2.13 LCD Color Lookup Table
2-36 Preliminary
Multimedia Application Processor LCD SYSTEM INTERFACE
3 LCD system interface
3.1 Overview
The TCC82xx has LCD system interface (LCDSI) for LCD module which has 68/80-
system interface. So, an LCD module that has 68/80-system interface with 16-bit / 9-
bit/8-bit data width can be connected to the TCC82xx via LCDSI. And LCDSI can be
accessed by both LCDC and on-chip CPU. Therefore, the type of input source must be
specified before it is used. And setup time, hold time, and pulse width of nRD and
nWR signals are programmable.
AHB
TFT
mode Register AHB to 80
bank system bus
LVSYNC
nCS0
GPA[12]
LHSYNC AHB nCS1
LCD to LBIAS, GPC[3]
LCD LPXCLK 80 nRD
to 80 system GPA[13]
controller nWR
LACBIAS AHB system bus GPA[14]
bus mux RS
LPXD LCDHS, GPC[1]
LCDXD
LCDPD, GPC[19:4]
RGB565
LCD System Interface
or
RGB888
Figure 3.1 LCD system interface block diagram
3.2 Operation
Because the TCC82xx supports various GPIO modes, ports related to LCDSI must be
configured before it is used. And LCDSI configuration is different as it is connected to
LCDC or on-chip CPU bus. Figure 3.1 shows its relationship simply. The flowing
describes how to configure LCDSI for connecting to LCDC and on-chip CPU bus.
LCDSI CTRL0.MD
S
On-chip CPU
HADDR[7:0] D0 HADDR[4]
bus nCS0
HADDR[5]
MUX nCS1
LCDC to HADDR[3]
HADDRlcd[7:0] D1 RS
AHB
HADDRlcd[7:6] = 0
HADDRlcd[5:4] = (LCDSI CTRL0.CS == 0) ? 1 : 2
HADDRlcd[3] = LCDSI CTRL0.RSP
HADDRlcd[2:0] = 0
Figure 3.2 Relationship between nCS/RS and address
Preliminary 3-1
3.2.1 GPIO configuration for LCDSI
GPIO configuration registers corresponding to LCDSI signals, which are nCS0, nCS1,
nWR, nRD, RS and LCDXD, must be configured to LCDSI mode. Table shows GPIO
configuration for LCDSI.
Table 3.1 GPIO configuration for LCDSI

LCDSI signals PIN Name GPIO CFG REG.
nCS0 GPA12 PORTCFG1.LCTRL=1
nCS1 LBIAS(=GPC3) PORTCFG1.LCDC=1
nRD GPA13 PORTCFG1.LCTRL=1
nWR GPA14 PORTCFG1.LCTRL=1
RS LCDHS(= GPC1) PORTCFG1.LCDC=1
LCDXD[3:0] LCDPD[7:0](= GPC[7:4]) PORTCFG1.LCD03=1
LCDXD[7:4] LCDPD[7:4](=GPC[11:8]) PORTCFG1.LCD47=1
LCDXD[15:8] LCDPD[15:8](=GPC[19:12]) PORTCFG1.LCDU8=0

- - PORTCFG2.LCDSEL=1
3.2.2 Reading/Writing operation through on-chip CPU
LCDSI allows on-chip CPU to read from and write to an external LCD module, which
has 68/80-system interface. To access the device which is connected to nCS0 or nCS1,
on-chip CPU must program LCDSI CTRL0.IM to 0. After that, if on-chip CPU accesses
LCDSI CS0RS0 register, then reading or writing operations are generated on the device
connected to nCS0. While these operations are executed, RS is low (Figure 3.3 (a)). If on-
chip CPU accesses LCDSI CS0RS1 register, RS is high (Figure 3.3 (b)). Similarly, to
access the device connected to nCS1, on-chip CPU must access LCDSI CS1RS0 or
LCDSI CS1RS1 register. Notice that RS signal is regardless of LCDSI CTRL0.RSP when
LCDSI CTRL0.IM = 0.
And timing and data width configuration about LCDSI output signals can be
programmed via LCDSI CTRL1-4 registers. Refer to page 2 -3-8 for more information
about LCDSI CTRL1-4 registers.
3-2 Preliminary
nCS0 or 1
RS
nWR
nRD
WDATA WDATA RDATA RDATA

LCDXD #1 #2
#1 #2
(a) Writing to and Reading from LCDSI CSxRS0
nCS0 or 1
RS
nWR
nRD
WDATA WDATA RDATA RDATA

LCDXD #1 #2
#1 #2
(b) Writing to and Reading from LCDSI CSxRS1
Figure 3.3 Writing / Reading operation through on-chip CPU
3.2.3 Writing operation through LCD Controller
For converting LCDC control signals to 68/80-system interface signals, LCDC must be
configured to TFT mode. And LPXD must be RGB565 or RGB888 and driven at
negative edge of LPXCLK. LACBIAS and LVSYNC polarity is also configured by
LCDSI CTRL0.IA and LCD CTRL0.IVS and the values must be same with them of
LCDC polarity registers. Refer to LCDC register set for more information.
Preliminary 3-3
Figure 3.4 Example of LCDC output signals for LCDSI
To enter this mode, LCDSI CTRL0.IM must be set to 1. If this register field is set, LCDSI
CTRL0.CS, CTRL0.RSP, CTRL0.FMT, CTRL0.IVS, and CTRL0.IA registers are
available. These register fields specify nCS, RS, and output pixel data format during
operation and polarity of LVSYNC and LACBIAS signal. For example, if an LCD
module is connected to nCS0 and requires RS signal to be low, LCDSI CTRL0.CS and
LCDSI CTRL0.RSP must be set to 0.
And LCDSI output signals can be adjusted by programming LCDSI CTRL1[31:16]

register. Notice that these registers can be accessed when CTRL0.IM = 0. Therefore,
timing parameters need to be set before CTRL0.IM is set to 1. LCDXD is dependent on
LCDC LPXD, LCDSI CTRL0.FMT register and LCDSI CTRL1,2,3,4.WBW register.
Refer to Figure 3.5 about all of LCDXD formats which are supported by LCDSI.
The following is the procedure that one frame data of LCDC send to LCD module
through LCDSI.
Set LCDSI CTRL0.IM=0.

Set LCDSI CTRL0 register except CTRL0.IM.
Set the timing parameters for LCD module via LCDSI CTRL1-4 registers.
Set LCDC register for one frame data.
Set LCDSI CTRL0.IM=1.
Enable LCDC and Disable it sequentially.
If LCDC is not disabled at 6, LCDC output data are sent to LCD module through
LCDSI continuously.
3-4 Preliminary
3.3 Register Descriptions
All control registers for LCDSI are listed in Table 3.2.
Table 3.2 LCDSI Register map(0x9000D000)

LCDSI CTRL0 0x400 R/W 0x00000000 Control register for LCDSI
LCDSI CS0RS01 0x810 R/W - If this register is read or written, reading
or writing operations are generated on
nCS0 while RS = 0.
nCS0 while RS = 1.
nCS1 while RS = 0.
nCS1 while RS = 1.
Preliminary 3-5
LCDSI CTRL0 0x9000D400

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
IA2 IVS2 0 CS 1 RSP2 FMT2 OM IM
IM Input Mode
It converts on-chip CPU signals to 68/80-system interface
0
signals.
It converts LCDC output signals to 68/80-system interface
signals. Before this bit is set, LCDC must be configured with
1
TFT RGB565 or RGB888 mode. If TFT RGB565 mode is used,
FMT[0] bit must be set to 0.
OM Output Mode
0 LCDSI output signals are 80-system interface type.
LCDSI output signals are 68-system interface type.
1 nRD : R/W signal
nWR: Enable signal
FMT[5:2] Pixel Data Format

LCDC pixel data output : D1[15:0] (RGB565)
0000 LCDSI pixel data output(8bits) : D1[7:0], D1[15:8]
LCDSI CTRL1-4.WBW must be 1.
0110 LCDSI pixel data output (16bits) : D1[15:0]
LCDC pixel data output : D1[7:0], D2[7:0], D3[7:0] (RGB888)
0001 LCDSI pixel data output (8bits): D1[7:0], D2[7:0], D3[7:0]
0011 LCDSI pixel data output (9bits) : {D1[7:2],D2[7:5]}, {D2[4:2], D3[7:2]}
0101 LCDSI pixel data output (16bits): D1[7:6], {D1[5:2], D2[7:2], D3[7:2]}
0111 LCDSI pixel data output (16bits): {D1[7:3], D2[7:2], D3[7:3]}
1000 LCDSI pixel data output (16bits): {D1[17:9]}, {D2[8:0]}
1010 LCDSI pixel data output (16bits): {D1[17:2]}, {D2[1:0]}
1100 LCDSI pixel data output (16bits): {D1[17:0]}
1
These bits are only available when LCD SI CTRL0.IM is 1.
3-6 Preliminary
nCS
RS LCDSI CTRL0.RSP LCDSI CTRL0.RSP
nWR
LCDXD D1 [7:0] D1[15:8] D2[7:0] LCDXD D1[15:0] D2[15:0] D3[15:0]

[7:0] #1 #2 #3
[15:0] #1 #2 #3
FMT = 000 FMT = 110
nCS
nWR
LCDXD D1[7:0] D2[7:0] D3[7:0] LCDXD D1[7:2]

D2[7:5]
D2[4:2]
D3[7:2]
D1[7:2]
D2[7:5]
[7:0] #1 #2 #3
[8:0] #1 #2 #3
FMT = 001 FMT = 011
nCS
nWR
LCDXD D1[7:6]
D1[5:2],
D2[7:2], D4[7:6]
D1[7:3]
D2[7:2]
D4[7:3]
D5[7:2]
D7[7:3]
D7[7:2]
[15:0] D3[7:2]
D3[7:3]
#1
D6[7:3]
#2
D8[7:3]
#3
FMT = 101 FMT = 111
Figure 3.5 LCDSI output pixel data organization according to FMT
Preliminary 3-7
RSP RS Polarity
0 If IM is high, RS is low. Otherwise, it is not applicable.
1 If IM is high, RS is high. Otherwise, it is not applicable.
CS Chip select
If IM is high, CS0 is active during operations. Otherwise, it is
0
not applicable.
If IM is high, CS1 is active during operations. Otherwise, it is
1
not applicable.
IA Inverse ACBIAS
0 LACBIAS(Data Enable) signal is active high.
1 LACBIAS(Data Enable) signal is active low.
IVS Inverse VSYNC

0 LVSYNC signal is active high.
1 LVSYNC signal is active low.
3-8 Preliminary
Multimedia Application Processor
LCDSI CTRL1 – 4 0x9000D800, 0x9000D804, 0x9000D808, 0x9000D80C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BW[1] WSTP WPW WHLD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BW[0] RSTP RPW RHLD
BW[1:0] Bus Width

00 Data width is 8 bits.
10 Not used
STP Setup Time

N cycles are issued between the falling edge of nCS and the
N falling edge of nWR(Writing operation) or nRD(Reading
operation).
PW Pulse Width
(N+1) cycles are issued between the falling edge of nWR(or
N
nRD) and the rising edge of nWR(or nRD).
HLD Hold Time

N cycles are issued between the rising edge of nWR(or nRD)
N
and the rising edge of nCS.
* BUS clock is used to generate control signals.
Figure 3.6 Timing configuration for LCDSI output signals
LCDSI CTRL5 – 8 0x9000D830, 0x9000D834, 0x9000D838, 0x9000D83C
Preliminary 3-9
Multimedia Application Processor
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
W 2BW WSTP WPW WHLD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
BW Bus Width
0 Refer to Figure 3.5
1 Refer to Figure 3.5
STP Setup Time

N cycles are issued between the falling edge of nCS and the
N falling edge of nWR(Writing operation) or nRD(Reading
operation).
PW Pulse Width
(N+1) cycles are issued between the falling edge of nWR(or
N
nRD) and the rising edge of nWR(or nRD).
HLD Hold Time

N cycles are issued between the rising edge of nWR(or nRD)
N
and the rising edge of nCS.
* LCD clock is used to generate control signals.
Figure 3.7 Timing configuration for LCDSI output signals
2
Prefix W means writing operation.
3-10 Preliminary
SAD
Multimedia Application Processor SAD
4 SAD Calculator
4.1 Overview
The TCC82x has the SAD calculator block that calculates sum of absolute difference
(SAD) and deviation value from the reference frame image and the current frame
image. This block may be used for motion estimation during video encoding.
Current Frame
Buffer 1-D SAD
ENGINE
DMA
AHB
Controller
CONTROL
REGISTER
Figure 4-1 Block Diagram of SAD Calculator
Block diagram of SAD calculator is shown in Figure 1-1. The SAD calculator caculates
SAD or DEV (deviation value) result between the current frame macroblock and the
reference frame macroblock pointed by software. The start addresses of the
current/reference frame macroblock can be set through the DMA current/reference
start address registers, respectively.
4-2 Preliminary
Figure 4-2 Operation of SAD Calculator
Figure 4-2 1-D SAD Engine
4.2 SAD Calculation
The SAD calculator has two SAD calculation modes. The one is SAD16 mode
and the other is SAD8 mode. In SAD16 mode, the SAD calculator results out
SAD16 (macorblock SAD) and SAD8 (blocks SAD) value between the
specified current and reference macroblock. In SAD8 mode, the SAD
calculator results out SAD8 value between the specified current and reference
block. Figure 1-3 shows macroblock and block configuration.
< SAD16 mode >
SAD16 = ∑i
| cur _ pel (i) − ref _ pel (i ) | , i = 0, ..., 255
SAD8B0 = ∑j
| cur _ pel ( j ) − ref _ pel ( j ) | , j = 0, ..., 63
SAD8B1 = ∑k
| cur _ pel (k ) − ref _ pel (k ) | , k = 0, ..., 63
Preliminary 4-3
SAD8B2 = ∑ l
| cur _ pel (l ) − ref _ pel (l ) | , l = 0, ..., 63
SAD8B3 = ∑ m
| cur _ pel (m) − ref _ pel (m) | , m = 0, ..., 63
< SAD8 mode >
SAD8 = ∑
i
| cur _ pel (i ) − ref _ pel (i ) | , i = 0, ..., 63
4.3 DEV Caclulation
The SAD calculator has two DEV calculation modes. The one is DEV16 mode
and the other is DEV8 mode. In DEV16 mode, the SAD calculator results out
DEV16 (macorblock DEV) and DEV8 (blocks DEV) value between the
specified current and reference macroblock. In DEV8 mode, the SAD
calculator results out DEV8 value between the specified current and
reference block. The calculation of deviation value in SAD calculator consists
of two steps. In first, the mean value of the specified macroblock or block is
calculated and in second, the deviation value of the specified macroblock or
block is calculated using the mean value. The following equation shows the
definition of the mean value and deviation value. Figure 1-3 shows
macroblock and block configuration.
< DEV16 mode >
MEAN16 = ∑ i
pel (i ) / 256 , i = 0, ..., 255
DEV16 = ∑ i
| pel (i ) − MEAN16 | , i = 0, ..., 255
DEV8B0 = ∑ j
| pel ( j ) − MEAN16 | , j = 0, ..., 63
DEV8B1 = ∑ k
| pel (k ) − MEAN16 | , k = 0, ..., 63
DEV8B2 = ∑ l
| pel (l ) − MEAN16 | , l = 0, ..., 63
DEV8B3 = ∑ m
| pel (m) − MEAN16 | , m = 0, ..., 63
< DEV8 mode >
MEAN8 = ∑ i
pel (i ) / 64 i = 0, ..., 63
DEV8 = ∑ i
| pel (i ) − MEAN 8 | , i = 0, ..., 63
4-4 Preliminary
B0(j) B1(k) B0(j) B1(k)
B2(l) B3(m) B2(l) B3(m)
Current MB(i) Reference MB(i)
< Macroblock mode >
B0(i) B0(i)
Current Block(i) Reference Block(i)
< Block mode >
Figure 4-3 block configuration
4.4 DMA Operation
The DMA controller of the SAD calculator loads a current/reference frame

MB (MacroBlock) data from frame memory when enabled. DMA transfer
modes are shown in Figure 4-4.
Preliminary 4-5
Figure 4-4 DMA Transfer Mode
4-6 Preliminary
4.5 Registers
Table 4.1 Base Address for SAD Calculator

Base Addr. ARM946ES
SAD_BASE 0x9000A000
Table 4.2 SAD DMAC register map

Name Offset TYPE Reset Description
Start address of the reference 20x20
REFADR 0x00 R/W 0x00000000
image.
Start address of the current
CURADR 0x04 R/W 0x00000000
macroblock.
OFFSET 0x08 R/W 0x00000000 Stride line register in word size.
STATUS 0x0C R/C 0x00000000 Status register
CONTROL 0x10 R/W 0x00000000 DMA control register
SAD result value (DF = 0)
SADOUT 0x14 R 0x00000000 DEV result value (DF = 1)
MEAN result value (MF = 1)
SAD8_B01OUT 0x18 R 0x00000000
SAD8_B23OUT 0x1C R 0x00000000
SADSTATUS 0x20 R/C 0x00000000 Status register
REFADR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
REFADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
REFADR[15:0]
REFADR[31:0] Reference Frame Address

It represents the start address of 16x16 macroblock (left-upper)
address
in the reference frame image.
CURADR
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CURADR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CURADR[15:0]
CURADR[31:0] Current Macroblock Address
Preliminary 4-7
It represents the start address of 16x16 macroblock (left-

address
upper) in the current frame image.
OFFSET
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
OFFSET[15:0]
OFFSET [15:0] OFFSET

It represents the horizontal line address offset of image in
0 ~ 0xFFFF words. (between the last MB pel of the previous line and the
first MB pel of the next MB line)
STATUS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved MAINFSM Reserved DMAFSM
DMAFSM[10:8] DMA FSM
DMA controller FSM state
MAINFSM[3:0] MAIN FSM
Main controller FSM state
CONTROL
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved BST Reserved IRQT IRQD
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved DF MF MODE Reserved IEN CEN EN
BST[24] BURST Transfer

0 DMA transfer executed with arbitration
(4 words burst, IDLE cycles are inserted between bursts)
1 DMA transfer executed with no arbitration

( 16 words burst, All MB pels transferred without IDLE cycle)
IRQT [19] Interrupt Type

0 Pulse (default)
1 Level
4-8 Preliminary
IRQD [18:16] Interrupt Pulse Duration
N (0 ~7) N + 1 clock duration (only for pulse mode)
DF [10] Deviation Flag

0 Disable deviation calculation
1 Enable deviation calculation
MF [9] Mean Flag

0 Disable mean calculation
1 Enable mean calculation
MODE[8] Mode
0 SAD16 mode
1 SAD8 mode
IEN[2] Interrupt Enable

0 Interrupt is not generated.
1 Interrupt is generated when DMA operation has been done.
CEN[1] Current macroblock load enable

Start current MB load (auto-cleared when current MB load
done)
1
If Mean mode enabled, also calculate mean value for current
MB
EN[0] SAD calculator enable
Start reference MB load and SAD calculation (auto-cleared
when SAD calculation done)
1
When Dev mode enabled, calculate deviation value for
current MB
SADOUT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved MEAN
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAD16[15:0]
Preliminary 4-9
MEAN[23:16] MEAN result

When mode = 0(SAD16 mode), MEAN16 result value (MF = 1).
MEANOUT
When mode = 1 (SAD8 mode), MENA8 result value (MF = 1)
SAD16[15:0] SAD16 result

When mode = 0(SAD16 mode), SAD16 result value (DF = 0).
When mode = 1 (SAD8 mode), SAD8 result value (DF = 0)
SADOUT
When mode = 0(SAD16 mode), DEV16 result value (DF = 1).
When mode = 1 (SAD8 mode), DEV8 result value (DF = 1)
SAD8_B01OUT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved SAD8_B1[13:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAD8_B0[13:0] SAD8_B0 result

Calculated Block0 SAD8 result value (DF = 0)
SAD8_B0
Calculated Block0 DEV8 result value (DF = 1)

Calculated Block1 SAD8 result value (DF = 0)
SAD8_B1
Calculated Block1 DEV8 result value (DF = 1)
SAD8_B23OUT
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SAD8_B2 Calculated Block2 SAD8 result value (DF = 0)
SAD8_B3 Calculated Block3 SAD8 result value (DF = 0)
4-10 Preliminary
SADSTATUS
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
Reserved
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
Reserved DONE
DONE[0] SAD DONE

SAD calculation has been done. This bit is cleared to 0 when
1
being read.
Preliminary 4-11
2D DMA
Multimedia Application Processor 2D DMA
1 2D DMA
1.1 Overview
The Two Dimensional DMA(2D-DMA) has the functions such as rotating or flipping
image or bitwise ROP(Raster Operation) in addition to general DMA function which
supports two dimensional DMA transfer. The 2D-DMA has two independent
channels and each channel contains two AHB master ports. But, the total four AHB
master ports are shared into the two external ports in the 2D-DMA through the port
arbitration logic as showed in the following figure. One of two isolated master ports is
connected directly to the 1Kbytes internal memory, and the other port is to access all
global address space. Each channel includes the input data buffer sized up to 8 words.
With the 2D-DMA, image data allocated in a memory region can be rotated by 90, 180,
and 270 degrees, and can be flipped horizontally or vertically, and can be the raster
operation. The 2D-DMA reads the original image data and writes these data in
modified addressing order for rotation and flipping. This process can be improved by
the intermediate buffer allocated in the internal memory. The buffering architecture
uses memory as double buffer, therefore the wait time can be minimized. The 2D-
DMA can apply these functions only to specific local region which is appointed by
configuration register. This mode is useful when a part of image should be operated
and the other part should be passed. The 2D-DMA supports several pixel-based
arithmetic functions such as adding, subtracting, filling, and multiplying. Additionally,
the 2D-DMA supports the ROP and the color image format converting. When the
2D-DMA operates in these functions, the general DMA function is prohibited.
Figure 1-1 2D-DMA Block Diagram
Preliminary 1-1
1.2 Registers
Table 1-1 2D DMA Register Map (Base Address = 0x90005000)
SRCA_F 0x00 R/W 0x00000000 Front Source Address Register
SRCOFF_F 0x04 R/W 0x00000000 Front Source Offset Register
DSTA_F 0x08 R/W 0x00000000 Front Destination Address Register
DSTOFF_F 0x0C R/W 0x00000000 Front Destination Offset Register
NUMT_F 0x10 R/W 0x00000000 Front Transfer Count Number Register
SRCA_B 0x14 R/W 0x00000000 Back Source Address Register
SRCOFF_B 0x18 R/W 0x00000000 Back Source Offset Register
DSTA_B 0x1C R/W 0x00000000 Back Destination Address Register
DSTOFF_B 0x20 R/W 0x00000000 Back Destination Offset Register
NUMT_B 0x24 R/W 0x00000000 Back Transfer Count Number Register
SRC1A_R 0x28 R/W 0x00000000 ROP Source 1 Address Register
SRC1OFF_R 0x2C R/W 0x00000000 ROP Source 1 Offset Register
SRC2A_R 0x30 R/W 0x00000000 ROP Source 2 (Y) Address Register
SRC2OFF_R 0x34 R/W 0x00000000 ROP Source 2 Offset Register
SRC2CBA_R 0x38 R/W 0x00000000 ROP Source 2 Cb Address Register
SRC2CRA_R 0x3C R/W 0x00000000 ROP Source 2 Cr Address Register
DSTA_R 0x40 R/W 0x00000000 ROP Destination (Y) Address Register
DSTOFF_R 0x44 R/W 0x00000000 ROP Destination Offset Register
DSTCBA_R 0x48 R/W 0x00000000 ROP Destination Cb Address Register
DSTCRA_R 0x4C R/W 0x00000000 ROP Destination Cr Address Register
IMGSIZE 0x50 R/W 0x00000000 Image Size Register
MEMADDR 0x54 R/W 0x00000000 Buffer Memory Address Register
LOCAL 0x58 R/W 0x00000000 Local Region Configuration Register
FPVALUE 0x5C R/W 0x00000000 Fill / Pattern Value Register
IMGFM_R 0x60 R/W 0x00000000 ROP Image Format Register
CHROMA_R 0x64 R/W 0x00000000 ROP Chroma Value Register
CONTROL 0x70 R/W 0x00000000 Control Register
INT 0x74 R/W 0x00000000 Interrupt Register
INTEN 0x78 R/W 0x00000000 Interrupt Enable Register
Preliminary 1-2
Front Source Address Register (SRCA_F) 0x90005000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRCADR_F
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRCADR_F
This register value means the source address of the first DMA channel in the case of
general DMA mode( DMAGeneralUse bit is set in the CONTROL register ), otherwise
the start address of the source image data. This register is not used in the case of the
raster operation.
SRCADR_F Front Source Address Register

[31:0]
n The source start address of the first(frontend) DMA channel.
Front Source Offset Register (SRCOFF_F) 0x90005004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 SRCOFF_F
This register is not used when the DMAGeneralUse bit is ‘0’ in the CONTROL register.
This register is not used in the case of the raster operation.
SRCOFF_F Front Source Offset Register

[12:0]
n The source address offset of the first(frontend) DMA channel.
In 2-dimensional transferring, this means the source address difference between start
addresses of the current hop transfer and next hop transfer. In 1-dimensional
transferring, the start address of the current hop transfer and the end address of the
previous hop transfer are in each neighborhood. This register is not used in the case of
the raster operation.
Preliminary 1-3
Front Destination Address Register (DSTA_F) 0x90005008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSTADR_F
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSTADR_F
general DMA mode( DMAGeneralUse bit is set in the CONTROL register ). This
register is not used when the DMAGeneralUse bit is ‘0’ in the CONTROL register. This
register is not used in the case of the raster operation.
DSTADR_F Front Destination Address Register

[31:0]
n The destination start address of the first(frontend) DMA channel.
Front Destination Offset Register (DSTOFF_F) 0x9000500C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 DSTOFF_F
DSTOFF_F Front Destination Offset Register

[12:0]
n The destination address offset of the first(frontend) DMA channel.
In 2-dimensional transferring, this means the destination address difference between

start addresses of the current hop transfer and next hop transfer. In 1-dimensional
previous hop transfer are in each neighborhood. This register is not used in the case of
the raster operation.
Preliminary 1-4
Front Transfer Count Number Register (NUMT_F) 0x90005010

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 NHOPS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 NTRANS
This is meaningful only in the general DMA mode. This register is not used in the case
of the raster operation.
NHOPS [23:16] Hop Number ( Line Number )

0 The source start address of the first(frontend) DMA channel.
The number of burst transfers means the number lines if you want to transfer the 2-
dimensional data. If you want to transfer the 1-dimensional data, it means the number
of burst transfer, which is described below.
NTRANS [3:0] Transfer Number ( Horizontal Word Number )

0 The source start address of the first(frontend) DMA channel.
The number of words to transfer with linear address means that the horizontal number
of words. In case of 2 dimensional transferring, this is the number of words in a
horizontal line.
Preliminary 1-5
Back Source Address Register (SRCA_B) 0x90005014

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRCADR_B
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRCADR_B
This register value means the source address of the second DMA channel in the case of
SRCADR_B Back Source Address Register

[31:0]
n The source start address of the second(backend) DMA channel.
Back Source Offset Register (SRCOFF_B) 0x90005018

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 SRCOFF_B
SRCOFF_B Back Source Offset Register

[12:0]
n The source address offset of the second(backend) DMA channel.
In 2-dimensional transferring, this means the source address difference between start
addresses of the current hop transfer and next hop transfer. In 1-dimensional
previous hop transfer are in each neighborhood.
Preliminary 1-6
Back Destination Address Register (DSTA_B) 0x9000501C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSTADR_B
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSTADR_B
DSTADR_B Back Destination Address Register

[31:0]
n The destination start address of the second(backend) DMA channel.
Back Destination Offset Register (DSTOFF_B) 0x90005020

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 DSTOFF_B
DSTOFF_B Back Destination Offset Register

[12:0]
n The destination address offset of the second(backend) DMA channel.
In 2-dimensional transferring, this means the destination address difference between

start addresses of the current hop transfer and next hop transfer. In 1-dimensional
previous hop transfer are in each neighborhood.
Preliminary 1-7
Back Transfer Count Number Register (NUMT_B) 0x90005024

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 NHOPS
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 NTRANS
This is meaningful only in the general DMA mode. This register is not used in the case
of the raster operation.
NHOPS [23:16] Hop Number ( Line Number )

0 The source start address of the second(backend) DMA channel.
The number of burst transfers means the number lines if you want to transfer the 2-
dimensional data. If you want to transfer the 1-dimensional data, it means the number
of burst transfer, which is described below.
NTRANS [3:0] Transfer Number ( Horizontal Word Number )

0 The source start address of the second(backend) DMA channel.
The number of words to transfer with linear address means that the horizontal number
of words. In case of 2 dimensional transferring, this is the number of words in a
horizontal line.
Preliminary 1-8
ROP Source 1 Address Register (SRC1A_R) 0x90005028

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRC1ADR_R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRC1ADR_R
This register value means the source 1 address of the third DMA channel for the raster
operation. This register is not used in the case of general DMA
mode( DMAGeneralUse bit is set in the CONTROL register ). This is meaningful only
in the raster operation.
SRC1ADR_R ROP Source 1 Address Register

[31:0]
n The source 1 start address of the third(ROP) DMA channel.
ROP Source 1 Offset Register (SRC1OFF_R) 0x9000502C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 SRC1OFF_R
This register is not used when the DMAGeneralUse bit is set in the CONTROL register.
SRC1OFF_R ROP Source 1 Offset Register

[12:0]
n The source 1 address offset of the third(ROP) DMA channel.
In 2-dimensional transferring, this means the ROP source 1 address difference between
start addresses of the current hop transfer and next hop transfer. . In 1-dimensional
transferring, this register is not used.
Preliminary 1-9
ROP Source 2 (Y) Address Register (SRC2A_R) 0x90005030

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRC2ADR_R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRC2ADR_R
This register value means the source 2 address of the third DMA channel for the raster
operation. This is source 2 Y start address when SRC2IMGFM_R field of IMGFM_R
register is YCbCr separated format. This register is not used in the case of general DMA
mode( DMAGeneralUse bit is set in the CONTROL register ). This is meaningful only
in the raster operation.
SRC2ADR_R ROP Source 2 Address Register

[31:0]
n The source 2 start address of the third(ROP) DMA channel.
ROP Source 2 Offset Register (SRC2OFF_R) 0x90005034

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 SRC2OFF_R
This is meaningful only in the raster operation.
SRC2OFF_R ROP Source 2 Offset Register

[12:0]
n The source 2 address offset of the third(ROP) DMA channel.
In 2-dimensional transferring, this means the ROP source 2 address differences

between start addresses of the current hop transfer and next hop transfer. . In 1-
dimensional transferring, this register is not used.
Preliminary 1-10
ROP Source 2 Cb Address Register (SRC2CBA_R) 0x90005038

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRC2CBADR_R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRC2CBADR_R
This register value means the source 2 Cb address of the third DMA channel for the
raster operation. This is source 2 Cb start address when SRC2IMGFM_R field of
IMGFM_R register is only YCbCr separated format. This register is not used in the
case of general DMA mode( DMAGeneralUse bit is set in the CONTROL register ).
SRC2CBADR_R ROP Source 2 Cb Address Register

[31:0]
n The source 2 Cb start address of the third(ROP) DMA channel.
ROP Source 2 Cr Address Register (SRC2CRA_R) 0x9000503C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
SRC2CRADR_R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SRC2CRADR_R
This register value means the source 2 Cr address of the third DMA channel for the
raster operation. This is source 2 Cr start address when SRC2IMGFM_R field of
IMGFM_R register is only YCbCr separated format. This register is not used in the
case of general DMA mode( DMAGeneralUse bit is set in the CONTROL register ).
SRC2CRADR_R ROP Source 2 Cr Address Register

[31:0]
n The source 2 Cr start address of the third(ROP) DMA channel.
Preliminary 1-11
ROP Destination (Y) Address Register (DSTA_R) 0x90005040

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSTADR_R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSTADR_R
This register value means the destination address of the third DMA channel for the
raster operation. This is destination Y start address when DSTIMGFM_R field of
IMGFM_R register is YCbCr separated format. This register is not used in the case of
general DMA mode( DMAGeneralUse bit is set in the CONTROL register ). This is
meaningful only in the raster operation.
DSTADR_R ROP Destination Address Register

[31:0]
n The destination start address of the third(ROP) DMA channel.
ROP Destination Offset Register (DSTOFF_R) 0x90005044

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 DSTOFF_R
DSTOFF_R ROP Destination Offset Register

[12:0]
n The destination address offset of the third(ROP) DMA channel.
In 2-dimensional transferring, this means the ROP destination address difference

between start addresses of the current hop transfer and next hop transfer. . In 1-
dimensional transferring, this register is not used.
Preliminary 1-12
ROP Destination Cb Address Register (DSTCBA_R) 0x90005048

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSTCBADR_R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSTCBADR_R
This register value means the destination Cb address of the third DMA channel for the
raster operation. This is destination Cb start address when DSTIMGFM_R field of
IMGFM_R register is only YCbCr separated format. This register is not used in the case
of general DMA mode( DMAGeneralUse bit is set in the CONTROL register ). This is
DSTCBADR_R ROP Destination Cb Address Register

[31:0]
n The destination Cb start address of the third(ROP) DMA channel.
ROP Destination Cr Address Register (DSTCRA_R) 0x9000504C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
DSTCRADR_R
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
DSTCRADR_R
This register value means the destination Cr address of the third DMA channel for the
raster operation. This is destination Cr start address when DSTIMGFM_R field of
IMGFM_R register is only YCbCr separated format. This register is not used in the case
of general DMA mode( DMAGeneralUse bit is set in the CONTROL register ). This is
DSTCRADR_R ROP Destination Cr Address Register

[31:0]
n The destination Cr start address of the third(ROP) DMA channel.
Preliminary 1-13
Image Size Register (IMGSIZE) 0x90005050

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 VSIZE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 HSIZE
This register specifies the size of the whole input image or one part of image to be
operated. The values are based on pixel unit( one byte size ). In the raster operation,
The values are based on pixel unit of the each image (one byte, halfword and word
size)
VSIZE [28:16] Image Vertical Size

n The input image height ( vertical size )
HSIZE [12:0] Image Horizontal Size

n The input image width ( horizontal size )
In the raster operation, this value must be configured by 4 pixel unit.
(HSIZE[1:0] = ‘00’)
Buffer Memory Address Register (MEMADDR) 0x90005054

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 MEMADDR
This register indicates the start address offset of the internal buffer memory. The
internal buffer can be extended to 1Kbytes, and the MEMSIZE field in the CONTROL
register determines the size. The transfer size is 16x16 bytes (MEMSIZE field is ‘0’) and
the total buffer size needed becomes 16x16x4 bytes because of the double buffering
architecture. The memory used for buffer is assigned to internal memory. This register
is not used in the case of the raster operation.
MEMADDR Buffer Memory Address

[12:0]
n The start address of 1Kbytes buffer memory
Preliminary 1-14
Local Region Register (LOCAL) 0x90005058

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BOTR_Y BOTR_X
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
TOPL_Y TOPL_X
This register indicates the position information of the local region to be operated. These
values are not pixel-based, are based on the unit determined by the MEMSIZE field in
the CONTROL register. In other words, if MEMSIZE field is ‘0’, the unit size is 16.
Accordingly, the resolution of the local region operation is restricted by the minimum
transfer unit size in the buffering. This register is not used in the case of the raster
operation.
BOTR_Y Bottom Right Y

[31:24]
n The vertical position of the bottom right corner in the local region
BOTR_X Bottom Right X

[23:16]
n The horizontal position of the bottom right corner in the local region
TOPL_Y [15:8] Top Left Y

n The vertical position of the top left corner in the local region
TOPL_X [7:0] Top Left X

n The horizontal position of the top left corner in the local region
Preliminary 1-15
FILL / PATTERN VALUE Register (FPVALUE) 0x9000505C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
FPVALUE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
FPVALUE
This register is used as two kinds of services. One is the filling constant in the general
DMA operation, which fills the destination region as the constant data. The other is the
operand in the raster operation and the pixel scalar arithmetic function, which includes
filling, adding, subtracting, and multiplying. In general DMA mode, this register uses
the whole 32-bit value, but only 8-bit is used in the pixel scalar arithmetic function. In
the raster operation,. This register uses 32-bit pattern value on the color of RGB888
image format.
FPVALUE Fill / Pattern Value

[31:0]
n This value is used as the operand in pixel scalar arithmetic, or simply
filling constant in the general DMA operation, or the pattern value in the
raster operation.
FPVALUE[31:0] [31:24] [23:16] [15:8] [7:0]

Fill Value 0 fill[7:0]
Pattern Value (ROP) 0 R[7:0] G[7:0] B[7:0]
Preliminary 1-16
ROP Image Format Register (IMGFM_R) 0x90005060

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 SRC1IMGFM_R SRC2IMGFM_R DSTIMGFM_R
This register indicates the image format information of the source and destination
images. This is meaningful only in the raster operation.
SRC1IMGFM_R ROP Source 1 Image Format

[11:8]
n 0: RGB888
1: RGB666
2: RGB565
3: YCbCr 4:2:2 Sequential Format
4, 5: Reserved
SRC2IMGFM_R ROP Source 2 Image Format

[7:4]
n 0: RGB888
1: RGB666
2: RGB565
4: YCbCr 4:2:2 Separated Format
DSTIMGFM_R Destination Image Format

[3:0]
n 0: RGB888
1: RGB666
2: RGB565
Preliminary 1-17
The below tables are the details of the source1, source2 and destination image format.
Table 1-2 Details of Source 1 Image Format

Bit [31:0]
Source 1
3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
Image Format
1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
RGB888 0 R[7:0] G[7:0] B[7:0]

RGB666 0 R[7:2] G[7:2] B[7:2]
RGB565 R n+1 [7:3] G n+1 [7:2] B n+1 [7:3]
B R n [7:3] Gn [7:2] Bn [7:3]
B
YCbCr 4:2:2 Sequential Cr n [7:0] Y n+1 [7:0] Cb n [7:0] Y n [7:0]
Table 1-3 Details of Source 2 and Destination Image Format

Source 2 and Bit [31:0]
Destination 3 3 2 2 2 2 2 2 2 2 2 2 1 1 1 1 1 1 1 1 1 1 9 8 7 6 5 4 3 2 1 0
Image Format 1 0 9 8 7 6 5 4 3 2 1 0 9 8 7 6 5 4 3 2 1 0
RGB888 0 R[7:0] G[7:0] B[7:0]

RGB666 0 R[7:2] G[7:2] B[7:2]
RGB565 R n+1 [7:3] G n+1 [7:2] B n+1 [7:3]
B R n [7:3] Gn [7:2] Bn [7:3]
B
YCbCr 4:2:2 Sequential Cr n [7:0] Y n+1 [7:0] Cb n [7:0] Y n [7:0]

Y Y n+3 [7:0] Y n+2 [7:0] Y n+1 [7:0] Y n [7:0]
YCbCr 4:2:2
Cb … … Cb n +1[7:0] Cb n [7:0]
Separated
Cr … … Cr n+1 [7:0] Cr n [7:0]
Y Y n+3 [7:0] Y n+2 [7:0] Y n+1 [7:0] Y n [7:0]
YCbCr 4:2:0
Cb … … … Cb n [7:0]
Separated
Cr … … … Cr n [7:0]
Preliminary 1-18
Chroma Register (CHROMA_R) 0x90005064

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0 CHROMAR
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CHROMAG CHROMAB
This register indicates the chroma-key value of the source 1 images and only uses in the
case of the raster operation. The values are based on the color of RGB888 image format.
CHROMAR Chroma-Key Value (Red)

[23:16]
n This value is used as the chroma-key value in the raster operation. This is
the red value of the RGB888 image format.
CHROMAG Chroma-Key Value (Green)

[15:8]
the green value of the RGB888 image format.
CHROMAB Chroma-Key Value (Blue)

[7:0]
the blue value of the RGB888 image format.
As see below table, the chroma-keying is only applied to the operations using both
source 1 and source 2.
Table 1-4 Use of Chroma-Key
Equation
ROP Functions Use of Chroma-Key
Src2 = Dst Src2 != Dst
Blackness 0 0 Impossible to use
Destination Invert ~Dst ~Src2 Impossible to use
Merge Copy Dst & Src Src2 & Src1 Possible to use
Merge Paint ~Src | Dst ~Src1 | Src2 Imossible to use
Not Source Copy ~Src ~Src1 Impossible to use
Not Source Erase ~(Src | Dst) ~(Src1| Src2) Impossible to use
Pat Copy P P Impossible to use
Pat Invert P ^ Dst P ^ Src2 Impossible to use
Pat Paint P | ~(Src| Dst) P | ~(Src1| Src2) Impossible to use
Source AND Src & Dst Src1 & Src2 Possible to use
Source Copy Src Src1 Impossible to use
Source Erase Src & ~Dst Src1 & ~Src2 Impossible to use
Source Invert Src ^ Dst Src1 ^ Src2 Possible to use
Source Paint Src | Dst Src1 | Src2 Possible to use
Whiteness 1 1 Impossible to use
Preliminary 1-19
Control Register (CONTROL) 0x90005070

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
BDTP BSTP BIEN BFILL BEN 0 FDTP FSTP FIEN FFIL FEN CHEN ROPFUNC
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
SCALARFUNC GEOFUNC 0 MEMSIZE DMAG LEN IEN MEN
The fields of the CONTROL register are categorized as two parts. One part as
CONTROL[31:20] is for two DMA channel in the general DMA functions, the other
part as CONTROL[19:0] is for geometric operation and pixel arithmetic and raster
operation in the 2D-DMA functions. If the DMAGeneralUse(DMAG) field is set to ‘1’,
the 2D-DMA operates only as a general DMA.
BDTP [31] Backend Destination Transfer Type

0 For writing port, the AHB port is used. This is to access global address
space.
1 For writing port, the internal memroy port is used. This is to access only
internal memory.
*) This bit is meaningless when the DMAGeneralUse is ‘0’.
BSTP [30] Backend Source Transfer Type
0 For reading port, the AHB port is used. This is to access global address
space.
1 For reading port, the internal memory port is used. This is to access only
internal memory.
BIEN [29] Backend Interrupt Enable
0 The interrupt is disabled.
1 The interrupt is enabled.
BFILL [28] Backend Fill Mode
0 Normal transfer
1 Writing the filling constant to the destination region
*) The filling constant is determined by the FPVALUE register. This bit is meaningless
when the DMAGeneralUse is ‘0’.
BEN [27] Backend DMA Enable
0 Backend DMA is disabled.
1 Backend DMA is enabled.
*) This bit is cleared automatically when the DMA transfer is over. This bit is
meaningless when the DMAGeneralUse is ‘0’. This bit is independent from the status
of the MEN bit.
Preliminary 1-20
FDTP [25] Frontend Destination Transfer Type

0 For writing port, the AHB port is used. This is to access global address
space.
1 For writing port, the internal memory port is used. This is to access only
internal memory.
FSTP [24] Frontend Source Transfer Type
0 For reading port, the AHB port is used. This is to access global address
space.
1 For reading port, the internal memory port is used. This is to access only
internal memory.
FIEN [23] Frontend Interrupt Enable
0 The interrupt is disabled.
1 The interrupt is enabled.
FFILL [22] Frontend Fill Mode
0 Normal transfer
1 Writing the filling constant to the destination region
*) The filling constant is determined by the FPVALUE register. This bit is meaningless
when the DMAGeneralUse is ‘0’.
FEN [21] Frontend DMA Enable
0 Frontend DMA is disabled.
1 Frontend DMA is enabled.
*) This bit is cleared automatically when the DMA transfer is over. This bit is
meaningless when the DMAGeneralUse is ‘0’. This bit is independent from the status
of the MEN bit.
Preliminary 1-21
CHEN [20] Chroma-Key Enable

0 Chroma-Key Disable
1 Chroma-Key Enable
ROPFUNC Raster Operation Function

[19:16] Mode Equation
n 0 : No Operation No Operation
1 : Blackness 0
2 : Destination Invert ~Dst
3 : Merge Copy Dst & Src
4 : Merge Paint ~Src | Dst
5 : Not Source Copy ~Src
6 : Not Source Erase ~(Src | Dst)
7 : Pat Copy P
8 : Pat Invert P ^ Dst
9 : Pat Paint P | ~(Src| Dst)
10 : Source AND Src & Dst
11 : Source Copy Src
12 : Source Erase Src & ~Dst
13 : Source Invert Src ^ Dst
14: Source Paint Src | Dst
15: Whiteness 1
*) The operand needed for this operation is assigned in the FPVALUE register, in
which only 32-bit data (RGB888) is used.
SCALARFUNC Scalar Arithmetic Function
[15:12]
n 0 : No operation
1 : Filling operation
2 : Pixel Inverting operation
3 : Pixel Adding operation
4 : Pixel Subtracting operation
5 : Pixel Multiplying operation
*) The operand needed for this operation is assigned in the FPVALUE register, in
which only 8-bit data is used.
GEOFUNC Geometric Function
[11:8]
n 0 : No operation
1 : Rotation 90 degrees
4 : Mirroring(flipping) horizontally
5 : Mirroring(flipping) vertically
6 : Mirroring(flipping) horizontally and vertically
*) The rotation direction is counter-clock-wise. The internal operation is identical when
GEOFUNC = 2 and GEOFUNC = 6.
Preliminary 1-22
MEMSIZE [5:4] Buffer Memory Unit Size

n 00 : One buffer transfer size is 16x16.
DMAG [3] DMA General Use

0 Image functional mode
1 General DMA mode
*) If user wants the 2D-DMA to operate as general DMA, DMAG should be set to ‘1’.
LEN [2] Local Region Enable
0 Normal mode
1 Local region operation mode
*) When this field is set, the 2D-DMA uses the LOCAL register as the information of
local region.
0 Interrupt disable
1 Interrupt Enable
*) This interrupt indicates that the 2D-DMA ends the geometric operations. Interrupts
in general DMA mode are controlled by the BIEN and the FIEN bits.
MEN [0] Main Enable
1 When the MODE bit is ‘0’, the next transferring is triggered only by this
bit. This bit is cleared automatically. In the case that the MODE bit is ‘1’,
this bit is meaningless.
*) This bit is used as the trigger when the MODE bit is ‘0’. But in the Pingpong
mode( the user should set the MODE bit as ‘1’) it is not used.
Preliminary 1-23
Interrupt Register (INT) 0x90005074

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 CB CF CD 0 B F DONE
CB [10] Clear Backend DMA Interrupt

1 The Backend DMA interrupt status is cleared.
*) This bit is write-only.

CF [9] Clear Frontend DMA Interrupt
1 The Frontend DMA interrupt status is cleared.

CD [8] Clear Done Interrupt
1 The Done interrupt status is cleared.

B [2] Backend DMA Interrupt Status
0 Not interrupted
1 Interrupted
*) This bit is read-only.
F [1] Frontend DMA Interrupt Status
0 Not interrupted
1 Interrupted
Done [0] Local Region Enable
0 Not interrupted
1 Interrupted
Preliminary 1-24
Interrupt Enable Register (INTEN) 0x90005078

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
0
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
0 B F DONE
B [2] Enable Interrupt for Backend DMA

0 Interrupt is disabled.
1 Interrupt is enabled.
F [1] Enable Interrupt for Frontend DMA

Done [0] Enable Interrupt for Done

Preliminary 1-25
1.3 General DMA Operations
The process of the 2D-DMA in the general DMA mode is similar to that of the VDMA.
Basically, the 2D-DMA supports two dimensional DMA transferring, which means
that arbitrary rectangular memory region is moved to another memory region through
one DMA programming. As the following figure, the user can configure vertical
count( NHOPS field in the NUMT register ), horizontal count( NTRNS field in the
NUMT register ), starting address, and horizontal line offset( SRCOFF or DSTOFF
register ). This function is suitable for image data transferring. Of course, it is possible to
transfer from/to linear address region by configuring the offset register.
Source Frame source start address Destination Frame
destination start
address
source Source destination Dest.

address Region address Region
offset offset
Src. NTRNS Dst. NTRNS
Figure 1-2 Example of two-dimensional DMA transfer
The configuration procedure is as following. Because there are two channel

DMA( Frontend and Backend ), the register naming omits the indication of the
frontend or the backend. Each channel has SRCA, DSTA, SRCOFF, DSTOFF, and
NUMT registers each other.
DMAG(DMAGeneralUse) bit in the CONTROL register should be set.

FDTP bit and FSTP bit in the CONTROL register should be defined. The value means
which port ( AHB or internal memory ) is used.
Source and destination starting address( SRCA, DSTA ) should be written.
Source and destination address offset( SRCOFF, DSTOFF ) should be defined.
Horizontal count(NTRNS) and vertical count(NHOPS) in the NUMT register should
be defined.
FEN or BEN bit in the CONTROL register is set, then the DMA channel starts to
operate.
Preliminary 1-26
1.4 Geometric Functions
The 2D-DMA has special features such as rotating, mirroring, and pixel arithmetic
operations. These features are based on memory-to-memory DMA operation. Namely,
a specific memory region is moved to another with modified address generation,
which is designed for rotating and mirroring. In order to improve speed and memory
burst characteristic, the whole input image is divided into uniform memory blocks,
which can be 16x16. The internal buffer is utilized when the memory blocks are
processed into rotated or mirrored blocks. The internal memory is mapped as the
internal buffer, therefore the user should not use internal memory for another purpose
when those special features of the 2D-DMA are enabled.
The following figure depicts the application examples of rotating and flipping. The
GEOFUNC field in the CONTROL register determines one of the total six modes.
These output images are obtained when the LOCAL bit is disabled in the CONTROL
register.
Horizontal Flip Horizontal & Vertical Flip Vertical Flip
Rotate by 90 degree Rotate by 270 degree

Rotate by 180 degree
Figure 1-3 Rotation and Flipping Image
The procedure of the geometric operation such as rotation or flipping is similar to the
general DMA register programming. In the geometric operation, both of two DMA
channels should be enabled. The first channel(fontend) DMA transfers input image
Preliminary 1-27
from frame memory to the internal buffer, and the second(backend) DMA is used to
transfer modified image block data from internal buffer to destination frame memory.
Because the connection and interface from/to the internal buffer are fixed, the
information of the destination in the frontend DMA and the information of the source
in the backend DMA are unnecessary. If the user wants to process only a part of input
image, the user can program the address register and the offset register as like a general
DMA programming.
The following describes the initial register setting.
CONTROL[31:16] field : not used for geometric operation.

SRCA_F : the input image start address
SRCOFF_F : the input image horizontal offset
DSTA_F : not necessary
DSTOFF_F : not necessary
NUMT_F : not necessary
SRCA_B : not necessary
SRCOFF_B : not necessary
DSTA_B : the output image start address
DSTOFF_B : the output image horizontal offset
NUMT_B : not necessary
IMGSIZE : write the width and height of the input image

MEMSIZE in the CONTROL : write as ‘0’(select 16x16)
DMAG in the CONTROL : write as ‘0’
GEOFUNC in the CONTROL : select one of six modes
MEN in the CONTROL : start the 2D-DMA operation
Image rotation or flipping is processed simply by several register programming. If only

one region of the whole image should be operated, the SRCA_F and SRCOFF_F
register can be modified. This is the same method that the memory region to be moved
is defined in the general DMA mode.
After the MEN bit is enabled, the 2D-DMA hardware start to operate as following
figure. That figure depicts in the case that the MEMSIZE is ‘0’( that is, 16x16 ).
Preliminary 1-28
Figure 1-4 Internal Process in the rotation by 90 degrees
As the above figure, the MEMSIZE means the minimum memory size to be transferred
once by DMA, and the minimum size to be operated once by rotator hardware. That
memory block(MB) becomes basic unit in the address generation of the frontend DMA
and the backend DMA. Generally, the frontend DMA generates the address
sequentially, but the backend DMA generated the destination address in according to
the selected geometric function. The above figure describes the destination address of
the first MB in the case of 90 degrees rotation.
The MEMSIZE value is an important factor in the performance. If this value is larger,
the data amount to be transferred one time is larger, so more bus bandwidth can be
established. But more buffer size is required. The following figure shows the internal
buffer memory interface. The internal buffer for the 2D-DMA is based on general
double buffer. Total buffer memory is classified into two memory region, and one of
them is to store the input image data temporally, the other is to store the output image
data temporally. Each region is divided into two parts: odd and even. While input
image is being moved to even part in the input buffer by the frontend DMA, the
hardware rotator can utilize odd part filled up before. In the same method, while the
hardware rotator is transferring to odd part in the output buffer, the backend DMA can
move the output data in the even part without waiting.
Preliminary 1-29
Internal Buffer Memory
One
Block
Input DeMuxing
( 16x16 )
Input Image
One
Block
( 16x16 )
Block
Rotator
One
Block
Output Muxing
Output Image ( 16x16 )
One
Block
( 16x16 )
Figure 1-5 Internal Buffer Interface
The 2D-DMA also supports the local region operation in the geometric function. This is
designed for the case when only a region in the input image should be operated, not
the whole image. In this mode, the other region is just copied into the destination
except the region defined by the LOCAL register. The following figure shows an
example of local region processing, in which the horizontal and vertical values in the
LOCAL register are based on the MEMSIZE value, not pixel unit.
Preliminary 1-30
Figure 1-6 Configuration of Local Region Processing
The jobs for local region processing are just to program the LOCAL register and to set
the LEN bit in the CONTROL register. The next figure shows an example of local
region processing.
Figure 1-7 Rotation and Flipping Local Region of Image
Preliminary 1-31
1.5 Pixel Arithmetic Functions
The 2D-DMA supports simple pixel arithmetic functions. Those functions can be
selected by the setting the SCALARFUNC field in the control register. Irrelative to the
type of geometric functions, the pixel arithmetic functions can process independently.
In other word, simultaneously with 90 degrees rotation the pixel inversion function can
be operated. The following describes the modes of the pixel arithmetic operations.
Table 1-5 Pixel Arithmetic Functions
SCALRFUNC Arithmetic equation Operand A Operand B
FPVALUE
FILL Y=B -
register
Input image pixel
INV Y = 255 – A -
data
Input image pixel FPVALUE
ADD Y=A+B
data register
Input image pixel FPVALUE
SUB Y=A-B
data register
Y=A*B
B is a fixed-point value.
Mantissa = B[7:6] Input image pixel FPVALUE
MUL
Fraction = B[5:0] data register
Y output is only the mantissa
part
The outputs of all above arithmetic are saturated to 8-bit pixel value between 0 and 255.
Preliminary 1-32
1.6 Raster Operation Function
The 2D-DMA supports bitwise ROP (raster operation) function for BitBLT function.
The BitBLT function performs a bit-block transfer of the color data corresponding to a
rectangle of pixels from the specified source device context into a destination device
context. The ROP function can be selected by the setting the ROPFUNC field in the
control register. The following describes the modes of the raster operation.
Table 1-6 Raster Operation Functions
ROP Functions Equation Operation Operand A Operand B Operand C Chroma-Key
Blackness 0 Y=0 - - - X
Source 2 image
Destination Invert ~Dst Y = ~B - - X
pixel data
Source 1 image Source 2 image FPVALUE
Merge Copy Dst & Src Y=B&A O
pixel data pixel data register
Source 1 image Source 2 image FPVALUE
Merge Paint ~Src | Dst Y = ~A | B X
pixel data pixel data register
Source 1 image FPVALUE
Not Source Copy ~Src Y = ~A - X
pixel data register
Source 1 image Source 2 image
Not Source Erase ~(Src | Dst) Y = ~(A | B) - X
pixel data pixel data
FPVALUE
Pat Copy P Y=C - - X
register
Source 2 image FPVALUE
Pat Invert P ^ Dst Y=C^B - X
pixel data register
Y = C | ~(A | Source 1 image Source 2 image FPVALUE
Pat Paint P | ~(Src| Dst) X
B) pixel data pixel data register
Source AND Src & Dst Y=A&B - O
Source 1 image
Source Copy Src Y=A - - X
pixel data
Source Erase Src & ~Dst Y = A & ~B - X
Source Invert Src ^ Dst Y=A^B - O
Source Paint Src | Dst Y=A|B - O
Whiteness 1 Y=1 - - - X
Preliminary 1-33
The next figure shows processing flow and parameters of the raster operation function.
Figure 1-8 Flow of The Raster Operation Function
The following describes the initial register setting.
CONTROL[31:20] field : not used for the raster operation.
SRC1A_R : the input image 1 start address

SRC1OFF_R : the input image 1 horizontal offset
SRC2A_R : the input image 2 start address (Y start address in the case of YCbCr separated format)
SRC2OFF_R : the input image 2 horizontal offset
SRC2CBA_R : the input image 2 Cb start address for YCbCr separated format
SRC2CRA_R : the input image 2 Cr start address for YCbCr separated format
DSTA_R : the output image start address (Y start address in the case of YCbCr separated format)
DSTOFF_R : the output image horizontal offset
DSTCBA_R : the output image Cb start address for YCbCr separated format
DSTCRA_R : the output image Cr start address for YCbCr separated format
IMGSIZE : write the width and height of the input image

FPVALUE : write the pattern value (if necessary)
ROPIMGFM : select the image format of the source 1, source 2 and destination images
ROPCHROMA : write the chroma-key value (if necessary)
DMAG in the CONTROL : write as ‘0’
ROPFUNC in the CONTROL : select one of 15 modes
MEN in the CONTROL : start the 2D-DMA operation
Preliminary 1-34
JPEG & DCT/IDCT
Multimedia Application Processor JPEG & DCT/IDCT
5 JPEG & DCT/IDCT
5.1 Overview
The JPEG block of TCC82xx is a high performance solution for image and video
compression/decompression applications. It can compress 24Mbyte/sec data stream
in real-time and compliance with the baseline ISO/IEC 10918-1 JPEG standard.
Additionally, the JPEG block can be used as DCT/IDCT calculator for video encoding
and decoding.
The JPEG block compress any image size up to 4096x4096 and the image samples
according to the user-defined quantization and Huffman tables, and it produces an
ISO/IEC 10918-1 compatible data stream. Each 8x8 image block is frequency
transformed by a forward DCT into the domain of 2-dimensional DCT(2D-DCT) basis
images. Image samples are frequency transformed from the DCT unit using 15-bit
internal accuracy. The 11-bit output DCT coefficients are then scanned int the Zig-Zag
order and quantized according to programmed Quantization tables.
The quantization prepares the blocks for efficient coding. Each DCT coefficient block
is divided by an 8x8 quantization matrix. The quantized DCT coefficients are then fed
to the differential coding and run-length coding unit that produces the Run-Amplitude
pairs for the Huffman coder. The Huffman encoder accepts symbols from RLE unit,
which are further compressed by Huffman encoder, which encodes them according to
one of the two possible programmed Huffman tables. Finally, Huffman compressed
data stream is written to the output FIFO. The AHB bus master stores data in output
FIFO to the predefined address pointer. The software header generator makes the
JPEG file header and merges with the body, generated by the JPEG block.
The JPEG block is capable of decoding Baseline ISO/IEC 10918-1 JPEG streams. It
outputs decoded image samples in MCU by MCU, raster scan order. The software
header parser parses the JPEG file header and configs Huffman and quantization table.
Then set the file body pointer and run the JPEG decoder. The AHB bus master reads
the body and stores in input FIFO. These data fed into the VLD block and decoded.
The Inverse Quantization block multiplies each coefficient according to the
quantization tables and produces the 11 bit DCT coefficients. These are then scanned in
the inverse Zig-Zag order and stored in the IDCT buffer. The IDCT is then applied on
the coefficients, to finally produce the image samples. When that image is too big to
stored in memory, that can be decimated by 1/4 or 1/16.
Preliminary 5-1
Figure 5-1 JPEC Block Diagram
Preliminary 5-2
5.2 Registers
Table 5-1 JPEG & DCT/IDCT Registers (Base Address = 0x90006000)
Name Addr Type Mode Reset Description
JP_RST 0x000 W ALL 0x00000000 JPEG block soft reset register
JP_MOD 0x004 R/W ALL 0x00000000 JPEG codec mode register
JP_INT_MASK 0x008 R/W ALL 0x0000001f Interrupt mask register
JP_INT_LEVEL 0x00c R/W SLV 0x000000ff FIFO interrupt level register
JP_TRG_MOD 0x010 R/W ALL 0x00000000 Polling or Interrupt mode selection register
R_YBUF_ADDR 0x020 R/W JP 0x00000000 Raw data buffer Y address register
R_UBUF_ADDR 0x024 R/W JP 0x00000000 Raw data buffer U address register
R_VBUF_ADDR 0x028 R/W JP 0x00000000 Raw data V address register
R_BUF_INFO 0x02c R/W JP 0x00000000 Raw data buffer information register
JP_SIZE 0x030 R/W JP 0x00000000 Image size information register
JP_CHROMA 0x034 R/W JP 0x00000000 Image format information register
JP_CBUF_ADDR 0x38 R/W JP 0x00000000 Coded data buffer address register
JP_CBUF_SIZE 0x03c R/W JP 0x00000fff Coded data buffer size register
JPD_TBL_ID 0x050 R/W JPD 0x00000000 Decoder table index register
JPD_RST_INTV 0x054 R/W JPD 0x00000000 Decoder reset interval register
JPD_OUT_SCL 0x058 R/W JPD 0x00000000 Decoder output scaling register
JP_SBUF_RP_A 0x060 R/W JPC 0x00000000 Source read pointer address register
JP_DBUF_WP_A 0x064 R/W JPD 0x00000000 Desination write pointer address register
JP_START 0x070 W ALL 0x00000000 Codec start command register
JP_SBUF_WCNT 0x080 R/W MST 0x00000000 Source buffer write count register
JP_SBUF_RCNT 0x084 R MST 0x00000000 Source buffer read count register
JP_DBUF_WCNT 0x088 R MST 0x00000000 Destination buffer write count register
JP_DBUF_RCNT 0x08c R/W MST 0x00000000 Destination buffer read count register
JP_IFIFO_ST 0x090 R SLV 0x00000000 Input FIFO status register
JP_OFIFO_ST 0x094 R SLV 0x00000000 Output FIFO status register
JP_INT_FLAG 0x0a0 R ALL 0x00000000 Interrupt flag register
JP_INT_ACK 0x0a4 R ALL 0x00000000 Interrupt ack register
JP_IFIFO_WD 0x0c0 W SLV 0x00000000 Input FIFO write data register
JP_OFIFO_RD 0x0e0 R SLV 0x00000000 Output FIFO read data register
Preliminary 5-3
JPC_QTAB0 0x100 - W JPC 0x00000000 Encoder Q table 0 (64 entries)

JPC_QTAB1 0x200 - W JPC 0x00000000 Encoder Q table 1 (64 entries)
JPD_IQTAB0 0x300 - W JPD 0x00000000 Decoder IQ table 0 (64 entries)
JPD_IQTAB1 0x400 - W JPD 0x00000000 Decoder IQ table 1 (64 entires)
JPD_IQTAB2 0x500 - W JPD 0x00000000 Decoder IQ table 2 (64 entires)
JPD_HT_DC0_C 0x600 - W JPD 0x00000000 Decoder huffman table (dc0 code, 16 entreis)
JPD_HT_AC0_C 0x640 - W JPD 0x00000000 Decoder huffman table (ac0 code, 16 entreis)
JPD_HT_DC1_C 0x680 - W JPD 0x00000000 Decoder huffman table (dc1 code, 16 entreis)
JPD_HT_AC1_C 0x6c0 - W JPD 0x00000000 Decoder huffman table (ac1 code, 16 entreis)
JPD_HT_DC0_A 0x700 - W JPD 0x00000000 Decoder huffman table (dc0 addr, 16 entreis)
JPD_HT_AC0_A 0x740 - W JPD 0x00000000 Decoder huffman table (ac0 addr, 16 entreis)
JPD_HT_DC1_A 0x780 - W JPD 0x00000000 Decoder huffman table (dc1 addr, 16 entreis)
JPD_HT_AC1_A 0x7c0 - W JPD 0x00000000 Decoder huffman table (ac1 addr, 16 entreis)
JPD_HT_DC0_V 0x800 - W JPD 0x00000000 Decoder huffman table (dc0 var, 12 entreis)
JPD_HT_AC0_V 0x840 - W JPD 0x00000000 Decoder huffman table (ac0 var, 162 entreis)
JPD_HT_DC1_V 0xc00 - W JPD 0x00000000 Decoder huffman table (dc1 var, 12 entreis)
JPD_HT_AC1_V 0xc40 - W JPD 0x00000000 Decoder huffman table (ac1 var, 162 entreis)
* ALL : ALL mode
* MST : Master mode
* SLV : Slave mode
* JP : JPEG encoder & decoder
* JPC : JPEG encoder
* JPD : JPEG decoder
Preliminary 5-4
Software Reset Register (JP_RST) 0x90006000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- RST
RST[0] Description
0 Ineffective
1 Block reset includes all tables.
JPEG Codec Mode Register (JP_MODE) 0x90006004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
- OPM
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- IPM
OPM [17:16] Description

0 JPEG encoder mode.
1 JPEG decoder mode.
2 DCT mode.
3 IDCT mode.
The IPM bit has meaning when JPEG encoder or decoder mode. In DCT/IDCT mode,
the IPM has no meaning. The DCT/IDCT calculator always operates in slave mode
IPM [0] Description

0 Master mode.
1 Slave mode.
Preliminary 5-5
Interrupt Mask(JP_INT_MASK) 0x90006008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- IMSK
In the interrupt mode, those bits can mask the interrupt.
IMSK [4:0] Description

IMSK[4] : Coded Buffer
IMSK[3] : Input FIFO
IMSK[2] : Output FIFO
IMSK[1] : Error
IMSK[0] : Operation End.
Input FIFO Interrupt Level Register(JP_INT_LEVEL) 0x9000600C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
IFIFO
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- OFIFO
In the JPEG encode/decoder or DCT/IDCT mode, The IFIFO value has meaning.
When input FIFO fill counter is lower then specified IFIFO value, then jp_ififo_intr is
generated. The unit of IFIFO value is word(32bits) and has between 0 to 127 value. If
the interrupt mask bit3 is ‘1’, jp_ififo_intr is masked.
IFIFO [23:16] Description

n Input FIFO interrupt level
In the JPEG encode/decoder or DCT/IDCT mode, The OFIFO value has meaning.
When output FIFO fill counter is lower then specified OFIFO value, then jp_ofifo_intr
is generated. The unit of OFIFO value is word(32bits) and has between 0 to 127 value. If
the interrupt mask bit2 is ‘1’, jp_ofifo_intr is masked.
OFIFO [7:0] Description

n Output FIFO interrupt level
Preliminary 5-6
Trigger Mode Register(JP_TRG_MOD) 0x90006010

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- TMD
TMD[0] Description
0 Polling mode. No interrupt generated..
1 Interrupt mode.
Preliminary 5-7
Raw Data Buffer Address Register (R_Y/U/VBUF_A) 0x900060(20/24/28)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
R_BUF_A[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
R_BUF_A[15:2] 0 0
In the encoding mode, these register values indicate raw data buffer start pointer.
In the decoding mode, these register values indicate decoded data buffer start pointer.
R_YBUF_A Description(0x90006020)
[31:2]
n The raw buffer Y start address.
R_UBUF_A Description(0x90006024)
[31:2]
n The raw buffer U start address.
R_VBUF_A Description(0x90006028)
[31:2]
n The raw buffer V start address.
Preliminary 5-8
Raw Buffer Information Register (R_BUF_INFO) 0x9000602C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
- IFRM_HSIZE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- IFRM_VSIZE
IFRM_HSIZE Description
[11:0]
n Input image frame horizontal size. (pixel)
IBUF_VSIZE Description
[11:0]
n Input raw buffer vertical size. (line)
Image Size Register (IMG_SIZE) 0x90006030

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
- IMG_HSIZE
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- IMG_VSIZE
IMG_HSIZE Description
[11:0]
Image horizontal size
In encoding mode : unit == pixel
n In decoding mode
- YUV420, YUV422 : unit == 16 pixel
- Yonly, YUV444 : unit == 8 pixel
JPC모드 및 JPD모드의 부호화영상 수직크기로 JPC모드의 경우 1라인 단위, 8의 배

수값만 가능하며 8~4088 사이의 값을 갖는다. JPD모드의 경우 MCU(minimum
coded unit) 단위(YUV420와 YUV422S는 MCU의 vsize가 16, Yonly, YUV422,
YUV444는 8)이다.
IMG_VSIZE Description
[11:0]
Image vertical size.
In encoding mode : unit == pixel
In decoding mode
n
- YUV420, YUV422 : unit == 16 pixel
- Yonly, YUV444 : unit == 8 pixel
Preliminary 5-9
Image Format Register(CHROMA) 0x90006034

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- CHROMA
CHROMA [2:0] Back Destination Address Register

0 Y only
1 YUV 420 (Y, U, V separated mode)
4 YUV 422S (Y, U, V sequential mode)
Preliminary 5-10
Coded Buffer Address Register(CBUF_A) 0x90006038

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
CBUF_A[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CBUF_A[15:2] 0 0
CBUF_A [31:0] Back Destination Offset Register

The coded data buffer start address..
n In encoding mode : encoding data output pointer
In decoding mode : JPEG file body pointer
Coded Buffer Size Register (CBUF_SIZE) 0x9000503C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- CBUF_SIZE
CBUF_SIZE[11:0] Description
n The coded data buffer size. (uint == 1024bytes)
Preliminary 5-11
Decoder Table ID(JPD_TBL_ID) 0x90006050

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
- Y_QT U_QT V_QT
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- Y_HT U_HT V_HT
The JPEG decoder has three quantization tables. These register values indicate table
number, each of color component(Y,U,V) use which table. “00” means table 0. “01”
means table 1. “10” means table 2.
Y_QT [21:20] Description

n Quantizaion Table ID for Y.
U_QT [19:18] Description

n Quantizaion Table ID for U.
V_QT [17:16] Description

n Quantizaion Table ID for V.
JPD모드에서 DC Huffman Tab 2개, AC Huffman Tab 2개 중 Y, U, V가 사용할

Huffman Tab를 지정한다. bit(5:4)는 Y, bit(3:2)는 U, bit(1:0)는 V의 huffman table
identifier를 지정하며 2비트의 htab_id는 bit1은 DC에 대한 Huffman tab 를 나타내
고, bit0는 AC에 대한 Huffman tab를 나타낸다.
The JPEG decoder has 2 DC Huffman table and 2 AC Huffman table. These register
values indicate table number, each of color component(Y,U,V) use which table. Each of
bit1 indicates DC table and bit0 indicates AC table.
Y_HT [5:4] Description

n Huffman Table ID for Y.
U_HT [3:2] Description

n Huffman Table ID for U.
V_HT [1:0] Description

n Huffman Table ID for V.
Preliminary 5-12
Decoder Restart Interval Register(JPD_RST_INTV) 0x90006054

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
INTV
If the JPEG header has Restart Interval, this register value is set by the Restart Interval
of the JPEG header. Any other case, set zero.
INTV [15:0] Description

n Decoder restart interval.
Preliminary 5-13
Decoder Output Scale Register (JPD_OUT_SCL) 0x90006058

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- SCL
SCL [1:0] Description

Decoder output scale ratio.
0 : no scale
n
1 : 1/4 (area ratio)
2 : 1/16 (area ratio)
Source Buffer Read Pointer (SBUF_RP) 0x90006060

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RP[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RP[15:0]
RP [31:0] Description
n Source buffer read pointer (must be “0”)
Destination Buffer Write Pointer (DBUF_WP) 0x90006064

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WP[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WP[15:0]
WP [31:0] Description
n Destination buffer write pointer (must be “0”)
Block Start Register (JP_START) 0x90006070

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- ST
ST [0] Description
n Codec start command
Source Buffer Write Counter (SBUF_WC) 0x90006080

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- WC
Preliminary 5-14
JPC모드 및 JPD모드에서 source buffer (JPC모드의 경우 IBUF, JPD모드의 경우

CBUF)에 쓰여진 데이터의 량을 나타냄, JPC모드의 경우 Y BUF 기준으로 1 frame
line 단위, JPD모드의 경우 1024bytes 단위, 일반적으로 JPC모드의 경우 SC모듈이
쓰며, JPD모드의 경우 Host가 씀
SBUF_WC Decription
[11:0]
n Source buffer write count
Source Buffer Read Counter (SBUF_RC) 0x90006084

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- RC
JPC모드 및 JPD모드에서 source buffer (JPC모드의 경우 IBUF, JPD모드의 경우

CBUF)에서 읽은 데이터의 량을 나타냄, JPC모드의 경우 Y BUF 기준으로 1 frame
line 단위, JPD모드의 경우 1024bytes 단위, 일반적으로 JPC모드의 경우 SC모듈이
읽어 참고하며, JPD모드의 경우 Host가 읽음, input_mode가 slave모드이면 의미가
없음.
SBUF_RC Decription
[11:0]
n Source buffer read count
Destination Buffer Write Counter (DBUF_WC) 0x90006088

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
- WC[17:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WC[15:0]
JPC모드 및 JPD모드에서 처리결과를 destination buffer(JPC모드의 경우 CBUF, JPD

모드의 경우 IBUF)에 쓴 데이터의 량을 나타내며 JPC모드의 경우 16bytes 단위이고
JPD모드의 경우 Y BUF 기준으로 1 frame line 임, 시스템적으로 JPC모드의 경우
Host가 읽어가며 JPD모드의 경우 JP모듈이 이 데이터를 SC모듈내의
jp_dbuf_wcnt_addr 번지에 씀
DBUF_WC[17:0] Decription
n Destination buffer write count
Destination Buffer Read Counter (DBUF_RC) 0x9000608C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- RC
Preliminary 5-15
JPC모드 및 JPD모드에서 처리결과를 destination buffer(JPC모드의 경우 CBUF, JPD

모드의 경우 IBUF)에서 읽어간 데이터의 량을 나타내며 JPC모드의 경우 1024bytes
단위이고 JPD모드의 경우 Y BUF 기준으로 1 frame line 임, 시스템적으로 JPC모드
의 경우 Host가 쓰며 JPD모드의 경우 SC모듈이 씀
DBUF_RC [11:0] Decription

n Destination buffer read count
Preliminary 5-16
Input FIFO Status (IFIFO_ST) 0x90006090

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- STATUS
FILL [7:0] Description

n Input FIFO fill count
Output FIFO Status (OFIFO_ST) 0x90006094

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- FILL
FILL [7:0] Description

n Output FIFO fill count
Preliminary 5-17
Interrupt Flags (INT_FLAG) 0x900060A0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- IFLAG
IFLAG[4:0] Description
[4] Coded buffer status
[3] Input FIFO status
[2] Output FIFO status
[1] Decoding error.
[0] Job finished.
Preliminary 5-18
Interrupt ACK Register (INT_ACK) 0x900060A4

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
-
When read this register, Interrupt Flags are cleared.
Preliminary 5-19
Input FIFO Write Data Register (IFIFO_WD) 0x900060C0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
WDATA[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
WDATA[31:16]
In slave mode (the JPEG decoding/encoding or DCT/IDCT mode), host feds data into
this register. (maximum burst size == 8 )
WDATA [31:0] Description

n The write data register in slave mode.
Preliminary 5-20
Output FIFO Read Data Register (OFIFO_RD) 0x900060E0

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
RDATA[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
RDATA[15:0]
In slave mode (the JPEG decoding/encoding or DCT/IDCT mode), host gets result
data from this register. (maximum burst size == 8 )
RDATA [31:0] Description

n The read data register in slave mode.
Preliminary 5-21
Encoder Q Table 0 (EN_QTAB0) (0x90006100 – 0x900061FC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- DATA
Encoder Q Table 1 (EN_QTAB1) (0x90006200 – 0x900062FC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- DATA
EN_QTAB0(64 entries) is the JPEG encoder quantization table for Y componet.

(4096/qstep) and raster scan ordered.
EN_QTAB1(64 entries) is the JPEG encoder quantization table for C componet.

(4096/qstep) and raster scan ordered.
DATA [11:0] Description

n Encoder quantization data (64 entries)
Preliminary 5-22
Decoder Inverse Q Table 0(DE_IQTAB0) (0x90006300-0x900063FC)

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- DATA

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- DATA

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- DATA
DE_IQTAB0(64 entries) is the de-quantization matrix table 0, zigzag scan orderd.

DATA [11:0] Description

n Decoder inverse quantization data (64 entries)
Preliminary 5-23
Decoder Huffman Table DC0 Code (DE_HT_DC0_C)

(0x90006600-0x9000663C)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CODE
Decoder Huffman Table AC0 Code (DE_HT_AC0_C)

(0x90006640-0x9000667C)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CODE
Decoder Huffman Table DC1 Code (DE_HT_DC1_C)

(0x90006680-0x900066BC)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CODE
Decoder Huffman Table AC1 Code (DE_HT_AC1_C)

(0x900066C0-0x900066FC)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
CODE
DE_HT_DC0_C values are DC Huffman table 0 code length. (LSB aligned)

DE_HT_AC0_C values are AC Huffman table 0 code length. (LSB aligned)
DE_HT_DC1_C values are DC Huffman table 1 code length. (LSB aligned)
DE_HT_AC1_C values are AC Huffman table 1 code length. (LSB aligned)
CODE [15:0] Description

n Huffman table code length
Preliminary 5-24
Decoder Huffman Table DC0 Address (DE_HT_DC0_A)

(0x90006700-0x9000673C)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- ADDR
Decoder Huffman Table AC0 Address (DE_HT_AC0_A)

(0x90006740-0x9000677C)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- ADDR
Decoder Huffman Table DC1 Address (DE_HT_DC1_A)

(0x90006780-0x900067BC)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- ADDR
Decoder Huffman Table AC1 Address (DE_HT_AC1_A)

(0x900067C0-0x900067FC)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- ADDR
DE_HT_DC0_A values are DC Huffman table 0 addresses of the JPEG decoder. (12
entires)
DE_HT_AC0_A values are AC Huffman table 0 addresses of the JPEG decoder. (162
entires)
DE_HT_DC1_A values are DC Huffman table 1 addresses of the JPEG decoder. (12
entires)
DE_HT_AC1_A values are AC Huffman table 1 addresses of the JPEG decoder. (162
entires)
ADDR [7:0] Description

n Huffman table address
Preliminary 5-25
Decoder Huffman Table DC0 Value (DE_HT_DC0_V)

(0x90006800-0x9000683C)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- VAL
Decoder Huffman Table AC0 Value (DE_HT_AC0_V)

(0x90006840-0x90006AC4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- VAL
Decoder Huffman Table DC1 Value (DE_HT_DC1_V)

(0x90006C00-0x90006C3C)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- VAL
Decoder Huffman Table AC1 Value (DE_HT_AC1_V)

(0x90006C40-0x90006EC4)
31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- VAL
DE_HT_DC0_A values are DC Huffman table 0 values of the JPEG decoder. (16
entires)
DE_HT_AC0_A values are AC Huffman table 0 values of the JPEG decoer. (162
entries)
DE_HT_DC1_A values are DC Huffman table 1 values of the JPEG decoder. (16
entires)
DE_HT_AC1_A values are AC Huffman table 1 values of the JPEG decoer. (162
entries)
VAL [7:0] Description

n Huffman table value
Preliminary 5-26
SCALER
Multimedia Application Processor SCALER
6 SCALER
6.1 Overview
Figure 6-1 Scaler Block Diagram
Preliminary 6-1
Registers
Table 6-1 Scaler Registers (Base Address = 0x9000C000)
SRC_Y_BASE 0x000 R/W 0x00000000 Scaler source image Y base address register
SRC_U_BASE 0x004 R/W 0x00000000 Scaler source image U base address register
SRC_V_BASE 0x008 R/W 0x00000000 Scaler source image V base address register
SRC_SIZE 0x00c R/W 0x00000000 Source image size register
SRC_OFFSET 0x010 R/W 0x00000000 Source image line offset register
SRC_CONFIG 0x014 R/W 0x00000000 Source image configuration register
DST_Y_BASE 0x020 R/W 0x00000000 Scaler destination image Y base address register
DST_U_BASE 0x024 R/W 0x00000000 Scaler destination image U base address register
DST_V_BASE 0x028 R/W 0x00000000 Scaler destination image V base address register
DST_SIZE 0x02c R/W 0x00000000 Destination image size register
DST_OFFSET 0x030 R/W 0x00000000 Destination image line offset register
DST_CONFIG 0x034 R/W 0x00000000 Destination image configuration register
SCALE_RATIO 0x040 R/W 0x00000000 Scale ratio register
SCALE_CTRL 0x044 R/W 0x00000000 Scaler control register
STATUS 0x048 R 0x00000000 Scaler status register
Preliminary 6-2
SRC Image Y Base Address (SRCBASEY) 0x9000C000

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR[15:2] 0 0
ADDR[31:2] Description
n Scaler source image Y address base
SRC Image U Base Address (SRCBASEU) 0x9000C004

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR[15:2] 0 0
n Scaler source image U address base
SRC Image U Base Address (SRCBASEU) 0x9000C008

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR[15:2] 0 0
n Scaler source image V address base
SRC Image Size(SRCSIZE) 0x9000C00C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
- VSIZE[11:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- HSIZE[11:0]
VSIZE[11:0] Description
n Input image vertical size by pixel
HSIZE[11:0] Description
n Input image horizontal size by pixel
Preliminary 6-3
SRC Image Offset(SRCOFFSET) 0x9000C010

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
- C_OFF[11:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- Y_OFF[11:0]
C_OFF[11:0] Description
n Input image line offset of chrominance
Y_OFF[11:0] Description
n Input image line offset of luminance
SRC Image Configuration(SRCCONFIG) 0x9000C014

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- WAIT - RDY - - - TYPE
WAIT[2:0] Description
n
RDY Description
TYPE [1:0] Description

3 : Invalid
2 : YUV422 seperated
n
1 : YUV422 sequential order 1
Preliminary 6-4
DST Image Y Base Address (DSTBASEY) 0x9000C020

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR[15:2] 0 0
n Scaler destination image Y address base
DST Image U Base Address (SRCBASEU) 0x9000C024

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR[15:2] 0 0
n Scaler destination image U address base
DST Image U Base Address (DSTBASEU) 0x9000C028

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
ADDR[31:16]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
ADDR[15:2] 0 0
n Scaler destination image V address base
DST Image Size(DSTSIZE) 0x9000C02C

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
- VSIZE[11:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- HSIZE[11:0]
VSIZE[11:0] Description
n Output image vertical size by pixel
HSIZE[11:0] Description
n Output image horizontal size by pixel
Preliminary 6-5
DST Image Offset(SRCOFFSET) 0x9000C030

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
- C_OFF[11:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- Y_OFF[11:0]
C_OFF[11:0] Description
n Output image line offset of chrominance
Y_OFF[11:0] Description
n Output image line offset of luminance
DST Image Configuration(DSTCONFIG) 0x9000C034

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- WAIT - RDY - PATH - TYPE
WAIT[2:0] Description
n
RDY Description
PATH Description
0 : to memory (Master mode, Scaler master writes result to memory)
1 : to LCD (Slave mode, LCD master reads scaling results)
TYPE [1:0] Description

3 : Invalid
2 : YUV422 seperated
n
Preliminary 6-6
Scale Ratio(SC_RATIO) 0x9000C040

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
- VRATIO[13:0]
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- HRATIO[13:0]
VRATIO [13:0] Description

n Vertical scale ration ( = 256*SRC_VSIZE/DST_VSIZE)
HRATIO [13:0] Description

n Horizontal scale ratio ( = 256*SRC_HSIZE/DST_HSIZE)
Scale Control(SC_CTRL) 0x9000C044

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- BUSY RDY EN
BUSY Description
Scaler busy interrupt enable
RDY Description
Scaler ready interrupt enable
EN Description
Scaler enable
Scaler Status(SC_STATUS) 0x9000C048

31 30 29 28 27 26 25 24 23 22 21 20 19 18 17 16
-
15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0
- IBUSY IRDY - - - -
IBUSY Description
Busy interrupt flag
IRDY Description
Ready interrupt flag
Preliminary 6-7
6.2
Preliminary 6-8

TCC8200 v0.2 20060425

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SPECIFICATION

For customers who use other firmware of mp3:

Date Version Description

Table 1.1 Derivatives of TCC82xx

ARM946E-S CPU core ( 16KB instruction/data cache, operating up to 200MHz )

• 0.13um low power CMOS process

• 1.1V ~ 1.3V for core, 1.8V ~ 3.3V for I/O port

1.3 Block Diagram

Figure 1.1 Functional Block Diagram of TCC82xx

1.4 Pin Description

Table 1.1 JTAG Interface Pins

Signal Name Type Description

Table 1.2 Host Interface & System Pins

Signal Name Type Description

Table 1.3 Serial I/O & External Interrupt

Signal Name Type Description

Table 1.4 NAND Interface

Signal Name Type Description

Table 1.5 SD Interface

Signal Name Type Description

Table 1.6 AUDIO Interface

Signal Name Type Description

Table 1.7 SENSOR Interface

Signal Name Type Description

Table 1.8 PLL

Signal Name Type Description

Table 1.9 RTC

Signal Name Type Description

Table 1.10 USB

Signal Name Type Description

1.5 Ball Assignment

Table 1.11 GPIO Group A

GPIO_A[0] D3 HPXD[0] NFC_D[0] HDD_D[0] LCD_D[0]

GPIO_A[1] C1 HPXD[1] NFC_D[1] HDD_D[1] LCD_D[1]

GPIO_A[2] D2 HPXD[2] NFC_D[2] HDD_D[2] LCD_D[2]

GPIO_A[3] D1 HPXD[3] NFC_D[3] HDD_D[3] LCD_D[3]

GPIO_A[4] E4 HPXD[4] NFC_D[4] HDD_D[4] LCD_D[4]

GPIO_A[5] E5 HPXD[5] NFC_D[5] HDD_D[5] LCD_D[5]

GPIO_A[6] E3 HPXD[6] NFC_D[6] HDD_D[6] LCD_D[6]

GPIO_A[7] E2 HPXD[7] NFC_D[7] HDD_D[7] LCD_D[7]

GPIO_A[8] E1 HPXD[8] NFC_D[8] HDD_D[8] LCD_D[8]

GPIO_A[9] F4 HPXD[9] NFC_D[9] HDD_D[9] LCD_D[9]

GPIO_A[10] F5 HPXD[10] NFC_D[10] HDD_D[10] LCD_D[10]

GPIO_A[11] F3 HPXD[11] NFC_D[11] HDD_D[11] LCD_D[11]

GPIO_A[12] F2 HPXD[12] NFC_D[12] HDD_D[12] LCD_D[12]

GPIO_A[13] F1 HPXD[13] NFC_D[13] HDD_D[13] LCD_D[13]

GPIO_A[14] G5 HPXD[14] NFC_D[14] HDD_D[14] LCD_D[14]

GPIO_A[15] G4 HPXD[15] NFC_D[15] HDD_D[15] LCD_D[15]

GPIO_A[16] G3 GPIO_A[16] GPIO_A[16] GPIO_A[16] LCD_D[16]

GPIO_A[17] G2 GPIO_A[17] GPIO_A[17] GPIO_A[17] LCD_D[17]

GPIO_A[18] G1 HPINT NFC_NCS[0] HDD_nCS[0]

GPIO_A[19] H5 HPXA NFC_NCS[1] HDD_nCS[1] LCD_XA

GPIO_A[20] H1 HPCSN NFC_NWE HDD_nDIOW LCD_CSN

GPIO_A[21] H4 HPWEN NFC_NOE HDD_nDIOR LCD_WEN

GPIO_A[22] H3 HPOEN NFC_CLE HDD_DA[0] LCD_OEN

GPIO_A[23] H2 - NFC_ALE HDD_DA[1] LCD_CSN_SEL

GPIO_A[24] J5 GPIO_A[24] NFC_READY0 HDD_DA[2]

GPIO_A[25] J4 GPIO_A[25] NRF_READY1 HDD_IORDY

GPIO_A[26] J1 MBOOT[0] GPIO_A[26] GPIO_A[26]

GPIO_A[27] J2 MBOOT[1] GPIO_A[27] GPIO_A[27]

VDD_IO_A H6 GPIO_A Group I/O power (1.8 - 3.3V)

VSS_IO_A G6 GPIO_A Group I/O ground

Table 1.12 GPIO Group B