King Saud University Semester I, 1445 H

College of Computer and Information Sciences CEN 415, VLSI Design

Computer Engineering Department 3 Credits
Homework 2

Homework number 4
Date 16/11/2023

Question 1
Figure 1 shows a system containing two edge-triggered flops and some combinational logic connecting the two
flops. The flops have the following characteristics:
 Setup time: 0.5ns
 Clock-to-Q delay: 0.8ns
 Hold time: 0.4ns
Unless otherwise stated assume there is no clock skew.

Figure 1
1. Assuming no clock skew, what is the minimum clock period?
2. Assume the the clock period is set to the value calculated in part a). For each of the following explain
whether the system would still work, and if it doesn't work, what could we do to the clock period to
make it work?
1. The clock arrives 1ns late to flop 2.
2. The clock arrives 1ns early to flop 2.
3. The clock arrives 3ns early to flop 2.

Question 2
Figure 2 shows a system with 3 flops with interconnecting logic.

Figure 2
Assume the same flop setup, clock-to-q and hold times as in Question 1. Assume there is no clock skew unless
otherwise stated.
What is the minimum clock period and maximum clock frequency at which the system can operate?
What is the delay between a value being input into the first flop and the output being available at the output of
the last flop? Assume the input is presented to the first flop at tsetup seconds before the clock edge.
How many inputs can be processed per second?

The second combinational logic section in the original system is split into two and an extra flop is inserted
between the split sections, as shown in Figure 3.

Figure 3
What is the minimum clock period and maximum clock frequency at which the system can operate?
What is the delay between a value being input into the first flop and the output being available at the output of
the last flop? Assume the input is presented to the first flop at tsetup seconds before the clock edge.
How many inputs can be processed per second?

1
Question 3
a) Compute the sheet resistance of a 0.22 mm thick Al wire in a 65 nm process. The resistivity of thin-film
Cu is 3.4 x 10-8 W•m. Ignore dishing. Find the total resistance if the wire is 100 µm wide and 2 mm long.
b) Shown below is an inverter that is driving a long poly wire. Find the delay to the end of the poly wire.
Please show your work (RC model).

If the poly wire is driven in the middle, does the delay change? Roughly by how much? Explain.

Question 4
a) Find G3:0, and P3:0 in terms of A, B, and Cin
b) Draw a Dual Rail Domino XOR/XNOR gate
c) Consider the function 𝑓 = ̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅̅
(a+b)(c̅+d̅)e. Assume that complementary inputs are available. Implement
this function in domino logic.