Test Generation of Crosstalk Delay Faults in VLSI Circuits

S. Jayanthy · M. C.
Bhuvaneswari
Test Generation
of Crosstalk
Delay Faults in
VLSI Circuits
Test Generation of Crosstalk Delay Faults in VLSI
Circuits
S. Jayanthy M. C. Bhuvaneswari
•
Test Generation of Crosstalk

Delay Faults in VLSI Circuits
123
S. Jayanthy M. C. Bhuvaneswari
Department of Electronics and Department of Electrical
Communication Engineering and Electronics Engineering
Sri Ramakrishna Engineering College PSG College of Technology
Coimbatore, Tamil Nadu, India Coimbatore, Tamil Nadu, India
ISBN 978-981-13-2492-5 ISBN 978-981-13-2493-2 (eBook)

https://doi.org/10.1007/978-981-13-2493-2
Library of Congress Control Number: 2018954035
© Springer Science+Business Media Singapore 2019

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Preface
This book describes the various test generation algorithms for testing crosstalk
delay faults in VLSI circuits.
Testing is an essential part of any integrated circuit manufacturing system. The
problem of test generation is NP-complete problems, and it is becoming more and
more difficult as system-on-chip designs have approached the deep submicron era.
In addition to the propagation delay, deep submicron technology (DSM) effects will
create severe signal integrity problems. Timing-related defects and signal integrity
problems are introduced by imperfect manufacturing process, process variations,
electromigration, voltage drop in power lines, crosstalk noise, and crosstalk delay
which will cause the chip to fail. Crosstalk delay and crosstalk noise are caused due
to the increased coupling capacitance. As more number of transistors are integrated
on a chip, there is an increase in their aspect ratio and a decrease in the spacing
between the interconnects, and thus, the interconnect coupling capacitances become
larger. This increases the ratio between the coupling capacitance and the total
capacitance leading to an increase in capacitive coupling noise. Crosstalk will
become the major contributor to the interconnect delay in the near future. It is
impossible to estimate the timing faults due to crosstalk delay in the design stage
due to process variations and manufacturing defects. Hence, there is a need for
automatic test pattern generation (ATPG) algorithms that can generate test vectors
for testing the chips for crosstalk delay faults to ensure quality.
Crosstalk delay fault is induced in the circuit if the victim and aggressor lines
have simultaneous transitions. Crosstalk is most frequently observed for long nets
which may have multiple fanouts. Thus, a long net is capacitively coupled with
multiple aggressors. Hence, test pattern generation algorithms need to generate test
vectors to activate multiple aggressors coupled to a victim.
This book provides an introduction to the various crosstalk effects and describes
the deterministic and simulation-based methods for testing crosstalk delay faults.
v
vi Preface
Organization of the Book
The content of this book is divided into ten chapters. The first three chapters focus
on the existing crosstalk delay models, test generation algorithms for delay faults,
and crosstalk delay faults. The remaining chapters deal with the deterministic
algorithms and simulation-based algorithms applied for testing crosstalk delay
faults. The experimental results for the algorithms and analysis are given.
Chapter 1 focuses on the current scenario in VLSI testing and provides an insight
into the crosstalk effects. The existing crosstalk delay fault models are discussed.
Chapter 2 discusses the delay fault testing in VLSI circuits. It describes various
delay fault models and test application schemes for the delay fault testing. It gives a
survey of existing test generation and simulation-based algorithms for testing the
delay faults in combinational and sequential circuits.
Chapter 3 discusses the existing test generation techniques for crosstalk delay
faults. Both deterministic and simulation-based techniques are discussed.
Chapter 4 describes the static timing analysis for the identification of crosstalk
delay faults. It deals with efficient ATPG for crosstalk delay faults based on the
modified PODEM and modified FAN. Experimental results for ISCAS’85 combi-
national circuits, enhanced scan version of ISCAS’89 sequential circuits, and ITC’
99 benchmark circuits are presented.
Chapter 5 focuses on the application of genetic algorithms for crosstalk delay fault
testing. Test results for four crossover operators, namely one-point, two-point, uniform,
and weight-based crossover operators, are reported for ISCAS’85 combinational cir-
cuits, several enhanced scan version of ISCAS’89 sequential circuits, and ITC’99
benchmark circuits. The results obtained are compared with the previous works.
Chapter 6 describes a crosstalk delay fault test generation methodology using
single-objective particle swarm optimization (PSO). The experimental results are
presented and discussed.
Chapter 7 deals with multiobjective genetic algorithms WSGA, NSGA-II, and
NSGA-II with redundancy for test generation for crosstalk delay faults. The
experimental results are presented and discussed.
Chapter 8 gives an introduction to fuzzy delay model. The fuzzy delay model-based
simulation algorithm for asynchronous circuits is presented. The simulation-based test
generation results for random patterns are presented for SIS benchmark circuits.
Chapter 9 explains a simulation-based method for test generation for crosstalk
delay faults in asynchronous sequential circuits. GA-based ATPG, WSGA-based
ATPG, and NSGA-II-based ATPG for crosstalk delay faults in asynchronous
sequential circuits are presented. Experimental results for SIS benchmark circuits
are reported.
Chapter 10 deals with the overall summary of the research discussed in each
of the chapters and the future research prospects of crosstalk delay fault testing.
Coimbatore, India S. Jayanthy

M. C. Bhuvaneswari
Contents
1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 1
1.1 Introduction . . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 1
1.2 VLSI Design Flow . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 2
1.3 VLSI Testing . . . . . . . . . . . . . . . . . . . . .. . . . . . . . . . . . . . . . 4
1.4 Test Challenges for Deep Submicron Technologies . . . . . . . . . . 5
1.5 Crosstalk Effects . . . . . . . . . . . . . . . ........... . . . . . . . . . 8
1.6 Crosstalk Fault Models . . . . . . . . . . ........... . . . . . . . . . 10
1.7 Conclusion . . . . . . . . . . . . . . . . . . . ........... . . . . . . . . . 13
References . . . . . . . . . . . . . . . . . . . . . . . . ........... . . . . . . . . . 13
2 Delay Fault Testing of VLSI Circuits . . . . . . . . . . . . . . . . . . . . . . . 15
2.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 15
2.2 Delay Fault Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.1 Transition Fault Model . . . . . . . . . . . . . . . . . . . . . . . . . 16
2.2.2 Gate Delay Fault Model . . . . . . . . . . . . . . . . . . . . . . . . 17
2.2.3 Line Delay Fault Model . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.4 Path Delay Fault Model . . . . . . . . . . . . . . . . . . . . . . . . 19
2.2.5 Segment Delay Fault Model . . . . . . . . . . . . . . . . . . . . . 20
2.3 Test Application Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . 21
2.3.1 Standard Scan Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 22
2.3.2 For Non-Scan Circuits . . . . . . . . . . . . . . . . . . . . . . . . . 24
2.4 Test Generation Methods for Path Delay Fault Model . . . . . . . . 25
2.4.1 Path Delay Fault Simulation . . . . . . . . ...... . . . . . . . 25
2.4.2 Test Generation for Path Delay Faults . ...... . . . . . . . 29
2.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . . . . 34
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ...... . . . . . . . 34
3 Test Generation Algorithms for Crosstalk Faults . . . . . . . . . . . . . . 37
3.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 37
3.2 Test Generation Algorithms . . . . . . . . . . . . . . . . . . . . . . . . . . . 38
vii
viii Contents
3.3 Test Generation for Crosstalk Pulses . . . . . . . . . . . . . . . . . . . . 42

3.3.1 Deterministic Algorithms . . . . . . . . . . . . . . . . . . . . . . . 42
3.3.2 Simulation-Based TG . . . . . . . . . . . . . . . . . . . . . . . . . . 44
3.4 Test Generation Techniques for Crosstalk Delay Faults . . . . . . . 46
3.4.1 Deterministic Algorithms . . . . . . . . . . . . . . . . . . . . . . . 46
3.4.2 Simulation-Based Test Generation . . . . . . . . . . . . . . . . . 50
3.5 Delay Testing of Asynchronous Sequential Circuits . . . . . . . . . 51
3.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 53
4 An Automatic Test Generation Method for Crosstalk Delay
Faults Using Modified FAN Algorithm . . . . . . . . . . . . . . . . . . . . . . 57
4.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 57
4.2 Static Timing Analysis . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 58
4.2.1 Identification of Target Crosstalk Faults . . . . . . . . . . . . 58
4.3 Seven-Valued Logic . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 60
4.4 Procedure for Modified PODEM-Based Test Generation . . . . . . 62
4.5 Procedure for Modified FAN-Based Test Generation . . . . . . . . . 65
4.6 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 67
4.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 74
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 77
5 ATPG for Crosstalk Delay Faults using Single-Objective
Genetic Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 79
5.2 Genetic Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 80
5.3 Test Generation Using GA . . . . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.1 Chromosome Encoding . . . . . . . . . . . . . . . . . . . . . . . . 82
5.3.2 Fitness Function . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.3.3 Crossover Operators . . . . . . . . . . . . . . . . . . . . . . . . . . . 83
5.4 Crosstalk Delay Fault Simulator . . . . . . . . . . . . . . . . . . . . . . . 85
5.5 GA-Based Crosstalk Delay Test Generation Algorithm . . . . . . . 86
5.5.1 Phase I: Pseudorandom Generation of Initial Test
Sequence . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 87
5.5.2 Phase II: GA-Based Test Generation . . . . . . . . . . . . . . . 87
5.7 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 96
6 ATPG for Crosstalk Delay Faults Using Particle Swarm
Optimization Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 99
6.2 Particle Swarm Optimization . . . . . . . . . . . . . . . . . . . . . . . . . . 100
6.3 PSO Algorithm-Based Test Generation Algorithm . . . . . . . . . . 102
Contents ix

6.5 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 107
7 ATPG for Crosstalk Delay Faults Using Multi-objective
Genetic Algorithm . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 109
7.2 Weighted Sum-Based ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . 110
7.3 Optimization Using NSGA-II . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.3.1 Elitism . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 112
7.3.2 Non-dominated Sorting . . . . . . . . . . . . . . . . . . . . . . . . 113
7.3.3 Crowding Strategy . . . . . . . . . . . . . . . . . . . . . . . . . . . . 113
7.4 NSGA-II-Based ATPG with Redundancy . . . . . . . . . . . . . . . . . 115
7.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 123
8 Simulation of Asynchronous Sequential Circuits Using Fuzzy
Delay Model for Crosstalk Delay Faults . . . . . . . . . . . . . . . . . . . . . 125
8.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 125
8.2 Races, Oscillations, and Non-confluence . . . . . . . . . . . . . . . . . 126
8.3 Delay Models . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 127
8.3.1 Types of Delay Models . . . . . . . . . . . . . . . . . . . . . . . . 127
8.4 Fuzzy Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 129
8.4.1 Fuzzy Delay . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
8.4.2 Logic Gate Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . 130
8.4.3 Representation of Fuzzy Delay . . . . . . . . . . . . . . . . . . . 131
8.5 Discrete Event-Driven Logic Simulation Based on Fuzzy
Delay Model . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 131
8.5.1 Component State . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8.5.2 State Change . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 132
8.5.3 Event . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 133
8.5.4 Processing of Events . . . . . . . . . . . . . . . . . . . . . . . . . . 134
8.6 Crosstalk Delay Fault Simulation Algorithm . . . . . . . . . . . . . . . 135
8.8 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 138
9 Simulation Based Test Generation for Crosstalk Delay Faults
in Asynchronous Sequential Circuits . . . . . . . . . . . . . . . . . . . . . . . . 141
9.1 Introduction . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 141
9.2 Feedback Identification . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
9.3 Crosstalk Delay Fault Simulator for Asynchronous
Sequential Circuits . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 142
x Contents
9.4 GA-Based ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

9.4.1 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 143
9.5 WSGA- and NSGA-II-Based ATPG . . . . . . . . . . . . . . . . . . . . 145
9.5.1 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . 146
9.6 Conclusion . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 150
10 Summary and Suggestions for Future Research . . . . . . . . . . . . . . . 151
10.1 Summary . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 151
10.2 Suggestions for Future Research . . . . . . . . . . . . . . . . . . . . . . . 155
References . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 155
About the Authors
Dr. S. Jayanthy is Professor in the Department of Electronics and Communication

Engineering, Sri Ramakrishna Engineering College, Coimbatore, India. She
received her master’s and Ph.D. from PSG College of Technology, Coimbatore,
and Anna University, Chennai, respectively. Her research interests are in VLSI
design and testing, genetic algorithms, and embedded systems. With more than
20 years of teaching experience, she has published 2 chapters and more than
40 research papers in journals and national and international conferences and has
organized a number of workshops and national conferences in the areas of VLSI,
embedded systems, and IoT. She is a life member of Indian Society for Technical
Education and Institution of Electronics and Telecommunication Engineers.
Dr. M. C. Bhuvaneswari is Associate Professor in the Department of Electrical
and Electronics Engineering, PSG College of Technology, Coimbatore, India. She
received her B.E. in electronics and communications engineering from Madras
University and her M.E. and Ph.D. from Bharathiar University. Her research
interests include applied electronics, VLSI design and testing, genetic algorithms,
digital system design, and microprocessors. She has published a book on VLSI and
embedded systems (2015) and authored more than 90 research papers in journals
and national and international conferences. She is a life member of Indian Society
for Technical Education, Institute of Engineers (India), Computer Society of India,
and Systems Society of India. She was honored with Dakshinamoorthy Award for
Teaching Excellence instituted by PSG College of Technology in the year 2010.
xi
Chapter 1
Introduction
1.1 Introduction
Rapid advances in integrated circuit (IC) technology have made it possible to fabri-
cate digital circuits with large number of devices on a single chip. The advantages of
integrated circuits are reduced system cost, better performance, and reliability. These
advantages would be lost unless integrated circuit devices can be economically tested.
Testing is one of the important fields, which validates the functionality of any man-
ufacturing process. The testing process detects the physical defects produced during
fabrication. The problem of test generation belongs to a class of NP-complete prob-
lems, and it is becoming more and more difficult as the complexity of IC increases.
Scaling of process technologies could be limited if testability issues are not
addressed adequately. This is because defect sizes have not reduced in proportion
with shrinking geometries. The major factors that affect the functionality in deep
submicron technologies (DSM) are process variations, manufacturing defects, and
noise. Process variations can have a major affect on chip’s failure to meet the speci-
fied performance. Delay defects which are caused by interconnect defects and noise
sources such as crosstalk, power supply noise, and substrate noise will result in chips
failing to meet the timing specifications. In order to guarantee optimal performance
of DSM chips, their functional correctness as well as timing behavior needs to be
tested. Hence, current test and verification techniques need to be improved. More
detailed fault models are required to model the behavior of faulty deep submicron
chips. Therefore, efficient test techniques are needed to detect such defects and elim-
inate them before products are shipped (Datta et al. 2009).
© Springer Science+Business Media Singapore 2019 1

S. Jayanthy and M. C. Bhuvaneswari, Test Generation of Crosstalk Delay
Faults in VLSI Circuits, https://doi.org/10.1007/978-981-13-2493-2_1
2 1 Introduction
1.2 VLSI Design Flow
VLSI is a field which involves packing of millions of components on the same chip.
Due to the significant improvements in the IC manufacturing, the capability of IC has
increased in terms of computational power, utilization of available area, and yield.
The design of such ICs has become a complicated and time-consuming process.
Therefore, there is a necessity for the development of powerful design tools and
software systems that help a VLSI design engineer to produce a fault-free IC chip.
The various steps in IC design and manufacturing are shown in Fig. 1.1. A
design specification is formulated based on a customer or project need. Specifications
describe the functionality, interface, and overall architecture of the IC to be designed.
This idea is casted into the model which captures the function that the circuit will
perform. Design engineers create a behavioral-, logical-, or circuit-level model of the
specification. Design typically starts at very high levels of abstraction using some
high-level hardware description language (HDL) (Bhuvaneswari and Sivanandam
2001). Design verification is done to ensure that the design will perform the required
functions when manufactured.
A logical-level implementation is synthesized from the HDL specifications which
should be verified to ensure that the final design meets timing, area, and power speci-
fications. When design error is found, modifications are done and design verification
is repeated. As a result, design verification is considered as a form of testing. The
logical-level description is transformed into physical-level description to obtain the
placement and interconnection of the transistors in the VLSI device. This physical-
level description is verified for timing and specified operating frequency specifica-
tions, and then, the design is fabricated. At the same time, test engineers develop
a test procedure based on the design specification and fault models associated with
the fabrication technology. The unavoidable statistical flaws in the materials and
masks used to fabricate ICs result in defects during the fabrication process. Hence,
the ICs fabricated on the wafer are tested for fabrication faults to determine which
devices are defective. The chips that pass wafer-level test are extracted and packaged.
The packaged devices are further tested for any damages in the packaging process.
Finally, devices pass through final quality test before going to market. This includes
measurement of input/output timing specifications, voltage, and current (Wang et al.
2006).
Better electronic design automation (EDA) tools, advanced technology IC man-
ufacturing, and design flow methodology are required for successful delivery of
finished products. The EDA tools and design flow methodology are directly affected
when there is a change in IC technology. The deep submicron IC manufacturing tech-
nology has had a direct influence on both the EDA tools and design flow methodology.
As design moves from the architectural level to the physical representation or fabri-
cation, the complexity of the design increases. There could be several iterations of
each phase during the IC development to ensure quality and performance. During the
various iterations, several computer-aided design (CAD) tools assist in translating
the design into an IC. The CAD techniques have reached good level of maturity
1.2 VLSI Design Flow 3
Fig. 1.1 Typical design flow

of IC Design
Architectural design
Functional verification
and testing
Logical design
Logical verification and

testing
Physical design
Physical layout
verification
Fabrication
Chip
in many areas. But as technology moves into nanometer age, in order to keep up
with the Moore’s law, many new technologies and circuit design techniques must
be devised and adopted. This may give rise to severe test challenges that must be
solved concurrently. When the feature size becomes less than 100 nm, a small defect
would result in a faulty transistor or an interconnection. But this one faulty tran-
sistor or interconnection is enough for improper functioning of the entire chip with
respect to its operation or timing. But these small defects during the manufacturing
process cannot be avoided, and it is required to test all the products whether it is a
VLSI device or a system consisting of many VLSI devices. During manufacturing
process, testing is done at various stages. Testing electronic devices includes test-
ing at the various manufacturing stages that are during IC fabrication, during PCB
4 1 Introduction
layout, during system integration, and during system operation. Testing is used to
find the fault-free devices during these stages. The source of defects is analyzed at
the various stages of manufacturing to improve production yield. Periodic testing of
systems is also performed to ensure that system operates as per requirements, and as
and when faults are detected, corrective action is initiated. VLSI testing is important
in all stages viz design, production, testing, manufacturing, and at field.
1.3 VLSI Testing
Tests may fall into two main categories, the functionality test and manufacturing test.
The functionality tests are usually done early in the design cycle to verify whether
the IC performs its intended function. Manufacturing test involves development of
test patterns to ensure ICs operate correctly before being delivered to customers. This
is an important stage of IC development as it affects the quality of the product. In
any manufacturing process, fabrication defects are invariably introduced. Common
defects are shorts, opens, improper doping profiles, mask alignment errors, and poor
encapsulation (Abramovici et al. 1990). The testing process detects the physical
defects produced during fabrication of an integrated circuit chip. Testing of a die/chip
can occur at the wafer level, packed chip level, board level, system level, or in the
field. The cost of identifying a faulty component is lowest before it is packed (Hurst
1998). This cost increases as component becomes a part of a larger system. Due to the
complexity of the IC manufacturing process, a number of defects might occur during
fabrication and hence no process can guarantee 100% yield. If these test issues are
not solved, in future the cost of testing a transistor might become more than the cost
of designing the transistor. Therefore, testing is an important aspect of any integrated
circuit manufacturing system.
Testing is a process which validates the functionality of any manufacturing pro-
cess. Testing a product after manufacturing is essential to reduce the risk of shipping
a defective product and is a process where circuit inputs are exercised using certain
patterns and the resulting response is compared to the golden response to eliminate
the defective parts. Automatic test generation refers to the test generation algorithms
that, given a model of the system, can generate tests for it. Covering all the faults
would be very difficult and would require an inordinate number of test vectors. There-
fore, automatic test generation tools operate on an abstract representation of defects
referred as faults and model a subset of potential faults. The faults in digital circuit
are referred as logic or parametric faults. A logic fault causes the logic function of
the circuit, on an output signal to be changed to some incorrect function. Paramet-
ric faults are the faults, which alter the magnitude of the circuit parameters causing
changes in speed of operation or the levels of voltages and currents.
The effects of manufacturing defects are represented at the logic level using a
fault model. Fault models can describe the faults at different abstraction levels. The
common abstraction level is the gate level. Most fault models assume that the circuit
contains only a single fault, as the number of potential multiple fault combinations
1.3 VLSI Testing 5
is so large that test generation becomes infeasible. The widely used gate-level fault
model for digital circuits is the single stuck-at fault model. This model assumes that
any physical defect in a digital circuit results in a node in the circuit being fixed either
at logic 0 or at logic 1 and appropriately called stuck-at-0 and stuck-at-1, respectively.
It can be considered as a direct connection between a node and power (stuck-at-1)
or ground (stuck-at-0). These faults occur most frequently in complementary metal
oxide semiconductor (CMOS) process technology due to thin oxide shorts, that is, in
a n-transistor gate may be shorted to V ss and in the p-transistor gate may be shorted
to V dd or metal to metal shorts. The stuck-at fault model has several advantages.
The advantages include simplicity, logical behavior, tractability, and measurability.
In multiple stuck-at fault model, a circuit with m signal can have (3m − 1) possible
faults since each signal can be s-a-0, s-a-1, or fault free. This is a very large number
even for relatively small circuits. For simplicity, it is assumed that only one stuck-at
fault will be present at any given time. In the single stuck-at (SSA) fault model, a
circuit with m signals can have at most 2m faults. The number of faults to be explicitly
analyzed can be further reduced by fault collapsing techniques. Fault collapsing can
be done by two methods: fault equivalence and fault dominance.
Fault-free operation of a logic circuit requires not only performing the logic func-
tion correctly but also propagating the correct logic signals along paths within a
specified time limit. A delay fault causes excessive delay along a path such that the
total propagation delay falls outside the specified limit. Delay faults have become
more prevalent with decreasing feature sizes.
1.4 Test Challenges for Deep Submicron Technologies
The advent of nanometer technology has paved way for a significant increase in the
level of integration and performance of VLSI chips. As more number of transistors
is fabricated on a single chip, the cost per transistor reduces. However, testability
becomes a significant factor for achieving acceptable reliability levels for modern
VLSI chips. This is because the defect size has not scaled down in proportion to
shrinking geometries. Further increase in wiring levels and wire delay demands new
fault models. Moreover, signal integrity problems such as crosstalk noise, excessive
voltage drop, and substrate and thermal noise cause devices to violate performance
specifications. Process variations also can have a considerable influence on a chip’s
failure to meet specified performance. The noise sources and process variations cause
timing-related defects that change the timing of the circuit. The advent of system-
on-chip (SOC) architectures, high-frequency circuits, and microelectromechanical
(MEMSs) circuits and programmable gate arrays further heightens these issues.
As semiconductor process technologies size down toward nanometer era, feature
size continues to shrink. Although lesser transistor size could result in lesser circuit
delay, a smaller feature size for interconnects does not reduce the signal propaga-
tion delay. This is because the cross section becomes smaller due to reduced feature
size and hence increases the line’s resistance. To reduce the resistance, the aspect
6 1 Introduction
ratio is made larger than one while maintaining high horizontal interconnect density,
but this increases the coupling capacitance. Further, the spacing between intercon-
necting lines is smaller. Hence, the effective capacitance increases. This along with
the increase in line resistance increases the RC time constant and hence the circuit
delay. Thus, the signal propagation delay in interconnects has become a major fac-
tor in determining the delay of a circuit. To solve these problems, low-resistivity
lines and low-permittivity dielectric materials can be used to reduce capacitance.
Another solution is reverse scaling of the upper levels of interconnects, presenting a
greater cross section. But these two solutions increase the inductive coupling, which
depends on the return current path, and do not scale proportionally with capacitance
and resistance. The upper levels which form the global interconnects are little fur-
ther from substrate and hence have higher characteristic impedance. This is called
as signal integrity problem which will have a significant adverse effect on the proper
functioning and performance of VLSI systems.
Simultaneous switching of digital gates produces spikes which cause simultaneous
switching noise, which is known as power supply noise, or ground/power bounce.
The supply voltage pin of the IC package produces a series resistance and inductance
in the path from the external power supply to the on-chip power supply. Considering
a single gate, the voltage at any instant at the power supply due to these effects will
be supply voltage subtracted by the voltage drop across the resistance and inductance
in the on-chip supply voltage. The return path of current passes through the ground
pin of the package thus closing the loop and generating a positive spike at the on-
chip ground pin. The overall effect is a transient reduction in the on-chip power
supply voltage. The time derivative of the current is proportional to the input rise or
fall time and the transistors’ maximum saturation current. When a number of gates
switch simultaneously, the combination of individual switching currents increases
the amount of SSN. To improve system performance and maximize clock frequency,
path delay distribution of different propagation paths is made as narrow as possible.
This increases simultaneity because nearly all paths have similar delays, and the
gates along those paths switch almost simultaneously and increase SSN. For deep
submicron designs with frequency in the gigahertz range and high circuit density, the
power supply voltage drop caused by instantaneous change in current is comparable
to IR drop. Therefore, the on-chip power supply is not the same across the chip. This
has caused power integrity problem which can affect reliability and performance of
VLSI circuits. This power supply noise can reduce the actual output voltage of a
device, which in turn can increase the cell and interconnection propagation delay,
causes false switching of logic gates, and affects the performance of the analog and
RF sections of mixed signal integrated circuits (Wang et al. 2006).
Substrate noise has become an important problem in mixed digital/analog circuits.
Noise sources include switching devices, substrate contacts, and switching intercon-
nects. Receiving device is affected through parasitic capacitances and body effect.
Regarding the propagation path, CMOS technology uses two different types of sub-
strates. Digital technologies use highly conductive substrates with a thin epitaxial
layer at the top. In these substrates, noise penetrates the upper layer and propagates on
top of the conductive layer. High-frequency analog circuits use substrates that have
1.4 Test Challenges for Deep Submicron Technologies 7
a uniform high resistivity. Here, noise current densities are higher near the surface,
decreasing more deeply inside the low-conductive substrate. Results in mixed signal
circuits show that first type of substrate propagates noise three times as substrates
with uniform resistivity. Special packaging and grounding techniques can reduce the
substrate noise. To reduce substrate noise, sensitive circuitry is designed so that it is
immune to noise. The amount of noise generated and injected into the substrate is
reduced, and the noise is prevented from reaching the critical parts by using either
inert barriers or noise sinking.
With significant advances in IC technology, precise control of the silicon process
has become difficult. There are two types of process variations: variations within
the same fabrication plant and between fabrication plants. The variations between
chips manufactured in the same fabrication plant include line-to-line, wafer-to-wafer,
inter-die, and intra-die variations. Process variations which influence the entire chip
or functional block are inter-die variations. These are caused due to process gradient
effects over the wafer. Process variations which are not uniform over the entire die
are called intra-die variations. Because of these effects, channel length of the tran-
sistor has become difficult to control, variation in thickness of interconnects, gate
length variation, random placement of dopant in channel. These variations result in
delays of wires and gates within a chip. Different fabrication plants use different cell
libraries, and hence, the resulting synthesized circuitry causes variations between
chips. However, latter is rarely used and hence does not produce a significant effect.
This is a process variation problem as design approaches submicrons. These varia-
tions cause distributed delay faults in the chip, which in turn give rise to small delay
faults on multiple gates in a given path to accumulate and result in the path failing
to meet performance specifications, which may affect the yield and performance of
devices.
Productivity gap results due to this timing inaccuracy, as both EDA tools and
design flow methodology break as they cannot change rapidly with the changes in IC
technology in deep submicron designs. Hence, new fault models and test methods
are to be developed concurrently with the development of new nanotechnologies and
circuit designs and placed in the various stages of design to reduce the productivity
gap. With increasing system complexity, current test and verification techniques need
to be improved. Fault models like stuck-at-fault model, which correctly modeled
the behavior of defective chips earlier, are not effective to adequately represent the
majority of IC defects and new failure mechanisms in deep submicron technologies.
Existing design for test, fault simulation, and ATPG tools must move to more realistic
fault types to meet increased quality expectations. Before the chip is fabricated on
silicon, there is a need to check for functional design errors, timing errors, and
design rule violations. Only a model-based design is verified and detailed modeling
of circuits increases computational cost. Hence, a structured technique for testing
becomes necessary to locate and rectify any design error in first silicon. Testing of
a chip requires analysis of its both internal behavior and external behavior under
known stimuli. The analysis is repeated and the responses obtained are compared
with a set of expected responses to locate design errors. Faults in design are located
and rectified by repeating the design cycle before the final chip is manufactured.
8 1 Introduction
When feature sizes are reduced, the observability of chips for timing violations
becomes difficult. For optimum yield, the chips should have both functional and
timing correctness. With decrease in feature sizes, delay faults in chips have become
a significant problem.
The Semiconductor Industry Association (SIA) has published an International
Technology Roadmap for Semiconductors (ITRS) which includes the updates on
test and test equipment trends for nanometer designs. The long-time challenges for
nanometer designs with feature size less than or equal to 45 nm include the full
spectrum of test technology trends which include new automatic test equipment
(ATE) interfaces, test methodologies, improved defect analysis, failure analysis, and
device technologies (Wang et al. 2006).
1.5 Crosstalk Effects
Noise is one of the most significant factors that affect the deep submicron VLSI
designs. Among the various noise sources, problems related to crosstalk noise
between circuit interconnects have become a dominant source of noise in deep submi-
cron circuits (Gal 1995). High-speed digital circuits to a great extent use the dynamic
logic family. Dynamic circuits with their two phases of operations are more suscep-
tible to crosstalk noise compared to the static logic (Heydari and Pedram 2001).
Line capacitance and load capacitance dominate circuit behavior for submicron pro-
cess. For deep submicron technologies, cross-coupling capacitance dominates due
to decrease in spacing between conductors, the increase in height to width ratio of
each conductor, the raise in length of adjoining conductors, and increase in metal
layers. The coupling capacitance becomes a significant contributor to signal integrity
problem Bhuvaneswari and Jayanthy (2015).
Coupling causes insertion of noise into near lines from active lines. This method
of noise coupling is called crosstalk. With the intensive scaling in process technology
and increase in switching speed, the problem of modeling gate delays becomes fur-
ther difficult. In deep submicron VLSI designs, the part of delay contributed by gates
reduces while interconnect delay becomes dominant. This is due to the fact that the
scaling of interconnect lengths is not in proportion to the shrinking size of transistors
that make up the gates. Further as operating frequencies increase, on-chip induc-
tance and cross-coupling capacitance between the interconnect lines also increase.
Inductances in a wire are of low magnitude value. It becomes significant only at
very high frequencies in global lines such as ground and power supply lines and is
important only in power circuits. Hence, the cross-coupling capacitance or crosstalk
noise effects are considered to have a predominant effect in digital circuits that may
result in improper functioning of a chip (Aragones et al. 2002). Crosstalk noise may
cause unwanted effects including excessive overshoot, undershoot, glitches, addi-
tional signal delay, and even a decrease in signal delay. These effects can lead to
possible circuit malfunction and increased power dissipation.
1.5 Crosstalk Effects 9
Fig. 1.2 a Positive pulse, b (a) (b)

negative pulse
Static 0 Static 1
Victim-line Victim-line
Aggress Aggressor-
or-line line
Rising Falling
transition transition
There are two main types of crosstalk effects: crosstalk-induced pulses and
crosstalk-induced delay. Given a pair of nodes with capacitive crosstalk interac-
tion, there is always one of them that act as affecting node or aggressor and the other
as affected or victim node. A crosstalk glitch is a pulse that is induced by coupling
effects among interconnect lines. The amplitude and the width of the glitch depend
on relative switching time of the aggressors, the amount of coupling capacitance,
line-to-ground capacitance, and the relative transition times of the aggressors. When
aggressor nodes are applied a transition signal and the stable signals applied to vic-
tim node, the stable signal may experience coupling noise due to transition in the
aggressor nodes.
In Fig. 1.2, the victim line remains in a static 0 state and one aggressor line has
a rising transition. The aggressor creates a positive pulse on the victim line, which
depending on its amplitude and width will have an effect on the circuit performance
(Moll and Rubio 1992). In the second case, victim line remains in a static 1 state and
one aggressor line has a negative transition, which creates a negative pulse on the
victim line.
Crosstalk delay is a signal delay induced by the identical coupling effects, that
is, simultaneous transitions among interconnect lines. Crosstalk causes a delay in
addition to normal gate delay and interconnect delay. Hence, it is difficult to estimate
the correct circuit delay which may lead to severe signal delay problems (Wang et al.
2006). These unexpected changes in signal propagation delays cause delay faults
which cause the delay of paths in a chip to be larger than expected resulting in the
output of a chip to deviate from the expected behavior, in spite of the chip being
functionally correct.
As shown in Fig. 1.3, the victim and aggressor have transitions in the opposite
direction, and hence, signal delay increases and speed of circuit decreases. In the
second case, if the transitions are in the same direction, signal delay decreases thus
increasing the speed of the circuit. These changes in signal propagation delays can
cause faulty behaviors of digital circuits.
When designing fault analysis tools, these delays have to be taken into consid-
eration. Several physical designs (Vittal and Marek-Sadowska 1997; Elgamel et al.
10 1 Introduction
Fig. 1.3 a Crosstalk (a) (b)

slowdown, b crosstalk
speedup
Victim- Victim-
line line
Aggresso Aggresso
r-line r-line
2005; Hunagund and Kalpana 2010) and analysis tools (Agarwal et al. 2006; Kaushik
and Sarkar 2008; Palit et al. 2009; Shahin and Pedram 2010) are being developed
to aid in designs that minimize crosstalk. But during manufacturing, process varia-
tions and manufacturing defects may aggravate crosstalk effects (Chen et al. 1998).
Hence, it is necessary to develop new crosstalk fault models and testing techniques
for manufacturing defects that produce crosstalk effects.
1.6 Crosstalk Fault Models
There are three important delay fault models at logic level: transition fault model,
gate delay fault model, and path delay fault model. Transition and gate delay models
represent delay defects lumped at gates, and path delay model represents defects that
are distributed over several gates.
Some researchers Chen et al. (1998, 1999, 2002) Sinha et al. (2003, 2008) have
used transition fault model, whereas the others Li et al. (2003, 2005, 2006), Chun
et al. (2009), Aniket and Arunachalam (2005) have used path delay fault model.
Combined transition and path delay fault model is used by Lee and Tehranipoor
(2008).
Crosstalk fault models were first developed by Gao et al. (1990) for lossy trans-
mission line system. In this model, the coupled transmission lines were first decou-
pled into a set of independent transmission line equations by linear transformations.
Then, the solutions of this decoupled equation were represented by a set of time-
varying equivalent circuits. This circuit model was implemented in a spice simulator.
Although these models were quite effective for the specific cases of high-speed Gal-
lium Arsenide integrated circuits, they are not applicable to VLSI circuits because of
the complexity of the circuit model and high computation time. Further, they provide
little insights into the coupling mechanism.
A simplified lumped RC model (Rubio et al. 1994) is assumed for crosstalk pulse
fault between a pair of coupled lines. Assuming a small wire resistance, the dis-
1.6 Crosstalk Fault Models 11
Fig. 1.4 Circuit showing

Ai A Aout
source of crosstalk due to
capacitive coupling
Cc
Vout
Vi V
tributed capacitance was modeled by a coupling capacitance between the aggressor

line denoted as A-line and victim line denoted as V-line. A layout tool is used to find
the coupling capacitance and aggressor line-to-ground capacitance. From this value,
the strength of aggressor lines which affect the victim lines was found to derive a
list of target crosstalk faults. However, crosstalk delay faults where both lines have
transitions had not been considered which is necessary for high-performance system.
To overcome this limitation, a model is developed by Chen et al. (1999) to evaluate
the effect of parasitic coupling crosstalk where inputs to one or both coupled lines
have transitions with arbitrary transition times and directions. All CMOS logic gates
were modeled as equivalent inverters, and then, the output response of crosstalk noise
was calculated through this gate using the transfer function of the equivalent inverter.
Figure 1.4 shows the source of crosstalk due to capacitive coupling. CC denotes the
coupling capacitance between the A-line and V-line.
The lumped model of coupling capacitance is shown in Fig. 1.5. The resistances
Ra1 and Ra2 are the line resistance and on-channel resistance associated with the line
driver, respectively. C 1 and C 2 denote line capacitance and gate capacitance of the
load driven by the line, respectively. The coupling network consists of C C , C 1 , and
C 2 . Figure 1.5 consists of three stages: input stage, a driver stage made of pulling
resistances, and the coupling network. Laplace transform is used for all three stages,
and an expression is obtained in the frequency domain, which can be transformed to
time domain. From these equations, the crosstalk effects that should be considered
for validation and test generation are identified. This model had been used for both
crosstalk pulse and delay analysis (Chen et al. 1997). However, this model is very
computationally intensive and takes a long time to simulate a small circuit.
Maximum aggressor (MA) fault model is suggested by Rubio et al. (1994) for
crosstalk which takes only the coupling capacitances into account. All aggressors
are assumed to make simultaneous transitions in the same direction while the victim
makes an opposite transition.
A constrained path delay fault (CPDF) model is used in Krstic et al. (2001). In
this model, the fault is defined as the critical path and a set of interconnects coupled
to it. Critical paths are paths whose delay is longer than a specified percentage of
the longest propagation delay in the circuit. A statistical timing analysis framework
was used for target fault selection phase. In statistical timing analysis, the delays of
cells/interconnects are modeled as correlated random variables with known proba-
12 1 Introduction
Fig. 1.5 Capacitive Ra1

coupling model A
Ai
C1
Ra2 Cc
Vi
C2
V
bility density functions. Using the cell delays, the cell-level net list and the clock
period, statistical timing analysis can derive the probability density functions of the
signal arrival times, required times, and slacks at internal signals and primary out-
puts. Using this information, the noise sources resulting in sensitivity higher than a
certain threshold are found. By intersecting the obtained noise sources and the set
of critical paths chosen without taking into account noise effects, set of crosstalk
faults is obtained. Each crosstalk fault consists of a path and a set of noise sources
interacting with the path. Exact delay information was not available in the CPDF
model. Hence, the time of transitions and the sub-paths from which the aggressor
transitions can be activated are unknown.
A coupled transition fault model (CTF) is used by Takahashi et al. (2005). A single
victim/aggressor crosstalk fault is considered. Four possible crosstalk delay faults
are considered. They are simultaneous rising or falling which are crosstalk-induced
speedup faults, one rising and another falling, and vice versa, which is crosstalk-
induced slowdown faults. This model uses a slow-fast-slow clock method to test
crosstalk delay faults in sequential circuits. The sequential circuit is expressed as an
iterative array model. In this model, crosstalk fault was induced in the victim line
when necessary conditions to excite the fault occur on the aggressor line. To calculate
the number of target faults, the static timing analysis algorithm uses structural and
timing information. False crosstalk faults that need not be tested were identified.
A single precise crosstalk-induced path delay fault model (S-PCPDF) is developed
by Li et al. (2006). In this path delay fault model, only robust paths are considered.
Crosstalk delay faults associated with robust path are taken as target faults. A crosstalk
fault is a path delay fault that is caused by a coupling effect between A-line and a
V-line on path denoted as p, such that there exists a sub-path denoted as sp-A starting
from the primary input and ending at line A-line and a sub-path denoted as sp-V
ending at V-line, satisfying the following conditions:
1. The difference in delay of the sp-V and sp-A should be within a specified interval.
2. The parity of the number of inverter gates on sp-A is different from the parity of
the number of inverter gates on sp-V.
1.6 Crosstalk Fault Models 13
An S-PCPDF can be represented using a 4-tuple (p, sp-A, V-line, A-line), while
p is usually a critical path, A-line is the aggressor line, V-line is the victim line,
and sp-A is the sub-path that propagates the aggressor transition to A-line. A single
precise crosstalk-induced path delay fault model (S-PCPDF) was developed by Li
et al. (2005) for non-robust paths.
1.7 Conclusion
The current scenario in VLSI testing and the test challenges in deep submicron
technologies is discussed in this chapter. The phenomena of unwanted crosstalk
pulses, crosstalk models at circuit level and gate level, and the various crosstalk
delay faults have also been presented.
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Chapter 2
Delay Fault Testing of VLSI Circuits
2.1 Introduction
The advances in VLSI technology have resulted in devices with millions of transistors
thus creating new test challenges. Moore’s law states that the scale of ICs has doubled
every 18 months. Reduction in feature size increases the speed of integrated circuits,
thus increasing the probability that a manufacturing defect in the IC will result in a
faulty chip.
Some manufacturing defects do not change the steady-state logical operation of
a system, but they may affect the timing behavior of a system and degrade overall
system timing performance and hence industry is forced to test timing anomalies in
circuits. The purpose of delay testing is to identify timing defects so that the design
adheres to the desired performance specifications. The need for delay testing is further
expected to grow with the current design trend of moving toward deep submicron
devices. Imprecise delay modeling, statistical variations of the parameters during
the manufacturing process, and physical defects in integrated circuits can sometimes
degrade circuit performance without altering its logic functionality. Delay testing
has been a topic of extensive research both in industry and in academia. Earlier delay
defects could be detected using tests for gross delay defects. Aggressive timing
requirements of high-speed designs have introduced the need to test smaller timing
defects and distributed faults caused by statistical timing variations.
The problems in delay fault testing are as follows:
• Testing of sequential circuits results in high area overhead and large execution
times.
• Requirement of high-speed testers.
• Small distributed defects require path delay model which requires testing of very
large number of paths for complex, large circuits.
• Critical path selection.

16 2 Delay Fault Testing of VLSI Circuits
• All paths cannot be sensitized and hence will result in a poor fault coverage.
• Design and synthesis techniques result in high area and large number of primary
inputs.
The reasons for timing failures in combinational circuits are excessive propagation
delay, correct output appears later than specified, inadequate propagation delay, cor-
rect output appears sooner than specified and static or dynamic hazards may appear
at the outputs. The basis for timing failures in sequential circuits are excessive prop-
agation delay, setup time (long path) violation, inadequate propagation delay and
hold time (short path) violation.
2.2 Delay Fault Models
Delay fault testing is back-end process which ensures that the product quality meets
established standards in terms of performance and physical defects. Defects in the
manufacturing process often result in propagation delays to fall outside the design
requirements. The effect of these performance degrading effects can be presented
using logical fault models. It is very important that these fault models clearly and
adequately understand the environment under which defects manifest.
Delay fault models can be primarily categorized into five types.
2.2.1 Transition Fault Model
This model considers a gross delay in every gate terminal in the circuit and assumes
that the additional delay is large enough to cause a logic failure (Waicukauski et al.
1987). The transition fault model is similar to the stuck-at fault model. There are two
types of transition delay faults: a slow-to-fall fault and slow-to-rise fault associated
with each gate. A slow-to-rise fault means that any transition from 0 to 1 on a node
does not produce the correct result when the device is operating at its maximum
operating frequency. Likewise, a slow-to-fall fault means that a transition from 1 to
0 does not produce the correct result at the desired frequency. In a fault-free circuit,
each gate has a nominal rise and fall delay. If there are delay faults, then the nominal
delay will increase. The size of the gate-level delay fault must be such that it exceeds
the slack of at least one path from the fault site to the primary output or scan flip-flop
such that the fault can be observed at the output.
The main advantage of the transition fault model is that the number of faults in
the circuit is small. Further, the existing test generation and fault simulation tools for
stuck-at faults can be modified for testing transition delay faults.
A test for a transition fault is a pair of input vectors which consists of one initial-
ization vector to set up the initial state of a transition and the second vector activates
2.2 Delay Fault Models 17
X,0 a
f
0,1 b
e
o
X,1 c
X,1 d
g
Fig. 2.1 Circuit with transition fault
the fault and propagates its effect to some primary output. The propagation vector is
identical to the pattern that detects the corresponding stuck-at fault.
The transition fault coverage is a measure of the efficiency of the delay test in
detecting large delay variations. Transition faults are a special case of gate delay
faults because the delay due to the defect is large enough to cause a logical failure
when propagated along any path through the site of the fault. The disadvantage is
that the assumption that one gate in the circuit is effected is not realistic. Several
delay faults together may be large enough to affect the performance of the circuit.
The transition fault model is normally used as a qualitative delay model, and circuit
delays are not considered in deriving tests.
It is known that a rising (falling) transition fault is detected if and only if: (i) The
first pattern places a 0/1 at the fault site and (ii) the second pattern detects a stuck-at-0
(stuck-at-1) fault at the transition fault site. In the circuit as shown in Fig. 2.1, to
detect a slow to rise fault in node b, vector 1: sets node b to 0, vector 2: sets the node
b to 1 (to detect s-a-0). So if there is fault in node b, the node will not change to 1.
Now, when the output e is read, the output will not change to 1. It will remain at 0.
Hence, a slow-to-rise fault manifests itself into a stuck-at-0 fault when a two vector
test is applied and if the delay fault is large enough. Further, the observation time at
the primary output should be longer than a predefined interval.
2.2.2 Gate Delay Fault Model
The gate delay fault model assumes that the delay fault is lumped at one gate in
the circuit. A localized timing failure at a gate causes the propagation delay of at
least one path in the circuit through the fault site to exceed the specified cycle time.
This model assumes that delays of logic gates are known with some precision. On
the other hand, the gate delay fault model does not assume that the increased delay
will affect the performance independent of the propagation path through the fault
5
(a) (b)
S0
Fig. 2.2 a Circuit not considering timing, b circuit with timing information
0 1
A E
2 6
C 2
F
2 2
2
B
6 8 10 12
0 D 1
Fig. 2.3 Circuit with delay fault at the output
site. It assumes that only long paths through the fault model will cause performance
degradation. It is a quantitative model that takes the circuit delays into account. The
number of faults is linear to the number of gates in the circuit. Similar to a transition
fault model, the disadvantage of this model is that the test may fail to detect delay
faults that are sum of several small delay effects. Figure 2.2a shows the AND gate.
If the information about the gate delays is not available, it is assumed that a static
hazard may prevent the propagation of some fault. If the information of the delays are
available and if the arrival time of the signals at the input are as shown in Fig. 2.2b,
the output will have a stable 0 which may propagate some fault to the primary output
(Krstic and Cheng 1998).
Figure 2.3 shows the problem with gate delay modeling. The delays of the gate
are as shown in the figure. At C, there is a slow-to-rise fault. As the value of C rises to
1, the output becomes high through shortest path with a delay of 6 time units. After
a delay of 2 time units, through the lower NOR gate the output goes back to logic 0
because output of NOR gate is logic 0. Again output goes to logic 1 taking the critical
path through the circuit at 10 time units as output of upper OR gate becomes logic 1.
Hence, a delay as large as time of observation of 12 units at output F is detectable. A
dynamic hazard is observed at the output due to different delays of the gates. Here,
only longest path through the circuit is considered. But a small gate delay fault is
difficult to detect because of hazards.
2.2.3 Line Delay Fault Model
Line delay fault model tests a rising/falling delay fault on a given line in the circuit
and propagates the fault through the longest sensitizable path in the circuit. It can
detect some distributed delay defects on the propagation paths. The number of faults
is equal to twice the number of lines in the circuits. Only one propagation path
through each line is considered.
2.2.4 Path Delay Fault Model
A path delay fault is associated with each logical path and is said to present if the
delay of any of its paths exceeds a specified limit. The delay of the path is the sum of
the delays of the gates and interconnections on that path. The model can detect small
distributed defects caused by statistical process variations. A delay fault caused by a
local defect, such as a resistive open or short, can only be detected by testing a path
through it, and testing the longest path through it can detect the smallest local delay
defect. The path delay fault specification consists of a physical path and a transition
that will be applied at the beginning of the path. This model is highly effective in
covering delay faults, but has a limitation because the number of paths in the circuit
can be very large. Process variation and noise can result in the longest path through
a gate varying from chip to chip or across operating conditions. Therefore, testing
only one critical path through each gate cannot guarantee the detection of the smallest
local delay faults. Testing the N longest paths through a fault site increases the fault
detection probability. The longest paths are selected because delay defects on shorter
paths might not be large enough to affect the circuit performance; moreover, even
if the defects on short paths are large and it could affect the circuit performance,
that defects could be detected by transition or gate delay tests. But in performance-
optimized designs almost all paths have long delays and most of the paths cannot be
tested. For performance-optimized circuits with aggressive timing necessities, small
process variations can lead to failures at the system clock rate. These defects can be
detected using tests for path delay faults (Wang et al. 2006).
This model overcomes the disadvantage of transition fault model in that the other
faulty gates may compensate for the delay of a faulty gate. Hence, path delay fault
tests are more likely to detect small delay defects.
The path delay fault model can be broadly classified into: (i) non-robust (NR)
path delay fault and (ii) robust path delay fault.
Non-robust (NR) path delay fault: This class of paths is statically sensitizable and
guarantees to detect the delay fault on the targeted path only if no other path delay
is increased.
A more proper definition of NR tests is: A vector pair {v1, v2} is said to detect a
path P non-robustly, if and only if:
g
f
X0 a
b
d
e
S1 c
Fig. 2.4 A robustly testable path
(i) The vector pair launches a transition (rising/falling) at the beginning of the path
and
(ii) All the off-paths inputs along the paths have a non-controlling value (NCV) for
v2.
Robust path delay faults: These types of paths can be tested independently of side
path delays. It is a more constrain form of non-robust test. A vector pair {v1, v2} is
said to detect a path P robustly, if and only if:
(i) The vector pair {v1, v2} should be an NR test for p and
(ii) Whenever the on-path input of a gate g is along the path transitions from a NCV
to a controlling value (CV), then all the off-path inputs of g should be held at a
steady NCV. Robust tests are difficult to generate, and a large number of paths
in a circuit are usually robustly untestable.
In Fig. 2.4, the falling transition on path ↓ bdeg is sensitizable irrespective of the
side path delays in the circuit. Hence, it is taken as the target path. The slow-to-fall
fault on b will not be prevented to be propagated to primary output even if there is
delay on primary input a. Hence, this path is robustly testable. But for some paths,
robust or non-robust tests may not exist. However, such functional paths can be tested
using functional sensitization.
2.2.5 Segment Delay Fault Model
It makes the assumption that delay affects several gates in a given region where it
occurs. The segment delay fault list consists of all segment of given length L and all
paths of length less than L which represents the delays distributed across the chip.
The model is a trade-off between transition fault model and path delay fault model.
Practically, many segments along path can be tested but the entire path may not be
testable. Further, it is more realistic than transition fault model. The upper bound on
the length of the segment is the maximum number of gates in the longest path.
Transition, gate and line delay fault models are used to represent delays lumped
at gates, whereas path and segment delay fault models are used to represent delays
distributed across the chip.
Path delay model is closest to ideal model. Most of the path delay faults cannot
be sensitized, but these paths might degrade the circuit performance. Developing
an accurate fault model and selection of critical paths that are sensitive to process
variations, defects, and signal coupling effects are important research problems.
2.3 Test Application Schemes
Delay testing is closely tied to test application strategy, type of circuit, and speed
of testing equipment. High-speed testers are costly. Testing high-speed design on
slower testers requires special test application and test generation strategies.
Combinational circuits require a vector pair {v1, v2}. The first vector is used to
initialize the circuit, and the second vector produces the desired transition. During
normal operation, a clock signal with a period T c is used for controlling both the
latches. Whereas, in test mode, two different clocks of period T s larger than T c and
having a skew equal to T c is used to control the input and output latches as shown in
Fig. 2.5. The first vector, v1, is applied at time t 0 , and the second vector, v2, is applied
at time t 1 at the primary inputs of the circuit under test. After application of vector
v1, the time required for the signals to become stable is assumed to be T s t 1 − t 0 .
Then, the second vector v2 is applied and the circuit stabilizes at time t 2, where t 2 −
t 1 T c . The logic value observed at the primary output is compared with fault-free
circuit response to check for a defect. The same scheme shown in Fig. 2.5 applies
even if the input and output clocks are the same. T s could be equal to or larger than
T c , and no skew will be present between the input and the output clocks. The rising
edges of the respective clock pulses are synchronized with timing of application of
input vectors and observation of output.
Delay fault testing of sequential circuits is more difficult than testing delay faults
in combinational circuits, because random vector pair cannot be applied to non-scan
or standard scan sequential circuits. Figure 2.6 shows the model of a sequential
circuit, represented as an iterative array of the combinational logic. Each copy of the
combinational logic is called as a time frame. The present state values of the current
time frame are equivalent to the next state values of the previous time frame. In case
of a sequential circuit, vector pattern (v1 , v2 ) is represented as (i1 + s1 , i2 + s2 ) where
i1 and i2 are the primary inputs and s1 and s2 are values of the present state values.
There are number of methods used for delay testing of sequential circuits
(i) For standard scan circuits: Enhanced Scan Testing, Functional Justification, and
Scan Shifting
(ii) For non-scan or partial scan circuits: Fast slow strategy and at-speed strategy
Input Combinational Output

Outputs
latches circuits latches
Clock C1 Clock C2
Clock C1
Clock C2
TS TC
t0 t1 t2
Fig. 2.5 Testing scheme for combinational circuits
2.3.1 Standard Scan Circuits
Test generation for delay faults in scan-based sequential circuit requires representing
sequential circuit in two time frames. All the lines corresponding to primary inputs
and present states are fully controllable in the first time frame, whereas only the
primary inputs are fully controllable in the second time frame.
Enhanced Scan
In enhanced scan, testing vectors v1 and v2 are shifted into the scan flops during the
shift process. These two values are stored in the enhanced scan flops at a time. Once
the vectors are shifted in, enable inputs of the scan flip-flops are made low. When
the clock is pulsed two times, response is shifted out. Any arbitrary vector can be
applied to the combinational part of the sequential, circuit and high fault coverage
is obtained in this method. Since the technique uses scan flip-flops, it has a high
overhead. Test application times are also very long and hence are not used widely in
application-specific integrated circuit area. However, in areas which require custom
designs such as microprocessors and other high-performance circuits, enhanced scan
designs are used. In custom designs, the circuit often is not fully decoded; hold scan
cells are used to prevent contention in the data being shifted and also prevent excessive
power dissipation in the circuit during the scan shift phase. In addition, the diagnostic
2.3 Test Application Schemes 23
Primary input PI Primary Output

Combinational.
Logic(C1)
PS NS
FFs
PI PO PI PO PI PO
C1 C1 C1
PS NS PS NS
time-frame n-1 time-frame n time-frame n+1
Fig. 2.6 Testing scheme for sequential circuits
capability associated with scan design for test is improved because the part in which
only the scan logic failed can often be retrieved. Hence, for high-performance designs
enhanced scan technique is preferred.
Functional Justification
The most common delay fault testing is functional justification. In this method, vector
v1 is scanned into the circuit during shift process and vector v2 is derived as circuit’s
response to the first vector. This technique is called functional justification because
the second vector is the functional response of the first vector. This method is also
called as broadside test or launch from capture. The broadside approach is cheaper
to implement compared to skewed-load approach.
Launch from Shift
This is also called as ‘Transition Shifting’ technique or skewed-load approach. In
skewed-load approach, both the vectors are shifted through the scan cells. The advan-
tage of skewed-load approach is test patterns with higher fault coverage are obtained
than broadside approach. Test pattern sets generated by the broadside approach are
usually larger than those generated by the skewed-load approach. For generating test
vectors for functional justification technique, a sequential ATPG that considers two
full time frames is required. On the other hand, for the skewed-load approach test
vectors can be obtained by a combinational ATPG with slight modification. Hence,
test generation cost is higher for the broadside approach.
In skewed-load approach, the second vector is obtained by shifting the contents

of the scan chain by one bit after application of the first vector. In this technique, the
second vector is no more the functional response of the circuit because the second
vector is shifted version of the first vector. The first vector is shifted, the system clock
is given, and the scan-enable is made low. The scan-enable is again made high after
the launch clock, and the capture clock is given.
This method gives improved fault coverage as compared to functional justification
because the second vector is partially controllable. But the drawback is that the scan-
enable has to switch its state exactly after the launch clock edge and before the capture
clock edge which is not always easy. To meet this timing, the scan-enable signal
should be driven by a complicated buffer tree, that is, a costly and time constraint
design requirement. Hence, this technique is infrequently used in the MUX-Scan
architecture. It is easier to use this technique in level-sensitive scan design (LSSD),
where the launch and capture clocks are separately controlled.
2.3.2 For Non-Scan Circuits
For non-scan circuits, slow fast slow and at-speed scan are used.
Slow Fast Slow Method
Delay fault testing in non-scan sequential circuits requires a sequence of vectors
which are applied in three phases in fault generation process: fault initialization,
fault activation, and fault propagation. In the fault initialization phase, vectors are
applied to set signal values in order to activate the fault. In the fault propagation
phase, the activated fault is propagated from an intermediate node to the primary
output. Test sequence is required for fault initialization and fault propagation, whereas
the fault activation phase requires a vector pair. The presence of delay defects in
the initialization and propagation phases can affect the observation of the fault. A
common solution is to apply a slow fast slow clock testing strategy. In this scheme,
circuit under test is considered fault free in initialization and propagation phase and
hence the clock is applied at a slow speed. In the activation phase, the first test vector
is applied under the slow clock while the second vector is applied at the rated speed.
Using this method simplifies test generation process since a slow clock is used
during fault initialization and fault propagation phases. On the other hand, two clocks,
slow and fast clocks, are needed which make difficult the test generation process.
Single fault assumption is usually not applicable for testing delay faults in partial
scan circuits. Therefore, during the end of fault activation phase, in slow fast slow
testing method more than one flip-flop latches a faulty value. The test generator has
to take account of this possibility during the fault propagation phase.
At-Speed Scan
At-speed testing strategy assumes fast clock which is used to initialize, activate, and
propagate the fault. Therefore, delay faults are present in all the three phases. Some
2.3 Test Application Schemes 25
faults that cannot be testable in the slow fast slow clock testing scheme can become
testable under the at-speed scheme and vice versa. The circuit is tested under its
normal operation conditions. The fault coverage for at-speed testing is lower.
Important factor in test application for delay faults is testers speed. Speed of
testers is less compared to the speed of new designs. Hence, new techniques have to
be developed that would allow high-speed design testing on slower testers.
2.4 Test Generation Methods for Path Delay Fault Model
Recently, scan-based structured techniques are used to test delay faults in digital logic
circuits. This is because less time is required to develop them, and it is relatively easier
to debug them. To reduce time complexity, test engineers use multiple parallel scan
chains as the number of flip-flops increases in long serial scan chains. But with large
circuit designs, test equipments cannot support the depth and large number of scan
chains. The difficulty of using structured scan-based techniques is the increase in
silicon area with the reduction in performance.
Another approach for testing delay faults is logic built-in self-test (BIST). In this
approach, test pattern generation and output response comparison functions are built
into the same chip (Hetherington et al. 1999). With a BIST-only approach, high
coverages have been reported (Kusko et al. 2001). To have a reduced test vectors
and high fault coverage, hybrids of logic BIST and deterministic ATPG techniques
have been proposed (Dorsch and Wunderlich 1998; Kiefer et al. 2000; Das and
Touba 2000). The disadvantages of BIST are as follows: area overhead for the BIST
controller, the requirement of additional pins, routing complexity, and reduced access
times.
Further, to have compatibility with commercial BIST tools, the clock distribution
and clock tree balancing tasks become more complicated (Hsu et al. 2001). Another
approach to test delay faults is ATPG. Efficient and powerful ATPG can alleviate
high costs of DFT.
There are two types of ATPG methods for generating tests for delay faults:
deterministic- and simulation-based test generation algorithms. Deterministic-based
test generators produce tests by processing a structural model of the circuit.
Simulation-based techniques typically involve generation of random vectors.
2.4.1 Path Delay Fault Simulation
A path can start at a primary input or a flip-flop and end at either a primary output or a
flip-flop. A path delay fault will cause the time of propagation of a signal through the
path to exceed the clock period. There are three steps in path delay test generation,
namely initialization, path activation, and propagation. One or more input vectors are
generated for each phase. The activation phase requires two test vectors to initiate
a signal transition at the source of the path and propagate it to the end of the path.
Path testing concepts in combinational circuits and scan-based sequential circuits are
applicable to this phase. There are two approaches for path delay fault testing based
on the way the path is activated. In the fully transitional path approach, the entire
path is sensitized at each gate by both the vectors. In the next approach only during
the second vector, the path is fully sensitized. But the first vector sensitizes the path
only through gates that propagates non-controlling values along the path.
Smith (1985) has developed a system for identifying paths that are testable inde-
pendent of gate delays. The six-valued logic used in his method represents two
vectors. The supported values are static 0, static 1, rising transition, falling transi-
tion, 0X where the first vector is 0 and second vector is unknown value and 1X where
the first vector is 1 and second vector is unknown value. Input vectors are generated
to the circuit, and inputs are set to any one of logic values except the unknown values.
The values are propagated through the circuit. Any path with the correct transition
direction and with the value of rising or falling transition is flagged as tested and
removed from path list. In this method, the delay of the gates along the path is not
considered during delay fault testing. This fault model is capable of modeling all
delay faults of any size. The time complexity of the test generation algorithm is
approximately a linear function of the number of gates and the number of paths.
Schulz et al. (1989) have a proposed a fast fault simulator for path delay faults.
Parallel test patterns are used for fault simulation-based test generation. Their simula-
tor could not test large number of paths under the restrictive condition of robustness.
They devised a four-valued algebra using Smith’s (1985) six-valued algebra for sim-
ulating robust and non-robust path delay faults. A data structure called the path tree
was employed to accommodate the large number of paths. The path tree stores parts
of paths that are common to several paths from a distinct primary input to primary
output only once rather than explicitly carrying them along for each path separately.
But explicit representation of all physical paths can consume more memory to store
the path tree for large circuits.
Pomeranz and Reddy (1992) have proposed a method for estimating the path delay
fault coverage without enumerating the paths. The three properties used in their work
for estimating the delay fault coverage without enumerating the paths are as follows:
(i) The number of paths in a circuit can be computed in time by making one
backward pass of the circuit.
(ii) When a single test pattern is used, one forward pass of fault-free logic simula-
tion will determine which lines in the circuit belong to path whose delay faults
are covered by the test. The number of paths found equals the number of path
delay faults covered by the test. Enumerating all the paths can be avoided.
(iii) Assuming a random test pattern, some of the faults detected by that test pattern
would have been detected by an earlier test pattern. Hence, only new faults
detected for the first time should be counted for calculating the fault coverage.
So new lines, which are logical lines (each line associated with rising or falling
transition) that are not already included in the previously detected list of path
delay faults, are calculated. The number of new path delay faults the particular
2.4 Test Generation Methods for Path Delay Fault Model 27
test pattern detects can be approximately calculated by counting the number

of path delay faults detected by the test pattern such that each path delay fault
counted includes at least one new line. These faults calculated can be added
with faults already detected to estimate the fault coverage.
The set of paths were divided into subsets by partitioning the circuit such that
every path passes through one line of the cut. A better estimate of fault coverage is
obtained as the number of partitions is increased. The estimate is always pessimistic
as the estimated fault coverage is lower than the actual fault coverage. The execution
time of the algorithm is equal to the number of lines in the circuit.
Heragu et al. (1995) have developed a new statistical technique for calculating
delay fault coverage in combinational circuits. Fault-free simulation of randomly
selected test vectors is done, and fault detection probability of each vector pair is
calculated. A thirteen-valued algebra is used for simulation. After simulation of cho-
sen vector, pair’s backward pass is done for observability calculation. The product of
the rising (falling) controllability and rising (falling) observability of line l gives the
rising (falling) fault detection probability of a path fault originating at l. Once detec-
tion probabilities are computed, the fault coverage is obtained. Only a fixed number
of sampled paths are considered for fault coverage computation, and hence, an error
of statistical estimates will result. But the computation time is smaller compared to
fault simulators. Results given for largest ISCAS-85 (c7552) and full-scan versions
of the ISCAS-89 benchmark circuits show that the savings in CPU time by vector
sampling and fault simulation is much significant.
Bose et al. (1993b) have proposed a path delay fault simulator for sequential
circuits. Only the active paths are considered. Active paths are those that actually
propagate the transition during a given input vector. The number of active paths
depends on previous and current vectors and is a dynamic property of the circuit and
input vectors. After simulation, the algorithm calculates the highest ranked sensitized
path in the subtrees present at all nodes of the circuit. This information is maintained
in one-bit flag, and an integer identifier called as maxpath is used to represent the
path. If the flag is true then a sensitized path from that node to output exists and the
maxpath uses the path count values available at each node of the circuit. The paths
are computed using depth-first search algorithm. The fault simulator gives robust
and non-robust fault coverage. For robust simulation, six-valued algebra is used and
a new update rule (optimistic update theorem) is used for updating latches. Results
for ISCAS benchmark circuits indicate that path pruning effectively decreases the
number of faults to be scanned per vector.
Gharaybeh et al. (1996) have proposed a path delay fault simulator for combina-
tional circuits which does not enumerate all the paths of a circuit. They have used
a data structure, called the path status graph (PSG), to efficiently hold the status of
each path delay fault using flags in the circuit to represent whether or not the fault is
tested. The status of a path delay fault is ‘true,’ if all path edges are ‘true,’ and ‘false,’
if at least one path edge is ‘false’. PSG retains all or part of the reconverging fanout
structure of the circuit. Hence, the PSG eliminates the need for tracing individual
paths. Instead, fanout-free sub-paths are traced. Experimental results indicate bet-
ter efficiency of fault coverage for singly testable path delay fault using non-robust
detection criteria.
Kapoor (1995) has proposed a delay fault simulator for calculating exact fault
coverage. He has used a set of consecutively numbered path delay faults which
can be represented as a closed interval over a pair of integers. A tree-based data
structure is used to store and manipulate these intervals. During the path delay fault
simulation, newly tested path delay faults, represented as intervals, are merged into
existing intervals thus reducing the memory requirement efficiently. Although their
algorithm has worst-case performance, the simulator is efficient in the sense the
memory and time requirement is O (1).
Pomeranz et al. (1992) have proposed a simulator for path delay faults in sequential
circuits where test sequences are applied under multiple clocking schemes, allowing
fast simulation for a given test sequence. The circuit is initialized to the desired state
using a slow clock, and fault is activated using a fast clock, and if fault is present, the
faulty values are observed at the primary outputs or latched in the memory elements
using slow clock. They have used a path representation scheme in which all paths
need not be enumerated. When a new path delay is detected, the number associated
with the path is computed and compared with the list of numbers already stored, and
the number is stored if it is not found in the list of tested faults. Thus, comparison of
sequences of line numbers is avoided when determining the fault coverage of a test
set. Their simulator simulates in parallel the set of all clocking schemes with a single
fast clock cycle in each for a given input sequence. The simulator also determines
the minimal number of clocking schemes, using multiple fast clock cycles to achieve
maximum fault coverage for a given input sequence. This allows the algorithm to
maximize the fault coverage and minimize the clocking schemes.
Majhi et al. (1996) have developed a path delay fault simulator for delay testing of
combinational logic circuits. Their simulator generates both robust and non-robust
tests for path delay faults. They have used a rule-based approach to identify all robust
and non-robust paths tested by two pattern test, while backtracking from primary
outputs to primary inputs in a depth-first manner. Rules are formed to identify likely
glitches which propagate through the circuit.
Chakraborty et al. (2000) have proposed simulator for path delay faults in sequen-
tial circuits. They have suggested separate algorithms for the variable clock and rated
clock modes. In the variable clock mode, a fault is designated by three items: path,
transition type, and vector number at which the transition propagates through the
path. A separate fault effect is produced at each activation of a path. In the rated-
clock mode, all the activations of a path are treated as effects of the same fault. Based
on various assumptions about the initial states of flip-flops, two fault models are sug-
gested for fault simulation of path delay faults. They have used a differential fault
simulator and thirteen-valued algebra. Their simulator has been used to select test
points in self-test circuits to increase the path delay fault coverage of pseudorandom
vectors.
Using the binary fault simulator developed by Majni et al. (1996), the Jayanthy
et al. (2008) have developed genetic algorithm-based ATPG for path delay faults.
First step in path delay fault simulator is to identify the total number of primary
inputs and outputs. After this, level of the circuit and total number of gates in that
are obtained. Next, the total number of paths in the circuit is calculated using the
depth-first search algorithm which uses recursive search procedure. The entire circuit
paths are examined using the tree data structure. This tree takes the primary input
as a parent then the next level as its child. This process continues until it reaches
the primary output. The paths of the circuit are saved in a text file. For finding the
robustness of the path, it is necessary to trace backwards that is from primary output
to primary input. So with this tree structure, the backward trace is also done. Test
vector pairs were generated using genetic algorithm, and the number of robust and
non-robust paths is found out. The number of logical path delay faults modeled is
twice the number of physical paths present in the circuit since the rising and falling
transitions are considered at the source of each path. Once a path fault is detected
by a vector pair, it is added to the list of detected faults to keep track of the fault
coverage. Figure 2.7 shows the flowchart of GA-based test generation algorithm.
Fitness is a quantity related to the chromosome, which serves to enable comparison
between chromosomes. The fitness function F1 is used.

F1 [µnew ]/ µtotal − µpast (2.1)
µnew includes path delay fault tests detected only by the test vector pair applied at
present,
µtotal includes the total number of path delay faults and
µpast includes the path delay faults detected at past.
The delay fault simulator and genetic algorithm-based test generator are imple-
mented in Visual C++. For evaluation, ISCAS85 benchmark circuit c17 and the
circuit shown in Fig. 2.8 were used. For GA, rank-based selection method is used.
In all the experiments, the default crossover probability is assumed to be 2 and the
mutation probability is assumed as 0.02. The default size of population is assumed
to be 10. The initial population is generated randomly, and then, GA is used to opti-
mize the population for 9 generations and the total number of applied test applied
test vector pairs is 9 * 5 45 vector pairs.
Experimental results gave 100% fault coverage for the c17 (total path delay
faults 22) with an execution time of 0.01 s. 100% fault coverage is achieved
in the second generation itself, and for circuit shown in Fig. 2.8 (total path delay
faults 24), fault coverage 100% is achieved with simulation time of 0.047. For
larger benchmark circuits, simulation algorithm takes high execution times.
2.4.2 Test Generation for Path Delay Faults
Most test generators use a modified version of PODEM.

Lin and Reddy (1987) have proposed a five-valued logic for generating robust tests
for path delay faults. They have proposed a five-valued logic to represent the two
Start
Generate random iniƟal populaƟon

of test vector pairs
Perform a simulaƟon using Binary

logic PDF simulator
Any new PDF detected by the test

vector pair enter into the resulted test
set
Yes Is the stop

condition
saƟsfied?
End
Calculate the fitness for every test
vector pair in the population
Generate next generation of

population using genetic operation
Fig. 2.7 Flowchart of simulation-based test generation algorithm
vectors and used a branch-and-bound algorithm to find a robust test, for a given fault.
They have formulated necessary and sufficient conditions for robust testing of path
delay faults in circuits consisting of simple gates. They have devised that existence
of fully transitional path test is neither necessary nor sufficient for robust testing of a
path delay fault. Patil and Reddy (1989) have used PODEM-like algorithm and the
heuristics specified by Lin and Reddy (1987) to derive tests for path delay faults.
The path delay test generation algorithm by Lin and Reddy (1987), using multiple-
valued logic to find robust tests, has been further improved by Fuchs et al. (1991).
They have proposed automatic test generation algorithm for path delay faults based
Fig. 2.8 Circuit for evaluating the fault coverage
on a ten-valued logic. Their test generator is capable of detecting both robust and
non-robust faults. A new path sensitization procedure is used, which is capable of
efficiently identifying large numbers of path faults as redundant. If a given subset of
paths is not testable, the algorithm switches to the next set of faults and thus generates
tests for all testable path delay faults and also identifies redundant paths. They have
also proposed a new path selection procedure which exploits value assignments in
order to select paths that can be sensitized. The advantage of their method is that their
algorithm is the fastest branch-and-bound procedure reported for path delay fault test
generation. The disadvantage is that large memory is required for storing path tree
for large circuits. This method is very effective in poorly testable circuits, but many
faults have to be dealt with separately in those circuits that are highly testable.
Bhattacharya et al. (1992) have proposed a new test generation technique for
path delay faults in circuits employing scan hold-type flip-flops. They have used
reduced ordered binary decision diagrams (ROBDDs) as the main data structure to
represent the behavior of any sub-circuit of the circuit as well as to represent the fault
detection constraints. General path activation conditions presented by Lin and Reddy
(1987) are used to generate the single input transition tests and non-robust tests. The
test generation process consists of manipulation of Boolean functions and does not
require enumeration of input patterns. The authors have considered only scan-hold-
type latches and hence have considered only two time frames in which transition
occurs. Two faults are considered for each path in the circuit. For each fault, two
constraint functions, corresponding to the two time frames that constitute a transition,
are evaluated. These constraint functions which are represented as reduced ordered
binary decision diagrams are then manipulated using Boolean algebraic operations.
If the constraint function in the second time frame is non-null, then the algorithm does
a robust test generation for the path delay fault. A robust test can be fully transitional
path tests or single input transition tests. If a robust test cannot be found, then test
generation algorithm proceeds with finding non-robust test for path delay faults as in
Lin and Reddy (1987). Boolean algebraic manipulation of the constraint functions
guarantees that if neither robust nor non-robust tests exist, the fault is undetectable.
Since test generation process consists of manipulation of Boolean functions, the
method is faster than branch-and-bound algorithms. The disadvantage is the memory

requirement for storing the binary decision diagrams may be high for large circuits.
Pomeranz et al. (1993) have proposed a non-enumerative test generation method
for path delay faults in combinational circuits. They have not considered all the paths;
instead, only single lines are considered. By propagating transitions robustly through
parts of the circuit, a large number of path delay faults can be detected. Their algorithm
identifies sub-circuits which have large numbers of paths going through them that
can be tested at the same time. This is done by using labeling techniques that consider
only lines and not paths of the circuit under test. The labeling algorithm backtraces
the circuit from primary outputs to primary inputs, assigning label to every line l that
is equal to the number of paths from line l to the primary outputs. The sum of the
labels assigned to the primary inputs gives the number of paths. Once the sub-circuit
is selected, test generation objectives are found. Once satisfied, these objectives are
used to generate a test that detects a large number of path delay faults. The fault
simulation algorithm used in Pomeranz et al. (1992) is used to find the number of
path delay faults detected by a two-pattern test. The advantage of their test generator
is that it can be used to test circuits with large numbers of detectable path delay faults.
The disadvantage is that their method provides a pessimistic estimate of robust path
delay fault coverage. Further, the algorithm is most useful in highly testable circuits,
but may not succeed in finding delay faults in poorly testable circuits.
Bose et al. (1993a) have proposed compact delay tests for path delay faults. They
have used a twenty-three-valued logic system. This logic system is complete, and the
signals can have minimum restrictions for satisfying path activation requirements.
They have used the path numbering scheme which is used in Bose et al. (1993b).
The test generation is similar to PODEM-like branch-and-bound search for test. Test
generation technique consists of selecting an untested fault and generating a two-
vector sequence to sensitize the fault. This fault is called as primary fault. If any input
is unspecified or partially specified, then it is assigned a basic or composite value
that is a subset of the currently assigned composite value such that they can test the
secondary faults also. The inputs thus give tests for both the primary and secondary
fault. Thus, the test generation algorithm makes a cautious choice of secondary faults
for further sensitization. The disadvantage of the proposed algorithm is multivalued
algebra which is used as the only guiding mechanism. There is no thought for circuit
connectivity. For few circuits, the number of backtraces is greater than the number
of secondary faults that are detected.
Fuchs et al. (1994) have proposed a recursive selection and sensitization algo-
rithm for path delay faults for combinational- and scan-based sequential circuits.
The authors have shown that their algorithm can generate tests for path delay faults
effectively in both highly testable and poorly testable circuits. Their algorithm makes
use of the fact the paths in a circuit usually have sections in common. To reduce the
number of value assignments during path sensitization, the common sub-paths are
sensitized only once. Without enumerating all the paths of the circuit, the untestable
faults are identified. Five test classes are introduced, and the algorithm derives a
composite logic system for each class such that the conflicting values assignments
are detected early. The authors have made a comparison with the other existing algo-
rithms and showed that their algorithm detects a significantly larger number of path
delay faults in a lesser amount of time. The disadvantage is that since the algorithm
still depends on path sensitization and backtracing, it can have evaluation conflicts
and thus requires iteration several times.
Agrawal et al. (1992) have suggested a test generation for delay faults in non-scan
circuits. Their algorithm augments the circuit net list such that the single stuck fault
testing is the same as testing of the path delay fault. The logic that is added to the net
list consists of combinational gates that are driven by the signals feeding the gates
on the path and a pair of flip-flops. In this logic, a stuck-at-1 fault is activated and
its effect is latched into the destination flip-flop of the path only when all signals
along the path are set to the states as required for a path delay test. The fault effect
is then propagated to a primary output. Their algorithm combines a path generation
technique and modified version of sequence test generator (Ghosh et al. 1991). The
disadvantage of their technique is that for large sequential circuits the execution time
is high.
Chakraborty et al. (1992) have suggested a test generation method for path delay
faults in random logic sequential circuits. The authors have used a thirteen-valued
algebra to compute robust and non-robust tests. An additional hazard condition is
introduced which represents multiple transitions between vectors thus the tests are
independent of gate delays. Three path delay fault models are proposed and examined
based on the assumptions on the initial state of the flip-flops for a given vector
sequence. The advantage of the algorithm is that it can test any type of sequential
circuit irrespective of its structure. Their complexity of test generation is reduced as
clock is run at rated speed only during path activation. They have implemented the
delay test generation algorithm by modifying an existing test generation algorithm,
Gentest (Cheng and Chakraborty 1989).
Chakraborty et al. (1997) have proposed variable clock method for test generation
of path delay faults where only one vector that propagates the transition through
the path is applied with rated clock. All other vectors are applied at slow speed to
guarantee fault-free initialization and fault effect observation. The advantage is that
the generation of tests is simplified since the slow clock allows the faulty circuit to
behave like a fault-free circuit. But the disadvantage is that the test application time
becomes large.
Bose et al. (1998) have suggested a rated-clock test method for delay fault test
generation. Three-vector algebra is used to activate the fault from input to output,
and a forty-one-valued algebra is used for effective backward justification. Results
have been given for much larger benchmark circuits compared to their previous
work (Bose and Agraval 1995). A difficulty with this technique occurs when the
rated-clock speed exceeds the capability of the test equipment.
Yihe and Qifa (2001) have suggested a path delay fault test generation technique
using fault simulation and genetic optimization. They have used a parallel vector fault
simulator for simulating several vectors simultaneously. The algorithm uses a four-
valued logic path status graph for representing the circuit structure. An optimized
test pattern is obtained by using genetic algorithm for searching the test vector space.
Comparison with other test generation algorithm shows that this technique detects
more path delay faults in reduced time. But the disadvantage of the algorithm is that
in later stage of test generation when the delay fault coverage is high the efficiency
of genetic algorithm is not obvious.
A combination of fault simulation and genetic algorithm-based test generation
methods with deterministic test generation will give better results.
2.5 Conclusion
Various delay fault models along with their relative advantages and disadvantages
are discussed. The test application schemes for delay faults in combinational and
sequential circuits are presented in this chapter. Prior work on test generation and
simulation of path delay faults for combinational and sequential circuits is presented.
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Chapter 3
Test Generation Algorithms for Crosstalk
Faults
3.1 Introduction
Several design techniques such as repeater insertion, shielding techniques, device

sizing, and net ordering have been proposed for elimination and minimization of
crosstalk. The most commonly known method is shield insertion. In this design
technique, the victim and aggressor are separated from each other using shield wires
which are tied to either ground or power supply (Kolodny 2006). In order to reduce
noise and unpredictable delays, ground or power lines are placed at the sides of a vic-
tim. This design technique, however, results in more power consumption, increases
routing area, and increases complexity in routing interconnects. Buffer/repeater inser-
tion technique is used to reduce delay between the interconnects, thus minimizing
the coupling effects. The delay of a signal wire is related to the length of the wire;
hence in order to reduce the wire lengths, buffers are inserted. Buffer can also be
used to decouple coupling effects, thus reducing crosstalk noise. But splitting the
wire into shorter segments makes the delay rise linearly. Buffer insertion is usually
done during the post-layout stage. To optimize the performance, if the number of
buffers inserted is increased, it becomes impractical to insert hundreds of thousands
of buffers when the entire routing region is occupied by routing wires. In device
sizing technique, drivers of the aggressor wires are downsized for noise reduction,
utilizing the interconnect information extracted from the routed layouts. But down-
sizing degrades robustness of the device. Upsizing drivers increase power dissipation.
Further, it is not possible to predict beforehand the full range of process variations
and manufacturing defects which could aggravate the capacitance coupling effects.
Redesign could also be very costly in terms of design effort (Ganeshpure and Kundu
2007a). Further crosstalk effects along with weak spot defects produce timing errors
that need to be addressed during testing.
Hence, there is a necessity to develop testing techniques for manufacturing defects
that produce crosstalk effects. Accurate modeling and test generation of intercon-

38 3 Test Generation Algorithms for Crosstalk Faults
nect delay due to crosstalk become increasingly important in the design of high-
performance integrated circuits (Chen et al. 2002a).
3.2 Test Generation Algorithms
Techniques used to detect the delay faults can be broadly classified into indirect
test methods (correlation based) and direct methods. However, aggressive scaling of
CMOS technology with reductions in supply voltage, threshold voltage, and effective
channel length makes indirect methods less effective. There has been increased focus
on direct test techniques which rely on (i) ATEs with improved capabilities/higher
frequencies and (ii) on-chip test logic like built-in self-test (BIST), design for testa-
bility (DFT), on-chip timing analysis, and delay fault testing circuitry for device
under test (DUT) chip for improved testability. The use of on-chip testing circuitry
allows for at-speed testing which is required to ensure exact performance in terms
of timing and characterization of chips.
Incorporation of the self-test capability increases the silicon area required to imple-
ment the chip, thus escalating the cost of manufacturing chips. Also, the hardware
added to the circuit increases the delays of the usual circuit path reducing the speed
of the normal operation of the circuit.
Hence, testing for delay defects using ATE appears to be the better alternative,
since it gives a minimum set of test patterns required to test the circuit under a
particular fault model.
Testing consists of applying a set of test vectors to the inputs of the circuit under
test and analyzing the output responses of the circuit. Any discrepancy in the output
response indicates the presence of fault.
Given today’s very large designs, the test process heavily relies on automation.
Various test pattern generation (ATPG) and pattern grading tools have been used to
reduce the product time to market (Cheng and Krstic 1999).
The objective of ATPG is to obtain a set of test vectors that will detect the defects
that arise during the manufacturing process. A fault simulator is used to evaluate the
quality of tests in terms of fault coverage, number of transitions, etc.
ATPG for digital circuits is a major research topic. Both deterministic and
simulation-based algorithms have been proposed. Deterministic test generation can
be fault oriented or fault independent. In a fault-oriented test generator, tests are gen-
erated for specified faults of a fault universe. Fault-independent test generator works
without targeting individual faults. In a deterministic algorithm, tests are generated
based on a model of the circuit and a given fault model. Efficient test generation
algorithms have been devised for crosstalk delay faults in combinational circuits.
Most of the test generators incorporate a modified path-oriented decision making
(PODEM) algorithm at gate level to generate test vectors for crosstalk delay faults
between local interconnects. Test vectors were generated to activate the required
signal transitions at the victim and aggressor pairs and propagate the fault effects to
the circuit outputs.
3.2 Test Generation Algorithms 39
Table 3.1 Eleven-valued Symbols Description

logic
S0 Steady 0
S1 Steady 1
T1 Rising transition
T0 Falling transition
P0 Positive pulse
P1 Negative pulse
SU T1 Speedup rising transition
SU T0 Speedup falling Transition
SD T1 Speed-down rising transition
SD T0 Speed-down falling transition
X Unknown value
Chen et al. (2002a) have used a deterministic algorithm using a modified version
of PODEM to detect crosstalk faults. The objective of their ATPG is to generate
test vector pairs that produce the required crosstalk effect and propagate the effect
to the primary output to produce either a logic error or the maximum noise effect,
under given timing assumptions and requirements. They have developed capacitive
coupling model to estimate the crosstalk effects based on certain circuit parameters
and signal timing properties.
Using static timing analysis, the timing window of transitions on the aggressor
line (A) and the victim line (V) is obtained. They have considered crosstalk slowdown
effects only. The symbol values used in their system are given in Table 3.1.
The five objectives in creating a crosstalk slowdown effect are as follows: a weak
signal on the victim line, a slow rising/falling transition on the aggressor line, a strong
signal on the aggressor line, a falling/rising transition in the victim line, and a path
that propagates the crosstalk effect to the primary output. Based on these objectives,
conditions are determined for maximizing the crosstalk effect.
When both the aggressor and victim lines have transitioned at the same time,
then maximum crosstalk slow down occurs. A late transition is created on the victim
line, which is delayed due to crosstalk, and propagated through the critical path to a
primary output to cause a timing delay. The pseudo-code for test generation algorithm
is shown in Fig. 3.1.
Simulation plays a crucial role in the design and test of integrated circuits. Digital
logic simulation involves the construction of a computer model of the hardware that
is being designed and execution of the model for a set of input signals and obser-
vation of output signals. Simulation can be done at various levels of abstraction:
device level, circuit level, switch level, gate level, register transfer level, and system
level. The basic methods to simulate a circuit at the gate level are compiler-driven
simulation and event-driven simulation. The output of any physical gate will take
some time to change after an input has changed. Delays effect the correct functioning
of the circuit (Gerez 1999). Compiler-driven simulation is the one that executes a
Test generation(fault list)

Begin
Check the transition Timing windows
do
if(the desired transition is set on the aggressor line and side fanins are set and if desired transition is set
on the victim line )
begin
if(can a timing violation be created at PO)
begin
Crosstalk effect observed;
record the vector;
update the values of gates on the propagation path for branch & bound
purpose
if(Are all PI combinations covered?)

begin
if(any vector recorded)
list there corded vectors
else
noise effect undetectable
end
else
begin
Backtrack and change PI assignments
Imply( )
end
end
else
If(noise is dropped due to branch & bound?)
If(Can the initial objective line under current assigned value of

PI be selected?)
begin
Set the objectives( )
Backtrace( )
Imply( )
end
else
begin
Backtrack and change PI assignments

Imply( )
end
else
Fig. 3.1 Pseudo-code for test generation algorithm

3.2 Test Generation Algorithms 41
begin
Backtrace( )
Imply( )
end
end
else
begin
if( Can the initial objective line under current assigned value of PI be selected?)
begin
Backtrace( )
Imply( )
end
else
begin
Back track and change PI assignments

Imply( )
end
while (fault count!=0))
Fig. 3.1 (continued)
compiled code model and is quite faster. But it deals only with limited delay models.
An event-driven simulator uses a structural model of a circuit to propagate events
and can deal with very general delay models at the expense of computer time. In
event-driven simulation, only those signals that are changing are computed. Fault
simulator consists of simulating the circuit in the presence of fault. It is used to
determine the ability of a test to detect faults for a given fault model of the design
under consideration. Fault list is created for the design based on the fault model.
Then, reduced set of fault list is obtained. The faults from the target fault list are
injected into the model by the fault simulator, and after simulating the given tests,
the fault coverage is repeated. If the fault coverage is high, the process is terminated.
If the desired fault coverage is not obtained, the ineffective tests are discarded and
the new tests are added. In some cases, the existing tests are modified and new tests
are specifically written for hard to test faults in the design. The general simulation
techniques are serial, parallel, deductive, and concurrent. The serial simulation is the
simplest method of simulating faults, and it consists of transforming the model of
fault-free circuit M into a faulty model MF by introducing the fault F and simulating
MF. The entire process is repeated for each fault in the fault list. That is, the faults are
simulated one at a time in a given time frame work. The other three techniques—-
parallel, deductive, and concurrent—simultaneously simulate the fault-free circuit
and set of faults {MF}.
Chary and Bushnell (2006) have proposed a simulation-based ATPG system, with
a multiple-delay sequential fault simulator which uses three logic values (0, 1, and
X) with glitch detection, for detecting crosstalk delay faults. The crosstalk fault list
obtained consists of all possible interconnect pairs. Static timing analysis was used
to find the target fault list because some of the faults cannot be tested. The circuit
extractor is used for parasitic extraction of resistance and capacitance. An analog
macro-model is used to provide analog effects due to faults during digital simulation.
The fault list included the aggressor and victim names, fault type, capacitance per
unit length, coupling capacitance value, and impedance of drivers and loads of both
lines. Signals on a path have two delays, namely switching and propagation delay.
The time for an input signal to reach output of a gate is called as the switching delay.
The time taken by a signal transition at a gate output to reach the input of a fanout
gate is the propagation delay of the signal. A multiple-delay model is used where
each gate is assigned a rising and a falling delay. To obtain these delays, each gate
type is simulated using the Cadence SpectreTM analog simulator. Normally, a zero
delay or unit delay simulator produces glitch in the output, but since gate delays are
considered, the simulator removes glitches that are narrower than the gate delay. For
calculating the propagation delay, they have considered fanout nodes that transmit
the signal from the stem to each branch with some delay. Thus, if a stem has n fanouts,
it will have n delays.
The ATPG algorithm is shown in Fig. 3.2. An analog macro-model is used to find
the delay that is to be injected into the simulator, and logic simulator is delayed by
the injected delay. Faults are read from the fault list, and circuit is simulated. The
output for faulty circuit and fault-free circuit is observed. During propagation, the
signal may get delayed and cause an incorrect value to be observed at the primary
output or a pseudo-primary output. Those faults are considered to be detected and
removed from fault list. The test generation continues till all the remaining faults are
tested for all the test sequences.
3.3 Test Generation for Crosstalk Pulses
3.3.1 Deterministic Algorithms
In generating test patterns for a crosstalk pulse fault, the logical value change 0-to-1
or 1-to-0 is applied to the affecting line, and the interference pulse at the affected
signal line is propagated to primary outputs after the transition point.
Therefore, to detect a crosstalk fault, two successive test vectors are required
for all the test generation algorithms and the algorithm becomes complex. The two
vectors can be generated separately, or a different logic system can be used such that
the vectors can be derived concurrently with a single copy of the circuit. When the
two vectors are generated separately, three-valued logic is used where the value of
each signal will be 0, 1, or X. If two vectors are to be generated simultaneously, a
3.3 Test Generation for Crosstalk Pulses 43
Start
Simulate the fault free circuit End

and find out the clock period.
Yes
No
Read the next fault from the End of test
target fault list sequences?
Simulate fault free and faulty No

Yes
circuit
Is fault list
Read the next test
empty
vector
Get the skew and pass it to the
macromodel
Fault injection by the amount of If faults are detected remove

delay from macromodel from fault list
Fig. 3.2 Fault simulation-based ATPG
value system different from the three values system can be used to represent values
over two vectors. S0 and S1 are signal values which represent steady logic ‘0’ and
steady logic ‘1’ in the first and second test vectors, respectively. T0 represents logic
‘1’ in the first test vector and logic ‘0’ in the second test vector. T1 represents logic
‘0’ in the first test vector and logic ‘1’ in the second test vector. These vectors are
required to produce a weak driver on the victim line, a fast signal transition on the
affecting line, and a propagation path that sustains/increases the noise effect until it
reaches an output.
In most of the papers (Chen et al. 1997, 1998; Rubio et al. 1994), a modified
version of PODEM algorithm is run as the core to obtain a two-vector test in VLSI
circuits for a crosstalk pulse fault by forcing values to the victim and aggressors
nodes and propagating the possible interference to the primary output nodes.
Rubio et al. (1991) have generated test patterns for logic crosstalk faults in combi-
national circuits. An algebraic method is applied to generate a two-vector test to test
crosstalk faults. An input sequence is derived that forces a determinate value to the
affected nodes and incites a transition of the affecting lines allowing the propagation
of the possible interference to the primary output nodes.
Rubio et al. (1994) had presented a test generation algorithm using a simplified
lumped RC model for crosstalk between a pair of coupled lines. In their case, the
crosstalk effect manifests as a pulse on the line whose input is held constant. These
models characterize crosstalk effects as static hazards having a full voltage swing
and result in an overestimation of noise strength. Since crosstalk is a finite energy
transient effect, test vectors generated using the above-said models may not truly
propagate the noise to POs or flip-flops because of the inertia inherent to gates.
To obtain a larger crosstalk effect at the output a model is proposed by Chen et al.
(1997). They have started with a model in the frequency domain to obtain a closed
form voltage transfer function quantifying the dependence of the pulse maximum
amplitude, width, energy, and timing on the values of circuit parameters. This is then
transformed to get expressions in the time domain. These expressions also charac-
terize the speedup or slowdown of transitions due to crosstalk. These expressions
show that the crosstalk pulse is directly proportional to the coupling capacitance and
the ratios of the strengths of the drivers driving the two lines. They have showed that
while the maximum amplitude of the crosstalk pulse reduces quickly as the rise–fall
time of the input increases, the energy of the pulse is nearly independent of the input
rise–fall time for a practical range of rise–fall time values. They have also discussed
how test patterns can be derived for crosstalk pulse and crosstalk delay faults.
In Chen et al. (1998), the same authors have proposed a mixed signal test generator
that generates a two-vector test for crosstalk-induced effects, such as pulses, signal
speedup and slowdown, in digital combinational circuits. They have developed a test
generator that has static values in the side fanin like in PODEM as well as dynamic
signals such as transitions and pulses, and timing information such as signal arrival
times, rise–fall times, and gate delay. They have also used an analog cost function
to guide the search process. Even when several objectives are to be satisfied for the
detection of fault their test generation algorithm processes only one objective at time.
This causes unnecessary backtracks and reduces ATPG efficiency, particularly when
the limit on the number of backtracks is low. Multiple crosstalk effects have been
ignored.
3.3.2 Simulation-Based TG
Test generation using this deterministic algorithm is highly complex and time-
consuming. Simulation-based test generation has been used to evade lengthy execu-
tion times of deterministic algorithms and to reduce complexity of test generation. In
particular in simulation-based approach, processing occurs in the forward direction
only. Complex component types can be easily handled. Development time is greatly
reduced.
Fault simulator is used in Itazaki et al. (1997a), Phadoongsidhi et al. (2002),
Itazaki et al. (1997b), and Phadoongsidhi and Saluja (2003) to develop test vectors
for crosstalk pulse faults in synchronous sequential circuits. In all the papers, the
combinational model for a sequential circuit is constructed by regenerating the feed-
back signals from earlier time copies of the circuit. Thus, the timing behavior of
the circuit is approximated by iterative combinational level. The simulators take an
aggressor as a primary input, primary output, or output of a gate in the circuit. The
victim can only be a flip-flop. All the simulators use three-valued logic.
3.3 Test Generation for Crosstalk Pulses 45
Itazaki et al. (1997a) have considered crosstalk fault as unexpected strong capaci-
tive coupling between one data line and clock lines because generated crosstalk pulses
on data lines can be eliminated by a clocking. They have assumed two crosstalk faults.
One is the crosstalk fault from one data line to one clock line of every FF, and the
other is the crosstalk fault from one data line to all clock lines for all FFs. The simu-
lator uses the concept of waveform simulation to store the changes in logic values of
a node that occur within a time frame. Logic value at each time step is recorded in a
bitmap buffer. For each time frame after good circuit simulation, waveform buffers
associated with the fault are examined to determine whether the target is a crosstalk
pulse fault. If the pulse-generating condition is satisfied, simulation of subsequent
time frames of faulty machines is done until resulting fault is observed in one or more
primary outputs. Fault is captured on the data line and simulated to the primary output
using test sequences similar to stuck-at faults. Since their scheme uses a unit delay
for gates, critical timing conditions will change according to physical conditions or
practical differences such as temperature or variations of delay time for each gate.
They have used all combinations of coupling faults, and test vectors are also random
vectors. Excessive time is required to simulate most of the benchmark circuits.
A simple update of this simulator with modifications suitable for crosstalk fault
diagnosis tool is described in Takahashi et al. (2001). A hold time is introduced to
determine the value that is captured in the flip-flop. The method compares observed
responses and simulated outputs at primary outputs to locate an actual fault. If the
simulated output and observed responses are the same, then the simulated fault is
added to the list of suspected faults. Suspected faults are a list of faults which are
consistent with the observed responses of the circuit. If not, simulated fault is removed
from set of suspected faults. In order to reduce CPU time, they have used stored state
information of previous time frames to calculate primary output values of present
time frame. The CPU time is still high for most of the benchmark circuits
The limitations of the above simulators are alleviated by Phadoongsidhi et al.
(2002) who have proposed a concurrent simulation technique for detection of
crosstalk-induced pulse faults. Gates are assumed to have unit delay. Each node in
a circuit has a 32-bit buffer which stores values for fault-free simulation and values
of faulty simulation. Hence, multiple faults are concurrently processed in each time
frame, and faulty machines could be dropped and added at any time during the course
of simulation. But then memory is very high. Further, the large number of crosstalk
faults took a large amount of CPU time. Vectors provided by FASTEST are used
for generating test sequences. Thus, their simulation algorithm leads to a significant
reduction in simulation time with higher memory consumption as a trade-off.
Itazaki et al. (1997b) have proposed a combined algorithmic test generator with
the fault simulator for crosstalk faults. They have used FASTEST as the base test
generation algorithm to generate the setup and propagation patterns. In order to check
the validity of patterns, logic simulation is performed for the propagation pattern
generated by FASTEST. However, they have not considered multiple aggressors.
The fault coverage is also very low.
Phadoongsidhi and Saluja (2003) have proposed a fault simulation method based
on event-driven simulation. All the papers discussed above have logic waveform sen-
sitization on each line which is computationally complex and results in more memory
usage. Hence, in their work logic event-driven simulation is extended for fault exci-
tation and fault grouping. Events lists are separated according to the direction of
transition. Good circuit simulation is done, and candidate fault group is formed by
determining the victim aggressors which satisfy a set of transformation rules and
which are able to cause capturing of a faulty value at the output of victim flip-flop.
Faults from candidate fault group are simulated, and faults are said to be detected
if there exists at least one primary output at which good and faulty machines have
different values. But since the test vectors generated were by FASTEST and HITEC,
the fault coverage was less and CPU time was still high.
3.4 Test Generation Techniques for Crosstalk Delay Faults
Many automatic test generation algorithms are developed for generating tests for
crosstalk faults. The objective of test generation for crosstalk fault is to generate a two-
vector pair that should be applied to the primary input of integrated circuit to identify
the faults that affect the functionality of the device due to fast signal transitions in the
adjacent interconnects. The two vectors can be generated separately, or a multiple
logic system may be used such that the two vectors can be derived concurrently
with a single copy of the circuit. When the two vectors are generated separately,
three-valued logic systems can be used. If two vectors are to be generated together,
a multiple-valued system can be used to represent values over two vectors.
Both deterministic and simulation-based algorithms have been proposed for test-
ing crosstalk delay faults. Deterministic test generators produce tests by processing a
model of the circuit. This model is the structural model of the design. The structural
test generation algorithms employ heuristics to guide the search space.
Simulation-based techniques normally involve generation of random vectors and
employ the results provided by the fault simulator to investigate the search space.
Simulation-based test generation has been used to avoid long execution times of deter-
ministic algorithms and to lessen the complexity of test generation. Test generation
time can be decreased using efficient fault simulators. Simulation-based technique
can generate test for any circuit and any type of fault that can be simulated. Circuit
timing can be taken into account. The disadvantage of this method is that it is not
capable of identifying redundant or untestable faults. Another problem was in finding
good heuristics to generate test vectors, and the test sets generated were much larger.
3.4.1 Deterministic Algorithms
In most of the approaches, a modified version of PODEM algorithm is used for

backtracing and sensitizing the path for propagation of fault effect to the primary
output. Almost all the approaches use multi-valued logic.
3.4 Test Generation Techniques for Crosstalk Delay Faults 47
The mixed signal test generation algorithm developed by Chen et al. (1999) uses
analytical models for timing analysis to find the target crosstalk faults. Before pro-
cessing the test generation objectives for victim and aggressor, a timing-oriented
backtrace is performed to check for compatible patterns at the gate inputs which
create single transition within the specific timing windows. An eleven-valued logic
is used. A branch-and-bound technique was proposed to reduce the search space as
the algorithm implicitly explores all primary input combinations. Test vectors were
generated for both types of capacitive coupling crosstalk noise, namely crosstalk
pulse and crosstalk delay. However, this approach only generates patterns for a single
aggressor affecting a target path. So it cannot propagate a maximal crosstalk-induced
effect on a critical path. Further, their method was computationally complex.
The same test generator is enhanced as XGEN by Chen et al. (2002b) which uses
the same analytical models described in Sect. 1.5 for timing analysis and backtrace.
Additionally, a cost function is evaluated that can guide the search for primary input
assignments and as well as find a path from victim to primary output. The cost
function consists of digital and analog part. In the digital part, controllability and
observability measures are used to decide the paths. The analog part consists of mea-
surement of gate strength, transistor gain, and load capacitance. The calculation of
cost starts with primary output and traverse backward. The path chosen for propagat-
ing the noise delay has the lowest cost. But the authors have manually selected pairs
of target faults. The entire fault universe was not taken into consideration. Only about
100 faults were selected for finding the efficiency of the test generation algorithm.
In the enhanced version of XGEN suggested by Sinha et al. (2003), the propa-
gating conditions were increased by including hazardous and non-hazardous values
in the multi-valued logic. The method is computationally intensive. Hence, the test
generation time is very high, and fault coverage increased only marginally.
Sinha et al. (2008) have further enhanced their previous test generator by deriving
a new fifty-seven-valued algebra. The modified ATPG procedure increases the fault
coverage and proves more faults as being untestable. The method considers single
element values called basis values, as well as many composite values made of multiple
basis values. The assignment of a composite value to a circuit node indicates that
any of the basis values comprising the composite value was possible. The use of
composite values allows their ATPG method to postpone making a decision until
one was absolutely necessary. This makes the search for a test pattern more efficient
as it reduces backtracking by reducing the number of assignments that cause conflicts.
The disadvantage of this method is that the test generation time is high. Further, the
algorithm has considered only a single pair of victim line and aggressor line and
hence cannot propagate a maximal crosstalk-induced effect along a critical victim
path, which is more likely to cause delay test failure.
A test pattern generation based on waveform sensitization is developed by Li et al.
(2003) in which the signal on each line is assumed to be a waveform that consists
of multiple transitions at different times. Static hazards and dynamic hazards are
implied in waveforms. Nine-valued logic was used. For the fault to be propagated to
the primary output, two parts of the circuit have to be sensitized. One is the longest
path and the other is the subpath from the primary input to the aggressor line that is
coupled with the longest path. The longest paths and critical paths are sensitized, and
then, justification was done. Testing a path delay fault usually should not specify all
the primary input values. Hence, the unspecified primary input values can be used
to generate necessary inputs for crosstalk noises. But their fault coverage is very
low. Only single victim/single aggressor pairs were considered. Further waveform
sensitization method cannot generate tests for large benchmark circuits.
A hybrid structural SAT-based solution developed by Bai et al. (2003) is used
for multiple aggressor crosstalk problems. An implication graph is constructed that
consists of logic variables and structural information to check for logic conflicts. The
conflicts arise due to the values assigned to the victim lines, the aggressor’s lines, and
the propagation path. If a logic conflict occurs, the algorithm will repeatedly search
for the best subset of suitable aggressors based on weights assigned to aggressors.
Once a set of aggressors are identified, a modified version of PODEM algorithm was
used to generate test vectors that can justify the required logic value for the victim,
activate the aggressors, and sensitize a propagation path for the fault to be propagated
to the primary output.
Shen et al. (2005) have proposed a non-robust test generation for crosstalk delay
faults based on S-PCPDF model explained in Sect. 1.5. Using static timing analysis,
a set of crosstalk delay faults is derived. The non-robust path delay test generation
was modified to generate tests for crosstalk delay faults.
Li and Li (2005) have suggested a test generation for crosstalk delay faults based
on S-PCPDF model. A path delay conventional ATPG is enhanced to generate tests
for crosstalk delay faults by adding constraints in the sub-paths. The number of target
faults is reduced by two ways: one is based on constraints for on-path inputs and
another based on prespecified states during generation of critical paths.
Li et al. (2006) have proposed a robust test generation technique based on a single
precise crosstalk-induced path delay fault model, S-PCPDF model. A ten-valued
logic is used in test pattern generation. Fanout-weighted delay model is used for
experimental evaluation. However, this approach only generates patterns for a single
aggressor affecting a target path. So it cannot propagate a maximal crosstalk-induced
effect on a critical path. Further, the algorithm is computationally complex.
An aggressor maximization algorithm is proposed by Aniket and Arunachalam
(2005) that maximizes the crosstalk effect by suitably activating the aggressors—vic-
tim pairs lying along any critical path. For a robust sensitizable path, the associated
multiple aggressors/victim pairs are activated in a manner that will maximize the
influence of the aggressor on the path to induce maximum crosstalk slowdown along
a path. In their algorithm, backtracing is considered successful only if the collective
crosstalk delay effects of the activated aggressor lines were greater than the collec-
tive delay effects of the deactivated aggressor lines. If the backtrace was successful,
then the primary input assignment is accepted. The results obtained for benchmark
circuits show that if their aggressor maximization algorithm is integrated into the test
generation algorithm, the total crosstalk induced slowdown and speedup increase and
decrease, respectively, for all the circuits. However, static timing analysis procedure
used in their work does not use timing information.
An ATPG in which a stuck-at fault ATPG is combined with a 0–1 integer linear
program (ILP) for zero gate delay is developed by Ganeshpure and Kundu (2007b).
The maximal aggressor activation is formulated as a linear programming problem,
while the fault effect propagation was treated as an ATPG problem. The prob-
lems are separated by min-cut circuit partitioning technique. Single victim/multiple
aggressors were considered. Both the logic circuit and the maximal aggressor weight
equations were represented as ILP equations. Then, an ILP solver was used to solve
simultaneous logic constraints for maximal aggressor switching requirement. The
test generator was enhanced to incorporate integer gate delays Ganeshpure and
Kundu (2007a). However, the selection of crosstalk faults is random.
Palit et al. (2008) have developed a test generator for crosstalk delay faults where
the test patterns were generated to activate both aggressor and victim individually
and to propagate the crosstalk effect to at least one primary output. For example, if a
0 to 1 transition is required at aggressor line, vectors were derived for exciting both
logic 0 and 1 separately. Once the vectors are derived for victims, aggressors, and
propagation paths, the common vectors were collected separately before transition
and after transition. Combining the vectors gave the transition test vector for crosstalk
delay fault. The randomly chosen faults were manually injected into the circuit using
Xilinx simulator. But the problem is collecting common transition vector to excite
all aggressors concurrently was impossible.
A test pattern generation procedure that combines path delay and transition delay
fault test pattern generation using test points on nearby nets is suggested by Lee and
Tehranipoor (2008). The test generation algorithm increases the crosstalk effects on
delay sensitive paths by producing transitions in adjacent wires which are identified
using the parasitic information derived from the layout. The set of final vectors
generated for each delay sensitive path is compressed using a compaction scheme.
These vectors increase the switching activity on the adjacent wires.
Chun et al. (2009) have proposed a test generation method for crosstalk-induced
delay effects, where multiple aggressor crosstalk faults were considered to maximize
the noise of the victim line. The proposed algorithm uses parasitic information, such
as coupling capacitance between a victim and an aggressor, and static timing windows
to reduce many false aggressors and handle multiple possible aggressors coupled to
a victim lying along a path. A conventional path delay ATPG was used to generate
the test patterns, and don’t care values in the test patterns were given appropriate
values to activate more number of aggressors to produce maximum crosstalk effect
at the output. Hence, the test generation algorithm can reduce the search space of the
backward implication of the aggressor’s constraints, thus reducing time.
Hasan et al. (2010) have proposed an ATPG for detecting both crosstalk glitches
and crosstalk-induced delay faults. Generated test patterns were compressed using
pattern matching and fault chaining algorithms. Test patterns were generated by con-
sidering the coupling capacitance, timing, and functional incompatibilities between
the victim and aggressor nodes.
Zhang et al. (2011) have proposed a path delay test generation method for crosstalk
delay effects. They have used a crosstalk-induced path delay fault model. The critical
paths are identified by transition map-based timing analysis instead of timing window.
The rise and fall transitions are characterized by two transition maps. Each transition
map was expressed as a bitmap structure, in which a bit denotes a time area. The
arrival time of the signals was recorded in the two transition maps. The target crosstalk
faults were selected by overlapping analysis between transition maps of aggressor
lines and victim lines. Then, a deterministic method is used to generate the robust
test patterns for crosstalk delay faults.
A modified FAN out-Oriented (FAN)-based deterministic algorithm is proposed
by Jayanthy et al. (2012) for test generation of crosstalk delay faults. Seven-valued
logic system has been used. Static timing analysis is used to derive a set of target
crosstalk delay faults. The results obtained using modified FAN-based ATPG give a
better fault coverage with reduced number of transitions for almost all the benchmarks
compared to results obtained using modified PODEM-based ATPG. The number of
backtraces is reduced in FAN-based ATPG, and hence, the CPU execution time of
modified FAN-based ATPG is also less compared to modified PODEM-based ATPG.
3.4.2 Simulation-Based Test Generation
A genetic algorithm-based test generation for crosstalk-induced faults has been pro-
posed by Krstic et al. (2001). The constrained path delay faults are derived by statis-
tical timing analysis. The genetic algorithm generates test that not only sensitizes the
target path but also produces large crosstalk delay by producing required transitions
on the identified coupled interconnects. However, the test generation time is high.
Sathe and Bushnell (2002) have developed a simulation-based test generation for
crosstalk-induced delay faults. A crosstalk candidate reduction algorithm is used
to get a set of target crosstalk delay faults by filtering out redundant faults. 10000
random test vectors are used for all the benchmark circuits to simulate the faults.
2000 vectors were simulated at a time, and five passes of random vector generation
and compaction were run. The fault simulator was a multiple-delay fault simulator in
which gates are assigned a rise delay and fall delay. A fanout-weighted delay model
was used for the propagation delay. An analog macro-model was developed to get the
required delay to be injected into the digital fault simulator. But the fault coverage
obtained is very less.
A delay fault generator was developed to generate delay fault tests for both resis-
tive and capacitive crosstalk delay faults (Chary and Bushnell 2006). The fault model
is layout dependent. A circuit extractor is used for parasitic extraction. The crosstalk
delay fault is generated from the parasitic capacitance between interconnect pairs.
The bridging fault is generated from the resistance between the interconnect pairs.
The set of target crosstalk delay faults and resistive bridging faults were got by using
reduction algorithms. Simulator used was a multiple-delay fault simulator. But the
disadvantage was that random test vectors are used which necessarily do not acti-
vate the worst case noise effects. Further single aggressor/victim fault is taken into
consideration.
A crosstalk delay fault simulator for sequential circuits is developed by modifying

the basic time wheel-based event-driven simulator (Phadoongsidhi and Saluja 2005).
The event-driven simulator is modified to activate, inject, and propagate crosstalk
delay faults to the primary output. The simulator handles single victim/multiple
aggressors. Gates are assumed to have a unit delay, and the crosstalk-induced delay
value to be injected is also assumed to be one. For small circuits, the input fault list
consists of every combination of victim/aggressor pair. The input test vectors were
generated using HITEC (Niermann and Patel 1991) and the FASTEST, which were
shorter test sequences. Hence, the fault coverage obtained is relatively low.
All the above works on simulation-based test generation are ad hoc with numer-
ous heuristics. There is no underlying well-defined algorithmic framework for
simulation-based test generation such as genetic algorithm or simulated annealing
for generating tests for crosstalk delay faults.
A simulation-based test pattern generator based on optimization algorithms,
namely single-objective genetic algorithm (Jayanthy and Bhuvaneswari 2011a) and
multi-objective genetic algorithm (Jayanthy and Bhuvaneswari 2011b) which is used
for detecting crosstalk delay faults for combinational, enhanced scan version of
sequential circuits, was proposed and developed. Better fault coverage with lower
transition times is obtained using these algorithms.
3.5 Delay Testing of Asynchronous Sequential Circuits
Due to their many benefits, asynchronous systems are viewed as an alternative to

purely synchronous systems. Asynchronous circuits have high-performance gains
and low power when compared to their synchronous counterparts. But the testing
of asynchronous circuits is a difficult task because of the following two reasons: (i)
absence of global clock and (ii) the correct operation of asynchronous circuits which
is obtained by introducing redundancies, that is, by sacrificing testability (Ghavami
et al. 2009).
The types of error to be tested in asynchronous circuits are stuck-at fault errors
and delay faults. The latter can disrupt proper operation of the circuit. The problem
with asynchronous test generation is that the test patterns must guarantee not only
that the deterministic fault effect is captured correctly, but also that the fault effect
is not overwritten and does not disappear during the subsequent operations. This
complicates the fault simulation and automatic test pattern generation processes
significantly.
Kishinevsky et al. (1998) have shown that delay testing of asynchronous circuits
can be reduced to a problem of test pattern generation for a related combinational
circuit. The first step was to find all the global feedback loops and to convert asyn-
chronous circuit into an asynchronous net. An asynchronous net consists of only
local feedback loops, simple gates, and latches. Then, a set of equations is formu-
lated to find paths whose delay was within the permissible limits. Initialization of
asynchronous net was done by converting it into an iterative combinational array
with initial values if pseudo-primary inputs are assumed to be don’t cares. Then, a
robust path delay fault testing similar to that of combinational circuit testing is used
to generate test vectors for path delay faults.
Sur-Kolay et al. (2000) have designed a serial fault simulator for testing gate delay
faults and transition faults in asynchronous circuits. They have used min-max tim-
ing analysis to compute the bounds on signal delays. The asynchronous circuit was
unfolded into time frames, and the unfolded circuit is simulated. Fundamental mode
of operation is assumed. Identification of frame boundaries involves breaking feed-
back loops. The feedback algorithm uses depth-first search approach. Simulations
are done frame after frame. Initially, the feedback inputs are set to logic 0. When
initialized, the current frame was simulated using min-max timing analysis and using
the first test vector as primary input values. When the primary output results become
stable, the pseudo-primary outputs are given as pseudo-primary inputs for the next
time frame. For a gate delay fault, the time stamps for the primary output signals at
the end of each time frame are checked to see if the minimum delay bound is lower
than the corresponding maximum bound for the fault-free simulation.
A design for test technique is developed by Shi et al. (2006) for testing delay
faults in asynchronous handshake circuits. There are two types of delay faults in
handshake circuits, one that occurs in the control block which causes performance
degradation and the other one which occurs in the data path which causes logic errors.
A multiplexer-based full-scan method is suggested for testing these delay faults in
asynchronous handshake circuits.
Favalli (2005) has proposed fuzzy model for path delay fault detection. The delay
faults are modeled using a path delay fault model. Non-robust testing is used to
detect delay faults. A fuzzy delay model was used to find the quality of non-robust
tests by finding the number of gates featuring robust test conditions, the timing of
the gates not satisfying robust test conditions, and the paths ability to propagate the
effects of a transition under non-robust conditions. Monte Carlo simulation was used
to evaluate test pairs which detect delay faults, and this data was compared with
the ranking obtained from fuzzy model implemented in a path delay fault simulator.
The results obtained for combinational circuits have shown that fuzzy delay for
non-robust detection of delay faults is more accurate.
An ATPG based on multi-objective genetic algorithm for testing crosstalk delay
faults in asynchronous sequential circuits has been proposed and developed by
Jayanthy et al. (2013). The asynchronous circuit is unfolded into time frames,
and the unfolded circuit is simulated. Fundamental mode of operation is assumed.
Identification of frame boundaries involves breaking feedback loops. A fuzzy delay
model is used to model the gate delay (Jayanthy and Bhuvaneswari 2015). A multi-
objective non-dominated sorting genetic algorithm (NSGA-II) is used for generating
optimized test patterns for testing crosstalk delay faults in asynchronous sequential
circuit. Two objectives, fault coverage and power consumption, are simultaneously
optimized using these algorithms. The experimental results obtained demonstrate
that the NSGA-II-based ATPG with redundancy is effective in providing a better fault
coverage and minimum power dissipation for most of the SIS benchmark circuits.
3.6 Conclusion 53
3.6 Conclusion
Deterministic and simulation-based test generation algorithms for both crosstalk

pulses and delays are discussed. Finally, delay testing of asynchronous circuits is
discussed, and a multi-objective genetic algorithm for crosstalk delay testing of
asynchronous circuits is proposed.
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Chapter 4
An Automatic Test Generation Method
for Crosstalk Delay Faults Using
Modified FAN Algorithm
4.1 Introduction
Many automatic test generation algorithms are developed for generating tests for
crosstalk delay faults. Both deterministic (Chen et al. 2002; Sinha et al. 2008;
Chun et al. 2009) and simulation-based algorithms (Sathe and Bushnell 2002) have
been proposed. Experiments have shown that in some circuits, the simulation-based
approach gave better results than the deterministic methods, while in other circuits the
performance of the deterministic algorithms was better. Deterministic algorithms are
effective in deriving tests for control dominant circuits and in identifying untestable
faults. For data-dominant circuits, the simulation-based algorithms were much effec-
tive (Saab et al. 1992; Srinivas and Patnaik 1993; Rudnick and Greenstein 1997).
Deterministic test generators produce tests by processing the model of the circuit.
The model is typically the structural or symbolic model of the design. Typical steps
in a deterministic test generation algorithm are fault excitation, fault propagation
to the primary output, and state justification through time processing (Hsiao et al.
1996). The complexity of test generation for crosstalk delay faults is rather high due
to the multiple objectives that are to be satisfied. Most of the deterministic test gener-
ators for crosstalk delay faults are based on modified path-oriented decision-making
algorithm (PODEM)-based (Goel 1996) test generation which is run as the core to
obtain a two-vector test in combinational circuits by forcing values to the victim and
aggressor nodes and propagating the possible delay to the primary output nodes.
In this chapter, an automatic test generation algorithm based on modified FAN
for crosstalk delay faults is proposed. The first section of this chapter presents static
timing analysis to derive a set of target crosstalk delay faults. Signal values used in
test generation are defined. The test generation algorithm based on modified PODEM
is presented followed by the discussion on the proposed modified FAN-based test
generation algorithm. The effectiveness of the proposed approach is demonstrated
by experimental results on combinational and enhanced scan version of sequential
circuits.

58 4 An Automatic Test Generation Method …
4.2 Static Timing Analysis
Static timing analysis is one of the techniques available to verify the timing of a digital
design. It is faster and simpler way of checking and analyzing all the timing paths in
a design for timing violations. The analysis of the design is carried out statically and
does not depend upon the data values applied at the input pins. One other approach
of verifying timing is based on timing simulation but it cannot handle the effects of
crosstalk, noise and on-chip variations. In this research work, static timing analysis
is used at gate level for digital circuits to derive a list of target faults caused due to
crosstalk delay effects.
A crosstalk delay fault is caused between an aggressor line denoted as A-line and
victim line denoted as V-line. A crosstalk delay fault is induced in the V-line during
a test when the necessary signal changes occur in A-line. The numbers of crosstalk
faults between all possible combinations of A-lines and V-lines in a digital VLSI
circuit are very large and impractical to detect for large complex circuits. Therefore,
static timing analysis is used to get a reduced set of crosstalk delay faults. In order
to obtain a reduced list of crosstalk delay faults, classes of false crosstalk faults that
need not be tested have to be identified and should not be included in the target fault
list.
The static timing analysis used in this research work uses logical-level imple-
mentation of the circuit and does not require layout information (Takahashi et al.
2005). Using both the topological and timing information of digital circuits, static
timing analysis derives a set of target crosstalk delay faults. This method without
using layout information is more amenable to the time to market need of the designs.
4.2.1 Identification of Target Crosstalk Faults
The entire paths in the circuit are analyzed using the tree data structure. The total
number of paths in the circuit is calculated using depth-first search algorithm which
employs recursive search procedure. From the total number of paths, a set of critical
paths whose delay is the largest of all the paths in the circuit is found. The victim
lines are lines that lie on the critical path. The selection of critical paths, number of
victims in the critical path, and the total number of target crosstalk delay faults found
using static timing analysis are described in the procedure given below.
The procedure for finding target crosstalk faults consists of two phases. In the
first phase, the earliest transition time and latest transition time of each line are
calculated. By using this information, the longest paths (critical paths) are found.
From the critical paths, the set of victim lines is derived. In the second phase, the
procedure determines whether the timing window of victim line overlaps with the
timing window of the aggressor line (Jayanthy et al. 2013). The conditions for victim
and aggressor to form a crosstalk target fault are:
4.2 Static Timing Analysis 59
• The victims should lie in the longest path.

• The relationship between transition time at the victim line Tvic and transition time
at the aggressor line Tagg should satisfy the inequality Tvic − τ ≤ Tagg ≤ Tvic + τ
where value of τ is assumed to be 1 unit delay. The transitions are limited to timing
window τ to cause slowdown on the V-line.
Phase 1
Step 1: For each line in the circuit, the latest transition time and earliest transition
time are calculated. Latest transition time at a line is the maximum delay on any path
from any primary input. The latest transition time for line L is calculated recursively
as follows.
• If line L is a primary input or pseudo-primary input.

Latest transition time for L one unit delay.
• If L is an output of a gate G having n inputs I 1 , I 2 , I 3 …I n .
Latest transition time for L MAX {latest transition time for I j , j 1, 2,…, n} +
delay of the gate.
• If line L is a fanout branch.
Latest transition time for L latest transition time for the fanout stem.
Earliest transition time at a line is the minimum delay on any path from any primary
input. The earliest transition time for line L is calculated recursively as follows.
• If line L is a primary input or pseudo-primary input.

Earliest transition time for L one unit delay.
• If L is an output of a gate G having n inputs I 1 , I 2 , I 3 …I n
Earliest transition time for L MIN {earliest transition time for I j , j 1, 2,…,
n} + delay of the gate.
• If line L is a fanout branch
Earliest transition time for L earliest transition time for the fanout stem.
The earliest transition time and latest transition time of all the lines are calculated.
Step 2: Using the maximum value of the latest transition time, the longest paths in
the circuit are identified.
Step 3: Every primary input or pseudo-primary input or gate outputs in the longest
path are the victims. The lines in the longest path form the set of victim lines.
Phase 2
Step 1: A V-line from the set of victim lines is selected. The timing windows of
victim and aggressor lines are calculated. The A-line has a timing window of [earliest
transition time, latest transition time]. The timing window of V-line is calculated as
[latest transition time − τ unit delays, latest transition time + τ unit delays].
1[1, 1]
22[3, 4]
10[2, 2]
2[1, 1]
3[1, 1] 16[2, 3]
6[1, 1] 11[2,2]
7[1, 1] 23[3, 4]
19[2, 3]
Fig. 4.1 Example circuit c17
Step 2: The timing window of the selected V-line is compared with timing windows
of A-lines. Aggressor’s lines are other primary inputs or gate outputs. If the timing
windows of V-line overlap with the timing window of a particular A-line, then the
crosstalk-induced transition fault caused by the selected (A-line, V-line) pair is added
to the target crosstalk fault list. The method is illustrated by using the circuit c17 as
shown in Fig. 4.1.
Phase 1 for Example Circuit C17
The earliest and latest transition times for each line in circuit c17 as indicated by line
number [earliest transition time, latest transition time] are shown in Fig. 4.1. The
longest paths for c17 circuit are indicated by bold lines in Fig. 4.1. The victims in
the longest path form a set [3, 6, 11, 16, 19, 22, and 23].
Phase 2 for Example Circuit C17
Select V-line 3 from the victim set. Victim 3 is compared with A-line 1. The timing
window of 1 (earliest transition time 1, latest transition time 1) overlaps with
the timing window of 3 (latest transition time − 1= 0, latest transition time + 1 2).
Hence (3, 1) form a target crosstalk fault. Considering the pair (3, 22), the timing
window of 3 (0, 2) does not overlap with timing window of 22 (3, 4). Hence (3, 22)
form a false crosstalk fault and hence should not be included in the target fault list
(Bhuvaneswari and Jayanthy 2015).
The number of target crosstalk faults for benchmark circuit c17 is 42. The input
fault list for the test generator is the reduced set of crosstalk faults.
4.3 Seven-Valued Logic
The objective of test generation for crosstalk delay fault is to generate a two-vector
pair that should be applied to the primary input of fabricated IC to detect the delay
4.3 Seven-Valued Logic 61
faults caused due to crosstalk. The two vectors can be generated separately, or a
different logic system may be used such that the two vectors can be derived simul-
taneously with a single copy of the circuit. When the two vectors are generated
separately, three-valued logic is used where value of each signal will be 0, 1, or X. If
two vectors are to be generated together, a value system different from the three values
system can be used to represent values over two vectors. Seven-valued logic system
has been used in this research work. S0 and S1 are signal values which represent
steady logic ‘0’ and steady logic ‘1’ in the first and second test vectors, respectively.
T0 represents logic ‘1’ in the first test vector and logic ‘0’ in the second test vector.
T1 represents logic ‘0’ in the first test vector and logic ‘1’ in the second test vector.
P0 represents the signal value which is logic ‘0’ in the first test vector and becomes
logic ‘1’ at the beginning of the second test vector because of the crosstalk fault and
goes back to logic ‘0’ after a definite time. P1 is reverse of P0. The different signals
in the seven-valued logic are shown in Table 4.1 (Aniket and Arunachalam 2005).
Tables 4.2 and 4.3 show the truth tables for 2 input AND and OR gates, respectively.
Similar tables can be derived for NAND, NOR, and XOR gates.
Table 4.1 Seven-valued Signal Description

logic
S0 Steady 0
S1 Steady 1
T1 Rising transition
T0 Falling transition
P0 Glitch on a 0 signal
P1 Glitch on a 1 signal
X Unknown value
Table 4.2 AND gate truth AND S0 S1 T0 T1 P0 P1 X

table
S0 S0 S0 S0 S0 S0 S0 S0
S1 S0 S1 T0 T1 P0 P1 X
T0 S0 T0 T0 P0 P0 T0 X
T1 S0 T1 P0 T1 P0 T1 X
P0 S0 P0 P0 P0 P0 P0 X
P1 S0 P1 T0 T1 P0 P1 X
X S0 X X X X X X
Table 4.3 OR gate truth table

OR S0 S1 T0 T1 P0 P1 X
S0 S0 S1 T0 T1 P0 P1 X
S1 S1 S1 S1 S1 S1 S1 S1
T0 T0 S1 T0 P1 T0 P1 X
T1 T1 S1 P1 T1 T1 P1 X
P0 P0 S1 T0 T1 P0 P1 X
P1 P1 P1 P1 P1 P1 P1 X
X X S1 X X X X X
Note Tables 4.1, 4.2, and 4.3 reprinted from Article ID 745861, Jayanthy et al. (2012), with per-
mission from M/s Hindavi Publishing Corporation
4.4 Procedure for Modified PODEM-Based Test

Generation
The fundamental steps in generating a test for a fault in fault-oriented test generation
algorithm are:
• Activate the fault: This is a line justification problem which deals with finding an
assignment of primary input values those results in a desired value on specified
node of the circuit. It is a recursive process in which a value of a gate output is
justified by values of the gate inputs until primary inputs are reached.
• Propagate the resulting error to the primary output: To propagate the error to the
primary output, the path from that node to the primary output needs to be sensitized.
The error propagation problem is transferred to line justification problem.
PODEM (Goel 1996), a test generation algorithm for stuck-at faults, is characterized
by a direct search process, in which decisions consist only of primary inputs. PODEM
treats a value to be justified for a node as an objective to be achieved via primary input
assignments. Values are assigned only by simulating primary input assignments.
For test generation of crosstalk delay faults, PODEM algorithm is used, similar to
stuck-at fault test generation for activating the crosstalk delay fault and sensitizing
the path for propagation of fault effect to the primary output. But in case of test
generation for crosstalk delay faults, for each crosstalk delay fault to be detected,
multiple objectives have to be satisfied. The primary objectives in creating a crosstalk-
induced delay fault are:
Objective 1: A rising transition or falling transition in the victim line.
Objective 2: A transition in the aggressor lines opposite to that of the victim line to
create a slowdown effect.
Objective 3: Setting the off-path inputs along the target path to suitable logic values
in order to propagate the transition in the victim line to the primary output. The path
chosen for propagation is the path with the longest path delay from current site to
the primary output.
4.4 Procedure for Modified PODEM-Based Test Generation 63
The first step in PODEM for generating tests for stuck-at faults is to excite the fault,
that is, target fault is set opposite to stuck value. For crosstalk delay faults, PODEM
has to excite both victim and aggressors for opposite transitions. Since transitions
have to be set on the victim node and aggressor nodes, two vectors have to be gener-
ated. In this research work, a multi-valued logic where two vectors are represented
by a single variable is used. For stuck-at fault, the excited fault is propagated from
the fault site to primary output along the best path. The path which can easily be
sensitizable is taken as best path. In case of crosstalk delay fault, the path chosen
is the longest path from the fault site to primary output. That longest path has to
be sensitizable. Backtracing to primary inputs and reversing decisions in case of
conflicts are similar to stuck-at faults. For stuck-at faults, conflicts occur between
the target fault and the propagation path objectives. In crosstalk delay fault, conflicts
occur between victim, activated aggressors, and on-path objectives.
The conditions used to set the off-path sensitizing inputs are as follows:
• If the transition at the gate input along the path has a controlling to non-controlling
transition value, any of the three values are allowed at the side inputs: a static non-
controlling value, a controlling to non-controlling transition and glitch.
• If the transition at the gate input along the path has a non-controlling to controlling
transition value, any of the three values are allowed at the side inputs: a static
controlling value, a non-controlling to controlling transition, and glitch.
The focus is on combinational and enhanced scan version of sequential circuits whose
inputs are primary inputs or pseudo-primary inputs and outputs are primary outputs
or pseudo-primary outputs.
The pseudo-code for modified PODEM-based test generation algorithm is shown
in Fig. 4.2. The input to the test generator is the target fault list derived from static
timing analysis. A single victim and multiple aggressors associated with the victim
are taken from the fault list. Desired values on the victim line and aggressor lines
are set to excite the crosstalk delay fault. From timing analysis of the circuit, the
longest path from the victim node to a primary output is selected to propagate the
fault. The off-path inputs along the target path are then set to suitable logic values.
The remaining lines are set to logic value X. Since multiple objectives have to be
satisfied, the objectives are first checked for contradiction because objectives have
local conflict with other objectives. Then, the aggressors which cause the conflict are
removed from the objective list. The victim is propagated along the chosen target
path. During the propagation phase, if there is a conflict between the victim objective
and on-path objective, then the next longest path is considered until all longest paths
are tried. If there is a conflict between the aggressors and other objectives, then the
aggressors which cause the conflict are removed from the objective list. The final list
of objectives is obtained. If all aggressors are removed, then test is not possible and
the next target fault is chosen.
The final objectives are extracted one by one from the objective list, and a modified
PODEM algorithm is used to search for vectors justifying the multiple objectives.
Each objective is backtraced. Backtrace will search and return an unassigned primary
input variable. Primary input is assigned a logic value. Simulation is done, and if
Test generation (Fault list)

begin
do
select victim/aggressors from fault list
Set primary objectives ( ); /*find all the primary objectives to be justified*/
set all other lines to X
if (there is conflict between two or more objectives on
the fan-out branches of the same stem) then
begin
drop the aggressor objectives;
if (all aggressors objectives dropped)
begin
then test not possible
exit
end
end
Imply ( ) /*with respect to the victim and other inputs*/
Propagate ( ) /*Propagate the victim along the chosen target path*/
if( there is conflict between the implied values and on path objectives) then
begin
drop the target path
if (all paths dropped) then
begin
test not possible
exit ( )
end
end
else ( there is conflict between the implied values and aggressors)
begin
if (all aggressor objectives dropped) then
begin
test not possible
exit ( )
end
end
do
remove one entry from the current objective
Backtrace ( )/*backtrace to primary inputs*/
Imply ( );
Success=Imply ()
if (success==0)
Reverse decision
Back trace ()
while (current objective count! =0)
Propagate ( )/*check if fault detected at primary output*/
if(fault detected )then fault count --
while (fault count!=0)
end
Fig. 4.2 Pseudo-code for modified PODEM-based test generation algorithm for crosstalk delay
faults
4.4 Procedure for Modified PODEM-Based Test Generation 65
there is a conflict with earlier assignment, reversal of decision is done at the primary
input till all the objectives are satisfied. The unassigned primary inputs are assigned
static values S0 and S1. Finally, the assigned primary inputs are propagated to the
primary output.
If fault effect is detected at the primary output, the victim/aggressor pairs are
removed from the target list and fault count is decremented. The procedure is repeated
until target fault list is empty. The primary inputs are assigned only S0, S1, RT, and
FT. All gates are assumed to have zero delay.
4.5 Procedure for Modified FAN-Based Test Generation
In test generation for crosstalk delay fault, the number of objectives to be satisfied is
larger compared to test generation of stuck-at faults. PODEM targets one objective
at a time. Hence, the decision process may sometimes be too localized and miss
the global picture. Hence, a modified FAN algorithm is used for test generation for
crosstalk delay faults. The multiple backtrace procedure adopted in FAN algorithm
concurrently traces more than one path and is more efficient than the backtrace along a
single path. In PODEM, the assignments are done at the primary inputs which results
in excessive decision points. In FAN algorithm, the assignment is done at the fanout
points, and hence, in case of contradiction, fruitless computation is avoided. Hence,
the number of backtraces is reduced. Therefore, test generation will be relatively
faster compared to PODEM-based test generation.
The FAN algorithm (Fujiwara and Shimono 1980) introduces two extensions to
the backtracing concept of PODEM.
• Backtracing in FAN stops at internal fanout lines, rather at the primary inputs.
• FAN uses multiple backtrace procedure that attempts to simultaneously satisfy a
set of multiple objectives.
The pseudo-code for modified FAN-based test generation algorithm is shown in
Fig. 4.3. The steps in the algorithm are explained below.
The final list of objectives is obtained as described in Sect. 4.4 for PODEM-based
ATPG. The multiple backtrace procedure which is the most important aspect of the
algorithm is applied to backtrace from primary outputs toward primary inputs in a
breadth-first manner to satisfy the multiple primary objectives.
The multiple backtrace returns values for primary inputs. The unassigned primary
inputs are assigned static values S0 and S1. The assigned primary inputs are propa-
gated to the primary output to find if a delay effect is observed. If delay is observed
at the primary output, the victim/aggressor pairs are removed from the target list.
The procedure is repeated until target fault list is empty.
The pseudo-code for multiple backtrace of modified FAN-based generation algo-
rithm is shown in Fig. 4.4. In multiple backtrace procedure, highest level objectives
generate the next objective. Backtracing stops at the fanout point to check for con-
tradictions with the already assigned value and the required logic value. If conflict
Test generation (Fault list)

begin
do
select victim/aggressors from fault list
Set primary objectives ( ); /*find all the primary objectives to be justified*/
Set all other lines to X
if (there is conflict between two or more objectives on
the fan-out branches of the same stem) then
begin
if (all aggressors objectives dropped)
begin
then test not possible
exit
end
end
Imply ( ) /*with respect to the victim and other inputs*/
Propagate ( ) /*Propagate the victim along the chosen target path*/
/* A transition observability cost is computed for each longest path and longest path with
minimum observability cost is selected to propagate the crosstalk delay fault */
if( there is conflict between the implied values and on path
objectives) then
begin
drop the target path
if (all paths dropped) then
begin
test not possible
exit ( )
end
end
else ( there is conflict between the implied values and aggressors)
begin
if (all aggressor objectives dropped) then
begin
test not possible
exit ( )
end
end
Multiple back trace ( )
Unassigned primary inputs are assigned
Propagate ( );/*Propagate the delay in the victim along the target path*/
if (delay effect at PO)
test is found;
else
begin
no test possible
exit( )
end
end
end
end
Fig. 4.3 Pseudo-code for modified FAN-based test generation algorithm for crosstalk delay faults
(Note Figure 4.3 reprinted from Article ID 745861, Jayanthy et al. (2012), with permission from
M/s Hindavi Publishing Corporation)
4.5 Procedure for Modified FAN-Based Test Generation 67
occurs, the objective is pushed to the secondary stack. If there is no conflict, the
objective is moved to the primary stack. If it is not a fanout point, backtracing con-
tinues to generate the next objective. After current objectives are tried, objectives
from the primary stack are taken and assigned most requested value and multiple
backtrace is continued. The objectives in the secondary stack are tried after all the
objectives in the primary stack are tried. All possible values are considered for the
secondary stack objectives. If assignment is not possible, the aggressors which result
in contradiction are removed. Test is not possible if all aggressors are removed. If
assignment is possible, the objective is added to the current objective and multiple
backtrace continues.
In this algorithm, two stacks are used for test generation which has greater advan-
tage over the single stack and it reduces the number of backtraces for generating a
test. Since decision is made only at the fanout points rather than at primary inputs,
backtraces are further reduced.
4.6 Experimental Results
The test generation algorithm for crosstalk delay faults is tested on ISCAS’85 combi-
national circuits and several enhanced scan version of ISCAS’89 sequential circuits.
Tables 4.4 and 4.5 give the characteristics of ISCAS’85 combinational circuits and
the enhanced scan version of ISCAS’89 sequential circuits and ITC’99 benchmark
circuits. The number of primary inputs (PI), number of primary outputs (PO), num-
ber of gates, number of paths, number of critical paths, number of victims, and total
number of target faults corresponding to each circuit are given. The test generation
algorithm using modified FAN is implemented in INTEL core I7 processor with
2.6 GHz and 4 GB RAM using C language in Linux environment. Results were
compared with the results of modified PODEM-based ATPG, coded using C lan-
guage. Comparison is done for fault coverage, average number of backtraces, CPU
time, and total number of transitions for each circuit.
Fault coverage total number of faults detected/total number of target faults.
Average number of backtraces total number of backtraces/total number of paths.
Number of transitions transitions at the primary inputs + transitions at the gate
outputs.
A transition observability cost is computed for each longest path, and longest path
with minimum observability cost is selected to propagate the crosstalk delay fault.
First experimental results are observed without observability cost, and then, compar-
ison results including observability cost are given.
Table 4.6 gives the comparison between the percentage fault coverage for each
circuit for FAN-based ATPG with PODEM-based ATPG. The bold number represents
the maximum number of faults detected for each circuit. The average fault coverage
increases by 10.4% for FAN-based ATPG when compared to PODEM-based ATPG.
Multiple backtrace ( )
begin
repeat
begin
remove one entry from the current objective;
if( objective follows a fan out point) then
begin
if( there is a contradiction with a previously assigned value)
move the objective to a secondary stack

else
move the objective to a primary stack
else
begin
Continue tracing
Select an input of gate with value x
assign( )
add to the current objective
return multiple back trace
end
end
end
until current objectives ≠ null
if (primary stack objective ≠null)then
begin
remove the highest level objective
assign most requested value
return multiple back trace()
end
if( secondary stack objective ≠ null)
begin
remove the highest level objective
repeat
begin
assign value to the fan-out point
Imply( )
if (success)
begin
return multiple back trace( )
end
else
assign next value
end
until all values assigned
if(assignment not possible)
begin
Fig. 4.4 Pseudo-code for multiple backtrace of modified FAN-based test generation algorithm for
crosstalk delay faults (Note Figure 4.4 reprinted from Article ID 745861, Jayanthy et al. (2012),
with permission from M/s Hindavi Publishing Corporation)
4.6 Experimental Results 69
drop the aggressor objectives

if (all aggressor objectives dropped)then
begin
test not possible
Exit( )
end
end
end
end
Fig. 4.4 (continued)
Table 4.4 Characteristics of ISCAS’85 and enhanced scan version of ISCAS’89 benchmark cir-
cuits
Circuit No. of PIs No. of POs No. of gates No. of paths No. of No. of Total faults
critical victims
paths
c17 5 2 6 11 6 7 42
c432 36 7 160 83,926 2199 103 9327
c880 60 26 383 8642 92 70 9279
c499 41 32 202 9440 14 207 21,879
c1355 41 32 546 4,173,216 97,372 607 157,387
c1908 33 25 880 729,057 32 93 25,916
c3540 50 22 1669 28,676,671 95 150 11,252
c5315 178 123 2307 1,341,305 79 132 60,554
c7552 207 108 3512 726,493 7 154 138,680
s27 7 4 10 28 6 10 74
s208 19 10 96 145 2 18 743
s208.1 18 9 104 142 1 12 558
s298 17 20 119 231 1 10 537
s344 24 26 160 355 1 21 1190
s526 24 27 193 410 1 10 891
s386 13 13 159 207 10 49 4195
s510 25 13 211 369 1 13 1098
s420.1 34 17 218 474 1 14 1276
s820 23 24 289 492 11 43 7738
s953 16 23 395 1133 2 20 3036
s1196 32 32 529 3097 9 55 10,630
s1488 14 25 653 962 1 18 4305
s1238 32 32 508 3558 30 45 5822
s1423 91 79 657 44,726 8 65 15,493
s1494 14 25 647 976 1 18 4283
s13207.1 700 790 7951 1,345,319 565 188 241,743
Note Reprinted from Article ID 745861, Jayanthy et al. (2012), with permission from M/s Hindavi Publishing Corporation
Table 4.5 Characteristics of ITC 99 benchmark circuits

Circuit No. of No. of No. of No. of paths No. of No. of Total
PIs POs gates critical victims faults
paths
b01_C 7 7 54 65 3 15 421
b02_C 5 5 32 26 1 7 103
b03_C 34 34 190 791 3 15 2957
b04_C 77 74 803 84,548 40 65 12,070
b06_C 71 150 65 70 6 15 456
b08_C 30 25 204 2809 49 43 2669
b10_C 28 23 223 703 2 21 1338
b11_C 38 37 801 10,566 2 37 7845
b14_C 277 299 10,343 57,121,179 92 68 411,412
b20_C 522 512 20,716 289,792,088 193 307 1,625,578
b22_C 767 757 30,686 437,362,328 30 85 812,700
The number of test vectors for each benchmark circuit is also given. The number of
test vectors that are generated is same for PODEM- and FAN-based ATPG.
Table 4.7 gives the comparison between average numbers of backtraces for FAN-
based ATPG compared to PODEM-based ATPG. The bold number represents mini-
mum number of backtraces obtained for each circuit. The algorithm achieved a high
degree of reduction in average number of backtraces (29.70%) due to checking of
contradictions at the fanout point instead of backtracing to primary inputs. Hence,
the CPU execution time is greatly reduced.
Table 4.7 also gives number of fanout points and the average aggressors activated
per victim. As an example, for s208 circuit for a particular victim, the number of total
aggressors is 99. Out of this 99, 94 aggressors are activated. Percentage of activated
aggressors (94/99) * 100 is calculated. The same procedure is followed for the all
the victims/activated aggressors of s208 circuit. Average of the percentage for all
the victims/activated aggressors is taken and the results are presented. The results
demonstrate that more number of aggressors are activated per victim. Hence, the
algorithm handles single victim/multiple aggressors efficiently.
Table 4.8 gives the comparison of number of transitions for PODEM- and FAN-
based ATPG. FAN gave less number of transitions for 16 of the 19 benchmark
circuits. FAN reduces the number of transitions by 28.93% compared to PODEM.
This is because compared to PODEM, backtracing in FAN results in more number of
unassigned primary inputs with value X. These unassigned primary inputs are finally
assigned static values S0 or S1. Because more number of primary inputs are assigned
static values in FAN-based ATPG, the number of transitions is reduced. Thus, the
efficient backtrace procedure in FAN reduces the number of transitions compared to
PODEM-based ATPG, thus reducing the power dissipation in VLSI circuits.
For c1355, c3540, c5315, and c7552, the number of target faults is limited to
10,000. The average fault coverage, percentage decrease in average number of back-
Table 4.6 Comparison of fault coverage

Circuit Fault coverage (%) No. of test vectors
FAN PODEM
c17 92 90 13
c432 80 79 3769
c499 71 46 5328
c880 80 30 1264
c1908 15 7 2379
*c1355 33 27 2427
*c3540 59 43 4933
*c5315 57 39 5275
*c7552 68 43 6110
s27 83 58 32
s208 68 42 67
s208.1 10 43 29
s298 85 59 115
s526 86 84 116
s386 62 77 212
s510 65 47 91
s420.1 22 12 55
s1196 62 52 942
s1238 87 86 543
Average 64.53 54.13
*The number of target faults is limited to 10000
traces, average CPU time, and average number of transitions are taken without con-
sidering c1355, c5315, c7552, and c3540.
Table 4.9 gives the comparison of fault coverage and number of transitions for
PODEM- and FAN-based ATPG for ITC’99 benchmark circuits. FAN gave higher
fault coverage for all the benchmark circuits. FAN gave less number of transitions
for 8 of the 10 benchmark circuits.
Figure 4.5 gives the comparison between the execution time of FAN and PODEM-
based ATPG. For large circuits such as c880 and c499, CPU time is reduced by 60%
for FAN-based ATPG.
The switching activity is reduced further by introducing a transition observability
cost factor during the propagation of fault to the primary output. The target paths for
propagating the fault to the primary output are normally chosen as the longest paths
from the victim site to the primary output.
A transition observability cost is computed for each longest path which indicates
the number of transitions required to propagate the fault to the primary output. The
longest path with minimum observability cost is selected to propagate the crosstalk
delay fault. Table 4.10 gives the fault coverage and number of transitions for each cir-
Table 4.7 Experimental results on benchmark circuits

Circuit No. of Average Average number of Decrease CPU time (s)
name fanout aggres- backtraces in average
points sors no. of
activated back-
(%) traces
(%)
FAN PODEM FAN PODEM
c17 3 73 5.15 8.461 39.13 0.000 0.000
c432 89 94 132.054 216.518 39.01 228.83 389.2
c499 59 98 163.789 233.418 29.83 746.783 3040.1
c880 125 97 314.460 436.56 27.97 1016.33 3145.9
c1908 384 80 646.377 842.28 23.25 3762.3 5786.5
*c1355 259 81 501.171 712.45 29.65 1865.8 3729.2
*c3540 579 84 6058.5 8236.8 26.45 8759.4 10,887.3
*c5315 806 91 7397.37 9865.12 25.01 7151.2 9034.6
*c7552 1300 86 10,872.99 13,763.21 20.99 9867.03 11,231.78
s27 4 94 9.593 12.218 21.48 0.017 0.019
s208 32 95 89.029 101.208 12.03 0.967 1.550
s208.1 28 80 89.55 103.93 13.83 0.450 0.900
s298 34 88 76.104 161.886 52.99 2.683 5.500
s526 54 93 132.353 301.284 56.07 8.81 19.433
s386 26 85 102.88 206.06 50.07 10.3 21.8
s510 73 91 156.615 218.48 28.32 9.00 23.05
s420.1 58 73 175.67 189.69 7.39 6.1 13.58
s1196 155 94 508.99 558.26 8.82 1292.417 2862.4
s1238 165 98 424.97 658.28 35.44 640.11 710.15
Average 29.70 515.0 1068.0
Note Reprinted from Article ID 745861, Jayanthy et al. (2012), with permission from M/s Hindavi
Publishing Corporation
*The number of target faults is limited to 10000
cuit for FAN-based ATPG when transition observability cost is introduced. Table 4.11
gives the percentage decrease in number of transitions, test vectors, and CPU time
for each circuit for FAN-based ATPG with a slight decrease in fault coverage, when
compared to results of FAN-based ATPG without taking observability cost. The num-
ber of transitions decreases by 33.48% with a decrease in fault coverage by 6.42%
when compared to the results taken without the observability cost. The CPU time is
also reduced. The number of test vectors is reduced by 29.98%.
Table 4.12 presents the comparison of the proposed FAN-based ATPG for
crosstalk delay faults with the results of Chen et al. (2002), Sinha et al. (2008),
Chun et al. (2009). The results are tabulated for combinational circuits. In Chen et al.
(2002) and Sinha et al. (2008), the number of victim/aggressors pairs taken into con-
Table 4.8 Comparison of number of transitions

Circuit No. of transitions Reduction in number
of transitions over
PODEM (%)
FAN PODEM
c17 94 117 19.66
c432 199,585 345,413 42.21
c499 380,926 374,882 −1.58
c880 130,217 112,465 −13.63
c1908 430,634 458,133 6.00
*c1355 36,431 39,536 7.85
*c3540 49,788 52,327 4.85
*c5315 41,490 42,980 3.46
*c7552 83,489 85,790 2.68
s27 338 285 −15.68
s208 2131 3317 35.75
s208.1 930 1837 49.37
s298 6388 8860 27.90
s526 8036 13,100 38.65
s386 15,385 26,760 42.50
s510 4747 10,175 53.34
s420.1 3435 8036 57.25
s1196 107,765 222,839 51.63
s1238 69,164 116,570 40.66
Average 28.93
*The number of target faults is limited to 10,000
Note Reprinted from Article ID 745861, Jayanthy et al. (2012), with permission from M/s Hindavi
Publishing Corporation
sideration was 100. In Chun et al. (2009), the numbers of target faults were limited
to 1000 and number of backtraces was limited to 10,000. In the proposed ATPG, all
the target faults are taken into consideration for most of the benchmark circuits. The
number of backtraces is also not limited. Comparatively, the proposed ATPG has a
better fault coverage for most of the benchmarks.
Table 4.13 represents the comparison of the proposed ATPG with the results of
Li et al. (2006), Shen et al. (2005), Li et al. (2003) for sequential circuits. In Li et al.
(2003), the waveform sensitization-based algorithm could not generate tests for the
large circuits. Compared to previous works, the proposed test generation algorithm
has produced comparable or greater fault coverage. For sequential circuits, the fault
coverage increases by an average of 30% for the six circuits.
Table 4.9 Experimental results on ITC’99 benchmark circuits

Circuit Fault coverage (%) No. of transitions
FAN PODEM FAN PODEM
b01_C 35 84 1675 2479
b02_C 88 79 133 180
b03_C 70 60 15,447 13,508
b04_C 62 53 112,885 145,847
b06_C 73 62 25,394 24,900
b08_C 63 54 86,527 111,014
b10_C 70 61 26,665 34,131
b11_C 70 60 128,340 165,815
*b14_C 64 52 4,369,929 4,514,389
*b20_C 54 42 18,806,453 19,331,202
*b22_C 53 41 12,932,226 12,475,579
*The number of target faults is limited to 10,000
12000
FAN
PODEM
10000
ExecuƟon Time(sec)
8000
6000
4000
2000
0
c432
c499
c880
c1908
c1355
c3540
c5315
c7552
s1196
s1238
Benchmark Circuits
Fig. 4.5 Comparison of execution time (Note Reprinted from Article ID 745861, Jayanthy et al.
(2012), with permission from M/s Hindavi Publishing Corporation)
4.7 Conclusion
In this chapter, a modified version of FAN algorithm for testing crosstalk delay
faults in combinational and enhanced scan version of sequential circuits is pre-
sented. The experimental results using modified FAN-based ATPG and modified
4.7 Conclusion 75
Table 4.10 Experimental results of FAN-based ATPG with observability cost

Circuit Fault coverage No. of transitions No. of test CPU time (s)
(%) vectors
c17 78 67 10 0.00
c432 77 181,851 3407 206.267
c499 66 378,798 4964 665.517
c880 76 69,122 685 511.817
s27 83 291 26 0.00
s208 55 1162 44 0.7
s208.1 10 647 23 0.350
s298 85 3822 73 1.783
s386 62 9015 135 7.250
s420.1 22 2224 38 4.5
s510 22 3066 59 6.217
s526 86 4834 75 5.933
s1196 54 51,248 562 741.883
s1238 87 35,082 336 388.18
Table 4.11 Comparison of fault coverage and number of transitions for FAN-based ATPG with
and without observability cost
Circuit Decrease in fault Decrease in no. Decrease in no. Decrease in CPU
coverage (%) of transitions (%) of test vectors time (%)
(%)
c17 14 28.72 23.07 0
c432 3 8.88 9.6 9.86
c499 5 0.56 6.83 10.88
c880 4 46.91 45.8 49.64
s27 0 13.9 18.75 100
s208 13 45.47 34.32 27.61
s208.1 0 30.43 20.68 22.22
s298 0 40.16 36.52 33.54
s386 0 41.4 36.32 29.61
s420.1 0 35.25 30.9 26.22
s510 43 35.49 35.16 30.92
s526 0 39.84 35.34 32.65
s1196 8 52.44 40.33 42.59
s1238 0 49.27 38.12 39.35
Average 6.42 33.48 29.98 32.50
Table 4.12 Comparison with previous works (ISCAS’85 combinational circuits)

Circuit Chen et al. (2002) Sinha et al. Chun et al. Proposed ATPG
(2008) (2009)
Fault coverage Fault coverage Fault coverage Fault coverage
(%) (%) (%) (%)
c432 35 15 – 80
c880 28 38 54.26 80
c1355 16 36 – 33
c1908 33 8 24.34 15
c5315 31 1 49 57
c7552 14 2 52 68
Table 4.13 Comparison with previous works (enhanced scan version of ISCAS’89 sequential cir-
cuits)
Circuit Li et al. (2006) Shen et al. (2005) Li et al. (2003) Proposed ATPG
Fault coverage Fault coverage Fault coverage Fault coverage
(%) (%) (%) (%)
s208 31.50 55.48 – 68
s298 42.66 – – 85
s386 34.43 51.89 – 62
s526 66.30 55.24 – 86
s420.1 27.19 – – 22
s1196 31.32 1.03 8.41 62
s1238 – 3.83 3.11 87
s13207.1 87.14 25.13 – 64
Note Tables 4.12 and 4.13 reprinted from Article ID 745861, Jayanthy et al. (2012), with permission
from M/s Hindavi Publishing Corporation
PODEM-based ATPG indicates that modified FAN-based ATPG increases the fault
coverage with reduced number of transitions and thus reduces power dissipation dur-
ing testing of VLSI circuits. During the propagation phase, an observability cost is
introduced which further reduces the number of transitions. The modified version of
FAN algorithm used for test generation significantly reduces the average number of
backtraces compared to PODEM. Therefore, the CPU time of modified FAN-based
ATPG reduces significantly compared to modified PODEM-based ATPG.
Acknowledgements Section 4.3, Tables 4.4, 4.7, 4.8, 4.12, and 4.13 are reproduced from the
reference Jayanthy et al. (2012) under the creative commons attribution license from M/s Hindavi
Publishing Corporation. This is gratefully acknowledged.
References 77
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Chapter 5
ATPG for Crosstalk Delay Faults using
Single-Objective Genetic Algorithm
5.1 Introduction
Test generation using deterministic algorithms is highly complex and time-

consuming. To obtain a particular output value for a component, backtracing is
required to determine its input values. It is difficult to handle components other
than simple gates (Rudnick and Greenstein 1997).
In a simulation-based approach, processing occurs in the forward direction only.
Hence, complex component types are handled more easily. Test can be generated
for any type of circuit, and any type of fault can be simulated. In a simulation-based
approach, a logic or fault simulator is used to select the best test to apply (Agrawal
et al. 1989).
Most of the existing simulation-based test generators for crosstalk-induced delay
faults were random based, and hence, the test sets generated were typically much
longer than those generated by deterministic test generators. These simulation-based
test generators were by and large ad hoc with numerous heuristics. Even though
the heuristics were very clever, there was no underlying well-defined algorithmic
framework such as genetic algorithm (GA) or simulated annealing.
Genetic algorithm is simulation based have been very effective for test generation
of stuck-at faults in both combinational and sequential circuits. The use of GA for
simulation-based test generation produces better fault coverage and lower execution
times (Mazumder and Rudnick 1999). GA-based algorithms tend to generate more
compact test sets when accurate fitness functions are used (Corno et al. 1996).
In this chapter, GA is used for testing crosstalk delay faults. Tests are gener-
ated for most of the ISCAS’85 combinational circuits and enhanced scan version
of ISCAS’89 sequential circuits. Results are obtained for four crossover operators,
namely one-point, two-point, uniform, and weight-based crossover operators. The
results demonstrate that GA-based test generation provides good results for most of
the benchmark circuits.

80 5 ATPG for Crosstalk Delay Faults …
5.2 Genetic Algorithm
Genetic algorithm is search algorithm that mimics the process of natural selection and
natural genetics as proposed by Darwin. They combine survival of the fittest among
string structures. Genetic algorithm has been developed by Holland (1975) at the
University of Michigan. The goal of their research has been robustness, the efficiency,
and efficacy necessary for survival in many different environments; thereby, artificial
systems can be made more robust and costly redesigns can be eliminated (Goldberg
2001). The simplicity, robustness, efficiency, and effectiveness of genetic algorithm
make them a promising tool for complex applications. GA has been investigated as
possible solution to large number of search and optimization problems (Davis 1991;
Drechsler 1998; Srinivas and Patnaik 1994). Several of tasks in VLSI design and
test involve optimization problems. Heuristic techniques which are used to obtain
solutions increase design complexity. Therefore, GA is a good choice in VLSI design
and test processes which are integrated into commercial electronic design automation
(EDA) tools. The advantages of GA are as follows:
• GA is superior to normal guided random method concerning with the test perfor-
mance.
• The improved level-oriented GA-based test generation method is more effective in
finding the distance between the levels to which the fault signal can be propagated.
• It can quickly scan a very large solution set through evolution.
• The inductive nature of the GA means that it does not have to know any rules of
the problem and it works by its own internal rules.
Figure 5.1 shows the flowchart of GA. GA maintains a population pool of candi-
date solutions called strings or chromosomes. Each string is a collection of genes.
Each string is associated with a fitness value (Jayanthy et al. 2013). The fitness
function is usually user-defined and problem-specific. GA starts with an initial pop-
ulation, which consists of many individual solutions or strings that are randomly
generated. Selection, crossover, and mutation are then used to generate an entirely
new population from the existing population. Selection is one of the key operators on
GA that ensures the survival of the fittest. Usually, members are selected for mating
with a selection probability proportional to their fitness values. The two selection
schemes commonly used are binary tournament selection and roulette wheel selec-
tion (Goldberg and Deb 1991). In binary tournament selection, two individuals are
taken at random and the better individual is selected from the two. There are two
types in binary tournament selection. They are with and without replacement. If they
are again replaced into the population, it is tournament selection with replacement,
and if they are not replaced into the population, it is tournament selection without
replacement. The second scheme is the roulette wheel selection. In this selection,
the search is more randomized but the fittest individuals have more probability to
be selected. Tournament selection is the most popular selection method in genetic
algorithm due to its efficiency and simple implementation (Razali and Geraghty
2011).
5.2 Genetic Algorithm 81
Fig. 5.1 Flowchart of GA

Start
Generate random initial

population of test sequences
Evaluate each individual
Select individuals by applying

a selection operator
With some probability perform

crossover to produce offspring.
Mutate the offspring with a

small probability
Replacement strategy
Criteria
met?
End
Roulette wheel selection method provides highest pressure in initial generations

when a few individuals have higher fitness than others do. Tournament selection
provides more pressure in later generations when the fitness values of individuals are
not significantly different (Rudnick and Greenstein 1997). In this work, tournament
selection is used for selecting the chromosomes for next generation.
Crossover combines the chromosomes of two individuals to obtain new fitter

individuals with probability called as the crossover rate. There are a number of
crossover operators (Goldberg 2001). Crossover operators used in this research work
are explained in Sect. 5.3. Mutation involves the modification of the values of some
genes of a solution with a given mutation rate. The last two operations are performed
on the individuals selected from present population through selection operation.
In the simple GA, the process of reproduction, crossover, and mutation is repeated
until all entries in a new population are filled. When the required number of child
chromosomes is produced, the new population and the existing population contend
for membership in the generation’s membership pool. Selection of the chromosomes
is governed by the replacement strategy, and numbers of replacement strategies are
available in literature (Goldberg 2001). The old population is discarded. The sequence
of selection, crossover, and mutation forms a one-generation cycle. GA progresses
through generations until the objective is reached, for example, a fixed number of
generations. The fitness of the overall population is expected to increase in successive
generations (Goldberg 2001).
5.3 Test Generation Using GA
Test pattern generation is a search process over a large vector space, and therefore, it
is an ideal candidate for GA (Rudnick et al. 1994). The goal of GA in test generation
is to find test vector which detects maximum faults.
5.3.1 Chromosome Encoding
The chromosomes are made up of units called genes. Group of chromosomes form a
population. Binary encoding scheme is employed. In crosstalk delay fault testing, a
two-vector test pattern, <v1, v2>, is required. Hence, the length of the test sequence
is equal to twice the number of primary inputs.
1 0 1 1 1 1 0 0 0 0 1 1
V1 V2
5.3 Test Generation Using GA 83
Fig. 5.2 One-point

crossover Parents 0 0 0 0 0 0 0 0 p1
1 1 1 1 1 1 1 1 p2
Children 0 0 0 0 1 1 1 1 c1
1 1 1 1 0 0 0 0 c2
5.3.2 Fitness Function
The fitness function for test generation is the number of faults detected.
5.3.3 Crossover Operators
Crossover is a GA operator that entails choosing two individuals to swap segments of

their string, thereby producing new offspring that is combination of their parents. The
one-point, two-point, uniform, and proposed weight-based crossovers are described
in this section (Bhuvaneswari and Jayanthy 2015).
5.3.3.1 One-Point Crossover
A single crossover point is randomly selected on both parents. All bits beyond that
point in either parent are swapped as shown in Fig. 5.2. The resulting strings are the
children.
5.3.3.2 Two-Point Crossover
Two-point crossover has two points to be selected on the parent strings. All bits
between the two points are swapped, rendering two children.
5.3.3.3 Uniform Crossover
In uniform crossover as shown in Fig. 5.3, the crossover operator decides with some
probability, which parent will contribute each of the gene values in the offspring
chromosomes (Rudnick and Greenstein 1997).
Fig. 5.3 Uniform crossover 1 1 1 1 1 1 1 1 p1
0 0 0 0 0 0 0 0
p2
.1 .6 .3 .7 .8 .2 .4 .6
Probability
1 0 1 0 0 1 1 0
c1
0 1 0 1 1 0 0 1
c2
Table 5.1 Rules for WCO

Bit weight of parent 1 Bit weight of parent 2 Operation
0 0 Same as uniform crossover
1 1 Same as uniform crossover
1 0 Assign bit of p2 to both children
0 1 Assign bit of p1 to both children
5.3.3.4 Weight-Based Crossover (WCO)
In GA, crossover operators differ from each other primarily in the way they choose
the gene from parents to form the offspring. In one-point, two-point, and uniform
crossover operators, the selection of the gene is purely random. The WCO oper-
ator depends on the weights assigned to the genes for crossover operation. It is a
combination of uniform crossover and weighted uniform crossover. If the number of
generations is N, uniform crossover is performed for the first N/2 generations and
for the next N/2 generations weights are assigned to the genes in the chromosome
according to the similarity of the test patterns in the population and weighted uni-
form crossover is performed. The scheme for weighted computation is defined in
(Bhuvaneswari and Sivanandam 2002). The rules for weighted crossover operator
are defined in Table 5.1.
Two parents p1 and p2 are selected to produce two child chromosomes c1 and
c2. Each gene Gi,1 with weight W i,1 in parent p1 competes against the corresponding
gene Gi,2 with weight W i,2 in parent p2. If the weights are equal, the bits are crossed
with the probability as in uniform crossover. If the weights are different, both the
child chromosomes are assigned the value of the lighter bit with weight 0.
Weight Wk,c is assigned for each gene position k in chromosome c. Initially,
weight zero is assigned to all Wk,c . After N/2 generations, the individuals in the new
population are compared for similarity. If more than 75% of the chromosome test
patterns in the population are identical in more than 75% of the bit position, then
weight 1 is assigned to bits that are similar and weight 0 is assigned to the remaining
bits.
5.3 Test Generation Using GA 85
Table 5.2 Examples for Population p1 Weight for p1

weight computation
10111100 00110011
01111000 01110111
01110000 01110111
11110001 01110110
Population p2 Weight for p2
11111111 00000000
00011011 00000000
00110011 00000000
11010001 00000000
Table 5.2 shows weight computation of two populations p1 and p2, with 2 test
vectors of length 8. In population p1, bits 1, 2,3,5,6, and 7 are similar bits, which
account for 75% of the total bits in a test vector. Weight 1 is assigned to those that
have the same value as the majority and weight 0 to the remaining unsimilar bits. In
population p2, bits 1, 2, 3, and 5 are similar bits which account for only 50% of the
total bits in a test vector. So zero weights are assigned to all bit positions
5.4 Crosstalk Delay Fault Simulator
The objective of the fault simulator is to determine the number of faults detected
by the test sequence, with a test vector sequence as inputs. The logic simulator uses
event-driven technique (Ulrich 1969). Event-driven simulator is to detect events, i.e.,
changes in signal values, and simulate the gate in response to the event. If there is no
change in signal values, then no gates will be simulated. In addition, nets are tested
for changes only when necessary. It is necessary to test nets for changes, when a new
input vector is read and instantaneously after a gate is simulated. When an event is
detected, an event queue is created and stored for future processing. The events are
processed one by one. In this research work, a circular event queue is used.
The fault simulator uses three valued logics: 0, 1, and X. The fault simulator is
capable of detecting single victim/multiple aggressor faults.
The simulation algorithm is shown as a flowchart in Fig. 5.4. Initially, the simulator
reads in a new test sequence. This is followed by fault-free circuit simulation, and
faults are read from the fault list. All aggressors for a particular victim are read and
concurrently checked for activation. Faults are activated when victim and aggressors
have opposite transition. The fault is injected by delaying the victim by a time step
equal to calculated delay value. Other events are scheduled as usual as for a fault-
free circuit. The simulation is continued until the end of time frame. At any primary
outputs of faulty circuit, if the delay effect is observed, then fault is detected and
the victim and activated aggressors pairs are removed from the fault list. The other
Start
Read new test

sequence
No
Simulate fault free End of test Yes
circuit sequences?
Fault excitation End
Fault injection and If faults are detected remove

simulation from fault list
Fig. 5.4 Flowchart of fault simulation-based ATPG
aggressors are considered for the next test pattern. The simulator reads the other
target faults from the fault list, and fault simulation is done. The whole process is
repeated for all the test vectors in the test set (Jayanthy and Bhuvaneswari 2011).
5.5 GA-Based Crosstalk Delay Test Generation Algorithm
The objective of crosstalk delay fault test generation is generating a reduced test
set, which contains smallest number of test vectors. This is fundamentally a process
of exploring the test vector space. So GA can be used to optimize the process of
exploring the test vector space. Every test vector/sequence can be treated as an
individual or string, with the string length equal 2Q, where Q is the number of primary
inputs in the circuit. Thus, the number of tests can be viewed as vector/sequence
pairs as a population. Each individual is associated with a fitness, which measures
the quality of this individual for detecting the faults. To assess the fitness of every
test vector/sequence pair in a population in any generation of evolution, the crosstalk
delay fault simulator is suitable. The individuals of the population which detect the
fault are added to the test set.
The pseudo-code for GA-based ATPG algorithm presented in this research work
is shown in Fig. 5.5. The ATPG algorithm performs in two phases. In the first phase,
the initial population of test vectors/sequences is obtained by pseudorandom process.
The test vectors are evolved based on fitness function in the second phase of GA-
based test generation. The fitness function used is:
5.5 GA-Based Crosstalk Delay Test Generation Algorithm 87
Fig. 5.5 Pseudo-code of Overrall ATPG algorithm

overall GA-based ATPG {
algorithm. Note Reprinted TFL= {reduced set of target crosstalk delay faults}
from Vol 9, Jayanthy and
Bhuvaneswari (2009), with initial pop=phase I (TFL);
permission from
ICGST-AIML if (FL =NULL)
break;
phase II (initial pop, TFL);
Fitness = Number of faults detected.

The crosstalk delay fault simulator is used to evaluate the fitness function.
5.5.1 Phase I: Pseudorandom Generation of Initial Test

Sequence
In phase I, the initial sequences consist of test vectors that are generated based on
pseudorandom process. The generated sequences are fault simulated for the faults in
the target fault list. The fault is removed from the fault list, if the sequence detects
that fault, and the resultant sequence is added into the solution set. The last sequence
generated in the corresponding cycle is added to the set, if no faults are detected
by the sequence. This process is repeated for maximum number of iterations. The
pseudo-code of phase I is shown in Fig. 5.6.
5.5.2 Phase II: GA-Based Test Generation
In phase II, the initial population consists of sequences generated in phase I. New
population is generated from the existing population by selecting two individuals
(parents), and the individuals are crossed to create two entirely new individuals
(child), and each child is mutated with a small mutation probability. The pseudo-
code for phase II is shown in Fig. 5.7. The selection operator is binary tournament
selection with replacement. In this selection scheme, two individuals are taken at
random, and the better individual is selected.
The two new individuals are then placed in the new population, and the process
continues until the generation is entirely filled. The previous population is discarded.
The number of generations is represented as no_gen, and size of population is repre-
Fig. 5.6 Pseudo-code of Function Phase I

pseudorandom generation of
initial test sequence. Note
Reprinted from Vol 9,
initial pop(FL)
Jayanthy and Bhuvaneswari for (n=0; n<max_iter, n++)
(2009), with permission
from ICGST-AIML {
initial pop=phaseI(TFL);
generate sequences randomly of length L;
for (each sequence)
{if the sequence detects faults in TFL
{
sequence added to the test set;
faults detected by that sequence are dropped;
}
}
return (initial population);
}
sented by popsize. The test generation process terminates when the required number
of generations is reached.
The crosstalk delay fault simulator and GA-based test generator are implemented
in INTEL core I7 processor with 2.6 GHz and 4 GB RAM using C language in
Linux environment. The GA-based test pattern generator is applied to ISCAS’85
combinational circuits and several enhanced scan version of ISCAS’89 sequential
circuits.
The target fault list for each circuit is obtained by static timing analysis as
described in Chap. 3. The input fault list for each circuit consists of every com-
bination of single aggressor/single victim pairs. Two versions of crosstalk delay
fault simulators were developed. In the first version (CDSIM1), gates were assumed
unit delay and the activated victim was given one unit delay. In the second version
(CDSIM2), gates are assigned a rise/fall delay and activated victim is given a delay
calculated from coupling capacitance and resistance value. The rise/fall delay of
gates, coupling capacitance, and resistance value is derived from 45 nm Nangate
generic open cell library (Benchmark site 3).
Function Phase II
{
initial pop from phase I;
for (j=0;j<no_gen;j++)
{
for (q=0; q<popsize;q++)
{
two individuals selected from pop;
crossover applied with probability 1;
mutation applied with probability 0.01;
}
compute fitness of the individuals;
for (each sequence)
if (the sequence detects the faults in TFL
{ sequence added to the solution set;
faults detected by the sequence are dropped;
}
}
}
Fig. 5.7 Pseudo-code of GA-based test generation. Note Reprinted from Vol 9, Jayanthy and Bhu-
vaneswari (2009), with permission from ICGST-AIML
GA-based ATPG for crosstalk delay faults using fault simulators CDSIM1 and
CDSIM2 is run for the four crossover operators, namely one-point crossover, two-
point crossover, uniform crossover, and weight-based crossover. During test gener-
ation, the number of generations is varied in the range 4, 12, 16, and 20. For most
of the benchmark circuits, a large population size and more number of generations
are chosen to get better results. A population size of 4, 8, 12, and 16 is used. The
maximum number of iterations in phase I is limited to 10. A crossover probability
of 1 and mutation probability of 0.1 are used.
Tables 5.3 and 5.4 summarize the results for the proposed GA-based ATPG using
CDSIM 1. Results for uniform crossover, one-point crossover, two-point crossover,
and weight-based crossover are tabulated.
The bold number represents the maximum faults detected and minimum number of
transitions for each circuit. The number of faults detected using two-point crossover
is greater than that of the other crossover schemes for 16 of 24 benchmark circuits.
The minimum number of transitions is obtained for 8 of the 24 benchmark circuits.
For larger benchmark circuits, two-point crossover gives better fault coverage when
Table 5.3 Experimental results for GA-based ATPG using CDSIM 1

Circuit No. of faults detected No. of test
vectors
Uniform 1-Point 2-Point WCO
c17 41 42 41 41 36
c432 7963 7963 7970 7955 476
c880 8893 8896 8907 8883 408
c499 20,635 20,532 20,715 20,684 544
c1355 127,922 126,542 128,956 127,623 544
c1908 24,319 24,165 24,809 24,214 544
c3540 9788 9789 9864 9847 544
c7552 103,196 105,874 126,524 106,823 544
s27 71 70 72 71 36
s208 676 657 652 675 408
s208.1 534 532 525 535 340
s298 523 531 529 527 136
s344 1184 1174 1181 1182 340
s386 4169 4141 4081 4169 340
s420.1 1154 1148 1156 1195 340
s820 7686 7696 7709 7686 340
s510 1077 1074 1073 1078 340
s526 879 878 880 879 340
s953 3002 2855 3004 3004 144
s1196 10,124 10,045 10,364 10,111 208
s1238 4655 4405 4674 4576 288
s1423 15,387 15,368 15,407 15,398 288
s1488 4296 4295 4301 4297 288
s13207.1 195,278 195,242 195,289 195,268 544
compared to other crossovers. CPU time and number of test vectors are nearly equal
for all the crossovers.
Table 5.5 represents the number of faults detected and the number of transitions
for ITC’99 benchmark circuits for GA-based ATPG using CDSIM 1. Results are
observed for uniform crossover.
Tables 5.6 and 5.7 represent the number of faults detected and the number of
transitions for each circuit for GA-based ATPG using CDSIM 2. Results are shown
for uniform, one-point, two-point, and weight-based crossover schemes. The bold
number represents the maximum faults detected and minimum number of transitions
for each circuit, respectively.
The number of faults detected using two-point crossover is greater than that of
the other crossover schemes for 14 of 24 benchmark circuits, and the number of
transitions is less for 6 of 24 benchmark circuits. Lower fault coverage is observed
Table 5.4 Experimental Circuit No. of transitions

results for GA-based ATPG
using CDSIM 1
c17 422 412 424 428
c432 80,123 80,768 82,991 81,930
c880 144,209 149,646 148,265 143,952
c499 108,637 108,296 108,127 107,942
c1355 304,245 302,548 301,498 307,452
c1908 509,613 506,463 507,589 508,545
c3540 865,409 866,998 867,007 866,424
c7552 2,105,553 2,103,252 2,104,268 2,105,421
s27 666 667 661 668
s208 33,430 32,343 32,439 32,980
s208.1 32,873 32,518 32,319 32,542
s298 14,605 14,503 14,343 14,621
s344 54,769 58,161 55,636 54,727
s386 40,391 41,171 40,409 41,348
s420.1 61,082 61,548 59,071 60,642
s820 77,031 78,524 77,787 76,804
s510 60,144 59,337 57,962 60,122
s526 56,624 57,415 57,718 56,584
s953 84,512 84,512 84,512 84,512
s1196 91,839 93,044 93,581 91,956
s1238 60,024 59,199 59,922 60,009
s1423 185,451 188,173 181,251 186,912
s1488 160,158 162,341 162,225 159,854
s13207.1 3,932,109 3,976,907 3,924,432 3,988,809
Table 5.5 Results for Circuit No. of faults No. of CPU time (s)
GA-based ATPG ITC’99 detected transitions
using CDSIM 1
b01_C 410 2254 0.067
b02_C 91 1525 0.033
b03_C 2847 11,151 1.58
b04_C 11,035 62,124 313.53
b06_C 454 24,349 0.367
b08_C 2450 21,090 2.46
b10_C 1307 23,990 1.38
b11_C 7633 109,785 61.4
b14_C 365,412 5,599,035 11,124.6
b20_C 1,395,421 23,068,024 43,567.87
b22_C 592,130 14,174,467 38,498.65
Table 5.6 Experimental Circuit No. of faults detected

using CDSIM 2
c17 39 40 41 40
c880 6848 6850 6856 6845
c499 8244 8248 8252 8249
c1355 73,398 73,440 73,449 73,436
c1908 3547 3572 3580 3568
c3540 3546 3560 3566 3558
c7552 57,486 57,509 57,511 57,498
s27 68 69 71 70
s208 662 643 647 660
s208.1 528 525 517 523
s298 484 483 486 485
s344 783 779 783 784
s386 3970 3968 3969 3970
s420.1 1145 1141 1143 1146
s820 7640 7644 7626 7645
s510 1051 988 945 1051
s526 805 805 823 805
s953 1580 1578 1584 1582
s1196 8663 8530 8778 8734
s1238 4626 4400 4658 4556
s1423 12,903 12,900 12,855 12,896
s1488 3608 3831 3627 3635
s13207.1 156,222 156,212 156,246 156,190
compared to GA-based ATPG using CDSIM 1 because when gates are given rise/fall
delay circuit timing becomes more accurate. Hence, the delay effect observed at
the primary output will be more accurate. The number of transitions is decreased
because of lower fault coverage. Execution time of GA-based ATPG using CDSIM
2 is higher when compared to GA-based ATPG using CDSIM1.
Table 5.8 gives the number of faults detected and the number of transitions for
each circuit for GA-based ATPG using CDSIM 1 with crossover probability of 0.9.
Comparing to the results of uniform crossover with crossover probability 1 as given
in Table 4.3, the fault coverage slightly decreases.
Table 5.9 gives the experimental results of GA-based ATPG using two-point
crossover is compared with results of modified FAN-based deterministic test gener-
ation algorithm without the observability cost.
The results of GA-based ATPG using CDSIM 1 are taken for comparison. GA-
based ATPG gave a better fault coverage in reduced CPU time for 17 out of 18
benchmark circuits compared with FAN-based ATPG. In FAN-based ATPG, for
larger benchmarks like c1355, c3540, c5315, and c7552 only 10,000 target faults are
Table 5.7 Experimental Circuit No. of transitions

using CDSIM 2
c17 453 415 442 437
c880 86,288 87,314 87,503 86,491
c499 51,257 51,202 50,982 51,256
c1355 225,689 226,123 226,148 228,750
c1908 188,900 186,980 187,748 188,419
c3540 62,208 62,325 62,374 62,287
c7552 1,302,001 1,301,996 1,302,032 1,301,008
s27 639 667 691 639
s208 27,330 26,943 27,446 27,679
s208.1 27,742 28,052 27,280 27,303
s298 19,349 18,967 19,309 19,349
s344 21,974 21,625 21,795 21,605
s386 36,674 38,099 37,572 36,585
s420.1 53,898 55,941 52,419 53,545
s820 136,032 134,269 135,880 136,447
s510 41,213 39,778 42,224 41,337
s526 68,316 67,318 67,992 68,778
s953 26,321 26,468 26,714 26,374
s1196 81,629 80,281 79,212 80,630
s1238 36,523 37,915 39,204 36,593
s1423 92,674 94,834 92,161 92,493
s1488 93,726 95,023 95,959 94,083
s13207.1 1,733,387 1,769,023 1,726,106 1,743,901
considered. In GA-based ATPG, the entire target fault list is taken for test generation
for all the benchmark circuits.
Table 5.10 presents the comparison of proposed approach using CDSIM2 with
the results of Sathe and Bushnell (2002) where a serial fault simulator with rise/fall
delay for gates has been used for detecting crosstalk delay faults. The crosstalk
reduction algorithm used in Sathe and Bushnell (2002) was similar to the proposed
approach; 10,000 random test vectors were used for all the benchmark circuits to
simulate the faults in Sathe and Bushnell (2002). Since the proposed method is
based on genetic algorithm-based test generation, a much-reduced set of test vectors
is obtained reducing run time. In the proposed method, the results are obtained for
most of the combinational and enhanced scan versions of sequential circuits. In Sathe
and Bushnell (2002), results are presented only for smaller benchmark circuits. The
proposed method also increases the fault coverage for almost all the circuits. The
sequential circuits used in the comparison are ISCAS’89 benchmarks.
Table 5.8 Experimental results for GA-based ATPG for uniform crossover
Circuit No. of faults detected No. of transitions
c17 41 390
c432 7945 79,599
c499 20,646 108,330
c880 8881 145,217
s27 72 627
s208 604 23,229
s208.1 533 32,868
s298 523 16,623
s344 1182 54,094
s386 4178 41,833
s420.1 1186 62,494
s820 7641 80,374
s510 1094 62,258
s953 2889 83,328
s1196 9877 90,806
s1238 4543 59,823
Table 5.9 Comparison of GA-based ATPG using CDSIM 1 with modified FAN algorithm
Circuit FAN-based ATPG GA-based ATPG
Fault coverage CPU time (s) Fault coverage CPU time (s)
(%) (%)
c17 92 0.000 97.61 0.01
c432 80 228.83 85.45 36.2
c880 71 746.783 95.99 14.4
c499 80 1016.33 94.68 10.8
c1355 33 1865.8 81.94 432.44
c1908 15 3762.3 95.73 344.7
c3540 59 8759.4 87.66 786.6
c7552 68 9867.03 91.23 1108.4
s27 83 0.017 97.30 0.033
s208 68 0.967 87.75 0.48
s208.1 10 0.450 94.09 0.45
s298 85 2.683 98.51 0.39
s386 62 10.3 97.28 2.1
s420.1 22 6.1 90.60 1.7
s510 65 9.00 97.72 1.13
s526 86 8.81 98.77 1.56
s1196 62 1292.417 97.50 12.36
s1238 87 640.11 80.28 10.8
Average 62.67 92.79
Table 5.10 Comparison results with previous work

Circuit Sathe and Bushnell (2002) Proposed ATPG
Target No. of Fault No. of Target No. of Fault No. of
faults faults coverage test faults fault coverage test
detected (%) vectors detected (%) vectors
c17 52 51 98.07 10,000 42 41 97.61 32
c880 – – – – 9279 6856 73.88 384
s27 132 66 50 10,000 63 59 93.65 288
s298 1206 112 9.29 10,000 537 332 61.82 1152
s344 3057 199 6.51 10,000 1162 748 64.37 1152
s349 3077 198 6.43 10,000 1169 722 61.76 864
Table 5.11 Fault coverage for proposed and previous works

Circuit Phadoongsidhi and Saluja (2005) Proposed ATPG
Target No. of fault Fault Target No. of fault Fault
faults detected coverage faults detected coverage
(%) (%)
s1196 279,312 9954 3.56 10,630 10,320 97.08
s1488 425,756 8386 1.97 4305 3273 76.02
s1494 417,962 13,925 3.33 4283 3278 76.53
s1238 257,556 4203 1.63 5822 5626 96.63
s13207.1 552 0 0 241,743 169,210 69.99
Note Tables 5.3, 5.4, 5.5, 5.6, 5.7, 5.8, 5.9, and 5.10 are reused from Jayanthy (2012) Ph.D. disser-
tation with permission from Anna University, Chennai)
Table 5.11 presents the comparison of proposed approach with Phadoongsidhi and
Saluja (2005). All combinations of crosstalk delay faults are taken into consideration
by Phadoongsidhi and Saluja (2005). For large circuits like s13207.1, deep faults
are considered. But in the proposed method the number of target faults is reduced
using static timing analysis for all the circuits. False crosstalk faults are eliminated.
Phadoongsidhi and Saluja (2005) have used fault simulator with unit delay for gates.
Hence, comparison is done using GA-based ATPG using CDSIM 1. Compared to
Phadoongsidhi and Saluja (2005), the fault coverage is much greater in the proposed
approach. The input test vectors in Phadoongsidhi and Saluja (2005) were generated
using stuck-at fault test generators like HITEC which were shorter test sequences.
The proposed method uses GA for generating optimized test vectors. The length of
the test sequence is taken as twice the number of primary inputs. Hence, higher fault
coverage is obtained with reduced set of test vectors.
5.7 Conclusion
In this chapter, single-objective genetic algorithm using unit delay simulator and
rise/fall delay simulator is used for testing crosstalk delay faults. The experimental
results for ISCAS’85 combinational and enhanced scan version of ISCAS’89 bench-
mark circuits are presented. The GA-based ATPG achieved 81–97% fault coverage
on ISCAS’85 combinational circuits and 80–98% fault coverage on enhanced scan
version of ISCAS’89 sequential circuits. GA-based ATPG gives better fault coverage
with reduced CPU time for almost all the benchmark circuits compared to FAN-based
deterministic algorithm. GA is capable of exploring a larger space of test vectors,
and hence, fault coverage increases. The reason for reduced CPU time may be that
deterministic algorithms require backtracing which increases CPU time. Better fault
coverage is obtained using two-point crossover when compared to other crossover
schemes.
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Chapter 6
ATPG for Crosstalk Delay Faults Using
Particle Swarm Optimization Algorithm
6.1 Introduction
In the field of VLSI testing, artificial intelligence has gained much attention because
of their simplicity and accuracy. One of the algorithms that are based on artificial
intelligence is the particle swarm optimization (PSO) algorithm. In PSO a number
of simple entities, the particles are placed in the search space of some problem or
function, and each evaluates the objective function at its current location (Brandstatter
and Baumgartner 2002).
In VLSI Testing, particle swarm optimization algorithm is used for the optimiza-
tion of the constrained test suite which is used to detect crosstalk delay faults in
the combinational and sequential circuits. PSO algorithm uses a population-based
research, and each particle is varied according to its past experience and relationship
with other particles in the population (Kennedy and Eberhart 2001). PSO has proved
to be an efficient method for numerous general optimization problems, as it requires
a lesser number of steps to reach the destination and hence as the initial convergence
is faster compared to other evolutionary computation techniques (Kennedy and
Eberhart 1995). Research proposals in the area of test pattern generation for single
faults using PSO were first reported (Hou et al. 2006). This method aimed at
generating test patterns for single stuck-at faults. The search space was evolved for
patterns that detect the maximum number of faults in the fault list. The diagnostic
test pattern generation was proposed using PSO and fault simulator. The whole
test generation algorithm includes two parts: test generator and fault simulator.
First, the test pattern of the target fault is generated by the test generator, and then,
the test pattern simulates all other faults using the fault simulator and deletes the
undetected faults. The initial population is generated randomly, and the population
evolves toward best test patterns based on the fitness function. PSO-based ATPG
was found to be generally superior to GA-based TPG in terms of fault coverage and
required execution time. A new approach was proposed by the same authors for test
generation for synchronous sequential circuits using PSO, and three aspects were

emphasized—initialization, test sequence generation, and test set compaction. An

intelligent hybrid optimization algorithm of ACO and PSO was utilized to delete the
redundancy of test vectors so as to solve the optimization problem for obtaining the
minimal test sets. This technique had the combined efficiency of searching speed
and solution set quality (Wu et al. 2006).
In this chapter, PSO is used for testing crosstalk delay faults. Tests are gener-
ated for most of the ISCAS’85 combinational circuits and enhanced scan version
of ISCAS’89 sequential circuits. Experimental results obtained from the testing of
ISCAS’85 and scan version of ISCAS’89 benchmark circuits show that PSO gives
good fault coverage in less number of generations with less number of test vectors
compared to genetic algorithms.
6.2 Particle Swarm Optimization
PSO was discovered by Kennedy and Eberhart (1995). It was based on the social
behavior such as the one seen in flock of birds and fishes (Kennedy and Eberhart
2001). PSO is a robust stochastic technique and is a member of wide category of
swarm intelligence methods. PSO can be easily implemented and is computationally
inexpensive since its memory and CPU speed requirements are low (Hu and Eberhart
2002). PSO explores the search space using the population of individuals called the
swarm, and the best performers affect the performance of the others. Each individual
is called particles, and it has its own position and velocity. The position and velocity
of the particles are updated based on its interaction with the other particles of the
swarm (Parsopoulos and Vrahatis 2002). PSO optimizes an objective function by
undertaking a population-based research. The particles are randomly initialized and
free fly across the multi-dimensional search space. During the flight, each particle
updates its velocity and position based on the best experience of its own and entire
population (Kennedy and Eberhart 1995). The updating policy drives the particle
swarm to move toward the region with the higher objective function value, and
eventually all the particles will gather around the point with the highest objective
value. Figure 6.1 shows the basic algorithm of PSO.
As shown in flowchart in Fig. 6.1, the swarm is generated, i.e., the position and
velocity of particles are randomly initialized within the search space. After that,
fitness function or objective values of particles are calculated. These first objective
values and positions are automatically considered as personal best values and per-
sonal best positions. The best fitness value among all particles position and fitness
value is considered as global best position and value in the entire swarm. By using
Eqs. (6.1) and (6.2), the position and velocity of particles are updated. In next itera-
tion, again fitness value is calculated at updated position of each particle. Next step
is to compare that personal best fitness with old personal best fitness value. If new
fitness value is better than old one, we update personal best fitness value. Best of per-
sonal best value among all particles in whole swarm is set as global best fitness value.
Then update particle’s position and velocity according to the equations. This process
6.2 Particle Swarm Optimization 101
Fig. 6.1 Flowchart of PSO

algorithm Start
Initialize the random

position and velocity of
each particle
Fitness function
calculation for each
particles position(p)
If fitness(p) is better than

fitness(pbest) then update
pbest(up )
Set best of all pbest of

particles as gbest(ug)
Update particles position

and velocity
Max-
iterations
No
Yes
Stop
continues with evaluating personal best positions and fitness values also global best
position and value. This algorithm stops running when termination criterion meets,
i.e., either satisfactory optimal solution has been achieved or number of iterations is
reached. Iteration stopping criteria can also be termination when no improvement is

observed over a number of iteration.
The personal best value is represented as up , and global best value is represented
as ug .
Particles’ movement is decided by the following iteration in PSO:
u (i) (n + 1) u (i) (n) + v i (n + 1) n 0, 1, 2, . . . , N − 1, (6.1)
where u(i) is the position of particle i, vi is the velocity of particle i, n is iteration,

n 0 indicates initialization, and N is total number of iterations (Raghavendra and
Ganesh Kumar 2010)
The velocity of the particle is given as
(i)

v (i) (n + 1) v (i) (n) + 2r1 (n) u ip (n) − u (i) (n)
(i)
+ 2r2 (n) u g (n) − u (i) (n) , (6.2)
where up is the personal best position, ug is the global best position. uip (n) − u(i) (n)
calculates vector in the direction of personal best position, and ug (n) − u(i) (n) gives
vector directed toward global best position. r (i) (i)
1 and r 2 both represent random vectors
which have values uniformly distributed between 0 and 1.
6.3 PSO Algorithm-Based Test Generation Algorithm
In the proposed approach, PSO-based ATPG is used to generate test patterns for the
crosstalk-induced delay faults. The particles in PSO refer to the test patterns used to
test the faults in the given circuit. The fitness value of each pattern is evaluated using
the crosstalk delay fault simulator explained in Sect. 5.4. During simulation, particles
update their own velocity and position based on the value of the fitness function
obtained. By doing so, PSO tries to provide the optimal solution to the problem. The
number of bits in the test vector/sequence is twice the number of primary inputs to
the circuit, and the values of the primary inputs determine the position of the pattern.
Each test vector is associated with a fitness, which measures the quality of this test
vector for detecting the faults. The velocity factor refers to the toggling count among
the patterns. The pattern will get updated or modified by a different velocity only if
the current fitness is greater. The optimal solution consists of minimum number of
test vectors with high fault coverage. Fitness Function = Number of faults detected.
Figure 6.2 shows the PSO algorithm-based test pattern generation. Steps followed
in PSO to generate the test patterns to detect the faults using this approach are as
follows.
Step 1: The search space initially consists of random patterns constituting the
initial population set. A random pattern is selected from the population.
6.3 PSO Algorithm-Based Test Generation Algorithm 103
Start
Generate the initial population

of test vectors
Calculate the initial velocity of

the test sequences
Evaluate the fitness of the initial

population of test vectors
using fault simulator
PBest=P
GBest=Best of PBest
Update velocity and position to

generate new population
Find the fitness of the new

population
Yes No
F(P)>F(PBest)
F(G)>F(GBest)
No Yes
PBest=P PBest=OLD PBest
GBest=G GBest=OLD GBest
End of test
sequences?
No
Yes
Stop
Fig. 6.2 Flowchart of PSO algorithm-based ATPG
Step 2: The initial velocity of the test pattern is calculated using the formula:
V [i][ j] Vmin + (Vmax − Vmin ) ∗ rand() (6.3)

where V [i][j] is the velocity of the ith test vector in the multi-dimensional search
space.
V max maximum velocity 1, V min minimum velocity 0,
rand() is the random function which generates a random number.
Step 3: For the fault to get propagated to the primary output, the circuit is fault
simulated using the crosstalk delay fault simulator with the selected pattern. Faults
are read from the target fault list. All aggressors for a particular victim are read and
concurrently checked for activation. Faults are activated when victim and aggressors
have opposite transition. The fault is injected by delaying the victim by a time step
equal to calculated delay value. Other events are scheduled as usual as for a fault-free
circuit. At any primary outputs of faulty circuit, if the delay effect is observed, then
the fault is detected. The value of the fitness function is evaluated.
Step 4: The PBest for the test pattern is calculated using the pseudo-code as
shown in Fig. 6.3. For the zeroth generation, each particle is assumed to be in its best
position. So every test vector is assigned to PBest[i]. PBest[i] is the personal best of
the test vector. For the upcoming generations, each particle’s fitness is compared with
its fitness in the previous generation. If the fitness value of the current generation is
greater than the previous generation, PBest[i] is updated or else it is retained.
Step 5:The algorithm given in Fig. 6.3.
Step 6: The GBest is calculated from the pseudo-code described in Fig. 6.4.
GBest global best is the best value obtained so far by any test vector in the neigh-
borhood of that vector. The GBest is calculated by comparing the fitness of each
pattern with one another. The test pattern with the highest fitness is assigned as the
GBest for the zeroth generation. For the upcoming generation, the same routine is
followed, but additionally, the GBest of the current generation and the previous gen-
eration is compared. If the fitness value of the current generation GBest is greater
than the previous, GBest is updated or else it is retained.
Fig. 6.3 Pseudo-code for If (current generation==0)

PBest of PSO
{ for(i=0;i<maxpopulation;i++)
{ PBest [i]=testvector[i]; }}
else
{ for(i=0;i<maxpopulation;i++)
{ if(testvector[i].fitness < PBest[i].fitness)
{ PBest[i]=testvector[i];
}
else
PBest[i]=PBest[i];
6.3 PSO Algorithm-Based Test Generation Algorithm 105
Fig. 6.4 Pseudo-code for If (current generation==0

GBest of PSO algorithm
{ iv=findfitness(0);
GBest=testvector[0];
for(i=0;i<maxpopulation;i++)
{ if(iv<findfitness(i))
{ iv=findfitness(i);
GBest= testvector [i]; }}}
else
{ ivnew=findfitness(0);
GBnew= testvector [0];
for(i=0;i<maxpopulation;i++)
{ if (iv<findfitness(i))
{ iv=findfitness(i);
GBnew= testvector [i]; }}
if (ivnew<iv)
{ GBest=GBnew;
iv=ivnew; }
else
{ GBest=GBest;
iv=iv; }}}
Step 7: The velocity and position of each particle are updated. It is updated using
Eqs. 6.4 and 6.5 (Wang et al. 2010)
V [i][ j](t + 1) w · V [i][ j] + c1 ∗ r 1 ∗ (PBest[i][ j](t) − X [i][ j](t))

+ c2∗ r 2∗ (GBest[ j] − X [i][ j](t)) (6.4)
X [i][ j](t + 1) X [i][ j](t) + V [i][ j](t + 1) (6.5)
where V [i][j] is the velocity, and X[i][j] is the position of the jth dimension of
the ith test vector, PBest[i][j] is the best previous position j of ith test vector, and
GBest[j] is the global best test vector found by all test vectors so far, and c1 and c2
are acceleration constants. The experimental results indicate that c1 c2 2 might
provide even better results. The parameters r1 and r2 are used to maintain the diversity
of the population with uniform distribution between 0 and 1. W 1 is inertia weight.
Step 8: Go to step 3, and the process is repeated iteratively, for all the patterns in
the test set.
Table 6.1 Fault effect at primary output

Circuit No of victims No of target Fault effect at PO CPU time (s)
faults
Random PSO
C17 7 42 42 42 0.467
C432 103 9327 6629 7548 14.317
C499 207 21,879 17,937 19,348 21.683
C880 70 9276 5722 8576 18.750
c1355 607 157,387 9521 113,856 372.4
c5315 132 60,554 49,467 53,543 696.6
c7552 154 138,680 84,790 102,324 1633
S27 10 74 70 72 1.067
S208.1 12 558 371 468 2.100
S208 18 731 559 633 3.250
S526 10 891 726 881 7.533
S420.1 14 1276 927 1129 12.750
S1196 55 10,630 5791 9722 29.533
The crosstalk delay fault simulator and particle swarm optimization algorithm-based
test generator are implemented in C language under the LINUX environment on an
IBM compatible PC. The random and PSO-based ATPG is applied to ISCAS’85
combinational circuits and scan version of ISCAS’89 sequential circuits.
Table 6.1 shows the coupling fault coverage obtained for a few benchmark circuits.
Fault effect at PO gives the number of faults for which delay effect due to the
coupling fault was noticed at the primary output. As it is not practical to test all faults
for large circuits, reduced set of target faults are calculated by selecting victims
which lie in the critical path and for each fault the aggressor-victim timing window
should overlap. The input fault list for each circuit consists of every combination
of single aggressor/single victim pairs. Gates are assumed to have a unit delay,
and the crosstalk delay value to be injected is also assumed to be one time unit
(Jayanthy and Bhuvaneswari 2009). The bold number in Table 6.1 represents the
maximum number of faults detected for each circuit for PSO compared to random
vectors (Saranya and Jayanthy 2013). This is graphically represented by Fig. 6.5
which shows the comparison chart. PSO algorithm shows high fault coverage than
the random vectors. PSO algorithm also shows that an average of above 85% total
fault coverage is achieved for combinational and sequential circuits with less CPU
time. The number of test vectors required to detect faults was high for random vectors
when compared to PSO. In PSO, 90% of the test vectors that are generated detect
faults.
6.5 Conclusion 107
100
90
80
Fault Coverage
70
60
50
40
30
20
10
0
C17
C432
C499
C880
c1355
c5315
c7552
S27
S208.1
S208
S526
S420.1
S1196
Benchmark circuits
random PSO
Fig. 6.5 Comparison chart
6.5 Conclusion
Thus, the reduction in size of the VLSI circuits due to deep submicron technologies
leads to high capacitive coupling or crosstalk effects. The test vectors to detect the
number of crosstalk delay faults can be optimized based on the PSO-based ATPG.
PSO serves to be the best algorithm for tackling the optimization of the test suite.
It gives good results for both combinational and sequential circuits. It also gives the
high fault coverage in less number of generations compared to random vector test
generation. Thus, PSO is an extremely simple algorithm for optimizing effectively.
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Chapter 7
ATPG for Crosstalk Delay Faults Using
Multi-objective Genetic Algorithm
7.1 Introduction
Power consumption and delay are two of the most important design criteria in today’s
deep submicron VLSI technology.
Energy dissipation has become a major concern in today’s VLSI technology with
increasing use of wireless communication and portable computers. The acceptance
of this area of communication and products depends on their power consumption.
Further periodic testing of VLSI circuits can cause generation of excessive heat
which can damage the chips under test (Jayanthy et al. 2012). The reason is that test
patterns cause as many nodes switching as possible while a power saving system
mode only activates a few modules at the same time (Girard 2002). Further, during
testing the low correlation between test vectors increases the switching activity in the
circuit leading to higher power dissipation than during its normal operation. In CMOS
combinational circuits, power dissipation is due to the following sources: static power
dissipation due to leakage currents and other currents drawn continuously from the
power supply, dynamic power dissipation due to switching transient current, and
charging and discharging of load capacitances (Weste and Eshraghian 1992). The
majority of the energy dissipation in the current-day technology is due to the later
source when gates undergo transitions (Shakya and Soundra Pandian 2009).
The total energy consumed in the circuit during application of the complete test
sequence is given in Eq. (7.1)

E tot 1/2Co VD2 D Swi (i, k) (7.1)
k i
where Co is the equivalent load capacitance, VD D is the power supply voltage in

CMOS logic, and Swi (i, k) is the number of switching provoked by test vectors T k
at node i, during the test time T . Co and VD D are constant; only switching varies.

110 7 ATPG for Crosstalk Delay Faults Using Multi-objective …
So the total number of transitions is taken as a measure for the estimation of power
consumption during test application.
Hence, efficient ATPG is to be devised for crosstalk delay faults which gives high
fault coverage with reduction in switching activity.
In this chapter, two multi-objective optimization algorithms, weighted sum
genetic algorithm (WSGA) and non-dominated sorting genetic algorithm (NSGA-
II), together with a crosstalk delay fault simulator are used for crosstalk delay fault
testing. Two objectives, fault coverage and power consumption, are simultaneously
optimized using these algorithms. The NSGA-II generates candidate test vectors
with high fault coverage with minimum switching activity, and the crosstalk delay
fault simulator computes the fitness of candidate test vectors.
The NSGA-II-based automatic test pattern generation for crosstalk-induced delay
faults generates test pattern set that has high fault coverage and low power consump-
tion. Redundancy is introduced in NSGA-II-based ATPG by modifying the fault
dropping phase, and hence, a very good reductions in transition activity is achieved.
Tests are generated for scan version of ISCAŚ’89 and ISCAS’85 benchmark cir-
cuits. Experimental results demonstrate that NSGA-II gives higher fault coverage,
reduced transitions, and compact test vectors for most of the benchmark circuits
when compared with those generated by weighted sum genetic algorithm (WSGA).
7.2 Weighted Sum-Based ATPG
In the area of VLSI test, WSGA has been successfully used to achieve multiple
objectives for stuck-at fault test. To design circuits, it is necessary to meet multiple
objectives which make it a typically difficult multi-objective optimization problem
(MOOP). This can be expressed as

Maximize f (x) f 1 (x), f 2 (x), . . . , f m (x) (7.2)
where f 1 (x), f 2 (x), …, f m (x) are m objective functions. Because the objective func-
tions usually cannot be optimized simultaneously, there could be no global optimal
solutions, but some best compromise ones to a MOOP. A solution f 1 (x) is called
Pareto-optimal if there exists no other solution f (x) that is strictly better than x 1 . A
MOOP may have multiple Pareto-optimal solutions, which constitute a set of the
best compromise solutions or a Pareto frontier in the objective space.
Evolutionary algorithms especially genetic algorithms (GAs) have been applied to
such problems. A well-known fitness function widely used with GAs is the weighted
sum of objective functions which converts a MOOP into its single-objective equiv-
alent.

n
F(x) wn Fn (x) (7.3)
i1
7.2 Weighted Sum-Based ATPG 111
where F(x) denotes the normalized objective function, and wn denotes the corre-
sponding non-negative weight which is given as

n
wn 1 (7.4)
i1
Although the fitness function mentioned above is incapable of guiding a GA to

parallel searching for obtaining multiple Pareto-optimal solutions via one execution,
it is chosen for its simplicity and efficiency (Zhao and Jiao 2006).
The dual objectives chosen are getting high fault coverage while minimizing the
gate transitions, and therefore, the fitness measure has essentially got two compo-
nents:
• Fault coverage
• Gate transitions
Three WSGA operators are selection, crossover, and mutation. The purpose of
selection operation is selecting individuals from present population according to their
fitness to enter into next generation. In crossover, the chromosomes of two individuals
are combined to obtain new fitter individuals. Crossover occurs only with some
probability (the crossover rate). Mutation involves the modification of the values
of some ‘genes’ of a solution with some probability (the mutation rate). Last two
operations are performed on the individuals selected from present population through
selection operation. In the simple WSGA, the process of reproduction, crossover,
and mutation is repeated until all entries in a new population are filled. When the
required number of child chromosomes is produced, the new population and the
existing population compete for membership in the generation’s membership pool.
Selection of the chromosomes is governed by the replacement strategy, and numbers
of replacement strategies are available. The old population is discarded. The sequence
of selection and crossover mutation completes one-generation cycle. GA progresses
through generations until the goal is reached such as fixed number of generations.
The fitness of the overall population is expected to increase in successive generations.
The WSGA-based ATPG algorithm performs in two phases. In the first phase,
the initial population of test vectors and sequences are generated by pseudorandom
process. In the second phase, the GA phase, the test vectors are evolved based on
fitness function. The fitness function used is:
Fitness (w1 ∗ NFi ) + (w2 ∗ NTr )
where NFi is the number of faults detected, NTr is the number of transitions, and w1
and w2 are weights, say w1 0.6 and w2 0.4.
In phase I, the initial sequences composed of M vectors are generated based on
pseudorandom process. The generated sequences are fault simulated for the faults in
the fault list. If the sequence detects fault, that fault is removed from the fault list and
the corresponding sequence is added into the solution set. If no faults are detected by
the sequence, then the last sequence generated in the corresponding cycle is added
to the set. This process is repeated for Max_iter.
The initial population of WSGA is composed of the sequences generated in phase
I. In phase II, a new population is generated from the existing one, two individ-
uals (parents) are selected and crossed to create two entirely different individuals
(child), and each child is mutated with some small mutation probability. The selec-
tion operator is binary tournament selection. In binary tournament selection, two
chromosomes are taken at random and one with higher fitness is selected. The two
parents obtained are crossed to create two entirely new individuals, i.e., child, and
each child is mutated with some small mutation probability. The two new individuals
are then placed in the new population, and the process continues until the generation
is entirely filled. The previous population is discarded (Jayanthy and Bhuvaneswari
2009). The experimental results for WSGA-based ATPG are shown in Sect. 7.5.
7.3 Optimization Using NSGA-II
The difficulty with weighted sum genetic algorithms is in handling-mixed optimiza-

tion problems, such as those with some objectives of the maximization type and
some of the minimization type, and all objectives have to be converted into one
type. Further, it is difficult to set the weight vectors to obtain a Pareto-optimal solu-
tion in a desired region in the objective space. Moreover, different vectors need not
necessarily lead to different Pareto-optimal solutions. They can lead to an identi-
cal optimal solution. The computational complexity of the weighted sum approach
increases because more tests are needed to know whether the obtained solution is
truly a minimum solution. Further, this weighted sum approach cannot find certain
Pareto-optimal solutions in the case of a non-convex objective space (Jayanthy et al.
2013).
Hence to have a diverse set of multiple non-dominated solutions which converge
close to the Pareto-optimal front and with a good spread multi-objective evolutionary
algorithm called NSGA-II is proposed by Deb (2002) and is used for the problem
analysis. It uses an elite preserving operator and a diversity preserving mechanism.
Non-dominated GA differs from simple WSGA mainly by two methods
(i) Non-dominated Sorting
(ii) Crowding distance assignment.
7.3.1 Elitism
Although the crossover and mutation are the core search operators of GA, there
exists a probability of destruction of the good solutions developed so far due to
these operators. Using elitism, it is possible to pass the best solutions of a particular
7.3 Optimization Using NSGA-II 113
generation to the next generation unaffected. This helps the evolutionary algorithm
to converge fast. To implement elitism in evolutionary algorithms, the old population
and new population are merged together. The next generation is formed from this
combined population by selecting the best individuals. Then, as many individuals
are selected in order to make the size of the new population same as the old one. This
ensures the preservation of the old and new population
7.3.2 Non-dominated Sorting
A non-dominated sorting is performed to classify the entire population into different

non-domination fronts.
The fronts with lesser number (F 1 ) are better non-dominated fronts and are
assigned higher fitness value compared to the one with larger number (F 2 ). The
populations corresponding to the higher fitness value are best fit to enter into next
generation. To obtain the new parent population, for the next generation, the new
population is filled by solutions of the different non-dominated front’s one at a time.
The filling begins with F 1 , and then F 2 , followed by F 3 , and so on. As the entire
population size of Rd is 2N, not all the fronts can be accommodated in the N slots
available in the new parent population. The fronts which cannot be accommodated
are deleted. The pseudo-code for non-dominated sorting of population is given in
Fig. 7.1.
7.3.3 Crowding Strategy
Crowding distance computation requires sorting of the population according to each

objective function value in their ascending order of magnitude. The pseudo-code for
calculating crowding distance of each point in set I is given in Fig. 7.2.
I(k). m is the value of the mth objective function of the kth individual in I. The
complexity of the procedure is governed by the sorting algorithm.
Crowded Selection Operator
The crowded selection operator (π ) guides the selection process at the various stages
of the algorithm toward a uniformly spread out Pareto-optimal front. Every individual
in the population has two attributes:
Non-domination rank (irank )

Crowding distance (idistance )
iπ j if (i rank < jrank ) or ((i rank jrank ) and (i distance > jdistance ))
for each (p Є P)
for each (q Є P)
if (p<q) then if p dominates q then
Sp = Sp U {q} add q in the set Sp
else if (q<p) then if p dominated by q
np = np +1 increment the dominated counter of P i.e. n p
end
end
if (np == 0) then no solution dominate p
F1 = F1 U {p} then p belong to first front i =1 initialize the front counter to
1
end
while (Fi ≠ Φ)
Q=Φ
for each (p Є Fi) for each p in front Fi
for each (q Є Sp) for each q in set Sp
nq = nq – 1 decrement the domination count nq by 1
if (nq = 0) then if nq is zero
Q = Q U {q} add the q in set Q
end
end
end
i=i+1 increment the Front by 1
Fi = Q Set Q is next front
end
Fig. 7.1 Pseudo-code for non-dominated sorting of population
l = |I| l is the number of solutions in I for each i

set I[i]distance = 0 initialize the distance to zero for each individual set I
for each objective m
I = sort(I,m) sort using each objective value m
I[1]distance = I[l]distance = ∞ Assign infinite distance to boundary value for a other point
end
for (I = 2 to (l-i))
I[i]distance = I[i]distance +
end
Fig. 7.2 Pseudo-code for crowding distance calculation

7.3 Optimization Using NSGA-II 115
NSGA-II Procedure
• Initialize the parent population Pd .

• Create the offspring population Qd from the current population Pd .
• First two populations are combined to form Rd of size 2N.
• Perform non-dominated sorting as given by the pseudocode in Fig. 7.1 to classify
the population Rd .
• Once the non-dominated sorting is over, the new population Pd+1 is filled.
• Initiate the new population Pd+1 0 and the counter of front for inclusion I 1.
• While Pd+1 + F i ≤ N pop , do
Pd+1 ← Pd+1 U Fi , i ← i + 1
• Sort the last front F i using the crowding distance in descending order and choose
the first (N pop Pd+1 ) elements of F i .
• Offspring population Qd+1 is generated by crowding selection, crossover, and
mutation operators.
7.4 NSGA-II-Based ATPG with Redundancy
The fitness function used in NSGA-II-based ATPG is
f (i) NFi −FCi

f (i) Pi
where NFi is the number of faults that is given to the ith test sequence, FCi is the
number of faults covered by that test sequence, and Pi is the number of transitions
during the application of the i-th test sequence.
NSGA-II-based ATPG algorithm performs in two phases. In the first phase, pseu-
dorandom process is used to generate the initial population of test sequences. If a
sequence detects a fault, that sequence is added to the set, which is given as input to
the second phase. In the second phase, child population is created from population
obtained in the first phase, by using selection, crossover, and mutation operators. To
the combined parent and child population, NSGA-II procedure described in Sect. 7.2
is applied to obtain the new population. The faults that are detected are removed from
the fault list, and the test sequence is added to the test set. The remaining faults are
passed to the next sequence (Bhuvaneswari and Jayanthy 2015).
The pseudo-code of the overall algorithm is given in Fig. 7.3. In NSGA-II-based
ATPG, a redundancy is introduced in test generation process. The aim in introducing
redundancy is to allow NSGA-II to select better test sequences so as to minimize the
{
FL= {reduced set of crosstalk delay faults}
initial pop=phase I (FL);

if (FL =NULL)
break;
phase II (initial pop, FL);
Faults detected by end population are removed from the fault list.
}
Fig. 7.3 Pseudo-code of overall NSGA-II-based ATPG
number of transitions during test pattern generation. This is achieved by the elitism
property of NSGA-II. Due to elitism out of the 2N solutions, only N better solutions
are selected and they are processed using the GA operators, where N is the population
size. So the best sequences will be retained up to the end. Redundancy is introduced
by modifying the fault dropping phase, where a fault is dropped only if it covered by
at least M sequences, where M being the redundancy factor.
Phase I
In this phase, the initial sequences composed of L vectors are generated based on
pseudorandom process. The generated sequences are fault simulated for the faults
in the fault list. If the sequence detects fault, that fault is removed from the fault list
only after it is detected by M sequences and the corresponding sequence is added
into the solution set. If no faults are detected by the sequence, then the last sequence
generated in the corresponding cycle is added to the set. This process is repeated for
Max_iter. The pseudo-code of phase I is shown in Fig. 7.4.
Phase II
In the second phase, child population is created from population obtained in phase
I, by using selection, crossover, and mutation operators. Then, new population is
obtained by applying NSGA-II procedure. For each generation, the same fault list
is forwarded and redundancy fault dropping approach is used. The faults that are
detected only by the end population are removed from the fault list, and the faults
that are not detected are forwarded to next run with same sequence length. Once the
population is evolved for a given number of generations, the population obtained
at this stage is evaluated. If a sequence in that population detects a fault, that fault
is dropped from the fault list and that sequence is added to test set. Number of
transitions is calculated for that sequence that is considered in the evaluation of
power dissipation for the circuit under test. The pseudo-code for phase II is shown
in Fig. 7.5.
initial pop(FL)
For (i=0; i<max_iter, i++)
{
initial pop=phase I(F L);
randomly generate sequences of length L;
for (each sequence)
{if sequence detects faults in the fault list
{
add sequence to the test set;
drop the faults detected only if they are detected by M sequences;
}
}
return (initial population);
}
Fig. 7.4 Pseudo-code of phase I of NSGA-II-based ATPG algorithm
The crosstalk delay fault simulator and genetic algorithm-based test generator are
implemented in 4000 lines of C language under the LINUX environment on an IBM
compatible PC.
The parameters used in WSGA-based test generator are as follows:
Population size: 12/16/20
Maximum number of generation in phase 2: (4–16)
Maximum number of iterations in phase I: (20)
Crossover probability: 1
Crossover operator: uniform crossover
Probability of mutation: 0.1
Selection scheme used: tournament selection
The parameters used in NSGA-II-based test generator are as follows:
Population size: 4/8/12/16
Maximum number of generation in phase-2: (16/20)
Maximum number of iterations in phase I: (20)
Probability of mutation: 0.1
Crossover probability: 1
Crossover operator: uniform crossover
{
Initial pop from phase1;
for (i=0;l<no_gen;l++)
{for (k=0; k<popsize;w++)
{select two individuals from population;
apply crossover with probability 1;
apply mutation with probability 0.01;}
get new population;
for (each sequence from new population)
if (sequence detects the faults in the fault list

{ add sequenceto thesolution set;
drop the faults detected only if they are detected by M sequences sequence;
}
FL which is given to NSGA -II phase is forwarded from one generation to next generation without
any modification.
}
Remove faults that are detected by the end population from faultlist;
Fig. 7.5 Pseudo-code of phase II of NSGA-II-based ATPG algorithm (Note Figures 7.3, 7.4, and 7.5
republished from Vol. 54, Jayanthy and Bhuvaneswar (2011) with permission from Advancement
of Modelling and Simulation Techniques in Enterprises (AMSE))
Selection scheme used: tournament selection

Redundancy factor: 5
Choice of these parameter values is a trade-off between fault coverage, execution
time, and number of transitions.
Redundancy factor has to be selected carefully because both the test generation
time and reduction in number of transitions depend on this. The experimental results
for a redundancy factor of 5 are given here.
Table 7.1 shows percentage reduction in fault coverage and percentage reductions
in transitions over WSGA. For each of the circuits, WSGA-based ATPG is run first
and fault coverage is obtained. The number of transitions occurring in the circuit is
also measured. Next, the NSGA-II-based ATPG is run, and the fault coverage and
number of transitions are recorded. It can be observed that with a slight increase in the
fault coverage, this approach achieves a good reduction in transition activity. Next,
redundancy is introduced in NSGA-II-based ATPG, and results are observed for fault
coverage and gate transitions. With a nominal increase in fault coverage (1.61%),
the algorithm achieved a high degree of reduction in transition activity (32.61%) due
to redundancy introduced in the fault dropping phase. The bold number in Table 7.1
2.50E+002
2.00E+002
No. of transitions
1.50E+002
1.00E+002
5.00E+001
0.00E+000
8.00E-001 8.50E-001 9.00E-001 9.50E-001 1.00E+000 1.05E+000 1.10E+000
Fault Coverage
Fig. 7.6 Graph showing initial population [generation 1]
2.50E+002
2.00E+002
No. of transitions
1.50E+002
1.00E+002
5.00E+001
0.00E+000
8.00E-001 8.50E-001 9.00E-001 9.50E-001 1.00E+000 1.05E+000 1.10E+000
Fault Coverage
Fig. 7.7 Fault coverage versus number of transitions after 16 generations
represents the maximum number of faults detected and number of transitions for
each circuit for NSGA-II.
The aim of the NSGA-II algorithm is to generate multiple Pareto-optimal solu-
tions, which the designer can use at the early stage of the design process to compare
and choose the optimal partitions required. A plot of simulation output is obtained for
circuit c17. Population size of 16 is used with a crossover probability and mutation
probability of 0.9 and 0.2, respectively.
Sample random population of the offspring Qd (Size N) was created from the
parent population Pt (Size N), and they are combined to form a new population Rd
(Size 2N). The initial population distribution of both the parent and offspring of
minimum population size of six for circuit c17 is shown in Fig. 7.6. Figure 7.7 shows
the plot of the simulation output after 16 generations.
120
Table 7.1 Comparison with WSGA

Circuit WSGA NSGA-II NSGA-II with redundancy
Fault No. of Fault No. of %increase % decrease Fault No. of %increase % decrease CPU time
coverage transitions coverage transitions in fault in coverage transitions in fault in
coverage transitions coverage transitions
over over over over
WSGA WSGA WSGA WSGA
c17 100 727 97.61 434 2.39 40.30 100 200 0 72.48 0.083
c432 85.20 78,631 85.32 67,553 0.12 14.08 92.08 60,387 6.88 23.30 61.53
c880 95.43 143,480 92.82 126,450 −2.61 11.86 93.11 112,489 −2.32 21.59 24.82
c449 94.45 108,422 94.71 95,091 0.26 9.21 94.10 88,945 −0.35 17.96 13.25
s27 87.83 842 94.59 431 6.76 48.81 97.29 223 9.46 73.51 0.100
s208 90.98 32,207 95.28 26,049 4.31 19.12 91.52 23,183 0.54 28.01 1.03
s208.1 81.36 31,097 88.35 23,626 6.99 24.02 92.29 21,025 10.91 32.38 0.967
s298 98.69 37,053 97.76 29,644 −0.93 19.99 99.06 26,872 0.37 27.47 0.983
s344 99.15 55,104 99.32 44,988 0.17 18.35 99.74 39,738 0.59 27.88 1.82
s386 96.82 41,423 98.09 33,586 1.27 18.92 99.18 29,476 2.36 28.84 2.133
s420.1 93.02 61,687 78.29 50,323 −14.73 18.42 84.63 44,463 −8.39 27.92 1.717
s820 98.15 79,901 99.40 79,149 1.25 0.94 99.50 58,626 1.35 26.63 7.35
s510 98.62 61,361 97.72 49,855 −0.9 18.75 99.27 46,216 0.65 24.68 1.4
s526 98.87 58,102 98.87 47,883 0 17.58 99.32 43,990 0.45 24.28 1.56
0.310 20.02 1.61 32.61
7 ATPG for Crosstalk Delay Faults Using Multi-objective …
Fig. 7.8 Comparison of 150

execution times (Note
Republished from Vol. 54,
Jayanthy and Bhuvaneswar 100
(2011) with permission from
Advancement of Modelling 50
and Simulation Techniques
in Enterprises (AMSE))
0
1 2 3 4 5 6 7 8 9 10 11 12 13 14
CPU Time-WSGA CPU Time-NSGA-II
As seen, the initial population is widely distributed throughout the objective space.
This population of individuals has to be optimized in both the objectives to determine
large number of Pareto-optimal solutions using the specified algorithm. Though this
method requires more computation effort, it allows a global non-domination check
among the parent and offspring solutions.
NSGA-II provides faster solutions that are almost equidistantly spaced, better
quality of distributed solutions and good convergence and good diversity preserving
ability.
Figure 7.8 gives the comparison chart for CPU execution time of WSGA and
NSGA-II for the 14 benchmark circuits. The execution time of NSGA-II was less
compared to WSGA for all the circuits.
Table 7.2 presents the comparison of proposed ATPG with the results of Aniket
and Arunachalam (2005) and Li and Li (2005) for delay faults. Compared to the
earlier works, it has been observed that NSGA-II-based approach increases the fault
coverage for almost all of the benchmarks circuits. 10,000 vectors are used to simulate
the faults in Aniket and Arunachalam (2005). The proposed NSGA-II-based ATPG
produced much reduced set of test vectors. For circuit c880 with largest number
of inputs 60 the number of test vectors required to detect the faults was 104. The
proposed approach in addition to increase in fault coverage also reduces the number
of transitions.
122
Table 7.2 Comparison with previous works

Circuit Aniket and Arunachalam (2005) Li and Li (2005) Proposed NSGA-II
Target faults Faults Fault Target faults Fault detected Fault Target faults Fault detected Fault
detected coverage (%) coverage (%) coverage
c17 52 51 98.07 – – – 42 42 100%
c432 8736 8534 97.68 – – – 9327 7963 92.08
c880 – – – – – 9279 8915 93.11
s27 132 66 50 – – – 63 62 98.41
s298 1206 112 9.28 286 122 42.66 537 366 68.15
s344 3057 199 6.51 992 560 56.45 1162 1125 96.81
s349 3077 198 6.43 1006 564 56.06 1169 967 82.72
s1196 – – – 1108 347 31.32 10,630 10,115 95.15
s1488 – – – 473 81 17.12 4305 2935 68.17
s1494 – – – 427 72 16.86 4283 2908 67.89
Note Tables 7.1 and 7.2 are republished from vol. 54, Jayanthy and Bhuvaneswar (2011) with permission from Advancement of Modelling and Simulation
Techniques in Enterprises (AMSE)
7 ATPG for Crosstalk Delay Faults Using Multi-objective …
7.6 Conclusion 123
7.6 Conclusion
Lowering power dissipation due to test application is now becoming a focus of intense
academic and industrial research.
In this chapter, two multi-objective genetic algorithms, namely WSGA-based
ATPG and NSGA-II-based ATPG, are proposed which increases the fault cover-
age with reduced switching activity and hence reduces the power consumption in
VLSI circuits. The NSGA-II-based ATPG tests both combinational and scan ver-
sion of sequential circuits. The results demonstrate the effectiveness of the proposed
approach. The method achieved 84 and 97% fault coverage on four combinational
circuits and 80–98% fault coverage on 11 scan version of sequential circuits with
an average of 16% reduction in the number of transitions. Compared to WSGA,
the NSGA-II produced reduced number of transitions with a slight decrease in fault
coverage for most of the benchmark circuits.
Acknowledgments Tables 7.1 and 7.2 and Figs. 7.3, 7.4, 7.5, and 7.8 are reproduced from the
reference Jayanthy and Bhuvaneswari (2011) from Advancement of Modelling and Simulation
Techniques in Enterprises (AMSE). This is gratefully acknowledged.
References
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ary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems (2015). ISBN
978-81-322-1958-3
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P. Girard, Survey of low-power testing of VLSI circuits. IEEE Des. Test Comput., 82–92 (2002)
using genetic algorithm. ICGST Int. J. Artif. Intell. Mach. Learn. AIML 9(2), 11–17 (2009)
testing of crosstalk delay faults in VLSI circuits. Adv. Model. Anal. 54(2), 28–48 (2011)
S. Jayanthy, M.C. Bhuvaneswari, S. Keesarapalli, Test generation for crosstalk-induced delay faults
in VLSI circuits using modified FAN algorithm. VLSI Des. 2012, 10 p (Article ID 745861) (2012).
https://doi.org/10.1155/2012/745861
(2013). ISSN: 1741-5047
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Appl. 21(2), 181–195 (2005)
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of NCSCV’09, vol. 106 (2009)
H. Weste, K. Eshraghian, Principles of CMOS VLSI Design: A Systems Perspective, 2nd edn.
(Addison-Wesley, Reading, MA, 1992)
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Chapter 8
Simulation of Asynchronous Sequential
Circuits Using Fuzzy Delay Model
for Crosstalk Delay Faults
8.1 Introduction
As CMOS technology reaches the deep submicron range and with clock speeds near-
ing the GHz range, concerns have been raised about the suitability of synchronous
designs for next-generation devices due to clock synchronization, power consump-
tion, and noise issues (Al-Assadi and Kakarla 2009). Asynchronous circuits can
successfully tackle many of the problems present in deep submicron technologies
(Efthymiou 2010). Asynchronous circuits have no clock skew, less power consump-
tion, have average-case instead of worst-case performance, timing and design flex-
ibility, electromagnetic compatibility and support automatic adaptation to physical
properties, compared to their synchronous counterparts (Petlin 1994; Hauck 1995;
Hulgaard et al. 1995; Furber 1996; Ronchen 1996). The research in asynchronous
circuits has been mainly focused to synthesis and verification techniques. It is dif-
ficult to simulate/test asynchronous circuits as they become large (Jayanthy et al.
2013).
Due to the lack of suitable CAD tools, the design of asynchronous VLSI circuits
for specific application is different. Moreover, designers of asynchronous systems
must pay attention to the dynamic state of the circuit. Due to the absence of the
clock, care must be taken to make the circuits hazard-free. For complex systems,
these issues become too difficult to handle by hand which necessitates an automated
design procedure (Shanthi et al. 2005).
In asynchronous circuits, elaborate timing relationships must be verified and
tested for any manufacturing defects. The asynchronous circuits cycle through sev-
eral unstable states before settling in a stable state. The final state of the system
may be different depending on the arrival time of the input events and the delays of
the internal gates and interconnection. Hence, an accurate modeling of the delay is
necessary. During simulation of the asynchronous circuits hazards, unstable states,
oscillations, and non-confluence of settling states must be taken into consideration.

126 8 Simulation of Asynchronous Sequential Circuits Using Fuzzy …
In digital circuits, the delays associated with each element are different and may
not be known with precision for a given fabrication technology. The delays of a
logic gate or interconnect are affected by various fabrication process parameters
and however accurate the delay models are, it is very difficult to model the process
uncertainties.
In this chapter, an event-driven simulation technique using a fuzzy delay model
is used for simulation of asynchronous sequential circuits. The fuzzy delay model
can handle uncertainties with respect to timing characteristics and manufacturing
anomalies. It can be used to detect oscillations and non-confluence of settling states,
caused due to delays in the input transitions and gates. A fault simulation based on
fuzzy delay model is used to validate the random test patterns generated for crosstalk
delay faults in asynchronous sequential circuits (Jayanthy and Bhuvaneswari 2015).
Experimental results for SIS benchmark circuits are given.
8.2 Races, Oscillations, and Non-confluence
Asynchronous circuits are difficult to simulate because of hazards, unstable states,

oscillations, and non-confluence of settling states (Hunger 1995; Roig et al. 1997).
Even if oscillations are not present in the original circuits, it may occur when faulty.
One cause for the occurrence of races, hazards, and state oscillations in testing is
that the tests usually consist of non-functional sequences, that is, the function which
the circuit has been designed to perform is not been taken into account in selecting
the test. Oscillations occur when the circuit cannot rest after input signal change.
Non-confluence occurs when the final state of the circuit can be different depending
upon the arrival time of the input events and the delays of the internal gates.
The setting of the asynchronous circuit parameters in different states is obvious
from the example given below: Consider the simple asynchronous circuit shown in
Fig. 8.1. Let the assumption be that the circuit is in the stable state abcdefy 0110111
and the input pattern cd 01 is applied. It cannot be assured that the inputs c and
d may not change at the same time, even if the inputs c and d change at the same
time, because of the delay on the primary inputs there will be a delay at the inputs of
the gates. Hence, depending upon either c or d changes first, the circuit will settle at
state abcdefy 0101100 and abcdefy 0101111, respectively. Thus, circuit settles
at different states depending on the delay of the primary inputs and gates.
Figure 8.2 is given to show the oscillation or cycles of unstable states. Assume
the circuit is in the initial stable state abcd 0001. When the input a 1 is applied,
the circuit oscillates. After a 1, the sequence of transition c ↑d ↓ c↓ d↑ is repeated
and the circuit never settles in a stable state. Thus, the test vectors generated may be
invalidated due to oscillations, unstable state, and non-confluence of settling state.
8.3 Delay Models 127
Fig. 8.1 Asynchronous

d e
circuit with non-confluence
c
y
b
f
a
Fig. 8.2 Asynchronous

circuit with oscillations
a
c
d
b
8.3 Delay Models
Each gate in a circuit incorporates a delay in the signals propagating through it.
Due to delays incorporated in the circuits, the simulated model also should have the
incorporation of delays. Delay modeling is a key element controlling the trade-off
between accuracy and complexity of the simulation algorithm. The passage of time
is an essential part of simulation. At the gate level, time is modeled in a discrete way
and all delays in the circuit are expressed as an integer multiple of some unit.
The output of any physical gate will take some time to switch after the moment
that an input has switched. The delays involved can affect the correct functioning of
the circuit especially when the circuit has asynchronous parts. Therefore, an accurate
modeling of the delays is important.
8.3.1 Types of Delay Models
There have been different types of delay models used in the literature (Chappell and
Yao 1971; Abramovici et al. 1990; Litovski and Wolinski 1997; Gerez 1999). Some
of the commonly used gate delay models are:
i. Zero delay model
ii. Unit delay model
iii. Nominal delay model

iv. Rise/Fall delay model
v. Min–max delay model
vi. Statistical delay model
Zero Delay Model
The simplest way to represent a logic state is to assume that there is no delay in
passing a change of state from an input to an output. The evaluation of the state of
the outputs of the gate is simply the evaluation of Boolean function. This model is very
easy to perform and therefore leads to very rapid simulation. For combinational logic
circuits, a zero delay simulator would only be able to verify the logical correctness
of the design. Timing problems such as hazards would not be identified. This model
is not suitable for asynchronous sequential circuits.
Unit Delay Model
This model assigns a unit delay to each gate in the circuit and a zero delay to the
interconnecting edge. The unit delay model can be used to detect glitches as seen in
the following example, which cannot be done in zero delay models.
Consider the circuit in Fig. 8.3.
If A changes from 0 to 1 and B changes from 0 to 1, C takes a unit delay of time
to change. Therefore, D changes to 1 from 0 due to change in A, for a unit delay of
time and then changes to 0. This glitch cannot be detected in zero delay model.
Nominal Gate Delay Model
The nominal gate delay model associates a fixed delay with the gates output. The
delay of a gate may be affected by the fanout of the gate. In general, a heavily loaded
gate will have a greater delay through it than one driving just one other gate. The
increased delay is primarily due to the extra capacitive load for each fanout gate. Thus,
fanout effect can be modeled by assigning a technology-dependent capacitance, to
each gate input. This model is better than the unit gate delay model, in that each
gate is relatively weighed depending on the size, type, and loading characteristics.
However, the nature and effect of the input transition are not considered in this model.
Rise/Fall Delay Model
In the rise/fall delay model, different delays are used when an output signal rises
(0–1 transition) and when it falls (1–0 transition). This model is more accurate as it
considers the effect of input signal slope, in addition to the loading characteristics.
However, it is more expensive than the normal gate delay model because the delay
Fig. 8.3 Circuit to detect

A D
hazard
C
B
8.3 Delay Models 129
analysis algorithm has to incorporate the signal slope at every node. Typically, the
data sheet for standard circuits’ cell library provides the rising/falling slopes and
the rising/falling intercept parameters for every library cell. The rising and falling
transition delays can be calculated after identifying the number of loads of each gate
using the linear equation:
Gate Delay (rising) SLOPE (rising) × number of loads + INTERCEPT (rising)
Gate Delay (rising) SLOPE (falling) × number of loads + INTERCEPT (falling)
Min–Max Delay Model
This is used in a min–max simulator in which the delay of the gates is specified as a
range. When a device is characterized, it is likely that the exact delays are unknown.
A cell library will describe a gate in terms of minimum, typical, and maximum prop-
agation delays. The min–max delays can be assigned according to the technology,
device type, and loading. But the minimum and maximum delays introduced in the
model provide pessimistic results, as the uncertainties in the transition of the signal
are not encountered in this model.
Statistical Delay Model
In statistical delay model, the delay of each gate is represented as a random variable
(Jyu et al. 1993). The joint probability density function of all the delay variables
is used for statistical timing analysis. However, the analysis is very complex and
computationally expensive. A wire between two gates has a delay that may be mod-
eled. It is possible to model the wire delay by inserting an element into the wire and
assigning a delay to it. Alternatively, the delay may be modeled by adding to the
delay at the output of the driving gate or to the delay at the inputs of the driven gates.
8.4 Fuzzy Delay Model
The delays of a logic gate or an interconnect are effected by various fabrication pro-
cess parameters and however accurate the delay models are it is difficult to model the
process uncertainties. The fuzzy delay model can handle uncertainties with respect
to timing characteristics and manufacturing anomalies. In fuzzy delay model, the
delay is represented by a possibility distribution. The possibility distribution of gate
delay is a statistical function that describes all the possible values and likelihoods
that a gate delay can take within a given range.
The use of fuzzy distribution allows us to
• Have reliable modeling of the uncertainties concerning delays.
• Avoid a systematic assumption of the different possible values of the delays.
• Handle imperfect information concerning delays and can express approximate
information, when a statistical study is difficult to perform.
8.4.1 Fuzzy Delay
In fuzzy delay model (Giambiasi et al. 1994; Jayabharathi et al. 1999), as shown in
Fig. 8.4, the delay F d is represented by a possibility distribution π fdm . In order to have
a model which gives reliable modeling of the imperfect information’s concerning the
delays, π fdm is defined by Eq. (8.1).
⎫
0 if (t ≤ a) or (t ≥ d) ⎪
⎪
⎪
⎬
(t − a)/(b − a) if (a ≤ t ≤ b)
πfdm (t) (8.1)
if (b ≤ t ≤ c) ⎪
⎪
⎪
⎭
(t − d)/(c − d) if (c ≤ t ≤ d)
where the fuzzy dates a, b, c, and d are elements of the reference set T (time scale).
The fuzzy delay F d is defined by the quadruplet (a, b, c, d).
The range of values between a and b, or c and d in the fuzzy delay model in
Fig. 8.4, has a grade of membership function. Thus by using possibility distribution,
the fuzzy delay model provides an environment for a more accurate representation
of uncertainty and vague concepts as compared to the other types of delay models.
Every manufacturing process is characterized using a test chip and the data collected
can be used for developing timing models. The manufacturing defect data can be
collected and used to create defect densities and to analyze layout sensitivities. A
fuzzy rule base can be created using the defect data and the process timing models
(Jayanthy and Bhuvaneswari 2015).
8.4.2 Logic Gate Model
A logic gate is defined by two elements: logic element and the delay element, illus-
trated in Fig. 8.5. The logic element represents the ideal logic gate without delay.
1
Fuzzy
Possibility 0.5
0
a b c d
Time units
Fig. 8.4 Fuzzy delay model

8.4 Fuzzy Delay Model 131
OUTPUT 0’
LOGIC DELAY
INPUT ELEMENT ELEMENT OUTPUT 0
INPUT
Fig. 8.5 Logic gate model
The delay element illustrates the delay of the physical gate. A propagation func-
tion is associated with each element of the model. The logic elements are generally
classified into two types:
Positive gate (e.g., AND, OR)
Negative gate (e.g., NAND, NOR)
8.4.3 Representation of Fuzzy Delay
The union and intersection operator can be used to propagate the fuzzy delays along
a path. For example, consider the OR gate with two inputs i 1 and i 2 and one output
C. Let πi1 and πi2 be the fuzzy delays of the 0–1 transitions of the input i 1 and i 2 ,
respectively. The output 0–1 transition depends on the earliest 0–1 transition on its
inputs. The fuzzy delay of the output transition can be represented using the fuzzy
arithmetic operators max and min as given in Eq. (8.2).
πc0→1 max(min(πi1 , πi2 (−∞, t)), min(πi2 , πi1 (−∞, t))) (8.2)
where πi1 (−∞, t) and πi2 (−∞, t) represent the fuzzy set of time points before the
respective transitions. That is πi1 (−∞, t) represents the condition when the input
i 1 is stable at zero. Equation (9.2) can be generalized to include different gate types
and transitions (Kandel 1986; Dubois and Prade 1989; Giambiasi et al. 1994).
8.5 Discrete Event-Driven Logic Simulation Based

on Fuzzy Delay Model
This section presents a gate-level simulation algorithm for asynchronous sequential

circuits. The delay model used is the fuzzy delay model. The fundamental mode of
operation is assumed, where signals at the primary inputs are allowed to change only
after the signals at the primary outputs have been stabilized. It is assumed that the
gate delay bounds are known in advance for a given circuit and process technology.
The component delays for both rise and fall transitions are represented as fuzzy
delays. The effect of the fanouts and the input slope are considered in generating the
delays. A discrete event simulation model assumes that the system being simulated
changes only at discrete points in simulated time. Each event contains a time stamp
and denotes a change in the state of the system. The simulator typically removes the
smallest time-stamped event from the event list and processes that event. Processing
an event involves executing some simulator code to effect the appropriate change in
state and scheduling one or more events. The simulation technique can be applied to
models other than logic gates (Bhuvaneswari and Sivanandam 2000).
The discrete event simulation of the fuzzy delay model involves two difficulties:
• The logical state changes occur at fuzzy dates covering time intervals that overlap.
• The conceptual model is continuous; a discrete model equivalent has to be defined
(Banks et al. 1996).
To overcome these two difficulties, a discrete event-driven logic simulation model
based on the concepts of states and events is defined (Giambiasi et al. 1994).
8.5.1 Component State
The state of a component D is described by two variables: state-at-logic 0 (state-0d)

1 1 1 (state-1d ). The two variables are defined by the triplets td , πd , ∂d
0 0 0
and state-at-logic
and td , πd , ∂d where for every S belonging to {0, 1}:
tdS is the date at which last change of the variable state-at-Sd occurs
πdS is the degree of possibility that d may be in the state S at the date tdS
∂dS is the slope that orients the function describing the possibility of d to be in the
state S beginning at the date tdS
The degree of possibility π D,T
S
that D may be in the state S at the current date T
is given as Eq. (8.3).

πD,T
S
∂ds ∗ T − tds + πds (8.3)
For example, if the fuzzy delay associated with an event of the signal i 1 changing
from 0 to 1 is Fd (a, b, b, c) as illustrated in the Fig. 8.6a, then the variables state-at-0
and state-at-1 can be characterized as shown in Fig. 8.6b, c.
8.5.2 State Change
A state change in the discrete event simulation model is defined as a discrete change
of at least one of the slopes that orients the function describing the possibility of a
8.5 Discrete Event-Driven Logic Simulation Based on Fuzzy Delay Model 133
Fig. 8.6 a Possibility (a)

distribution representation of
the signal i1 changing from 0
1
to 1, b the membership
function characterizing
state-at-0 of i1 , c the Fuzzy 0.5
membership function Possibility
characterizing state-at-1 of i1 0
a b c
Time units
(b)
Fuzzy 0.5
Possibility
0
b c
Time units
(c)
1
Fuzzy
Possibility 0.5
0
a b
Time units
component to be in the state at logic 0 or 1. An event is associated with this state

change. The date of occurrence of the event is the date at which the slope change
occurs.
8.5.3 Event
An event is defined by quintuplet (t, p, δ, S, D) where (t, p, δ) represents the state

at S of the component D in which the fuzzy event has occurred at fuzzy date t.
For example, consider the input i 1 of a logic gate changing from logic state 0–1
at fuzzy date Fd (1, 2, 2, 3). The initial state-at-0 of i 1 is (0, 1, 0) as illustrated in Fig.
9.7. Two events (2, 1, −1, 0, i 1 ) and (3, 0, 0, 0, i 1 ) are created at the fuzzy dates 2
and 3, respectively, for the state-at-0, as illustrated in Fig. 8.7.
1 Event (2, 1,-1, 0, i1)
Fuzzy 0.5 Event (3, 0, 0, 0, i1)

Possibility
0
1 2 2 3
Time units
Fig. 8.7 Events created at state-at-0 of i1
Similarly, two events (1, 0, 1, 1, i 1 ) and (2, 1, 0, 1, i 1 ) are created at fuzzy dates
1 and 2, respectively, for the variable state-at-1. Thus, four events are created for an
input transition with fuzzy delay Fd .
An event (t, p, δ, e, d) is compatible with state tα0 πα0 , ∂α0 , tα1 , πα1 , ∂α1 of a com-
ponent α when c α, as shown in Eq. (9.4).
⎫
πα0 − π ⎪
δ δα et ∂ 0
0
, if e 0⎪ ⎪
⎬
tα − t
(8.4)
πα1 − π ⎪
⎪
δ δα et ∂ 1
1
, if e 1⎭ ⎪
tα − t
8.5.4 Processing of Events (Giambiasi et al. 1994)
The processing of the events depends on the type of the component D. The component
may be a primary input, input of the logic element, output of the delay element, or the
primary output. The processing of the event E(t, p, δ, S, D) on D is detailed below.
i. D is a primary input: The event E on D may provoke a state change on

each successor α. If α is an output of a logic element of type positive gate
(negative gate),
the possible state change on α is expressed by the event
(t, p, δ, S, α) t, p, δ, S , α , where S is the complement of state-at-S.
ii. D is the output of any logic element: If the event E is compatible with state-at-S
of the component D with fuzzy delay πfd , the event may provoke a state change
on each successor α, i.e., output of the delay element, expressed by the event
(t + t , p, combine (δ, δ ), S, α), where δ is upslope of the πfd if δ > 0 and the
downslope of πfd if δ < 0, t is the time point that corresponds to the possibility
π of δ , as shown in Eq. (6.5).
8.5 Discrete Event-Driven Logic Simulation Based on Fuzzy Delay Model 135
⎫
combine δ, δ δ∗δ
δ+δ
if δ ±∞ and δ ±∞ ⎪
⎪
⎬
δ if δ ±∞ and δ ±∞ ⎪ (8.5)
⎪
⎭
δ otherwise

If the event E is not compatible with state-at-S of α, an E t , p , δ, S, D is produced

the component D, if (t, p, δ) intersects with state-at-S of D where t , p is the
intersection point.
iii. D is the output of a delay element: If the event E is compatible with the state
at S of D, then the event (t, π, a, S, α) or (t, π, a, S , α) is created based on the
type of the gate. If the event E is not compatible with the state at S of D, then
an event E is created on itself.
iv. D is a primary output. If the event E is compatible with state-at-S of the com-
ponent D, the value of state-at-S changes to (t, p, δ).
8.6 Crosstalk Delay Fault Simulation Algorithm
The proposed architecture of the fault simulation algorithm for crosstalk delay fault
is shown in Fig. 8.8. The simulation environment allows the user to easily describe a
logic circuit and to define the input vectors. The kernel manages the main functions
of simulation. This algorithm consists of the following steps:
Step 1: Initialization of the circuit
This step allows the circuit to be initialized for the first test vector and the state of
all the components of the circuit is initialized.
Step 2: Creation of the initial events and initialization of the scheduler
The aim of this step is to create the corresponding events as described in Sect. 8.5.3
for the second test vector. The events are inserted into the event list.
Step 3: Development of the fault simulation
While the schedule is not empty, the following are repeated.
1. Current time takes its value the occurrence time of the event that is at the top of
the schedule.
2. The events having an occurrence time equal to the current time are inserted in
the current events.
3. While current events are not empty do
a. Extract the first event of current time and process it according to the element
concerned. The processing of events is as described in Sect. 8.5.4.
b. If the events have been created then insert those having an occurrence time equal
to value of current time in the current events and the others in the schedule.
Fault list Circuit description

Input vectors
Initial events Internal model
Scheduler Management State change

Management module
Simulator
kernel
Event Result Time

Management Management Management
Fig. 8.8 Architecture of the simulation environment
c. Crosstalk delay faults are read from the fault list. All aggressors for a particular
victim are read and simultaneously checked for activation. Faults are activated
when victim and aggressors have opposite transition. If the fault is activated, the
fault is injected by inserting the victim events in the schedule at a time instant
equal to the estimated delay. The delay is calculated by coupling capacitance and
resistance value from the cell library. Other events are scheduled as for a good
circuit as in step 3.b.
d. The events are processed and if the delay effect is observed at the primary output
event, the fault is detected and removes from the fault list.
Detection of oscillation: The simulation of the circuit that oscillates will result
in repeated scheduling and processing of the same sequence of events, with the
simulation program apparently caught in an endless loop. The detection of oscillation
is performed by counting the number of events generated. When this number exceeds
a predefined value (50), simulator assumes that an oscillation has occurred.
Detection of non-confluence of settling state: When simulation completes
with incompatible probabilities for state-at-0 and state-at-1, it was assumed non-
confluence of settling states has occurred. For example, non-confluence is said to
occur, if the state-at-1 and state-at-0 variables of the primary output have the same
probabilities, i.e., (t, 0, 0) and (t , 0, 0), respectively (Bhuvaneswari and Sivanandam
2001).
Table 8.1 SIS benchmark circuit characteristics

Circuit No. of No. of No. of No. of No. of No. of Total
PIs POs gates + feed- paths critical faults
latches backs paths
alloc_outbound 4 5 15 2 16 3 197
chu172 3 3 9 0 7 1 34
dff 2 1 9 2 8 3 60
isend 4 6 42 6 66 1 390
nak-pa 4 6 20 1 20 1 75
sbuf-send-ct1 3 5 19 3 18 1 177
sbuf-send-pkt2 4 5 18 2 24 1 150
ram-read 5 6 23 3 23 1 109
The serial fault simulator for crosstalk delay faults using fuzzy delay model for gates
was implemented in INTEL core I7 processor with 2.6 GHz and 4 GB RAM using
C language in Linux environment.
The delay for each element was derived using a 45 nm Nangate generic open
cell library Benchmark site 1 (2011). Fuzzy delay model for rising and falling tran-
sitions of the logic gates and zero wire delays are assumed. Random test patterns
(50) are generated using a pseudorandom process for SIS benchmark circuits. The
activated victim events are given a delay calculated by using coupling capacitance
and resistance value from cell library.
Table 8.1 gives the characteristics of SIS benchmark circuits synthesized using
Petrify Benchmark site 2 (2001). The circuit name, the number of primary inputs,
number of primary outputs, number of gates, number of feedback paths, number
of paths, number of critical paths, and the reduced set of target crosstalk faults
corresponding to each circuit are given (Jayanthy et al. 2013).
The random test patterns are validated using unit delay simulator, rise/fall delay
simulator, and fuzzy delay simulator. Table 8.2 gives the comparison results between
unit delay simulator, rise/fall delay simulator, and fuzzy delay simulator. Compared
to unit delay simulator, rise/fall delay simulator gives lower fault coverage for 6 out
of 8 benchmark circuits and for the remaining two circuits nearly the same fault
coverage. Since fault coverage is less, the numbers of transitions are also reduced in
rise/fall delay simulator. Lower fault coverage is reported in rise/fall delay simulator
because the timing is more accurate in rise/fall delay simulator and hence fault effect
at the primary output is also more accurate. The execution time of fuzzy delay fault
simulator is given in seconds.
Compared to unit delay and rise/fall delay simulator, lower fault coverage is
obtained for fuzzy delay simulator for most of the benchmark circuits. This is because
the tests that cause non-confluence of settling states are identified and invalidated by
the fuzzy delay model-based fault simulator. Hence from the results on SIS bench-
Table 8.2 Comparison of fault coverage and number of transitions

Circuit Unit delay Rise/Fall delay Fuzzy delay CPU
Time
Fault No. of Fault No. of Fault No. of Tests
(s)
cover- transi- cover- transi- cover- transi- invali-
age tions age tions age tions dated
(%) (%) (%) (%)
alloc_outbound 46.70 197 46.19 303 44.16 353 4 0.08
chu172 76.47 36 58.82 30 58.82 48 0 0.06
dff 48.33 152 41.67 127 40 164 28 0.18
isend 57.69 75 35.89 73 34.62 276 12 0.29
nak-pa 36 90 36 301 33.33 355 6 0.19
sbuf-send-ct1 69.49 234 21.47 99 13.55 121 20 0.18
sbuf-send-pkt2 70 150 25.33 100 18.66 105 16 0.20
ram-read 62.39 92 38.53 90 37.61 121 12 0.19
Note Part of Table 8.2 is republished from vol. 40, Jayanthy and Bhuvaneswari (2015) with permis-
sion from Sadhana Indian Academy of Sciences
mark circuits, it is concluded that the test validation using fuzzy delay model is more
accurate than unit delay model and rise/fall delay model. The number of transitions
is higher for fuzzy delay simulator compared to rise/fall delay simulator and unit
delay simulator.
8.8 Conclusion
In this chapter, a fuzzy delay model that can handle uncertainty in gate delays is
described. The event-driven simulator based on fuzzy delay model is used to detect
non-confluence of settling states, unstable states, and oscillations. The fuzzy delay
simulator is used to validate the test patterns generated for crosstalk delay faults in
asynchronous circuits and the test results for benchmark circuits are presented.
Acknowledgements Sections 8.4, 8.5, 8.6, and 8.7 and Table 8.1 are reproduced from the reference
Jayanthy and Bhuvaneswari (2015) from Sadhana—Academy Proceedings in Engineering Sciences.
This is gratefully acknowledged.
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Chapter 9
Simulation Based Test Generation
for Crosstalk Delay Faults
in Asynchronous Sequential Circuits
9.1 Introduction
A number of efforts have been recently devoted to fault modeling, fault simulation,
and test generation for asynchronous circuits (Shi and Makris 2004). Simulation-
based approach for testing gate delay faults in asynchronous sequential circuits was
proposed by Sur-Kolay et al. (2000). Shi and Makris (2006) have proposed a test
method for path delay faults based on a design for test strategy. In simulation-based
approach, no backtracking is required but their quality in terms of fault coverage is
less. The quality of simulation-based approach can be improved with the help of GA,
which is suited for optimization and search problems.
In this chapter, the fuzzy delay model-based simulator presented in Chap. 8 is
employed in the two GA techniques for test generation of crosstalk delay faults in
asynchronous sequential circuits. The first technique uses single-objective genetic
algorithm and targets a single objective of maximizing fault coverage. The second
technique uses multi-objective genetic algorithms, namely weighted sum genetic
algorithm and non-dominated sorting genetic algorithm (NSGA-II). In NSGA-II-
based ATPG, a redundancy is introduced during the automatic test generation pro-
cess. The aim in introducing redundancy is to allow NSGA-II to select better test
sequences so as to minimize the number of transitions during test pattern generation.
Redundancy is introduced by modifying the fault dropping phase, where a fault is
dropped only if it is covered by at least M sequences, where M being the redundancy
factor (Bhuvaneswari and Jayanthy 2015).
The multi-objective genetic algorithm targets two objectives of maximizing fault
coverage and minimizing the number of transitions. Experimental results are tab-
ulated for SIS benchmark circuits for three gate delay models, namely unit delay
model, rise/fall delay model, and fuzzy delay model. Uncertainty in delays can be
handled effectively by fuzzy delay model. Fuzzy delay model is used for evaluating
the test patterns. Results are obtained for four crossover operators, namely one-point,
two-point, uniform, and weight-based crossover operators.

142 9 Simulation Based Test Generation for Crosstalk Delay Faults …
9.2 Feedback Identification
A basic technique to simulate asynchronous sequential circuit is to unfold the circuit

in time and simulate the unfolded circuit. Fundamental mode of operation is assumed
where signals at the primary inputs are allowed to change only after the signals at the
primary outputs have stabilized. Feedback loops have to be identified to unfold the
circuit. The feedback algorithm uses a breadth-first approach which leads to lower
number of iterations per frame (Sur-Kolay et al. 2000).
The procedure for identifying feedback loops in the asynchronous circuit is
described. The levelized circuit is traversed starting from the primary inputs. The
level for every fanin of a particular gate is checked with the level of that gate. If the
level of fanin is greater than the level of the gate, then that fanin (feedin) is identi-
fied as feedback element and added to the feedback list. The fanout of the feedback
element is taken as feedout.
The feedbacks are cut, and the pseudo-primary inputs (PPIs) and pseudo-primary
outputs (PPOs) are identified. The feedback element name is split (e.g., if feedback
element is x, it is split as xin and xout), and the corresponding nature is changed
as PPIs and PPOs. PPIs are added to the input list which contains primary inputs,
and PPOs are added to the output list which contains primary outputs. Feed out
of feedback elements are added to the fanout list of pseudo-primary input. PPI is
added to the fanin list of feed outs. The fanin of feed out element is checked to
verify whether it is equal to PPO. If so PPO is removed from the fanin list of feed
out element, then the procedure is repeated until the feedback list becomes NULL
(Jayanthy et al. 2013).
Thus, the asynchronous sequential circuit is converted into time frame of combi-
national circuit with PPI and PPO. Static timing analysis as described in Sect. 9.3 in
Chap. 4 is performed to the converted asynchronous circuits with PPI and PPO. The
static timing analysis gives a reduced list of target crosstalk delay faults.
9.3 Crosstalk Delay Fault Simulator for Asynchronous

Sequential Circuits
Given a test vector sequence as inputs, the objective of the fault simulator is to
determine which of the target crosstalk delay faults are detected. The basic simulator
is a time wheel-based event-driven simulator which is modified to activate, inject,
and propagate crosstalk delay faults to the primary output. The algorithm for fault
simulation of crosstalk delay faults for asynchronous sequential circuits is described
below
Step 1: Initially, all the inputs have their values as do not care (x). The simulator reads
in a new test vector which is assigned to the primary inputs. The pseudo-primary
inputs are initialized to logic 0. The circuit is simulated until primary outputs reach
a stable value. When primary output becomes stable, the final output value of fanin
9.3 Crosstalk Delay Fault Simulator for Asynchronous Sequential Circuits 143
gate of every feedback is given as the next input value for the corresponding fanout
gate, and the primary input is set to the next test vector and good circuit simulation
is done for the next time frame.
Step 2: This is followed by crosstalk delay fault simulation. Crosstalk delay faults
are read from the fault list. All aggressors for a particular victim are read and simul-
taneously checked for activation. Faults are activated when victim and aggressors
have opposite transition.
Step 3: If the fault is activated, the fault is injected by delaying the victim alone by
a time step equal to calculated delay value. Other events are scheduled as for a good
circuit. Two versions of crosstalk delay fault simulators for asynchronous circuits
were developed. In the first version, gates were assumed unit delay and the activated
victim was given one unit delay (unit delay simulator). In the second version (rise/fall
delay simulator), gates are assigned a rise/fall delay and activated victim is given a
delay derived using coupling capacitance and resistance value derived from 45 nm
Nangate generic open cell library.
Step 4: The simulation is continued until the end of time frame. If delay effect is
observed at the primary output, the fault is detected and removed from the fault list.
This is done at the end of each simulated time frame. If the fault is detected, then
the victim and activated aggressors pairs are removed from the fault list. The test
sequence is added to the test set. The steps are repeated until the test set is empty.
9.4 GA-Based ATPG
GA-based ATPG discussed in Chap. 5 is applied to asynchronous sequential circuits.

To find the fitness of each test sequence, the crosstalk delay fault simulator based on
fuzzy delay model discussed in Chap. 8 is used.
Fitness No. of faults detected

+ No. of faults the produce a delay effect at pseudo primary output.
The results are compared with the results of GA-based ATPG using unit delay
and rise/fall delay crosstalk fault simulator for asynchronous circuits.
9.4.1 Experimental Results
GA-based ATPG is applied to several SIS benchmark circuits. GA-based test gen-
erator is implemented in INTEL core I7 processor with 2.6 GHz and 4 GB RAM
using C language in Linux environment. Results are obtained using crosstalk fault
simulator based on fuzzy delay model.
Table 9.1 Crossover scheme comparison: number of transitions

Circuit No. of No. of transitions No. of test
faults vectors
detected Uniform One-point Two-point WCO
alloc_outbound 122 325 315 324 325 24
chu172 26 203 229 221 203 30
dff 41 338 332 310 341 48
isend 228 721 730 736 699 24
nak-pa 48 610 628 668 660 72
sbuf-send-ct1 115 647 664 654 664 48
sbuf-send-pkt2 102 604 694 618 608 72
ram-read 60 460 530 538 542 24
The GA parameters affect the quality of the results and the CPU execution time.
The CPU execution time is proportional to the population size and number of gen-
erations. Experiments are conducted for various population sizes, number of gener-
ations, to determine the values which give good results at reasonable computation
time and better fault coverage with less number of transitions. The number of gener-
ations is assumed to be 3 for smaller benchmark circuits and 5 for larger benchmark
circuits. A population size in the range of 2–8 was used. A crossover probability of
1 and mutation probability of 0.1 are used. The selection scheme used is the binary
tournament selection.
Table 9.1 depicts the results of GA-based ATPG for the four crossover schemes,
namely uniform crossover, one-point crossover, two-point crossover, and weight-
based crossover. The bold number represents minimum number of transitions for each
circuit. Of the four crossovers, uniform crossover gives less number of transitions
for 5 out of 8 benchmark circuits. The number of test vectors and the fault coverage
were nearly equal for all the crossover schemes.
Experimental results obtained using unit delay simulator, rise/fall delay simulator,
and fuzzy delay simulator are summarized in Table 9.2. In the unit delay, crosstalk
delay fault simulators for asynchronous sequential circuits gates were assumed unit
delay and delay injected is also one unit. In the rise/fall delay, crosstalk delay fault
simulators for asynchronous sequential circuits gates were assigned a rise/fall delay
and delay to be injected is calculated by coupling capacitance and resistance value
(Jayanthy and Bhuvaneswari 2013). Tests are generated using GA-based ATPG with
uniform crossover. The number of faults detected and the number of transitions are
compared. The fault coverage decreases for GA-based ATPG using rise/fall delay
fault simulator because the timing is more accurate. Therefore, the number of transi-
tions for GA-based ATPG using rise/fall delay fault simulator is also less compared
to unit delay simulator. CPU time is higher for GA-based ATPG using rise/fall delay
fault simulator. GA-based ATPG using fuzzy delay simulator gave comparatively
lower fault coverage because test vectors that cause non-confluence of settling states
9.4 GA-Based ATPG 145
Table 9.2 Experimental results for GA-based ATPG

Circuit Unit delay Rise/fall delay Fuzzy delay
Fault No. of Fault No. of Fault No. of
coverage transitions coverage transitions coverage transitions
(%) (%) (%)
alloc_outbound 81.21 382 69.54 269 61.92 325
chu172 97.05 181 91.17 166 76.47 203
dff 76.66 349 73.33 282 68.33 338
isend 63.07 688 59.84 466 58.46 721
nak-pa 77.33 645 66 577 64 610
sbuf-send-ct1 75.14 677 66.10 675 64.97 647
sbuf-send-pkt2 84 907 72 416 68 604
ram-read 67.89 486 57.71 436 55.04 460
are identified (Jayanthy and Bhuvaneswari 2015). Fuzzy delay fault simulator is more
accurate than unit delay and rise/fall delay fault simulators.
9.5 WSGA- and NSGA-II-Based ATPG
Multi-objective genetic algorithms WSGA-based ATPG, NSGA-II based ATPG, and

NSGA-II-based ATPG with redundancy discussed in Chap. 7 are applied to asyn-
chronous sequential circuits and results observed. Redundancy is introduced by mod-
ifying the fault dropping phase, where a fault is dropped only if it is covered by at
least M sequences, where M being the redundancy factor. Hence, for each generation
the fault list is forwarded and redundancy fault dropping approach is used. The faults
that are detected only by the end population are removed from the fault list.
Two objectives that are optimized are the fault coverage and the number of tran-
sitions.
The fitness function used in WSGA-based ATPG is given in Eq. (9.1).
Fitness (w1 ∗ NFi ) + (w2 ∗ NTr ) (9.1)
where NFi is the sum of the number of faults detected at primary output and delay
effect at pseudo-primary output, NTr is the number of transitions, w1 0.6, w2
0.4
The fitness function used in NSGA-II-based ATPG is given in Eqs. (9.2) and (9.3).
F1 TFi − NFi (9.2)

F2 NTr (9.3)
where TFi is the number of faults that is given to the i-th test sequence, NFi is the
number of faults covered by that test sequence plus the delay effect at the pseudo-
primary output, and NTr is the number of transitions during the application of the
i-th test sequence. To find the fitness, that is, the fault coverage and the number of
transitions of each test sequence, the fuzzy delay fault simulator is used.
9.5.1 Experimental Results
WSGA-based ATPG, NSGA-II-based ATPG, and NSGA-II-based ATPG with redun-

dancy are applied to several SIS benchmark circuits. The test generators are imple-
mented in INTEL core I7 processor with 2.6 GHz and 4 GB RAM using C language in
Linux environment. Experimental results for WSGA-based ATPG, NSGA-II-based
ATPG, and NSGA-II-based ATPG with redundancy are taken using fuzzy delay sim-
ulator. The results obtained are compared with rise/fall delay simulator and unit delay
simulator.
The number of generations is assumed to be 2 or 3 for smaller benchmark circuits
and 4 or 5 for larger benchmark circuits. A population size in the range of 2–4 is
used. A crossover probability of 1 and mutation probability of 0.1 are used. The
selection scheme used is the binary tournament selection. The redundancy factor of
5 is chosen. By experimental results, it is observed that this redundancy factor gives
better fault coverage with less number of transitions for all the benchmark circuits.
Experimental results illustrated in Table 9.3 are performed using the WSGA-based
test generator. Results for the four crossover operators, namely uniform crossover,
one-point crossover, two-point crossover and weight-based crossover are tabulated.
The bold number represents minimum number of transitions for each benchmark
circuit. Of the four crossover schemes, uniform crossover gives less number of tran-
sitions for 4 out of 8 benchmark circuits. The fault coverage and CPU time are nearly
equal for all the crossover schemes since the same progress limit for test generation
is used.
Experimental results using NSGA-II-based ATPG are depicted in Table 9.4. The
number of faults detected and the number of transitions for the various crossover
schemes are compared. The bold number represents minimum number of transitions
for each circuit. Of the four crossover schemes, uniform crossover gives less number
of transitions for 5 out of 8 benchmark circuits.
9.5 WSGA- and NSGA-II-Based ATPG 147
Table 9.3 Experimental results for WSGA-based ATPG

Circuit No. of faults No. of transitions
detected
Uniform One-point Two-point WCO
alloc_outbound 122 314 315 324 324
chu172 26 200 229 203 195
dff 41 326 307 308 333
isend 228 680 613 630 664
nak-pa 48 544 611 634 640
sbuf-send-ct1 115 585 626 639 629
sbuf-send-pkt2 102 583 584 537 556
ram-read 60 458 502 520 524
Table 9.4 Experimental results for NSGA-II-based ATPG

Circuit No. of faults No. of transitions
detected
Uniform One-point Two-point WCO
alloc_outbound 121 208 210 211 211
chu172 27 199 202 195 194
dff 36 102 112 114 119
isend 216 517 518 524 526
nak-pa 55 439 422 441 431
sbuf-send-ct1 117 296 293 294 298
sbuf-send-pkt2 109 507 526 529 519
ram-read 64 276 278 314 314
Redundancy is introduced in the fault dropping phase of NSGA-II-based ATPG

where a fault is dropped only after it is detected by 5 sequences where 5 is chosen
as the redundancy factor. Redundancy factor is selected carefully because both the
test generation time and reduction in the number of transitions depend on this. By
experimental trial, redundancy factor of 5 is chosen. The results are tabulated in
Table 9.5. The number of faults detected and the number of transitions for the various
crossover schemes are compared. The bold number represents minimum number of
transitions for each circuit. Of the four crossover schemes, uniform crossover gives
less number of transitions for 5 out of 8 benchmark circuits. The fault coverage
and the number of test vectors are nearly equal for all the crossover operators. The
CPU time in seconds gives the execution time of the NSGA-II-based ATPG with
redundancy. The CPU time is nearly equal for all the test generators.
Table 9.6 summarizes the results for NSGA-II-based ATPG with redundancy using
unit delay simulator, rise/fall delay simulator, and fuzzy delay simulator. Results are
obtained using uniform crossover. The number of faults detected and the number of
transitions are compared. The fault coverage decreases for NSGA-II-based ATPG
using rise/fall delay fault simulator, and hence, the number of transitions is also
Table 9.5 Experimental results for NSGA-II-based ATPG with redundancy

Circuit No. of No. of transitions No. of CPU
faults Uniform One- Two- WCO test time (s)
detected point point vectors
alloc_outbound 115 102 104 105 105 16 0.27

chu172 27 91 94 87 89 32 0.27
dff 32 58 59 60 61 8 0.19
isend 216 253 252 260 258 16 0.56
nak-pa 45 167 168 170 168 32 0.36
sbuf-send-ct1 112 126 123 131 128 32 0.23
sbuf-send-pkt2 108 223 242 264 224 32 0.38
ram-read 62 217 221 229 230 24 0.27
Table 9.6 Test results using NSGA-II-based ATPG with redundancy

Circuit Unit delay Rise/fall delay Fuzzy delay
Fault No. of Fault No. of Fault No. of
coverage transitions coverage transitions coverage transitions
(%) (%) (%)
alloc_outbound 83.75 106 76.64 66 58.37 102
chu172 85.29 94 79.41 81 79.41 91
dff 68.33 78 55 39 53.33 58
isend 62.30 141 56.92 130 55.38 253
nak-pa 68 184 65.33 150 60 167
sbuf-send-ct1 71.18 112 63.84 70 63.27 126
sbuf-send-pkt2 76.66 192 74 224 72 223
ram-read 66.05 159 58.71 152 56.88 217
less compared to NSGA-II-based ATPG using unit delay simulator. CPU time is
higher for NSGA-II-based ATPG using rise/fall delay fault simulator. Compared to
the other two test generators, GA-based ATPG using fuzzy delay simulator gives
comparatively lower fault coverage. This is because test patterns that cause non-
confluence of settling states are invalidated using fuzzy delay simulator.
Table 9.7 shows percentage increase in fault coverage and percentage reductions in
transitions for NSGA-II-based ATPG and NSGA-II-based ATPG with redundancy
over WSGA-based ATPG. The bold number represents the maximum number of
faults detected and minimum number of transitions obtained for each circuit, respec-
tively. The results are taken with uniform crossover. It is observed that with a slight
increase in the fault coverage of 1.23% NSGA-II-based ATPG achieves a reduction
in transition activity of 31.01%. When redundancy is introduced in the NSGA-II-
based ATPG, the fault coverage is decreased by 2.32% but the method achieved a
good reduction in the number of transitions of about 66.15%.
Table 9.7 Comparison of fault coverage and number of transitions
Circuit WSGA-based ATPG NSGA-II-based ATPG NSGA-II-based ATPG with redundancy
Fault coverage No. of Fault coverage No. of Increase in Decrease in Fault coverage No. of Decrease in Decrease in
(%) transitions (%) transitions fault coverage transitions (%) transitions fault coverage transitions
over WSGA over WSGA over WSGA over WSGA
(%) (%) (%) (%)
9.5 WSGA- and NSGA-II-Based ATPG
alloc_outbound 61.92 315 61.42 208 −0.5 33.96 58.37 102 3.55 67.61
chu172 76.47 200 79.41 199 2.94 0.005 79.41 91 −2.94 54.5
dff 68.33 326 60 102 −8.33 68.71 53.33 58 15 82.20
isend 58.46 680 55.38 517 −3.08 23.97 55.38 253 3.08 62.79
nak-pa 64 544 73.33 439 9.33 19.30 60 167 4.0 69.30
sbuf-send-ct1 64.97 585 66.10 296 1.13 49.40 63.27 126 1.7 78.46
sbuf-send-pkt2 68 583 72.66 507 4.66 13.03 72 223 −4.0 61.74
ram-read 55.04 458 58.71 276 3.67 39.73 56.88 217 −1.84 52.62
1.23 31.01 2.32 66.15
Note Tables 9.3, 9.4, 9.5, 9.6, and 9.7 are republished from Vol. 40, Jayanthy and Bhuvaneswari (2015) with permission from Sadhana Indian Academy of
Sciences
149
9.6 Conclusion
In this chapter, single-objective genetic algorithm and multi-objective genetic algo-

rithms, namely weighted sum genetic algorithm, NSGA-II, and NSGA-II with redun-
dancy are developed for use in asynchronous sequential test generation. Experimental
results for SIS benchmark circuits are reported. High fault coverage is obtained for
most of the benchmark circuit. Test generator based on NSGA-II with redundancy
reduces the number of transitions by 66.15% with a slight decrease in fault coverage
compared to WSGA-based ATPG.
Acknowledgements Tables 9.3, 9.4, 9.5, 9.6, and 9.7 and Analysis Sects. 9.4 and 9.5 of the results
are reproduced by Jayanthy and Bhuvaneswari (2015) from Sadhana Academy Proceedings in
Engineering Sciences. This is gratefully acknowledged.
Some parts of the chapters are reproduced from Jayanthy S. and Bhuvaneswari M.C. “Development
of Algorithms for Test Generation and Simulation of Crosstalk Delay Faults in VLSI Circuits”
Ph.D. Dissertation, ANNA University, Chennai, 2012. This is gratefully acknowledged.
References
M.C. Bhuvaneswari, S. Jayanthy, Cross-talk delay fault test generation, in Application of Evolu-
tionary Algorithms for Multi-objective Optimization in VLSI and Embedded Systems (Springer,
2015), ISBN 978-81-322-1958-3
(2013)
S. Jayanthy, M.C. Bhuvaneswari, Fuzzy Delay Model Based Fault Simulator for Crosstalk Delay
Fault Test Generation in Asynchronous Sequential Circuits, vol. 40, Part 1 (Sadhana Indian
Academy of Sciences, Feb 2015), pp. 107–119
F. Shi, Y. Makris, SPIN-SIM: logic and fault simulation for speed-independent circuits, in Proceed-
ings of International Test Conference (2004)
F. Shi, Y. Makris, Testing delay faults in asynchronous handshake circuits, in Proceedings of
ICCAD’06 (5–9 Nov 2006)
S. Sur-Kolay, M. Roncken, K. Stevens, P.P. Chaudhuri, R. Roy, Fsimac: a fault simulator for asyn-
chronous sequential circuits, in Proceedings of the 9th Asian Test Symposium (2000), pp. 114–119
Chapter 10
Summary and Suggestions for Future
Research
10.1 Summary
The deep submicron technologies are challenging test in a number of areas. The
fabrication cost of transistors continues to reduce while the cost of testing is not
scaling. Geometries shrink while the defect sizes do not shrink in proportion. The
increase in wiring levels demands new fault models. Many of the design problems due
to deep submicron technology which include distributed delay variations, crosstalk-
induced delay and logic errors, excessive voltage drop, and swing on power nets have
become test problems as well. The problem of test generation due to this deep submi-
cron parametric variation belongs to the class of non-deterministic polynomial (NP)
complete problems, and it is becoming more complex as complexity of integrated
circuit increases. Hence, to ensure the proper functionality and reliability of VLSI
circuits, complicated design and effective test methods are the requirements. Efforts
are required to analyze and to develop test methods for crosstalk, delay, and power
dissipation in current technology moving into an ultra-DSM and nanotechnology.
Of the various noise sources, signal integrity problems due to increasing cross-
coupling will have a significant adverse effect on the proper functioning and perfor-
mance of VLSI systems. The number of design and analysis tools is available in the
literature to minimize the effects of crosstalk. However, it is not possible to predict
all the manufacturing defects and process variations in advance that may increase the
cross-coupling effects. Hence, there is a need for testing manufacturing anomalies to
screen out defective parts. The development of efficient test generation methodolo-
gies for crosstalk delay faults has been an active area of research. A survey of related
literature revealed that there is a considerable scope for the development of algo-
rithm for test generation and simulation of crosstalk delay faults in combinational
and sequential circuits.

152 10 Summary and Suggestions for Future Research
Chapter 1 gives the test challenges in deep submicron technologies and the neces-
sity for test generation for crosstalk faults. A review of the various crosstalk fault
models is done. There are two main types of crosstalk effects: crosstalk-induced
pulses and crosstalk-induced delay. In this work, crosstalk-induced delay is consid-
ered. If a coupling effect is present between interconnect lines, then a signal transition
on one aggressor line may cause coupling noise on the victim line. A signal transition
on an aggressor may cause a slowdown or speedup of the signal transition on the
victim. If the aggressor and victim line have transition in the opposite direction, then
there will be increase in delay referred to as crosstalk slowdown. If the delay effect is
propagated to the primary output, it would affect the timing of the circuit and cause
the chip to fail. Crosstalk may affect the scan flip-flops causing errors in test results
(Vishal et al. 2006).
In Chapter 2, test generation algorithms for delay faults that effect timing behavior
of VLSI circuits are discussed. In Chapter 3, a review of test generation algorithms
for crosstalk delay faults is described.
Since the number of crosstalk delay faults may be extensive, techniques are devel-
oped to select a small set of target faults. Hence, in Chapter 4, static timing analysis is
performed to obtain a reduced list of crosstalk delay faults. The static timing analysis
uses the logical-level implementation of the circuit. Using both the topological and
timing information of digital circuits, static timing analysis derives a set of target
crosstalk delay faults. The input to the test generator is the target fault list derived
from static timing analysis. In this work, single victim and multiple aggressors having
transitions in the opposite direction are considered.
The objective of test generation algorithm is to generate patterns that will produce
delay at the victim by activating multiple aggressors to detect the delay faults caused
due to crosstalk. Seven-valued logic system is used where two vectors can be derived
simultaneously with a single copy of the circuit.
In test generation for crosstalk delay faults, for each crosstalk delay fault to be
detected, three objectives have to be satisfied.
Objective 1: A rising transition or falling transition in the victim line.
Objective 2: The victim and aggressors should have opposite transition to produce
slowdown effect.
Objective 3: Sensitizing the off-path inputs along the chosen critical path to propagate
the delay affect to the primary output.
Since the number of objectives is to be satisfied is larger compared to test gen-
eration of stuck-at faults, a modified FAN algorithm is proposed for test generation
for crosstalk delay faults. The multiple backtrace procedure adopted in FAN algo-
rithm concurrently traces more than one path and is more efficient than the backtrace
along a single path. In FAN algorithm, the assignment is done at the fanout points
and circuit is simulated for any contradiction at the fanout point instead of tracing
to the primary output, thus avoiding unnecessary computations. Hence, the number
of backtraces is reduced. Therefore, execution time of test generation algorithm is
much reduced. A transition observability cost is computed for each critical path,
and the critical path with minimum observability cost is selected to propagate the
10.1 Summary 153
crosstalk delay fault. This reduces the number of transitions thus reducing the power
dissipation of the circuit.
The test generation algorithm for crosstalk delay faults was tested on ISCAS’85
combinational circuits, several enhanced scan version of ISCAS’89 sequential cir-
cuits, and ITC’99 benchmark circuits. The modified FAN-based ATPG was imple-
mented in C language on an IBM compatible PC under the LINUX environment. To
demonstrate the efficiency of the algorithm, a modified PODEM-based ATPG was
developed. The experimental results using modified FAN-based ATPG and modified
PODEM-based ATPG indicate that modified FAN-based ATPG increases the fault
coverage with reduced number of transitions. The modified version of FAN algo-
rithm reduces the average number of backtraces, and hence, the CPU time reduces
significantly compared to modified PODEM-based ATPG.
Test generation using deterministic algorithm is highly complex and time-
consuming. To obtain a particular output value for a component backtracing is
required to determine its input values. In a simulation-based approach, processing
occurs in the forward direction only. Hence, the execution time is greatly reduced.
Evolutionary algorithms have been investigated as an efficient approach for test gen-
eration, as they mimic nature’s evolutionary principles to drive its search toward an
optimal solution faster. In Chapter 5, single-objective genetic algorithm is used for
test generation of crosstalk delay faults. Tests are generated for ISCAS’85 combina-
tional circuits, enhanced scan version of ISCAS’89 sequential circuits, and ITC’99
benchmark circuits. A crosstalk delay fault simulator is used to validate the test pat-
terns generated. Two versions of the crosstalk delay fault simulators are developed.
In the first version, gates are assumed to have unit delay and the activated victim is
given a delay of one unit. In the second version, gates are assigned a rise–fall delay
and activated victim is given a calculated delay. The delay is calculated from cou-
pling capacitance and resistance value derived from 45-nm Nangate generic open
cell library. Experimental results for four crossover operators, namely one-point
crossover, two-point crossover, uniform crossover, and weight-based crossover, are
detailed. Comparison of the results with modified FAN-based ATPG indicates that
the GA-based ATPG gives a better fault coverage in reduced CPU time for most of
the benchmark circuits.
Particle swarm optimization is also an evolutionary algorithm like GA, which
is inspired by intelligent, social flocking behavior of birds. It is a population-based
search strategy that can be used to find solutions from a large search space. The
population consists of test vectors (particles), which are randomly initialized and are
applied for the test problem. In Chapter 6, single-objective particle swarm optimiza-
tion algorithm is used for generating tests for crosstalk delay faults. Tests are gener-
ated for ISCAS’85 combinational circuits and enhanced scan version of ISCAS’89
sequential circuits. Comparison of the results with random vectors shows that PSO
gives a better fault coverage with reduced execution time.
Most of the real-world problems involve one or more objectives that are to be maxi-
mized or minimized simultaneously. The presence of the conflicting objectives is nat-
ural in many test problems and makes the optimization NP hard. The multi-objective
optimization techniques are used for optimizing multiple objectives simultaneously
that resort to a number of trade-off optimal solutions called pareto-optimal solutions.

Chapter 7 proposes two multi-objective genetic algorithms, namely weighted sum
genetic algorithm, non-dominated sorting genetic algorithm-II and non-dominated
sorting genetic algorithm-II with redundancy for test generation of crosstalk delay
faults. Tests are generated for ISCAS’85 combinational circuits and enhanced scan
version of ISCAS’89 sequential circuits. Experimental results are given for uniform
crossover and crossover probability as 1. Experimental results indicate that NSGA-
II-based ATPG with redundancy gives a better fault coverage with reduced number
of transitions in reduced CPU time for most of the benchmark circuits compared to
WSGA-based ATPG.
The accuracy of the crosstalk delay fault simulator depends on the delay models
used in the simulation. As design trends move toward nanometer technologies, more
number of new parameters affects the delay of the component. Fuzzy delay models
are ideal for modeling the uncertainty found in the design and manufacturing steps.
In Chap. 8, a crosstalk delay fault simulator based on fuzzy delay model is developed
for asynchronous sequential circuits. The fault simulator based on fuzzy delay detects
unstable states, oscillations, and non-confluence of settling states in asynchronous
circuits. Random test patterns are validated using unit delay, rise–fall delay, and
fuzzy delay simulator. Experimental results for SIS benchmark circuits demonstrate
the efficiency of the fuzzy delay simulator in comparison with the unit delay and
rise–fall delay simulation. The delay for each element is derived using a 45-nm
Nangate generic open cell library. The test sequences that cause non-confluence of
settling states in asynchronous circuits are identified and invalidated by the fuzzy
delay simulator.
As clock rates have increased and feature size has decreased, clock skew has
become a major problem in digital logic circuits. To achieve acceptable skew, larger
portions of the area in high-performance circuits need to be dedicated to clock
drivers, which cause an increase in power dissipation. Designers are considering
asynchronous circuits as a potential solution to these problems because they are
modular and do not require clock synchronization (Van Berkel et al. 1999). Further
asynchronous circuits are more robust to noise, temperature, and process variations
and have low electromagnetic emission (Unger 1995). In Chap. 9, ATPG algorithms
in GA, WSGA, and NSGA-II framework are formulated and tested for asynchronous
sequential circuits. Results on the SIS benchmark circuits indicate good quality tests
in comparison with the random test vectors. A crosstalk delay fault simulator based
on fuzzy delay model is used to find the fitness function. Test generator based on
NSGA-II with redundancy reduces the number of transitions with a slight decrease
in fault coverage compared to WSGA-based ATPG.
10.2 Suggestions for Future Research 155
10.2 Suggestions for Future Research
• GA is a powerful search technique that is used to solve complex optimization

problems. Optimization refers to finding one or more feasible solutions which cor-
respond to extreme values of one or more objectives (Deb 2002). Multi-objective
genetic algorithm is used for simultaneously optimizing several objectives. The
multi-objective genetic algorithms discussed in this thesis are used for optimizing
two objectives, namely the fault coverage and the number of transitions. These
multi-objective genetic algorithms can be extended for optimizing more number
of objectives, namely area and execution time simultaneously.
• The accuracy of timing verification depends on the proper modeling of the gate
delays. With the advent of deep submicron technology, more parameters affect the
delay of the gates. The fuzzy delay model can be used for identifying the critical
paths in static timing analysis of VLSI circuits. Uncertainty implicit in the design
and manufacturing flow is handled effectively by this delay model.
• The execution time for serial crosstalk delay fault simulator for larger bench-
mark circuits is high. CPU time can be improved by using parallel or concur-
rent crosstalk fault simulator. Parallel implementations can potentially provide
significant speedups while retaining good quality results (Knysh and Kureichik
2010; Klenke et al. 1992). The implementation of event-driven simulation in par-
allel environment has been successful (Banerjee 1994). Further, the crosstalk fault
model can be improved to include resistive bridging faults.
• If layout information is available, it can be used in static timing analysis to fur-
ther reduce the set of target crosstalk delay faults. Physical layout would contain
information about the coupling capacitance between interconnects, gate input-to-
output, and interconnect delays.
• The crosstalk delay fault test generator can be extended to include multiple victim
lines (Zhongliang and Ling 2013).
• During timing analysis, power supply noise effects can be considered. Since the
noise effects are highly input pattern dependent, traditional timing analysis cannot
consider these effects. Use of dynamic timing analysis is a possible solution (Krstic
et al. 2001).
• Timing-aware test generation methods can be developed taking power supply noise
and process variations into account (Peng et al. 2013).
References
P. Banerjee, Parallel Algorithms for VLSI Computer-Aided Design (PTR Prentice Hall, New Jersey,
1994)
K. Deb, Multi-objective Optimization using Evolutionary Algorithms (Wiley, Chichester, 2002)
K. Peng, M. Yilmaz, K. Chakrabarty, M. Tehranipoor, Crosstalk- and process variations-aware high-
quality tests for small-delay defects. IEEE Trans. Very Large Scale Integr. (VLSI) Syst. 21(6),
1129–1142 (2013)
R. Klenke, R.D. Williams, J. Aylor, Parallel processing techniques for automatic test pattern gen-
eration. IEEE Comput. 25(1), 71–84 (1992)
D.S. Knysh, V.M. Kureichik, Parallel genetic algorithms: a survey and problem state of the art. J.
Comput. Syst. Sci. Int. 49(4), 579–589 (2010)
A. Krstic, Y.-M. Jiang, K.-T. Cheng, Pattern generation for delay testing and dynamic timing analysis
considering power-supply noise effects. IEEE Trans. CAD 20(3), 416–425 (2001)
P. Zhongliang, C. Ling, An approach to generate tests for multiple victim lines of crosstalk faults
in integrated circuits. J. Theor. Appl. Inf. Technol. 50(2) (2013)
S.H. Unger, Hazards, critical races, and metastability. IEEE Trans. Comput. 44(6), 754–768 (1995)
C.H. Van Berkel (Kees), M.B. Josephs, S.M. Nowick, Applications of asynchronous circuits. Proc.
IEEE 87(2), 223–233 (1999)
Vishal J. Mehta, M. Marek-Sadowska, K-H. Tsai, J. Rajski, Timing Defect Diagnosis in Presence
of Crosstalk for Nanometer Technology, International Test Conference, (IEEE, 2006)

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S. Jayanthy · M. C.

Test Generation of Crosstalk

ISBN 978-981-13-2492-5 ISBN 978-981-13-2493-2 (eBook)

Library of Congress Control Number: 2018954035

© Springer Science+Business Media Singapore 2019

Organization of the Book

Coimbatore, India S. Jayanthy

3.3 Test Generation for Crosstalk Pulses . . . . . . . . . . . . . . . . . . . . 42

6.4 Experimental Results . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 106

9.4 GA-Based ATPG . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 143

Dr. S. Jayanthy is Professor in the Department of Electronics and Communication

© Springer Science+Business Media Singapore 2019 1

1.2 VLSI Design Flow

Fig. 1.1 Typical design flow

Logical verification and

1.3 VLSI Testing

1.4 Test Challenges for Deep Submicron Technologies

1.5 Crosstalk Effects

Fig. 1.2 a Positive pulse, b (a) (b)

Fig. 1.3 a Crosstalk (a) (b)

1.6 Crosstalk Fault Models

Fig. 1.4 Circuit showing

tributed capacitance was modeled by a coupling capacitance between the aggressor

Fig. 1.5 Capacitive Ra1

© Springer Science+Business Media Singapore 2019 15

2.2 Delay Fault Models

2.2.1 Transition Fault Model

Fig. 2.1 Circuit with transition fault

2.2.2 Gate Delay Fault Model

Fig. 2.3 Circuit with delay fault at the output

2.2.3 Line Delay Fault Model

2.2.4 Path Delay Fault Model

Fig. 2.4 A robustly testable path

2.2.5 Segment Delay Fault Model

2.3 Test Application Schemes

Input Combinational Output

Fig. 2.5 Testing scheme for combinational circuits

2.3.1 Standard Scan Circuits

Primary input PI Primary Output

time-frame n-1 time-frame n time-frame n+1

Fig. 2.6 Testing scheme for sequential circuits

In skewed-load approach, the second vector is obtained by shifting the contents

2.3.2 For Non-Scan Circuits

2.4 Test Generation Methods for Path Delay Fault Model

2.4.1 Path Delay Fault Simulation

test pattern detects can be approximately calculated by counting the number

2.4.2 Test Generation for Path Delay Faults

Most test generators use a modified version of PODEM.

Generate random iniƟal populaƟon

Perform a simulaƟon using Binary

Any new PDF detected by the test

Yes Is the stop

Generate next generation of

Fig. 2.7 Flowchart of simulation-based test generation algorithm

Fig. 2.8 Circuit for evaluating the fault coverage

method is faster than branch-and-bound algorithms. The disadvantage is the memory

Several design techniques such as repeater insertion, shielding techniques, device

© Springer Science+Business Media Singapore 2019 37

3.2 Test Generation Algorithms

Table 3.1 Eleven-valued Symbols Description

Test generation(fault list)

if(Are all PI combinations covered?)

If(Can the initial objective line under current assigned value of

Backtrack and change PI assignments