1.

Implement an 8x4 unsigned multiplier by using 4x2 AMMs (Make detailed connections) and calculate the
delay in units of FA (Full Adder) by neglecting AND gate delay)
2. (20%) Implement a 4x3 unsigned array multiplier by Full adders(FAs), Half adders(HAs), and AND
/NAND/NOT gates (Each gate has 1 unit delay). Show your algorithm, Calculate the delay units in each
product output and Mark a critical path. Assume that the delays in FA (HA) are 3(1) and 2(1) in sum and
carry, respectively.
3. (10%) Draw the truth table of a modified Booth multiplier (scan 3 bits each time) and take A * 01110101
for example (=A*?).
 4. Find the 12 inputs of an AMM (Additive Multiply Module) that implements an
unsigned square function of 3-bit inputs (y2y1y0) without any additional logic gate(s) as 4.
shown in Fig. 1. (Hint: Neglect 2 MSB outputs of AMM)

Fig. 1 AMM and 3-bit square function

5. Implement a 3x3 signed 2’s complement array multiplier by Full adders, Half adders, and AND /NAND/NOT
gates. Show your algorithm and Mark the critical path.
5.
6. Implement a 4x3 signed 2’s complement array multiplier by using at least 2 types of type 0-4 Full adder
cells(FAs) and AND gates (1 unit delay) only. Show your algorithm, Calculate the delay units in each product
output and Mark a critical path. Assume that the delays in all type of FAs are the same of 3 and 2 in sum and
carry, respectively.

6.
7. For 16-bit unsigned binary computer division, answer the following questions
( 0 ) (1) ( m −1)
z zx x  x
(a) For convergence division q = d = dx x  x , find m=?, and how many MUL and SUB operations are needed?
( 0 ) (1) ( m −1)

(b) Draw the Old/New Partial reminder diagram (s(j)-2s(j-1) Plot) for restoring division of 0.010 010  0.101 with 4
bits (0.q-1q-2q-3 q-4) of quotient.
8. For IEEE 754-2008 standard FLP short format, answer the following questions:
(a) Find the value of 0100 0010 0111 0000 0000 0000 0000 0000
(b) What is the representation of 0100 0010 0001 0110 1 plus 0100 0000 0111 0110 1 if round-to-the-nearest-odd
is applied with fraction part changing to 8 bits instead of 23 bits?

8.
7. (a) m= log 16 = 4, 7MUL 4 SUB
9. For IEEE 754-2008 standard FLP short format, answer the following questions:
Find the value of 1110 0000 1110 0000 0000 0000 0000 0000
What is the representation of 7?

10. For the ROM rounding of (k+m)-bit input xk–1…x3x2x1x0.x–1… x–m (k-bit integer m-bit fraction) and k-bit integer output
xk–1… x3x2y1y0, answer the following questions.
Find the ROM size. (2Input Number x output number)
Which input(s) to the ROM that produce(s) the maximum error? (Each input has k+m bits)
Draw the ROM rounding function in Fig. 2 if signed-magnitude representation is applied for input x=(x1x0) and output
ROM(x)= (y1y0).

10.

9.

Fig. 2 for problem 10.

11. For the rounding schemes, fill the following table for 1011.01, 1011.10, and
1011.11 to get the integer answers (No fraction).

1011.01 1011.10 1011.11

Chop

Round to the nearest Even

Round to the nearest odd

ROM rounding with 2 outputs

ROM rounding with 3 outputs

12. (a) What is the result of square root of (0111 0110)2?
(b) How to compute A1/2 (A>0) by using CORDIC operations?