Aparna Upreti

ASIC Digital Design Engineer SR II

er.upreti.aparna@gmail.com +919582970409 Noida, India

PROFILE

An organized and detail-oriented individual with a proactive and hardworking attitude enthusiastic about achieving
professional growth that is linked with organizational goals. I'm a Design Verification engineer with years of experience
working in simulation, emulation verification and product validation

PROFESSIONAL EXPERIENCE

ASIC Digital Design Engineer SR II, Synopsys May 2021 – present

UVM-based Design IP verification Noida, India
Created Test Plan targeting Pipe6.0 for PCIE6
Debugged various scenarios and verified the Customer's IP
Updated Monitor checkers and assertions
Created coverage plan and implemented coverage model

Lead Member Technical Staff, Siemens EDA (Mentor Graphics) Sep 2018 – May 2021
Developing Transactor Library for Veloce Emulation Platform Noida, India
Developed SMBus VTL Transactor from scratch.
Enhance the SMBus VTL to be supported on the Virtual Prototyping System PRIMO
Functional feature implementation and enhancement of USB2.0 in VTL
Provide technical support to the customers to help them identify the bugs in their design or
to help them with their environment bring up or set up
Resolve bugs and support enhancement in VTLs based on QA.

Design Engineer, Truechip Solutions Pvt Ltd Jan 2015 – Sep 2018
Verification IP development for USB3.2,USB3.0,USB2.0 and SATA Noida, India
Implementation of the driver for the protocol layer in USB3.0 VIP
Created Test plans and Test cases for covering different scenarios of the USB3.0 VIP protocol
layer with the help of XHCI.
Test the customer DUT to help them identify bugs in their design.
Implement the protocol layer and Hub controller for USB 2.0 VIP
Sequence creation for testing of HUB. Regression cleaning and debugging.
Implemented transport layer monitor and coverage model in System Verilog
Debugging the test cases of SATA 3.3 VIP.

Consultant, Cadence Design System Oct 2014 – Apr 2014

System Verilog Assertion-based IP Verification Noida, India
Feature level and integration Level testing of different features.
Created test Plan and Specs which covers all test scenarios

EDUCATION

Master of Technology in VLSI, Banasthali Vidyapith University Jul 2010 – Jul 2012
77% Rajasthan, India

Bachelors of Technology in Electronics and Communication Engineering, Jul 2006 – Jul 2010
Uttrakhand Technical University Dehradun, India
76%

SKILLS

Verilog | System Verilog | UVM | Functional Verification | Emulation | USB 2.0 | USB 3.0 | SMBus | PCIe

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