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  • Task 4n5 DSD

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    N Bhargav
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    This document summarizes several digital logic design tasks completed by Niket Bhargav. It describes implementing a 2-bit multiplier with a 7-segment display, a counter with a clock divider, and various flip-flops and registers using Verilog including D, JK, SR, and T flip-flops as well as PIPO, PISO, SISO, and SIPO registers. The outputs were successfully verified for each implementation through Quartus compilation and output checking.

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    This document summarizes several digital logic design tasks completed by Niket Bhargav. It describes implementing a 2-bit multiplier with a 7-segment display, a counter with a clock divider, and various flip-flops and registers using Verilog including D, JK, SR, and T flip-flops as well as PIPO, PISO, SISO, and SIPO registers. The outputs were successfully verified for each implementation through Quartus compilation and output checking.

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    © All Rights Reserved
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    3 views21 pages

    Task 4n5 DSD

    Uploaded by

    N Bhargav
    This document summarizes several digital logic design tasks completed by Niket Bhargav. It describes implementing a 2-bit multiplier with a 7-segment display, a counter with a clock divider, and various flip-flops and registers using Verilog including D, JK, SR, and T flip-flops as well as PIPO, PISO, SISO, and SIPO registers. The outputs were successfully verified for each implementation through Quartus compilation and output checking.

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    of 21

    DSD LAB TASK- 4B & 5

    NAME- NIKET BHARGAV


    REG NO- 22BEC0823
    FACULTY- SRIDEVI S

    TASK 4B
    (this was supposed to be submitted with task 5)

    Problem statement :-

    Implementing a 2 bit multiplier with a 7 segment display on fbga

    Quartus code:-

    Compilation success :-
    FBGA implementation
    Hence the output has been verified.

    DSD LAB TASK-5A


    Problem statement :-

    Implementing a counter with a clock divider

    Quartus code:-
    Verified code:-
    Output verification and compilation :-
    DSD LAB TASK-5B

    Problem statement :-

    Implementing jk,t,sr,d flip flop and siso,pipo,sipo,piso registers using Verilog

    D FLIP FLOP
    JK FLIP FLOP
    SR FLIP FLOP
    T FLIP FLOP
    PIPO REGISTER
    When we change the input to 0001, the output follows the input only after the clock passes the
    posedge.

    PISO REGISTER
    SISO REGISTER
    SIPO REGISTER

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