Ahsanullah University of Science and Technology

Department of Computer Science and Engineering

SET A, Class Test #1, Spring 2022
Course Code: CSE 2213 Course Title: Computer
Architecture
Time: 20 Minutes Date:05/12/2022 Full Marks: 10
ID: Name:

Questions Marks
1. Given the following 32 bits bit pattern: 5
1000 1101 0010 1000 0000 0000 0011 1000
Write the MIPS instruction of the above machine codes.

2. Define the activities of PC register? 5

Ahsanullah University of Science and Technology

Department of Computer Science and Engineering
SET B, Class Test #1, Spring 2022
Course Code: CSE 2213 Course Title: Computer
Architecture
Time: 20 Minutes Date:05/12/2022 Full Marks: 10
ID: Name:

Questions Marks
1. Given the following assembly instruction: 5
lw $t2, 72 ($s1)
Write the corresponding machine codes.
2. Several different instructions can be used to change the control flow in a MIPS 5
program. Selecting from j, jr, beq, and bne, which instruction has the greatest
range? In other words, which instruction can be used to go the furthest away
relative to where the instruction is located? Explain your answer.

Ahsanullah University of Science and Technology

Department of Computer Science and Engineering
Class Test #1, Spring 2022
SET C, Course Code: CSE 2213 Course Title: Computer
Architecture
Time: 20 Minutes Date:05/12/2022 Full Marks: 10
ID: Name:

Questions Marks
1. Given the following 32 bits bit pattern: 5
0001 0001 0000 1001 0000 0000 0011 1001
Write the MIPS instruction of the above machine codes.

2. MIPS addressing is 32 bits and j-type instructions store only 26 bits. Explain, how 5
does j-type encode the full (32 bits) destination address, and when does jr (jump
register) need?

Ahsanullah University of Science and Technology

Department of Computer Science and Engineering
Class Test #1, Spring 2022
SET D, Course Code: CSE 2213 Course Title: Computer
Architecture
Time: 20 Minutes Date:05/12/2022 Full Marks: 10
ID: Name:

Questions Marks
1. Given the following assembly instruction: 5
sw $t3, 72 ($s4)
Write the corresponding machine codes.

2. Explain the use of a loader program with necessary figures. 5

Ahsanullah University of Science and Technology

Department of Computer Science and Engineering
Class Test #1, Spring 2022
SET E, Course Code: CSE 2213 Course Title: Computer
Architecture
Time: 20 Minutes Date:05/12/2022 Full Marks: 10
ID: Name:

Questions Marks
1. Given the following 32 bits bit pattern: 5
1000 1110 0110 1000 0000 0000 0010 1000
Write the MIPS instruction of the above machine codes.

2. Explain how does a branch instruction (beq/ bne) store destination address in 5
(binary) machine code?
 Ahsanullah University of Science and Technology
Department of Computer Science and Engineering
Class Test #1, Spring 2022
SET F, Course Code: CSE 2213 Course Title: Computer
Architecture
Time: 20 Minutes Date:05/12/2022 Full Marks: 10
ID: Name:

Questions Marks
1. Given the following assembly instruction: 5
addi $sp, $t2, 8
Write the corresponding machine codes.

2. Explain the difference between Instruction Set Architecture (ISA) and 5

Microarchitecture.

Ahsanullah University of Science and Technology

Department of Computer Science and Engineering
Class Test #1, Spring 2022
SET G, Course Code: CSE 2213 Course Title: Computer
Architecture
Time: 20 Minutes Date:05/12/2022 Full Marks: 10
ID: Name:

Questions Marks
1. What is the MIPS assembly code to load the following 32-bit constant into register 5
$s0.
0000 0000 0011 1101 0000 1001 0000 0000

3. Explain what types of data are stored in memory segments including Code segment, 5
Data Segment (Static and Dynamic) and Stack Segment.

Ahsanullah University of Science and Technology

Department of Computer Science and Engineering
Class Test #1, Spring 2022
SET H, Course Code: CSE 2213 Course Title: Computer
Architecture
Time: 20 Minutes Date:05/12/2022 Full Marks: 10
ID: Name:

Questions Marks
2. Given the following assembly instruction: 5
slt $t1, $t2, $t3
Write the corresponding machine codes.

3. Explain the difference between Computer Architecture and Building 5

Architecture.