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203 Expt1
203 Expt1
Tech E&TC
VLSI Design
Aim: Using Behaviour style of modelling design, simulate and synthesize 8:1 Multiplexer using
Verilog HDL
Multiplexer is a combinational logic circuit which allows only one input at a particular time to
generate the output. The SELECT lines control which input will be reflected at the output end . A
multiplexer is often written as MUX in the abbreviated form. It is also called as Many-to-One
circuit. This is because of its ability to select one signal out of many inputs.
Cummins College Of Engineering For women, Pune-52 Third Year B.Tech E&TC
Verilog Code:
module muxtest(S, D0, D1, D2, D3, D4, D5, D6, D7, OP);
input [2:0] S;
input D0;
input D1;
input D2;
input D3;
input D4;
input D5;
input D6;
input D7;
output OP;
reg OP;
always @ (S or D0 or D1 or D2 or D3 or D4 or D5 or D6 or D7)
begin
if(S==000)
OP=D0;
else if(S==001)
OP=D1;
else if(S==010)
OP=D2;
else if(S==011)
OP=D3;
else if(S==100)
Cummins College Of Engineering For women, Pune-52 Third Year B.Tech E&TC
OP=D4;
else if(S==101)
OP=D5;
else if(S==110)
OP=D6;
else if(S==111)
OP=D7;
else
OP=0;
end
endmodule
Simulation Result:
Cummins College Of Engineering For women, Pune-52 Third Year B.Tech E&TC
Conclusion:
The experiment utilized the Behavior style of modeling to simulate and synthesize an 8:1
multiplexer in Verilog HDL revealed valuable insights into digital circuit design.
Through simulation, we observed the performance across various inputs, while synthesis effectively
translated Verilog HDL code into gate-level configurations.
This experiment not only emphasized the importance of abstraction in digital design but also
highlighted the critical role of accurate synthesis in creating functional hardware.
Practice:
1. Write a Verilog code for 8:1 mux using structural style of modeling.
2. Compare both the modelling styles of designing.