IA 3 QP Ans Key

ST JOSEPH ENGINEERING COLLEGE, VAMANJOOR, MANGALURU-575028
An Autonomous Institution
Affiliated to VTU Belagavi, Recognised by AICTE New Delhi, Accredited by NAAC with A+ Grade
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Accredited by NBA New Delhi
USN
III INTERNAL TEST
Subject : Verilog HDL Sections : A&B
Subject code : 18EC56 Semester : V
Date : 27/01/2022 Duration : 1 Hr 30 Min
Time : 2.00 pm – 3.30 pm Max Marks : 50
Answer any 5 full questions.

Q.No Question
1. 1. Outline the differences between Task and Function (5 Marks)
Ans:
Functions Tasks
A function can enable another A task can enable other

function but not another task. tasks and functions.
Functions always execute in 0 Tasks may execute in non-

simulation time. zero simulation time.
Functions must not contain any Tasks may contain delay,

delay, event, or timing control event, or timing control
statements. statements.
Functions must have at least one Tasks may have zero or

input argument. They can have more arguments of type
more than one input. input, output, or inout.
Functions always return a single Tasks do not return with a

value. They cannot have output value, but can pass multiple
or inout arguments. values through output and
inout arguments.
(1 Mark for each difference)
b) Model a function to calculate the factorial of a 4-bit number. The output

is a 32- bit value. Invoke the function by using stimulus and check results.
(5 Marks)
Ans:
module top;
function automatic integer factorial;
input [3:0] num;
begin
if(num>=2)
factorial=factorial(num-1)*num;
else
factorial=1;
end
endfunction
integer result;
initial
begin
result=factorial(10);
$display("Factorial of 10 is %d", result);
end
endmodule (5 Marks)
2. a) Model a JK flipflop using a Verilog case statement. (5 Marks)
Ans:
module jk_ff(clk,reset,in_j,in_k, out_q,out_qbar);
input clk,reset,in_j,in_k;
output out_q,out_qbar;
reg out_q;
always @(posedge clk or posedge reset)
begin
if(reset)
out_q<=1'b0;
else
begin
case({in_j,in_k})
2'b00:out_q<=out_q;
2'b01:out_q<=1'b0;
2'b10:out_q<=1'b1;
2'b11:out_q<=~out_q;
default:out_q<=out_q;
endcase
end
end
assign out_qbar=~out_q;
endmodule ( 5 Marks)
b) Write a program using the repeat loop to delay the statement a= a+1 by
10 positive edges of clock (5 Marks)
Ans:
module test;
reg clk;
integer a;
initial
begin
a=0;
clk=1'b0;
forever #10 clk=~clk;
end
initial
begin
$monitor("%4d | %3b |%d|", $time, clk, a );
$display("Time | clk | a|");
end
always@(posedge clk)
begin
repeat(10)
@(posedge clk)a=a;
a=a+1;
end
initial
#500 $finish;
endmodule ( 5 Marks)
3. Describe “assign and deassign” and design a positive edge-triggered D flipflop
with procedural continuous assignments. (10 Marks)
Ans:
 The keywords assign and deassign are used to express the first type of
procedural continuous assignment.
 The left-hand side of procedural continuous assignments can be only be a
register or a concatenation of registers. It cannot be a part or bit select of a
net or an array of registers.
 Procedural continuous assignments override the effect of regular procedural
assignments.
 Procedural continuous assignments are normally used for controlled periods
of time.
(4 Marks)
module edge_dff(q, qbar, d, clk, reset);
output q,qbar;
input d, clk, reset;
reg q, qbar;
always @(negedge clk)
begin
q = d;
qbar = ~d;
end
always @(reset)
if(reset)
begin
assign q = 1'b0;
assign qbar = 1'b1;
end
else
begin
deassign q;
deassign qbar;
end
endmodule (6
Marks)
4. What will the following statement translate to when run on a logic synthesis
tool? (10 Marks)
a) assign out= (x^y) & z where out, x,y and z are 3 bit vectors
Ans:
( 5 Marks)
b) if (s)
out=i1;
else
out=i0;
Ans:
(5 Marks)
5. Consider the 4-bit full adder. Write a stimulus file to do random testing of the
full adder. Use a random number generator to generate a 32-bit random
number. Pick bits 3:0 and apply them to input a; pick bits 7:4 and apply them
to input b. Use bit 8 and apply it to c_in. Apply 20 random test vectors and
observe the output. (10 Marks)
Ans:
Design block
module fulladd4(c_out,sum, a, b, c_in);

output [3:0] sum;
output c_out;
input[3:0] a, b;
input c_in;
assign {c_out, sum} = a + b + c_in;
endmodule (4 Marks)
Stimulus block
module test;
wire [3:0] sum;
wire c_out;
reg [3:0] a, b;
reg c_in;
reg[31:0]addr;
fulladd4 f1 (c_out,sum, a, b, c_in);
initial
begin
repeat (20)
begin
#10 addr=$random;
a=addr[3:0];
b=addr[7:4];
c_in=addr[8];
end
end
initial
$monitor($time,"a=%b, b=%b, c_in=%b,c_out=%b, sum=%b, ",a,b,c_in,
c_out,sum);
endmodule (6 Marks)
6. Outline the impact of automated logic synthesis on the digital design industry.
(10 Marks)
Ans:
Before the days of automated logic synthesis, when designs were converted to gates
manually, the design process had the following limitations:
 For large designs, manual conversion was prone to human error. A small
gate missed somewhere could mean redesign of entire blocks.
 The designer could never be sure that the design constraints were going to
be met until the gate-level implementation was completed and tested.
 A significant portion of the design cycle was dominated by the time taken to
convert a high-level design into gates.
 If the gate-level design did not meet requirements, the turnaround time for
redesign of blocks was very high.
 What-if scenarios were hard to verify. For example, the designer designed a
block in gates that could run at a cycle time of 20 ns. If the designer wanted
to find out whether the circuit could be optimized to run faster at 15 ns, the
entire block had to be redesigned. Thus, redesign was needed to verify
what-if scenarios.
 Each designer would implement design blocks differently. There was little
 consistency in design styles. For large designs, this could mean that smaller
blocks were optimized, but the overall design was not optimal.
 If a bug was found in the final, gate-level design, this would sometimes
require redesign of thousands of gates.
 Timing, area, and power dissipation in library cells are fabrication-
technology specific. Thus if the company changed the IC fabrication vendor
after the gatelevel design was complete, this would mean redesign of the
entire circuit and possible change in design methodology.
 Design reuse was not possible. Designs were technology-specific, hard to
port,and very difficult to reuse. (5
Marks)
Automated logic synthesis tools addressed these problems as follows:
 High-level design is less prone to human error because designs are
described at a higher level of abstraction.
 High-level design is done without significant concern about design
constraints. Logic synthesis will convert a high-level design to a gate-level
netlist and ensure that all constraints have been met. If not, the designer
goes back, modifies the high-level design and repeats the process until a
gate-level netlist that satisfies timing, area, and power constraints is
obtained.
 Conversion from high-level design to gates is fast. With this improvement,
design cycle times are shortened considerably. What took months before
can now be done in hours or days.
 Automated logic synthesis tools addressed these problems as follows:
obtained.

obtained.
obtained.
(5 Marks)

IA 3 QP Ans Key

Uploaded by

Document Information

Copyright

Available Formats

Share this document

Share or Embed Document

Sharing Options

Did you find this document useful?

Is this content inappropriate?

Copyright:

Available Formats

IA 3 QP Ans Key

Uploaded by

Copyright:

Available Formats

ST JOSEPH ENGINEERING COLLEGE, VAMANJOOR, MANGALURU-575028

Answer any 5 full questions.

1. 1. Outline the differences between Task and Function (5 Marks)

A function can enable another A task can enable other

Functions always execute in 0 Tasks may execute in non-

Functions must not contain any Tasks may contain delay,

Functions must have at least one Tasks may have zero or

Functions always return a single Tasks do not return with a

(1 Mark for each difference)

b) Model a function to calculate the factorial of a 4-bit number. The output

module fulladd4(c_out,sum, a, b, c_in);

 High-level design is less prone to human error because designs are

You might also like