ST JOSEPH ENGINEERING COLLEGE, VAMANJOOR, MANGALURU-575028

An Autonomous Institution
Affiliated to VTU Belagavi, Recognised by AICTE New Delhi, Accredited by NAAC with A+ Grade
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Accredited by NBA New Delhi

USN
II INTERNAL TEST
Subject : Verilog HDL Sections : A&B
Subject code : 18EC56 Semester : V
Date : 20/12/2021 Duration : 1 Hr 30 Min
Time : 2.00 pm – 3.30 pm Max Marks : 50

Answer any 5 full questions.

Marks CO
Q.No Question BTL
Allocated Mapping

1. Develop a 2-to-1 multiplexer using bufif0 and bufif1 gates. The 10 4.2 L3
delay specifications for these gates as follows:

Delay Min Typ Max

Rise 1 2 3

Fall 3 4 5

Turn-off 5 6 7

Write gate-level description and stimulus in Verilog.

2. What would be the output of the following a = 4’b1110, b = 10 4.4 L3

4’b1001

a) a & b b) a && b c) |a d) a >>> 2

e) y = {2{ a },b[0] } f) a <= b g) a % b

h) a / b i) a ? 1: 0 j) a = = b

3. Explain Procedural assignments used in behavioral modeling style 10 5.1 L3

with relevant examples.

4. a) Design a clock with time period = 50 and a duty cycle of 75% 6 5.1 L3
by using the always and initial statements. The value of clock
 ST JOSEPH ENGINEERING COLLEGE, VAMANJOOR, MANGALURU-575028
An Autonomous Institution
Affiliated to VTU Belagavi, Recognised by AICTE New Delhi, Accredited by NAAC with A+ Grade
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Accredited by NBA New Delhi

at time = 0 should be initialized to 0. Finish the simulation by

200 time units. Draw the waveform of generated clock signal.
b) Using the wait statement, design a level-sensitive latch that
takes clock and d as inputs and q as output. q = d whenever 4 5.2
clock = 1.

5. A full subtractor has three 1-bit inputs x, y, and z (previous 10 4.4 L3

borrow) and two 1- bit outputs D (difference) and B (borrow). The
logic equations for D and B are as follows:

D = x'.y'.z + x'.y.z' + x.y'.z' + x.y.z

B = x'.y + x'.z + y.z
Write the Verilog description using dataflow modeling. Instantiate
the subtractor module inside a stimulus block and test all possible
combinations of inputs x, y, z.

6. a) List the characteristics of continuous assignments with an 5 4.3 L2

example.
b) Design and write a Verilog code for 4-to-1 mux using 5 4.4 L3
Conditional operator.

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