ST JOSEPH ENGINEERING COLLEGE, VAMANJOOR, MANGALURU-575028

An Autonomous Institution
Affiliated to VTU Belagavi, Recognised by AICTE New Delhi, Accredited by NAAC with A+ Grade
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Accredited by NBA New Delhi

V Semester B.E.(ECE) Assignment No:1

Course Description :Verilog HDL Course Code :18EC56
Assignment to students On: 10-11-2021 To be submitted by:29-11-2021
To be submitted to: Ms Deepthi S R

Q Question Max Mapping Bloom’s

No marks TLO Level

1 5 1.2 L2
What are the advantages of HDL compared to traditional
schematic based design?
2 What are the two styles of stimulus application? Explain each 10 1.3 L2
method in brief.
3 Explain system tasks and compiler directives in Verilog. 10 2.3 L2
4 i. Declare the following variables in Verilog: 10 2.2,2.3 L3
a. An 8-bit vector net called a_in.
b. A 32-bit storage register called address. Bit 31 must be
the most significant bit. Set the value of the register to a
32-bit decimal number equal to 3.
c. An integer called count.
d. A time variable called snap_shot.
e. An array called delays. Array contains 20 elements of the
type integer.
f. A memory MEM containing 256 words of 64 bits each.
g. A parameter cache_size equal to 512
ii. What would be the output/effect of the following statements?
a. latch = 4'd12;
$display("The current value of latch = %b\n", latch);
b. in_reg = 3'd2;
$monitor($time, " In register value = %b\n", in_reg[2:0]);
c. `define MEM_SIZE 1024
$display("The maximum memory size is %h", 'MEM_SIZE);
ST JOSEPH ENGINEERING COLLEGE, VAMANJOOR, MANGALURU-575028
An Autonomous Institution
Affiliated to VTU Belagavi, Recognised by AICTE New Delhi, Accredited by NAAC with A+ Grade
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Accredited by NBA New Delhi