ST JOSEPH ENGINEERING COLLEGE, VAMANJOOR, MANGALURU-575028

An Autonomous Institution
Affiliated to VTU Belagavi, Recognised by AICTE New Delhi, Accredited by NAAC with A+ Grade
DEPARTMENT OF ELECTRONICS & COMMUNICATION ENGINEERING
Accredited by NBA New Delhi

V Semester B.E.(ECE) Assignment No:2

Course Description :Verilog HDL Course Code :18EC56
Assignment to students On: 31-12-2021 To be submitted by:10-01-2022
To be submitted to: Ms Deepthi S R

Q Question Max Mapping Bloom’s

No marks TLO Level

1 Write a Verilog code for JK flipflop using a case statement. 10 5.3 L3

2 Explain structured procedure statements in Verilog. 10 5.1 L2
3 Explain the methods of creating generate statements in 10 5.3 L2
behavioural modelling style
4 Explain Conditional Compilation and Execution with examples. 10 6.2 L2