School of Electronics Engineering

ECE 2003 (Fall 20-21) / Assignment / D1 Slot / Dr.M.Geetha Priya

Max marks: 100

Si.no. Questions Marks

M1.1 (a) Express the following unsigned decimal numbers in binary, octal, and 6
hexadecimal: 225.5, 10.1

(b) Find r such that (121)r =(144)8 , where r and 8 are the bases 3

M1.2 (a) Find out the 8-bit 2’s complement signed binary representation of the 3
following decimal numbers: +125, -57, -1

(b) Work out the following additions using 1’s complement signed 3
representation: (the numbers are all expressed in hexadecimal)
FA+8C, 7A+9B, 80+7F

M2.3 Solve AB+BC’+AC using Consensus theorem 5

M2.4 Implement the Boolean function Y=PQ’+R using only NAND gates 5

M3.5 Solve F(A,B,C,D)=π(3,5,7,8,10,11,12,13) using K- map 5

M3.6 Minimise the following function in SOP minimal form using K-Maps: F(A, B, C, D) = 5
m(0, 1, 2, 3, 4, 5) + d(10, 11, 12, 13, 14, 15)
M4.7 Design and implement a BCD adder to add the 4-bit numbers A and B 5
M4.8 (a) Implement an EX-OR gate using 2 : 1 Mux 5

(b) Implement a full adder using a suitable decoder with active low output 5

M5.9 Write a verilog description of 4-bit ripple carry adder at gate level abstraction, with a neat 7
block diagram. Also write stimulus block.

M5.10 If a= 4’b1010 and b= 4’b1111, what would be the output of the following 8
i) a&b
ii) a&&b
iii) &a
iv) a>>1
v) a>>>1
vi) y={2{a}}
vii) a^b
viii) z={a,b}

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M6.11 Design a 4 bit ripple counter using D flipflop (up counter) 10

M6.12 Give the differences between the following: 10

a) Combinational and sequential logic circuit
b) Synchronous and asynchronous sequential
c) Latch and flipflop
d) Moore and Mealy

M7.13 A full subtractor has three 1-bit inputs x, y and z (previous borrow) and two 1-bit outputs 8
D(Difference) and B(Borrow). Write a verilog description using dataflow modeling.
Instantiate the subtractor module inside a stimulus block and test all possible combinations
of inputs x,y and z.

M7.14 Write a verilog code and testbench for a 4 bit synchronous up counter 7

Note:
 Submit the pdf of hand written assignments only.
 If found copied or material of others submitted, it will be viewed seriously.
 Submit before 10/10/2020

Module wise Mark split-up

Si.no. Module & Course Outcomes Marks

1 Module-1 (CO-1 Understanding the number systems and IC characteristics) 15

2 Module-2 (CO-2 Understanding the Boolean algebra and its properties ) 10

3 Module-3 (CO-3 Optimizing the logic functions using K-map ) 10

4 Module-4 (CO-4 Design and analyse the combinational logic circuits) 15

5 Module-5 (CO-5 Understanding Verilog HDL syntax ) 15

6 Module-6 (CO-6 .Design and analyse the sequential logic circuits) 20

7 Module-7 (CO-7 Implement and simulate the combinational logic circuits using 15
Verilog HDL)

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 Outcome
Outcomes from the Assignment
Course Objectives: The course is aimed at,

1. To represent logical functions in canonical form and standard forms X

2. To design and analyse the combinational logic circuits X

3. To design and analyse the sequential logic circuits X

4.To implement the combinational and sequential logic circuits using Verilog HDL X

Expected Course Outcome: At the end of the course the student should be able to

1. Understanding the number systems and IC characteristics X

2. Understanding the Boolean algebra and its properties X
3. Optimizing the logic functions using K-map X
4. Design and analyse the combinational logic circuits X
5. Understanding Verilog HDL syntax X
6.Design and analyse the sequential logic circuits X
7. Implement and simulate the combinational logic circuits using Verilog HDL X

Student Learning Outcomes (SLO): 2, 5

2. Having a clear understanding of the subject related concepts and of contemporary X
issues
3. Having design thinking capability X

CO – SLO mapping
Module CO SLO
1 CO_01 2
2 CO_02 5
3 CO_03 5
4 CO_04 5
5 CO_05 5
6 CO_06 5
7 CO_07 5

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