ROLL NO.

BABU BANARASI DAS

INSTITUTE OF TECHNOLOGY & MANAGEMENT, LUCKNOW
B.TECH, ECE BRANCH, II YEAR
(SEM 3rd ) , First Sessional Examination 2021-22
Digital System Design (KEC 302)
Faculty Name: Navneet Kumar Pandey
Duration: 01:30 Hrs ` Max. Marks: 30
Note: (i) No student will be allowed to leave the examination Room before end of exam.
(ii) Mention Question number/section correctly.
(iii) Be precise in your answer.
Course Outcomes:
Following are the course outcomes of the subject:
CO Code Course Outcome (CO) Bloom's Level
KEC302.1 Design and analyze combinational logic circuits. L2,L3
KEC302.2 Design and analyze modular combinational circuits with MUX / DEMUX, L3
Decoder & Encoder
Section: A
1. Attempt all question: (5 x 2 = 10)

Q. Questions Marks CO BL
No.
a) What are the features of Gray code? 2 KEC302.1 L2
b) State Demorgan’s theorem. 2 KEC302.1 L1
c) Give comparison between combinational and sequential circuits. 2 KEC302.2 L1
d) How many NAND gates are required to design a Half Adder? 2 KEC302.2 L2
e) Write 6’s compliment of (435)7. 2 KEC302.1 L2

Section-B (4X5=20)
Q. No. Question (Attempt Any one part from each question) Marks CO BL
Minimize the following switching function using Tabular
A method: 5 L3
F(x1,x2,x3,x4) = Σm (1,2,3,7,8,9,10,11,14,15)
2. KEC302.1
Obtain the minimal SOP expression for the function:
B Y=Σm(1,5,7,13,14,15,17,18,21,22,25,29) + Σd(6,9,19,23,30) 5 L3
by using K map
A Design combinational circuit Binary to Gray code converter. 5 L3
3. KEC302.2
B Design a full Adder using NAND gates only . 5 L3
A Design 2 bit magnitude comparator. 5 L3
4. KEC302.2
B Design 3 X 4 bit multiplier circuit. 5 L3
5. A Implement a full adder using 3 to 8 line decoder or by using 5 KEC302.2 L2
MUX.

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B
Design a full subtractor circuit with three inputs x,y,z and two 5 L2
outputs D and B.

Checked By
(Head of Department)

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