Laboratory Manual: ELE-203 Digital Logic Design

Digital Logic Design ELE – 203
Laboratory Manual
ELE-203 Digital Logic Design
Student Name Zunaira Namal
Student ID F18BME18
Batch 2022
Lab Instructor:
Ms. Tooba Khan
Barrett Hodgson University – Department of Biomedical Engineering

Assessment Criteria
(Laboratory Experiment)
Understanding of experiment & designing / construction & Lab preparation:

 Read and understand the lab manual before going into the lab.
 Stay on task.
 Self-reliance in solving experimental problem without any guidance.
Usage of modern tools / apparatus & Safety:

 Can setup independently.
 Operate and handle the equipment / device / engineering software’s.
 Make careful observation.
 Follow the safety instructions.
Team work & time management:

 Fully participate in the experiment and use time wisely.
 Share workload and ideas with lab partner.
 Able to work individually or in a team.
Organization / content:
 All observation is recorded completely in a team / individually.
 All data is recorded and neatly presented with units / graph / truth table to the correct
number of significant figures.
 Student demonstrates an accurate understanding of the lab objectives and concepts.
 All sections are in a correct order and submitted on time.
Result & conclusion:

 Conclusion written in coherent manner with proper English syntax.
 Results are explicitly interpreted and compared with literature data and/or concepts
discussed in lecture.
 Explain with relevant examples.

Assessment Criteria
(Open Ended Laboratory Experiment)
Problem statement:
 Problem related with real world
 How strongly object is interacting with the course
 Literature review.
 Quality of references (min 5)
Selection of tool / Usage of modern tool:

 Operate and handle the equipment / device / engineering software’s.
 Make careful observation.
 Use appropriate engineering tools for the implementation of project.
Testing analysis and Team Work:

 Use engineering software to test the project idea.
 Able to analyse the output in every stage before cascading the whole project as a
systematic approach.
 Achieving accurate result after debugging and testing procedure in a given time frame.
Organization / content.
 Content should be in logical order.
 Professional looking and accurate representation of the data in tables, graphs and
written form with labelling.
 All calculations are included and neatly presented with details including units.
Result & conclusion.

 Conclusion written in proper manner in coherent manner with proper English syntax.
 Results are explicitly interpreted and compared with literature data.
 Clearly discussed what result mean and what conclusion may be drawn from them.

Content
S. No. Date Objective Sign Remarks
Lab 1
An Introduction to Digital Logic Design Trainer Boards
and Experimenting with the AND, OR, NOT, NAND
and NOR integrated circuits. (On-Campus)
Lab 2
To find an expression for the given logic diagrams,
implementing the circuits on bread board, and observing
output for various combinations of inputs. (On-Campus)
Lab 3
To Design different logic gates using the NOR and
NAND gate. (On-Campus)
Lab 4 (a) An Introduction to National Instrument Multisim
14.0 software.
(b) To Design XOR and XNOR gates using logic gates

Lab 5 To design switching circuits using logic gates.
Lab 6
To Implement half and full adder circuits.
Lab 7 To study multiplexer and demultiplexer functions.
Lab 8 To check the operation of common anode BCD to 7-

segmant decoder.
Lab 9 To check operation of common anode 7-segment display
Lab 10 To design SR latch using NOR & NAND logic gates
Lab 11 (a) To understand the working of gated SR latch

(b) To understand the working of D latch
(c) To design a D latch using logic gates
Lab 12 To study the JK flip flop.
Lab 13 To study 4-bit shift registers
Lab 14 To design an electronic dice using what we have studied

in the previous labs.
Lab 15 To design an electronic digital stopwatch.

Assessment Criteria
Lab # 4A
Outcomes Assessment:
Lab Performance & Lab Manual Assessment
PROFICIEN SATISFACTOR
SUBSTANDARD UNSATISFACTORY Marks
T Y
Assessment Parameters
(1) (0) obtained
(3) (2)
Understanding of experiment &

designing / Construction & lab
preparation.
Usage of modern tools /

Apparatus & safety
Team work & time

management.
Organization & content.
Marks (out of 15)
Final lab marks

(out of 0.5)
Lab Instructor signature: ____________________

4A LAB EXPERIMENT
OBJECT:
An Introduction to National Instrument Multisim 14.0 software.
INBTRODUCTION
1. MULTISIM:
Multisim integrates industry-standard SPICE simulation with an interactive schematic
environment to instantly visualize and analyze electronic circuit behavior. Its intuitive
interface helps educators reinforce circuit theory and improve retention of theory
throughout engineering curriculum. By adding powerful circuit simulation and
analyses to the design flow, Multisim helps researchers and designers reduce printed
circuit board (PCB) prototype iterations and save development costs.
2. MULTISIM OPTION:
1. MULTISIM FOR EDUCATION:
Multisim for Education is circuits teaching application software for analog,
digital, and power electronics courses and laboratories.
2. MULTISIM FOR DESIGNER:
Multisim provides engineers the SPICE (Simulation Program with Integrated
Circuit Emphasis) simulation, analysis, and PCB design tools to quickly iterate
through designs and improve prototype performance.
3. WHAT CAN YOU DO WITH MULTISIM FOR EDUCATION?

Multisim empowers students to understand the circuits in a way that maximizes
student learning and real-world preparedness. Explore the subjects below to see how
Multisim can improve your program.
1. ANALYZE CIRCUIT BEHAVIOUR:

Simulated benchtop instruments and advanced analyses in Multisim lend a
thorough understanding of circuit behavior, which reinforces textbook theory.

Figure 1: Analyze Circuit response of RC circuit.
2. TEACH ELECTRONICS:
As a learning tool, Multisim connects abstract theory to concrete signals through
intuitive design, interactive simulation, and seamless hardware integration.
Figure 2: Circuit of Differential Amplifier.
3. REINFORCE THEORY BY COMPARING REAL AND

SIMULATED SIGNALS:
Multisim embraces the need to take a hands-on approach to engineering
education.

Figure 3: Band pass filter circuit simulation.
4. TEACH DIGITAL LOGIC AND DEPLOY IT TO

HARDWARE:
Multisim goes beyond standard SPICE simulation to include an extensive digital
component library that you can simulate and deploy to any Digilent FPGA device.
Figure 4: FPGA circuit design.
4. HOW TO START WITH NI MULTISIM 14.0:

1. Open The National Instrument Multisim 14.0 by clicking over this icon.
2. This Window will appear.
3. Click to create the new file.

Figure 5: Creating new file.

4. Go for the blank icon and click on the create button.
Figure 6: Selecting type of design.

5. Now you can design your desired electronic circuit on this window.
Figure 7: Main window of NI Multisim with labelling.
Assessment Criteria

Lab # 4B
T Y
(1) (0) obtained
(3) (2)

preparation.

Apparatus & safety
Team work & time

management.
Marks (out of 15)
Final lab marks

(out of 0.5)
4B LAB EXPERIMENT
OBJECT:
To Design XOR and XNOR gates using logic gates
LEARNING OUTCOME:
In this lab, student will be able to understand the following points:
 Internal structure and working of XOR gate.

 Designing of XOR gate using basic logic gates
 Internal structure and working of XNOR gate.
 Designing of XNOR gate using basic logic gates
1. INTRODUCTION:
The Exclusive-OR (Ex-OR) and its complement Exclusive-NOR (Ex-NOR) are the last
two of the 7 types of logic gates. Both these gates are designed using other logic gates
therefore these gates may be referred to as “hybrid” or special gates. The output of each
of these gates is significant enough to be considered as separate logic gates. The ExOR
gate is applicable while performing arithmetic operations specifically in the case of
Adders and Half-Adders. Similarly, the Ex-NOR gate is used in error detecting circuits,
encryption, security alarms, and quantity measuring circuits.
2. XOR GATE:
An Exclusive-OR gate gives a true output only when its inputs are different. Otherwise
when both inputs are same the output is false.
2.1. SYMBOL:
Figure 1: Symbol of XOR Gate [3]
 XOR Gate IC: 7486
 Pin Diagram of XOR Gate IC:

Figure 2: Pin Diagram of XOR Gate [3]
3. The XNOR Gate

The Exclusive-NOR gate has a complementary output to a XOR gate. The output is true
only when both the inputs are same. It is also known as the equivalence function.
 Symbol:
Figure 3: Symbol of XNOR Gate [3]
 XNOR Gate IC: 74266
 Pin Diagram of XNOR Gate IC:
Figure 4: Pin Diagram of XNOR Gate [3]
4. METHODS AND MATERIALS:
4.1. APPARATUS:
 DC Power supply.
 Breadboard.
 Logic gate IC
 Logic probe.
 Jumper wires.
4.2. PROCEDURE:
The following steps will be used for performing the tasks
 Insert the relevant gate IC on breadboard.
 Connect Vcc pin 14 to + 5V of power supply.
 Connect Gnd pin 7 to 0V of power supply.
 Now follow the truth table and observe the output using Logic probe.
 Repeat the above steps for each IC.
4.3. OBSERVATIONS:
XOR GATE
A B Expected Output Observed Output

0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
XNOR GATE

0 0 1 1
0 1 0 0
1 0 0 0
1 1 1 1
5. DESIGNING OF XOR & XNOR GATE USING BASIC LOGIC

GATES VIA MULTISIM 14.0:

5.1. COMPONENTS REQUIRED:

 Logic gate IC
 Logic probe.
 Switch.
5.2. PROCEDURE:
The procedure for construction the circuit using Multisim is as follows:
1. First place relevant IC’s on the Multisim Editor window.
2. Now place the switches for input.
3. Place probe for observing output.
4. Connect all the components as prescribed in the circuit diagram.
5. Run the simulation.
6. Observe the output for different input combinations.
5.3. IMPLEMENTATION:
5.3.1. XOR GATE USING AOI GATES:

Design the given circuit on Multisim 14.0 as shown in Figure 5:
Figure 5: XOR Gate using AOI Gates
5.3.2. XNOR GATE USING AOI GATES:

Design the given circuit on Multisim 14.0 as shown in Figure 6:

Figure 6: XNOR Gate using AOI Gates

6. OBSERVATION:
XOR GATE USING AOI GATES:

0 0 0 0
0 1 1 1
1 0 1 1
1 1 0 0
XNOR GATE USING AOI GATES:

0 0 1 1
0 1 0 0
1 0 0 0
1 1 1 1
EXERCISE:
Question 1:
Describe any three applications of XOR Gate.
 In arithmetic circuits (circuits requiring addition or subtraction).

 As comparators.
 XOR gate can also be used as an inverter.
Question 2:
Describe any three applications of XNOR Gate.
 XNOR Gate is used in microprocessor circuits.

 It is vastly used in digital electronic circuits.
 Can be used in arithmetic circuits.
Question 3:
Write any three applications of using MULTISIM software?
 To troubleshoot problems that can arise in circuits or for analyzing different circuits.
 As a medium to educate people on how circuits work and how different components can
be used to make a circuit.
 Can be used to test out new circuit designs or use different components in a circuit
without having to make it physically in real life

Assessment Criteria
Lab # 5
T Y
(1) (0) obtained
(3) (2)

preparation.

Apparatus & safety
Team work & time

management.
Marks (out of 15)
Final lab marks

(out of 0.5)

5 LAB EXPERIMENT
OBJECT:
To design switching circuits using logic gates.
LEARNING OUTCOMES:
 Designing automated switches using combinational logic.
 Applications of switches with logic gates.
1. INTRODUCTION:
Combinational logic circuits have numerous applications within the digital world and
can therefore be designed to perform different tasks. One of the most common
applications however lies within the multiplexer and demultiplexer type circuits
where logic gates are used to perform the switching function to decide the output and
input lines. Similarly, logic gates may be also used to perform the functions of
electromechanical switches and relays.
2. MATERIAL AND METHOD:

The following circuit diagrams have been designed and simulated on Multisim 14.0
a) SWITCH USING AND GATE:

Figure 1 shows the circuit diagram of the switching circuit designed using
AND gate. Design the circuit as shown in Figure 1.
Key = X 1 100Ω
Key = Y 0
74LS08N
Fig 4.1: Switch using AND gate
For the inputs of the AND gate the interactive digital constant has been used
which allows the user to change the input values while the simulation is
running. Each of the input can be assigned a separate key. The input value
changes once the respective key is pressed by the user. To indicate the ‘open’

and ‘close’ stages a LED is used. When the LED is off the switch is open and
when the LED is glowing, it means that the switch is closed.
b) SWITCH USING OR GATE:

Figure 2 shows the circuit diagram of the switching circuit designed using
AND gate. Design the circuit as shown in Figure 2.
Key = X 1 100Ω
Key = Y 0
74S32N
Fig 4.2: Switch using OR gate
Like the previous circuit this circuit also uses the interactive digital constants
as inputs and a LED to indicate the output. The difference is however in the
output generated by both circuits. This circuit uses the OR gate logic.
c) SWITCH USING 3-INPUT NAND GATE:

Figure 3 shows the circuit diagram of the switching circuit designed using 3-
input NAND gates. Design the circuit as shown in Figure 3.
2.5 V
logic_probe
Key = X 1
74F10N
Key = Y 1
74F10N
Key = Z 1
74F10N
Fig 4.3: Switch using 3-input NAND gate
A 3-input NAND gate follows the same logic as of the 2-input NAND gate,
but it has an additional input. This means that the output is false only when all
three inputs are true. For the rest of the combinations the output remains true.
For the inputs the same interactive digital constant has been used. To indicate
the output a logic probe has been used. The logic probe may be found within
the indicators group in the components section. The logic probe can be placed
on any single line to indicate the output of that line. It simplifies the circuit
because it does not require additional components such as a ground and a
resistor.

1)
a)
b)
i)
3. CONCLUSION:
A)
Table 4.1: Switch using AND gate
X Y Output
0 0 0
0 1 0
1 0 0
1 1 1
B)
Table 4.2: Switch using OR gate
X Y Output
0 0 0
0 1 1
1 0 1
1 1 1
C)
Table 4.3: Switch using NAND gate
X Y Z Output
0 0 0 0
0 0 1 0
0 1 0 0
0 1 1 0
1 0 0 0
1 0 1 0
1 1 0 0
1 1 1 1

Assessment Criteria
Lab # 6
T Y
(1) (0) obtained
(3) (2)

preparation.

Apparatus & safety
Team work & time

management.
Marks (out of 15)
Final lab marks

(out of 0.5)

6 LAB EXPERIMENT
OBJECT:
To Implement half and full adder circuits.
LEARNING OUTCOME:
 Working and Construction of Half and Full Adders.

 Design a Half and Full Adder using logic Gates.
 Observe outputs at various Inputs.
1. INTRODUCTION:
The arithmetic logic unit (ALU) also known as the integer unit (IU) is the hub of
calculations for any processing unit. It is a digital combinational circuit that performs
logical, bit shifting and arithmetic operations. These tasks require the ALU to be
equipped with various combinational logic circuits that are able to perform basic
operations such as addition, subtraction, multiplication and division. Adders and
subtractors are examples of combinational logic circuits that are incorporated inside an
ALU. Modern day engineers focus on designing faster ALU’s that significantly reduce
the processing times and result in a powerful central processing unit (CPU). However, the
challenge that engineers face is that a faster ALU has a complex circuit which requires
more space and significantly increases the CPU cost. Therefore, engineers need to
maintain a correct balance to keep the ALU efficient and economic.
2. ADDERS
Adders are an integral part of ALU. Broadly there are two types of adders, half adder and
full adder. A half adder can add two bits whereas a full adder is able to perform 3-bit
addition. Fig 6.1 and 6.2 show the block diagrams for a half and a full adder. The output
of both adders are similar and have the ‘sum’ and carry outputs. The full adder has a
additional input known as ‘carry in’. However, it should be understood that a full adder is
designed using two half adders as shown in Fig 6.3. Adders are part of complex
processing systems such as GPU and CPU. Apart from this Adders are also used to
generate memory addresses inside a computer.

Fig 6.1: Half adder
Fig 6.2: Full adder
Fig 6.3: Full adder by half adders

2.1. HALF ADDERS:
A combination circuit that performs the addition of two bits without accounting for the
previous carry is called half adder. It needs two binary inputs and two binary outputs. The
input variables designate the augend and addend bits. The output variables produce the sum
and carry. The simplified sum of product expressions for a half adder are:
S= x ⋅ y + x ⋅ y=x ⊕ y
C=x ⋅ y
2.2. FULL ADDERS:

A combinational circuit that performs the addition of three input bits. It consist of three inputs
and two outputs. Two of the input variables, represent the two significant bits to be added.
The third input, represents the carry from the previous lower significant position. The output
variables produce the sum and carry. The simplified sum of product expressions for a half
adder are:
S= x ⋅ y ⋅ z+ x . y . z + x . y . z + x . y . z= x ⊕ y ⊕ z
C=y.x + x.z +y. z = ( x ⊕ y ¿ . z+ x . y
3. PROCEDURE:
1. Insert the relevant gate IC on breadboard.
2. Connect Vcc pin 14 to + 5V of power supply.
3. Connect Gnd pin 7 to 0V of power supply.
4. Follow the circuit diagram to make the connections
5. Follow the truth table and record the output with the help of logic probe
4. CIRCUIT DIAGRAM:
4.1. HALF ADDER
A
Sum
B
7486N
Carry
7408J
Fig 6.4: Half adder circuit
4.2. FULL ADDER

A
B Sum
7486N
Carry in 7486N
7408J
Carry out
7432N
7408J
Fig 6.5: Full adder circuit
5. RESULTS:
5.1. HALF ADDER:

Inputs Output
A B Sum Cary out
0 0 0 0
0 1 1 0
1 0 1 0
1 1 0 1

Table 6.1: Output of Half Adder
6. FULL ADDER:
Inputs Output
A B Carry-In Sum Carry-Out
0 0 0 0 0
0 0 1 1 0
0 1 0 1 0
0 1 1 0 1
1 0 0 1 0
1 0 1 0 1
1 1 0 0 1
1 1 1 1 1
Table 6.2: Output of Full Adder

Assessment Criteria
Lab # 7
UNSATISFACTOR Marks
PROFICIENT SATISFACTORY SUBSTANDARD
Assessment Parameters Y
(3) (2) (1) obtained
(0)

preparation.

Apparatus & safety
Team work & time

management.
Marks (out of 15)
Final lab marks

(out of 0.5)

Experiment No. 7
Object: To study multiplexer and demultiplexer functions.
Components:
 DC Power Supply
 Breadboard
 Multiplexer IC (74LS151)
 Demultiplexer IC (74LS138)
 LEDs
 Switches
Introduction:
Digital computers process and transfer a tremendous number of digital signals. It would be
prohibitive to make separate straight-wire connections for the transfer of all this data within
the computer or to a peripheral device. A procedure called multiplexing uses one wire in the
place of many wires to transfer signals between multiple sources. Multiplexers and
demultiplexers are used to perform multiplexing. The transmission of telephone signals was
one of the first applications of multiplexing. This allowed multiple telephone conversations to
be sent simultaneously over the same wire. To perform multiplexing, binary counter is
connected to the select input lines of both the multiplexer and demultiplexer; this allows the
inputs of the multiplexer to be transferred to the corresponding outputs of the demultiplexer.
Multiplexer:
In electronics, a multiplexer (or mux), also called a data selector, is a combinational logic
circuit that selects one of several input signals and forwards the selected input into a single
output line. A multiplexer of 2n inputs has n select lines, which are used to select which input
line to send to the output. A 2 n-to-1 multiplexer sends one of 2n input lines to a single output
line.
A multiplexer has two sets of inputs:

 2n data input lines
 n select lines, to pick one of the 2ndata inputs
The mux output is a single bit, which is one of the 2 n data inputs. The simplest multiplexer is
a 2-to-1 mux where there are 2 inputs and 1 output. This multiplex has one select line and is
made up of 3 AND gates, a NOT gate, and an OR gate as shown in figure 10.2. When the
select line (s) is 0, the second input (x 2) will be forwarded to the output. The first input (x 1)
will appear at the output when the select line (s) is set to 1. A major application of

multiplexers is in the computer memory. Multiplexers are used to implement huge amounts
of memory into the computer. This also reduces the number of copper lines required to
connect the memory to other parts of the computer.
Symbol:
Figure 13.1: Symbol for 2n-to-1 multiplexer
Internal Circuitry:
Figure 13.2: Internal circuitry for 2-to-1 multiplexer
Demultiplexer:
The demultiplexer (or demux), often referred to as a data distributor, is a combinational logic
circuit that performs the reverse operation of a multiplexer. It has only one input, n selectors
and 2n outputs. Depending on the combination of the select lines, one of the outputs will be
selected to take the state of the input. Therefore, the demultiplexer converts a serial data
signal at the input to a parallel data at the output.
A 1-to-4 demultiplexer circuit consist of 2 NOT gates and 4 3-input AND gates. The input
data is sent to all 4 AND gates. When both selector inputs, A and B, are zero, only the output
of the first AND gate will be high. Therefore, the data will appear at Y 0. When A=0 and B=1,
the second AND gate’s output will be high and the rest low; now the data will be transmitted
to the output Y1. Y2 will receive data when A=1 and B=0. When both A and B are high, the
data will be forwarded to Y3.
One application of the demultiplexer is in the digitally adjustable amplifier gain circuit where
each output of the demultiplexer is connected to a different resistor. In addition,

demultiplexers are also used in ALU (Arithmetic Logic Unit) circuits to store the output in
multiple registers or storage units.
SYMBOL:
Figure 13.3: Symbol for 1-to-n demultiplexer
Internal Circuitry:
Figure 13.4: Internal circuitry for 1-to-4 demultiplexer
Procedure:
1. Insert the relevant IC on breadboard
2. Connect VCC pin to +5V of power supply
3. Connect the Gnd pin 7 to 0V of power supply
4. Connect the remaining pins as shown in the circuit diagram
a. Connect switches to the selector data inputs
b. Connect LEDs to the 8 pins labeled 0-7
5. Follow the truth table and record the output
Circuit Diagram:

Multiplexer
Figure 13.5: Circuit diagram for 8-to-1 Multiplexer
Demultiplexer
Figure 13.6: Circuit diagram for 1-to-8 Demultiplexer
Observation:
Multiplexer:

Table 13.1: Truth table for 8-to-1 Multiplexer
Inputs Select Data Inputs Output

D0 D1 D2 D3 D4 D5 D6 D7 S2 S1 S0 Y
1 0 0 0 0 0 0 0 0 0 0 Y0
0 1 0 0 0 0 0 0 0 0 1 Y1
0 0 1 0 0 0 0 0 0 1 0 Y2
0 0 0 1 0 0 0 0 0 1 1 Y3
0 0 0 0 1 0 0 0 1 0 0 Y4
0 0 0 0 0 1 0 0 1 0 1 Y5
0 0 0 0 0 0 1 0 1 1 0 Y6
0 0 0 0 0 0 0 1 1 1 1 Y7
Demultiplexer:
Table 13.2: Truth table for 1-to-8 Demultiplexer
Select Data Inputs Output

C B A D0 D1 D2 D3 D4 D5 D6 D7
0 0 0 1 0 0 0 0 0 0 0
0 0 1 0 1 0 0 0 0 0 0
0 1 0 0 0 1 0 0 0 0 0
0 1 1 0 0 0 1 0 0 0 0
1 0 0 0 0 0 0 1 0 0 0
1 0 1 0 0 0 0 0 1 0 0
1 1 0 0 0 0 0 0 0 1 0
1 1 1 0 0 0 0 0 0 0 1
Conclusion:
In today’s lab we learnt the functions of multiplexer and de-multiplexers.
The multiplexer combines multiple inputs into one long code in a specific period of time while the de-
multiplexer does the opposite; it takes an input code and separates it into multiple different inputs in a
specific time.

Assessment Criteria
Lab # 8
UNSATISFACTOR Marks
(0)

preparation.

Apparatus & safety
Team work & time

management.
Marks (out of 15)
Final lab marks

(out of 0.5)

Experiment No. 8
Object: To check the operation of common anode BCD to 7-segmant decoder.

Components:
 7-Segment display (common anode)
 Resistors 180-220 Ω
 IC 74LS47
Introduction:
Decoder
A decoder is a circuit that changes a code into a set of signals. It is called a decoder because it
does the reverse of encoding, but we will begin our study of encoders and decoders with
decoders because they are simpler to design.
Binary Coded Decimal

Binary Coded Decimal, or BCD, is a process for converting decimal numbers into their
binary equivalents. Binary Coded Decimal, use binary digits 0 which represent “off” and 1
which represent “on”. Each digit is called a bit. Four bits are called a nibble and is used to
represent each decimal digit (0 through 9). The binary numbering system use a base of 2
whereas the decimal numbering system use a base of 10. When the binary number is 0, then
the number is off, when the binary number is 1, then the number is on. The configuration of
BCD is "8421" a 4 bit binary called a nibble. Therefore, the decimal 5 is a BCD 0101: where
0=8, 1=4, 0=2, 1=1; the 8 and 2 are turned off.
BCD to 7-segment Decoder Driver

The 74xx47 chip is used to drive 7 segment display. You must use the 74xx47 with a
common anode 7-segment. The input to the 74xx47 is a binary number DCBA where D is 8s,
C is 4s, B is 2s and A is 1s. The inputs DCBA often come from a binary counter. The display
is only sensible if the binary number is between DCBA=0000 (0) and DCBA=1001 (9); this
is called Binary Coded Decimal or BCD for short. If the number is larger than 9 you get a
strange output on the display.

Figure 8.1 Pin Diagram of 7447 IC
Procedure:
 Connect the IT-400 trainer to the 220V AC power supply.
 Install the 7447 IC and 7-segment display on the trainer’s breadboard.
 Connect both with VCC and ground.
 Wire the circuit according to the circuit diagram given.
 Use logic switches S1 to S4 for inputs a through 7447 IC.
 Fill the truth table as results.

Circuit Diagram:
VCC
S1
S2
S3
S4
Figure 8.2 Circuit Diagram
Observation:

Table 8.1. Truth Table for BCD to 7-Segment Decorder
S4 S3 S2 S1 Display Decimal Digit
0 0 0 0 0
0 0 0 1 1
0 0 1 0 2
0 0 1 1 3
0 1 0 0 4
0 1 0 1 5
0 1 1 0 6
0 1 1 1 7
1 0 0 0 8
1 0 0 1 9
Conclusion:
Today’s lab was regarding the working of BCD (Binary Coded Decimal). We learnt about it
along with performing a task on multisim in which we used a BCD on a 7-segment decoder.
BCD takes in binary codes as input and then changes them into numbers or letters i.e.
depending on the data. In order to decode this coded data, we can either use LED’s, LCD
screens or a 7-segment display.

TASK 2:
OBJECTIVE: Using what you have learnt above, design a circuit that can display numbers from
00-99.
CIRCUIT DIAGRAM:
VCC
5V
1
CA
16
1 7
VCC
13
A OA
1 12
1 2
B OB
11
C OC
6 10
VCC 0 D OD
9
OE
3 ~LT OF 15
5 ~RBI OG 14
4 ABCDEFGHABCDEFGH
8 ~BI/RBO
GND
5V
VCC
1 5V
1 16
VCC
7 13
1 1
A OA
12
B OB
2 11
0 6
C OC
10
VCC D OD
9
OE
3 ~LT OF 15
5 ~RBI OG 14
4 ~BI/RBO
8
GND
5V
Figure 8.3
VCC
5V
1
CA
16
1 7
VCC
13
A OA
1 12
0 2
B OB
11
C OC
6 10
VCC 0 D OD
9
OE
3 ~LT OF 15
5 ~RBI OG 14
4 A BCDEF GHABC DEFGH
8 ~BI/RBO
GND
5V
VCC
1 5V
0 16
VCC
7 13
1 1
A OA
12
B OB
2 11
0 6
C OC
10
VCC D OD
9
OE
3 ~LT OF 15
5 ~RBI OG 14
4 ~BI/RBO
8
GND
5V
Figure 8.4

VCC
5V
0 CA
16
0 7
VCC
13
A OA
1 12
0 2
B OB
11
C OC
6 10
VCC 1 D OD
9
OE
3 ~LT OF 15
5 ~RBI OG 14
4 A BC DE FG H AB CD EF G H
8 ~BI/RBO
GND
5V
VCC
1 5V
1 16
VCC
7 13
0 1
A OA
12
B OB
2 11
0 6
C OC
10
VCC D OD
9
OE
3 ~LT OF 15
5 ~RBI OG 14
4 ~BI/RBO
8
GND
5V
Figure 8.5
CONCLUSION:
This task was completed using multiple BCD to 7-segment decoder IC’s with many 7
segment displays. At the end of this task we were able to display numbers in double and triple
digits. Displaying multiple digits is very useful in many other devices like digital clocks and
electronic meters. Electronic devices that display a numeric value use decoder to decode
binary codes.

Assessment Criteria
Lab # 9
UNSATISFACTOR Marks
(0)

preparation.

Apparatus & safety
Team work & time

management.
Marks (out of 15)
Final lab marks

(out of 0.5)

Experiment No. 9
Object: To check operation of common anode 7-segment display/

Required Components:
 7-segment display (common anode)
 220 Ω resistances
 IT-400 Trainer
Introduction:
Seven segment displays are the output display devices that provide a way to display
information in the form of image or text. For displaying the images or text in a proper
manner, some types of displays can show only alphanumeric characters and digits. But, some
displays can also show characters and images. Most commonly used displays along with the
microcontrollers are LCD, LEDs and seven segment displays etc.
Figure 10.1. Seven Segment Display
The seven segment display is the most common display device used in many gadgets, and
electronic appliances like digital meters, digital clocks, microwave oven and electric stove,
etc. These displays consist of seven segments of light emitting diodes (LEDs) and that is
assembled into a structure like numeral 8. Actually seven segment displays contain about 8-
segments wherein an extra 8th segment is used to display dot. This segment is useful while
displaying non integer number. Seven segments are indicated as A-G and the eighth segment
is indicated as H. These segments are arranged in the form of 8 which is shown in the seven
segment display circuit diagram.

Seven Segment Display Working:

When the power is given to all the segments, then the number 8 will be displayed. If you
disconnect the power for segment G (that means 7) then that will result number 0. The circuit
of the seven segment display is designed in such a way that the voltage at different pins can
be applied at the same time. In the same way, you can form the combinations to display
numerals from 0 to 9. Practically, seven segment displays are available with two structures,
both the type of displays consists of 10 pins.
Types of 7-Segment Displays

There are two types of seven segment displays available in the market. According to the type
of application, these displays can be used. The two configurations of seven segment displays
are discussed below.
 Common Anode Display

 Common Cathode Display
Figure 10.2. Common cathode and common anode 7-segment display’s pin configuration
Common Anode 7-segment Display

In this type of display, all the anode connections of the LED segments are connected together
to logic 1. The separate segments are lightened by applying of the logic 0 or LOW signal
through a current limiting resistor to the cathode of the particular segment a to g.

Figure 10.3. Common Anode 7-segment Display
Procedure:
 Connect the IT-400 trainer to the 220V AC power supply.
 Install the 7-segment display on the trainer’s breadboard.
 Wire the circuit according to the circuit diagram given.
 Use logic switches S2 through S9 for inputs a through g and dp respectively.
 Connect the common pin of 7-segment display to +5V.
 Fill the truth table as results.
Circuit Diagram
Figure 10.4. Circuit Diagram of Common Anode 7-segment Display
Observation:
Table 10.1. Truth Table for 7-Segment Display Output

S2 S3 S4 S5 S6 S7 S8 S9
A b C d E f G dp Digit Displayed
0 0 0 0 0 0 1 0 0
1 0 0 1 1 1 1 0 1
0 0 1 0 0 1 0 0 2
0 0 0 0 1 1 0 0 3
1 0 0 1 1 0 0 0 4
0 1 0 0 1 0 0 0 5
1 1 0 0 0 0 0 0 6
0 0 0 1 1 1 1 0 7
0 0 0 0 0 0 0 0 8
0 0 0 1 1 0 0 0 9
CONCLUSION:
Today’s lab was regarding the usage of a 7-segment display on multisim along with the
working behind the display component. The component consists of 8 input options via a
switch which controls the turning the LED lines on or off on the display.
As a high input is provided via a switch, the LED’s in a particular part of the display are
switched on. When these together make a combination of different high and low inputs a
decimal number is generated and visible on the 7-segment display.

Assessment Criteria
Lab # 10
UNSATISFACTOR Marks
(0)

preparation.

Apparatus & safety
Team work & time

management.
Marks (out of 15)
Final lab marks

(out of 0.5)

Experiment No. 10
Object:
To design SR latch using NOR & NAND logic gates
Apparatus:
 Breadboard.
 Logic gate IC
 Logic probe.
 Jumper wires.
Introduction:
A latch is considered to be the building block of sequential circuits. Latches have the ability
to retain data. A single latch can hold up to 1 bit of data. Latches are asynchronous which
means that the output is changed as soon as the inputs are changed. A short delay known as
the propagation delay may exist due to presence of multiple logic gates within the latch. The
most common types of latches are SR, D, JK and T. Latches are widely used in computing to
store the binary state.
SR Latch:
The SR latch is the simplest form of a bi-stable multi-vibrator which means that it has two
stable states. One state is typically known as the ‘Set’ state and the other is known as the
‘Reset’ state. Fig 7.1 shows the symbol of a SR latch.
Fig7.1: SR latch symbol.

The SR latch has two inputs and two outputs. The outputs Q and Q-not are supposed to be
opposite however, a general complication with a SR latch is the presence of illegal state. An
illegal state occurs when both Q and Q-not have the same value which means that either Q
and Q-not are both high or Q and Q-not are both low depending upon the logic gates used
within the circuit. Apart from this generally setting S=1 and R=0 results in Q=1 and Q-not =
0 which is the set state. Similarly setting S=0 and R=1 results in Q=0 and Q-not = 1 which is
the reset state.
Procedure
The following standard procedure will be used for performing the tasks. Only the gate IC will
be changed depending upon the requirement of the circuit.
Circuit Diagram
The following circuit diagrams have been designed on Multisim 14.0
a. SR LATCH USING NOR GATE
S
Q
7402N
R Q'
7402N
Fig 7.2: SR latch using NOR gate

b. SR LATCH USING NAND GATE
S
Q
7400N
R Q'
7400N
Fig 7.3: SR latch using NAND gate
Results
a. SR LATCH USING NOR GATE
Table 7.1: truth table for SR latch with NOR gate
S R Q Q State
1 1 0 0 Invalid
1 0 1 0 Set
0 0 1 0 Latch
0 1 0 1 Reset
0 1 0 1 Latch
b. SR LATCH USING NAND GATE

Table 7.2: truth table for SR latch with NAND gate
S R Q Q State
0 0 1 1 Invalid
1 0 0 1 Set
1 1 0 1 Latch
0 1 1 0 Reset
1 1 1 0 Latch
Conclusion:
In today’s lab we made an SR latch using NOR and NAND gate. The SR latch has an invalid
state that occurs when both outputs are either high or low. The latch is a very important
aspect of data storage and is used in storage circuits and in clocks. The experiment was done
using DC Power supply, Breadboard, Logic gate IC, Logic probe and Jumper wires.

Assessment Criteria
Lab # 11
UNSATISFACTOR Marks
(0)

preparation.

Apparatus & safety
Team work & time

management.
Marks (out of 15)
Final lab marks

(out of 0.5)

Experiment No. 11
Object:
(d) To understand the working of gated SR latch
(e) To understand the working of D latch
(f) To design a D latch using logic gates
Apparatus:
 Breadboard.
 Logic gate IC.
 Logic probe.
 Jumper wires.
Introduction:
The difference between a latch and a flip-flop is that a latch is asynchronous, and the outputs
can change as soon as the inputs do (or at least after a small propagation delay). A flip-flop,
on the other hand, is edge-triggered and only changes state when a control signal goes from
high to low or low to high.
The difference between a latch and a flip-flop is that a latch is asynchronous, and the outputs
can change as soon as the inputs do (or at least after a small propagation delay). A flip-flop,
on the other hand, is edge-triggered and only changes state when a control signal goes from
high to low or low to high.
The D Flip-Flop is just a modified version of the SR latch with control input. It is designed
by shorting both the S and R inputs and adding a inverter on the S input. This means that
there is only one input to the latch. Now ‘set’ and ‘reset’ are always complimentary due to the
presence of the inverter. This simple modification eliminates the invalid states which were
encountered in the SR latch. As a result, the final circuit has a more reliable output. The
output is high whenever the D input and the control input is high, and output is low when the
D input is low and the control input is high. The output latches whenever the control input is
low. D Flip-flops are widely used in various applications as I/O ports specifically in
integrated circuits. They are also used for data storage and reducing the transit count in
synchronous two-phase systems. Fig 7.1 shows the D-latch with a ‘enable’ input which acts
as a control.

Fig 8.1: D-Flip-flop
Procedure:
The following standard procedure will be used for performing the tasks. Only the gate IC will
be changed depending upon the requirement of the circuit.
Circuit Diagram:
a. Gated SR Flip-flop:
7400N Q
7400N
C
Q'
R 7400N
7400N
Fig 8.2: Gated SR Flip-flop.

b. D Flip-flop:
Fig 8.3: D Flip-flop
Results:
a. Gated SR Flip-flop:
Table 8.1: Output of gated SR Flip-flop
E S R Q Q' STATE
0 0 0 - - No change
0 0 1 - - No change
0 1 0 - - No change
0 1 1 - - No change
1 0 0 - - No change
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 - - Invalid
b. D Latch:
Table 8.2: Output of D Flip-flop
D E Q Q' STATE
0 0 - - No change
0 1 - - No change
1 0 0 1 Reset
1 1 1 0 Set
Conclusion:
Today’s lab was about understanding the working of gated SR latch and D latch.
Initially we were given a brief introduction to have basic knowledge about both the
latches. Afterwards we designed circuits to obtain outputs and have an idea about
designing a D latch using logic gates.

Assessment Criteria
Lab # 12
UNSATISFACTOR Marks
(0)

preparation.

Apparatus & safety
Team work & time

management.
Marks (out of 15)
Final lab marks

(out of 0.5)

Experiment No. 12
Object:
To study the JK flip flop.
LEARNING OUTCOMES:
 Working of JK flip-flop
 Designing JK flip-flop using AND & NAND gates
INTRODUCTION:
Flip-flops are synchronous bistable devices. Synchronous in this case refers to that fact that
the output changes state at a specified point on the control input; in other words, the output
changes in sync with the control input. The control input in flip-flops is known as the clock.
Flip flops are edge-triggered (or edge-sensitive) meaning that their state changes at either the
rising edge or falling edge of the clock signal. The three basic types of flip-flops are SR, JK,
and D.
1. JK FLIP-FLOP:
The JK flip-flop was designed to overcome the invalid state present in the SR flip-flop when
both inputs are high. It is the most widely used flip-flop and is considered to be a universal
flip-flop circuit. The two inputs labelled “J” and “K” are not abbreviations for other words as
is the case in the SR flip-flop, instead they are letters chosen by the inventor Jack Kirby to
distinguish the design from others.
Figure 1: Symbol of JK Flip-Flop

The JK flip-flop is a gated SR flip-flop with an additional input known as the clock. The
sequential operation of the JK flip-flop is the same as the SR flip-flop with the only
difference being the absence of the invalid state due to the presence of a clock. The JK flip-
flop has four possible states: high, low, no change, and toggle (replaces invalid state in SR
flip-flop). State changes only occur when the clock pulse is high.

Figure 2: Pin configuration for JK flip flop (74LS73)
2. MATERIAL & METHOD:

2.1. APPARATUS:
 DC Power supply
 Breadboard
 NAND gate IC
 Logic probe
 Jumper wires
 Multisim 14.0
2.2. PROCEDURE FOR BREADBOARD:

 Insert the NAND gate ICs on the breadboard.
 Connect VCC pin 14 to +5V of power supply.
 Connect Gnd pin 7 to 0V of power supply.
 Follow the circuit diagram to make the connections.
 Follow the truth table and record the output with the help of logic probe.
2.3. PROCEDURE FOR MULTISIM:
 Place the JK flip-flop IC on the sheet.
 Follow the circuit diagram to make the connections.
 Play the simulation and observe the changes in the output as the inputs are
changed.
3. CIRCUIT DIAGRAM:
The following circuit diagrams have been designed on Multisim 14.0.
3.1. JK FLIP-FLOP USING NAND GATE:

Figure 3: JK flip flop using Nand Gate
4. RESULTS:
c. JK FLIP-FLOP USING NAD GATE:
Table 1: Output of JK Flip-Flop using Nand Gate
CLK J K Q Q' STATE

0 0 0 - - No change
0 0 1 - - No change
0 1 0 - - No change
0 1 1 - - No change
1 0 0 - - No change
1 0 1 0 1 Reset
1 1 0 1 0 Set
1 1 1 1 1 Toggle
5. TASK 2:
Draw timing diagram to observe the working of JK Flip flop.

6. CONCLUSION:
Today’s lab was all about understanding the working of JK flip-flop along with learning the
basic knowledge of designing JK flip-flop using AND & NAND gates. After getting slight
understanding of the pin configuration of a JK flip flop we proceeded towards making a
circuit and obtaining the results noted in the observation table. As part of our lab task, we
also drew timing diagram to observe the working of a JK flip flop.

Assessment Criteria
Lab # 13
UNSATISFACTOR
PROFICIENT SATISFACTORY SUBSTANDARD Marks
(0)

preparation.

Apparatus & safety
Team work & time

management.
Marks (out of 15)
Final lab marks

(out of 0.5)

13 LAB EXPERIMENT
OBJECT:
To study 4-bit shift registers
LEARNING OUTCOMES:
 Working of 4-bit shift register
 Types of 4-bit shift register
 Applications of 4-bit shift registers
1. INTRODUCTION:
Shift registers are basically sequential logic circuits composed of flip flops which have the
ability to shift between data sequences. Generally, registers have the ability to store data
depending upon the number of flip flops included in the construction. Adding to this general
function, shift registers can also shift sequences. Usually shift registers are designed using D-
flip flops. This is because D-flip flops have a straightforward output, in the presence of a
clock signal the output goes high if the D input is high and vice versa. The working of shift
registers resembles to that of a counter however a shift register unlike a counter does not have
a fixed sequence.
2. Shift Registers:
Based on their design and working there are approximately 4 types of shift registers as listed
below:
2.1. SISO:
This type of shift register has a single input and a single output. As shown in Fig 14.1 all the
D-flip flops are cascaded and the output is taken from the right most flip flop whereas the
input is given to the left most flip flop.

Figure 13.1: Serial in-serial out 4-bit shift register
2.2. SIPO:
This type of shift register has a single input and multiple outputs. The data input is given
similar to a serial in-serial out shift register however the outputs are taken from each flip flop.
Fig 14.2 shows a serial in-parallel shift register.
Figure 13.2: Serial in-parallel out 4-bit shift register
2.3. PISO:
This type of shift register uses multiple inputs and a single output. Using a combination of
logic gates input is fed separately into each flip flop. The flip flops are cascaded as in
previous types. The output is then taken from the right most flip flop. Fig 14.3 shows a
parallel in-serial out design for a shift register.
Figure 13.3: Parallel in-serial out 4-bit shift register

2.4. PIPO:
This type of shift register is different from other types of the shift register as the flip flops are
not cascaded as in the previous types. Each flip flop is given a separate input and a separate
output is taken. This means that there are multiple inputs and multiple outputs. Fig 14.4
shows the organization of a parallel in-parallel out shift register.

Figure 13.4: Parallel in-parallel out 4-bit shift register
3. MATERIAL AND METHOD:

This lab was performed on the software and requires Multisim 14.0
3.1. PROCEDURE:
1. Place the 74LS74 D-flip flops on the sheet.
2. Follow the circuit diagram to make the connections.
3. Observe the results on by playing the simulation.
3.2. CIRCUIT DIAGRAM:

A. SISO
Figure 13.5: Serial in-serial out 4-bit shift register
B. SIPO:
Figure 13.6: Serial in-parallel out 4-bit shift register

C. PISO:

Figure 13.7: Parallel in-serial out 4-bit shift register
D. PIPO:
Figure 13.8: Parallel in-parallel out 4-bit shift register

4. RESULTS:
A. SISO:
CLOCK D Q0
0 0 0
1 1 0
2 1 0
3 1 0
4 1 1
TIMING DIAGRAM:

B. SIPO:
CLOCK D0 Q0 Q1 Q2 Q3
0 0 0 0 0 0
1 1 1 0 0 0
2 1 1 1 0 0
3 0 0 1 1 0
4 1 1 0 1 1
TIMING DIAGRAM:

C. PISO:
CLOCK D0 D1 D2 D3 Q0
0 0 0 0 0 0
1 1 0 0 0 0
2 1 1 0 0 0
3 1 1 1 0 0
4 1 1 1 1 1
TIMING DIAGRAM:

D. PIPO:
CLOCK D0 D1 D2 D3 Q0 Q1 Q2 Q3
0 0 0 0 0 0 0 0 0
1 0 1 1 0 0 1 1 0
2 1 1 1 1 1 1 1 1
TIMING DIAGRAM:

CONCLUSION:
In this lab, we studied about the shift registers. We studied their structure and their
applications. We also studied the four different types of registers, which are:
 SERIAL IN,
 SERIAL OUT,
 SERIAL IN PARALLEL OUT,
 PARALLEL IN SERIAL OUT
 PARALLEL IN PARALLEL OUT.

Assessment Criteria
Lab # 14
UNSATISFACTOR
(0)

preparation.

Apparatus & safety
Team work & time

management.
Marks (out of 15)
Final lab marks

(out of 0.5)

14 LAB EXPERIMENT
OBJECT:
To design an electronic dice using what we have studied in the previous labs.
1. INTRODUCTION:
Using a dice to roll a number between 1 and 6 is a game of luck where the player cannot
judge or plan on what they will get. It’s an age old way of playing a game with a wooden or
plastic dice.
In this project LED’s, different IC’s and counter have been used to generate a number
between 1 and 6 by lightening up the LED corresponding to the number. LEDs start flashing
as we press the Push button and stops when we release it. After release, illuminated LED tells
the numbers, you got on Dice. We have connected 6 LEDs to the output Q 0 to Q5, and the
seventh output Q6 is connected back to the reset pin 15. So that after LED 6 it starts from the
First LED at Q0.
This circuit uses 555 Timer IC. In this mode, the circuit is arranged with R2 = 100 KΩ, R3 =
100 KΩ and C2 = 0.1 µF. With this configuration, the circuit operates as a pulse generator
with a frequency in order of kilo hertz. This means that the circuit produces a clock cycle of
about 0.000210 seconds which is imperceptible to the human eye. We cannot observe the
values which change at that faster rate so there is hardly any possibility of getting the dice
biased. The clock pulses are given to a counter cum decoder circuit IC 4017 with the seventh
output given to reset. It has nine possible outputs out of which, the seventh is given to reset
because we only need a count up to 6 as a dice has six faces only. The first six outputs are
given respectively to the LEDs, so that the respective LED will glow for the corresponding
count.
2. THEORY:
2.2. 555 Timer IC.

The 555 timer IC is an integrated circuit used in a variety of timer, delay, pulse generation,
and oscillator applications. The voltage divider consists of three identical 5k resistors which
create two reference voltages at 1/3 and 2/3 of the supplied voltage, which can range from 5
to 15V. Next are the two comparators. The first comparator negative input terminal is
connected to the 2/3 reference voltage at the voltage divider and the external “control” pin,
while the positive input terminal to the external “Threshold” pin. On the other hand, the
second comparator negative input terminal is connected to the “Trigger” pin, while the
positive input terminal to the 1/3 reference voltage at the voltage divider.

So using the three pins, Trigger, Threshold and Control, we can control the output of the two
comparators which are then fed to the R and S inputs of the flip-flop. The flip-flop will output
1 when R is 0 and S is 1, and vice versa, it will output 0 when R is 1 and S is 0. Additionally
the flip-flop can be reset via the external pin called “Reset” which can override the two
inputs, thus reset the entire timer at any time.
Figure 14.1: 555 timer IC internal circuit and pinout
2.3. CD 4017 Decade Counter.

The CD4017 is a CMOS Decade counter IC. CD4017 is used for low range counting
applications. It can count from 0 to 10 (the decade count). The circuit designed by using this
IC will save board space and also time required to design the circuit. CD4017 is as ‘Johnson
10 stage decade counter’. This IC is also used in electronic industries, automotive industries,
manufacturing medical electronic devices, alarms and in electronic instrumentation devices.
Figure 14.2: Pinout of 4017decade counter
3. COMPONENTS:
 Resistors
 Capacitors
 LED’s
 555 timer IC
 Switch
 CD 4017 IC
 Battery

4. CIRCUIT DIAGRAM:
Key = A
S1A
U1
R2 555_TIMER_RATED
100kΩ VCC U2
RST 14 CP0 O0 3
OUT 13 2
~CP1 O1
DIS O2 4
V1 15 MR O3 7
10
12 V THR O4
1
O5
TRI O6 5
R1 O7 6
R3 CON O8 9
1kΩ O9 11
100kΩ GND
~O5-9 12
4017BD_15V
C1 C2
1nF 1µF
Figure 14.2: Circuit diagram of the electronic dice
5. APPLICATION:
This unbiased electronic dice with LEDs can be used wherever traditional dice is used like:
 Snakes and Ladders

 Ludo
 Monopoly
Any game that has the use of a dice can be replaced with this electronic dice.
6. DISCUSSION:
Using electronics to make and replace things used in the physical world is an important
aspect as the electronic items to not degrade over time. A wooden dice will start degrading,
become beaten or be deformed due to dampness or other environmental factors. Any mistake
made in the production of such an item can cause the unbiased nature of the item to turn into
biased therefore having an electronic replacement for the item is always a positive.

Assessment Criteria
Lab # 15
UNSATISFACTOR
(0)

preparation.

Apparatus & safety
Team work & time

management.
Marks (out of 15)
Final lab marks

(out of 0.5)

15 LAB EXPERIMENT
OBJECT:
To design an electronic digital stopwatch.
INTRODUCTION:
A stopwatch is a handheld timepiece designed to measure the amount of time that elapses
between its activation and deactivation. A large digital version of a stopwatch designed for
viewing at a distance, as in a sports stadium, is called a stop clock.
This lab project describes the principle, design and operation of a digital stopwatch circuit. A
digital stopwatch can be a circuit displaying the actual time in minutes, hours and seconds or
a circuit displaying the number of clock pulses. Here we design the second type wherein the
circuit displays count from 0 to 59, representing a 60 second time interval. In other words
here the circuit displays the time in seconds only. This is a simple circuit consisting two
counter ICs to carry out the counting operation.
Theory:
Every stopwatch is composed of four elements: a power source, a time base, a counter, and
an indicator or display. The design and construction of each component depends upon the
type of stopwatch. Digital Stopwatches.
The power source of a stopwatch is usually a silver cell or alkaline battery, which powers the
oscillator, counting and display circuitry. The time base is usually a quartz crystal oscillator,
with a nominal frequency of 32 768 Hz (215 Hz). The inside of a typical device is the printed
circuit board quartz crystal oscillator and battery visible. The counter circuit consists of
digital dividers that count the time base oscillations for the period that is initiated by the
start/stop buttons. The display typically has seven or eight digits.
Components:
 Decade counter
 BCD to seven segment display
 Seven segment display(common anode)
 7408N (AND Gate)
 Battery/power source
 Ground
 Function generator

CIRCUIT DIAGRAM:
Figure 15.1: Circuit Diagram of the stopwatch
APPLICATIONS:
Stopwatch needs no introduction; we use them at many points of our life to measure timings
for several purposes like: During cooking to avoid the food to either overcooked or
undercooked, during a sport event like a race such as swimming or track, a stop watch can
provide split or lap times to determine an athlete’s performance during an event or even at
science lab.
The stopwatch function is also present as an additional function of many electronic devices
such as wristwatches, cell phones, portable music players, and computers. Now a day, stop
watch is used mostly in online games such as speed testing games, games that require the
ability to accurately perceive time, online stop watch games and educational games.
RESULTS:
This project of making “Digital Stop Watch”, which can count from 0 to 59 seconds and has
Hold and reset capabilities has been completed. After completion of this digital stopwatch
project, I have learnt some knowledge in designing the circuit and understood the
implementation using 555timer and Johnson counter, designing the circuit and understood the
coding process. Calibration process yielded combined “coarse & fine” delay of 1ms. The
circuit has been implemented on Multisim.

CONCLUSION:
A digital counter built around two decade counters, two BCD to seven segment display
counters, two seven segment display which have common anode, one AND Gate IC-7408. 5
volts VCC and ground are provided to the circuit and a function generator is used to generate
different type of electrical waveforms. It can easily assemble on a general-purpose PCB. And
most importantly it is designed on Multisim.
We started designing simple stopwatch circuit on Multisim to understand the basic circuit
used in manufacturing stopwatch and to analyze the operation of stopwatch. We also learn
using seven segment displays and their driver ICs for displaying digital data.

Laboratory Manual: ELE-203 Digital Logic Design

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Laboratory Manual: ELE-203 Digital Logic Design

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Digital Logic Design ELE – 203

Student Name Zunaira Namal

Barrett Hodgson University – Department of Biomedical Engineering

Understanding of experiment & designing / construction & Lab preparation:

Usage of modern tools / apparatus & Safety:

Team work & time management:

Result & conclusion:

Barrett Hodgson University – Department of Biomedical Engineering

Selection of tool / Usage of modern tool:

Testing analysis and Team Work:

Result & conclusion.

Barrett Hodgson University – Department of Biomedical Engineering

(b) To Design XOR and XNOR gates using logic gates

Lab 8 To check the operation of common anode BCD to 7-

Lab 11 (a) To understand the working of gated SR latch

Lab 13 To study 4-bit shift registers

Lab 14 To design an electronic dice using what we have studied

Barrett Hodgson University – Department of Biomedical Engineering

Lab Performance & Lab Manual Assessment

Understanding of experiment &

Usage of modern tools /

Team work & time

Organization & content.

Result & conclusion.

Marks (out of 15)

Final lab marks

Lab Instructor signature: ____________________

Barrett Hodgson University – Department of Biomedical Engineering

3. WHAT CAN YOU DO WITH MULTISIM FOR EDUCATION?

1. ANALYZE CIRCUIT BEHAVIOUR:

Barrett Hodgson University – Department of Biomedical Engineering

Figure 1: Analyze Circuit response of RC circuit.

Figure 2: Circuit of Differential Amplifier.

3. REINFORCE THEORY BY COMPARING REAL AND

Barrett Hodgson University – Department of Biomedical Engineering

Figure 3: Band pass filter circuit simulation.

4. TEACH DIGITAL LOGIC AND DEPLOY IT TO

Figure 4: FPGA circuit design.

4. HOW TO START WITH NI MULTISIM 14.0:

3. Click to create the new file.

Barrett Hodgson University – Department of Biomedical Engineering

Figure 5: Creating new file.

Figure 6: Selecting type of design.

Figure 7: Main window of NI Multisim with labelling.

Barrett Hodgson University – Department of Biomedical Engineering

Lab Performance & Lab Manual Assessment

Understanding of experiment &

Usage of modern tools /

Team work & time

Organization & content.

Result & conclusion.

Marks (out of 15)

Final lab marks

Lab Instructor signature: ____________________

To Design XOR and XNOR gates using logic gates

In this lab, student will be able to understand the following points:

 Internal structure and working of XOR gate.

Figure 1: Symbol of XOR Gate [3]

 XOR Gate IC: 7486

 Pin Diagram of XOR Gate IC:

Barrett Hodgson University – Department of Biomedical Engineering

Figure 2: Pin Diagram of XOR Gate [3]

3. The XNOR Gate